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SSIF

The SSIF driver implements transmission and reception functionality which uses the SSIF in the RZ/A Series.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Ssif.h"
00003 #include "sine_data_tbl.h"
00004 
00005 //I2S send only, The upper limit of write buffer is 8.
00006 R_BSP_Ssif ssif(P4_4, P4_5, P4_7, P4_6, 0x80, 8, 0);
00007 
00008 static void callback_ssif_write_end(void * p_data, int32_t result, void * p_app_data) {
00009     if (result < 0) {
00010         printf("ssif write callback error %d\n", result);
00011     }
00012 }
00013 
00014 int main() {
00015     rbsp_data_conf_t   ssif_write_end_conf = {&callback_ssif_write_end, NULL};
00016     ssif_channel_cfg_t ssif_cfg;
00017     int32_t            result;
00018 
00019     //I2S Master, 44.1kHz, 16bit, 2ch
00020     ssif_cfg.enabled                = true;
00021     ssif_cfg.int_level              = 0x78;
00022     ssif_cfg.slave_mode             = false;
00023     ssif_cfg.sample_freq            = 44100u;
00024     ssif_cfg.clk_select             = SSIF_CFG_CKS_AUDIO_X1;
00025     ssif_cfg.multi_ch               = SSIF_CFG_MULTI_CH_1;
00026     ssif_cfg.data_word              = SSIF_CFG_DATA_WORD_16;
00027     ssif_cfg.system_word            = SSIF_CFG_SYSTEM_WORD_32;
00028     ssif_cfg.bclk_pol               = SSIF_CFG_FALLING;
00029     ssif_cfg.ws_pol                 = SSIF_CFG_WS_LOW;
00030     ssif_cfg.padding_pol            = SSIF_CFG_PADDING_LOW;
00031     ssif_cfg.serial_alignment       = SSIF_CFG_DATA_FIRST;
00032     ssif_cfg.parallel_alignment     = SSIF_CFG_LEFT;
00033     ssif_cfg.ws_delay               = SSIF_CFG_DELAY;
00034     ssif_cfg.noise_cancel           = SSIF_CFG_DISABLE_NOISE_CANCEL;
00035     ssif_cfg.tdm_mode               = SSIF_CFG_DISABLE_TDM;
00036     ssif_cfg.romdec_direct.mode     = SSIF_CFG_DISABLE_ROMDEC_DIRECT;
00037     ssif_cfg.romdec_direct.p_cbfunc = NULL;
00038     result = ssif.ConfigChannel(&ssif_cfg);
00039     if (result < 0) {
00040         printf("ssif config error %d\n", result);
00041     }
00042 
00043     while (1) {
00044         //The upper limit of write buffer is 8.
00045         result = ssif.write((void *)sin_data_44100Hz_16bit_2ch, 
00046                             sizeof(sin_data_44100Hz_16bit_2ch), &ssif_write_end_conf);
00047         if (result < 0) {
00048             printf("ssif write api error %d\n", result);
00049         }
00050     }
00051 }

API

Import library

Public Member Functions

R_BSP_Ssif (PinName sck, PinName ws, PinName tx, PinName rx, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor.
virtual ~R_BSP_Ssif ()
Destructor.
int32_t GetSsifChNo (void)
Get a value of SSIF channel number.
bool ConfigChannel (const ssif_channel_cfg_t *const p_ch_cfg)
Save configuration to the SSIF driver.
bool GetStatus (uint32_t *const p_status)
Get a value of SSISR register.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Interface

See the Pinout page for more details


SCUX

The SCUX module consists of a sampling rate converter, a digital volume unit, and a mixer.
The SCUX driver can perform asynchronous and synchronous sampling rate conversions using the sampling rate converter. The SCUX driver uses the DMA transfer mode to input and output audio data.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Scux.h"
00003 #include "USBHostMSD.h"
00004 
00005 R_BSP_Scux scux(SCUX_CH_0);
00006 
00007 #define WRITE_SAMPLE_NUM (128)
00008 #define READ_SAMPLE_NUM  (2048)
00009 
00010 const short sin_data[WRITE_SAMPLE_NUM] = {
00011  0x0000,0x0000,0x0C8C,0x0C8C,0x18F9,0x18F9,0x2528,0x2528
00012 ,0x30FB,0x30FB,0x3C56,0x3C56,0x471C,0x471C,0x5133,0x5133
00013 ,0x5A82,0x5A82,0x62F1,0x62F1,0x6A6D,0x6A6D,0x70E2,0x70E2
00014 ,0x7641,0x7641,0x7A7C,0x7A7C,0x7D89,0x7D89,0x7F61,0x7F61
00015 ,0x7FFF,0x7FFF,0x7F61,0x7F61,0x7D89,0x7D89,0x7A7C,0x7A7C
00016 ,0x7641,0x7641,0x70E2,0x70E2,0x6A6D,0x6A6D,0x62F1,0x62F1
00017 ,0x5A82,0x5A82,0x5133,0x5133,0x471C,0x471C,0x3C56,0x3C56
00018 ,0x30FB,0x30FB,0x2528,0x2528,0x18F9,0x18F9,0x0C8C,0x0C8C
00019 ,0x0000,0x0000,0xF374,0xF374,0xE707,0xE707,0xDAD8,0xDAD8
00020 ,0xCF05,0xCF05,0xC3AA,0xC3AA,0xB8E4,0xB8E4,0xAECD,0xAECD
00021 ,0xA57E,0xA57E,0x9D0F,0x9D0F,0x9593,0x9593,0x8F1E,0x8F1E
00022 ,0x89BF,0x89BF,0x8584,0x8584,0x8277,0x8277,0x809F,0x809F
00023 ,0x8001,0x8001,0x809F,0x809F,0x8277,0x8277,0x8584,0x8584
00024 ,0x89BF,0x89BF,0x8F1E,0x8F1E,0x9593,0x9593,0x9D0F,0x9D0F
00025 ,0xA57E,0xA57E,0xAECD,0xAECD,0xB8E4,0xB8E4,0xC3AA,0xC3AA
00026 ,0xCF05,0xCF05,0xDAD8,0xDAD8,0xE707,0xE707,0xF374,0xF374
00027 };
00028 
00029 #if defined(__ICCARM__)
00030 #pragma data_alignment=4
00031 short write_buff[WRITE_SAMPLE_NUM]@ ".mirrorram";
00032 #pragma data_alignment=4
00033 short read_buff[READ_SAMPLE_NUM]@ ".mirrorram";
00034 #else
00035 short write_buff[WRITE_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00036 short read_buff[READ_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00037 #endif
00038 
00039 void scux_setup(void);
00040 void write_task(void const*);
00041 void file_output_to_usb(void);
00042 
00043 int main(void) {
00044     // set up SRC parameters.
00045     scux_setup();
00046 
00047     printf("Sampling rate conversion Start.\n");
00048     // start accepting transmit/receive requests.
00049     scux.TransStart();
00050 
00051     // create a new thread to write to SCUX.
00052     Thread writeTask(write_task, NULL, osPriorityNormal, 1024 * 4);
00053 
00054     // receive request to the SCUX driver.
00055     scux.read(read_buff, sizeof(read_buff));
00056     printf("Sampling rate conversion End.\n");
00057 
00058     // output binary file to USB port 0.
00059     file_output_to_usb();
00060 }
00061 
00062 void scux_setup(void) {
00063     scux_src_usr_cfg_t src_cfg;
00064 
00065     src_cfg.src_enable           = true;
00066     src_cfg.word_len             = SCUX_DATA_LEN_16;
00067     src_cfg.mode_sync            = true;
00068     src_cfg.input_rate           = SAMPLING_RATE_48000HZ;
00069     src_cfg.output_rate          = SAMPLING_RATE_96000HZ;
00070     src_cfg.select_in_data_ch[0] = SELECT_IN_DATA_CH_0;
00071     src_cfg.select_in_data_ch[1] = SELECT_IN_DATA_CH_1;
00072 
00073     scux.SetSrcCfg(&src_cfg);
00074 }
00075 
00076 void scux_flush_callback(int scux_ch) {
00077     // do nothing
00078 }
00079 
00080 void write_task(void const*) {
00081     memcpy(write_buff, sin_data, sizeof(write_buff));
00082     // send request to the SCUX driver.
00083     scux.write(write_buff, sizeof(write_buff));
00084 
00085     // stop the acceptance of transmit/receive requests.
00086     scux.FlushStop(&scux_flush_callback);
00087 }
00088 
00089 void file_output_to_usb(void) {
00090     FILE * fp = NULL;
00091     int i;
00092 
00093     USBHostMSD msd("usb");
00094 
00095     // try to connect a MSD device
00096     for(i = 0; i < 10; i++) {
00097         if (msd.connect()) {
00098             break;
00099         }
00100         wait(0.5);
00101     }
00102 
00103     if (msd.connected()) {
00104         fp = fopen("/usb/scux_input.dat", "rb");
00105         if (fp == NULL) {
00106             fp = fopen("/usb/scux_input.dat", "wb");
00107             if (fp != NULL) {
00108                 fwrite(write_buff, sizeof(short), WRITE_SAMPLE_NUM, fp);
00109                 fclose(fp);
00110                 printf("Output binary file(Input data) to USB.\n");
00111             } else {
00112                 printf("Failed to output binary file(Input data).\n");
00113             }
00114         } else {
00115             printf("Binary file(Input data) exists.\n");
00116             fclose(fp);
00117         }
00118 
00119         fp = fopen("/usb/scux_output.dat", "rb");
00120         if (fp == NULL) {
00121             fp = fopen("/usb/scux_output.dat", "wb");
00122             if (fp != NULL) {
00123                 fwrite(read_buff, sizeof(short), READ_SAMPLE_NUM, fp);
00124                 fclose(fp);
00125                 printf("Output binary file(Output data) to USB.\n");
00126             } else {
00127                 printf("Failed to output binary file(Output data).\n");
00128             }
00129         } else {
00130             printf("Binary file(Output data) exists.\n");
00131             fclose(fp);
00132         }
00133     } else {
00134         printf("Failed to connect to the USB device.\n");
00135     }
00136 } 

API

Import library

Public Member Functions

R_BSP_Scux ( scux_ch_num_t channel, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor: Initializes and opens the channel designated by the SCUX driver.
virtual ~R_BSP_Scux (void)
Destructor: Closes the channel designated by the SCUX driver and exits.
bool TransStart (void)
Sets up the SCUX HW and starts operation, then starts accepting write/read requests.
bool FlushStop (void(*const callback)(int32_t))
Stops accepting write/read requests, flushes out all data in the SCUX that is requested for transfer, then stops the HW operation.
bool ClearStop (void)
Discards all data in the SCUX that is requested for transfer before stopping the hardware operation and stops accepting write/read requests.
bool SetSrcCfg (const scux_src_usr_cfg_t *const p_src_param)
Sets up SRC parameters.
bool GetWriteStat (uint32_t *const p_write_stat)
Obtains the state information of the write request.
bool GetReadStat (uint32_t *const p_read_stat)
Obtains the state information of the read request.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Write request state transition diagram

/media/uploads/dkato/scux_write_state_transition.png

Read request state transition diagram

/media/uploads/dkato/scux_read_state_transition.png

Committer:
dkato
Date:
Wed Dec 16 06:33:17 2015 +0000
Revision:
7:30ebba78fff0
Parent:
6:aa1fc6a5cc2a
Child:
10:c5c630882b90
Standardization of processing

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 6:aa1fc6a5cc2a 1 /*******************************************************************************
dkato 6:aa1fc6a5cc2a 2 * DISCLAIMER
dkato 6:aa1fc6a5cc2a 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 6:aa1fc6a5cc2a 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 6:aa1fc6a5cc2a 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 6:aa1fc6a5cc2a 6 * all applicable laws, including copyright laws.
dkato 6:aa1fc6a5cc2a 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 6:aa1fc6a5cc2a 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 6:aa1fc6a5cc2a 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 6:aa1fc6a5cc2a 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 6:aa1fc6a5cc2a 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 6:aa1fc6a5cc2a 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 6:aa1fc6a5cc2a 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 6:aa1fc6a5cc2a 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 6:aa1fc6a5cc2a 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 6:aa1fc6a5cc2a 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 6:aa1fc6a5cc2a 17 * and to discontinue the availability of this software. By using this software,
dkato 6:aa1fc6a5cc2a 18 * you agree to the additional terms and conditions found by accessing the
dkato 6:aa1fc6a5cc2a 19 * following link:
dkato 6:aa1fc6a5cc2a 20 * http://www.renesas.com/disclaimer
dkato 6:aa1fc6a5cc2a 21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
dkato 6:aa1fc6a5cc2a 22 *******************************************************************************/
dkato 6:aa1fc6a5cc2a 23
dkato 6:aa1fc6a5cc2a 24 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 25 * @file scux.c
dkato 6:aa1fc6a5cc2a 26 * $Rev: 1674 $
dkato 6:aa1fc6a5cc2a 27 * $Date:: 2015-05-29 16:35:57 +0900#$
dkato 6:aa1fc6a5cc2a 28 * @brief SCUX Driver functions
dkato 6:aa1fc6a5cc2a 29 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 30
dkato 6:aa1fc6a5cc2a 31 /*******************************************************************************
dkato 6:aa1fc6a5cc2a 32 Includes <System Includes>, "Project Includes"
dkato 6:aa1fc6a5cc2a 33 *******************************************************************************/
dkato 6:aa1fc6a5cc2a 34
dkato 6:aa1fc6a5cc2a 35 #include "scux.h"
dkato 6:aa1fc6a5cc2a 36
dkato 6:aa1fc6a5cc2a 37 #if(1) /* mbed */
dkato 6:aa1fc6a5cc2a 38 /******************************************************************************
dkato 6:aa1fc6a5cc2a 39 Macro definitions
dkato 6:aa1fc6a5cc2a 40 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 41 #define INIT_WAIT_TIME_MSEC (1)
dkato 6:aa1fc6a5cc2a 42 #define INIT_WAIT_NUM (1000U)
dkato 6:aa1fc6a5cc2a 43
dkato 6:aa1fc6a5cc2a 44 #endif /* end mbed */
dkato 6:aa1fc6a5cc2a 45 /******************************************************************************
dkato 6:aa1fc6a5cc2a 46 Exported global variables (to be accessed by other files)
dkato 6:aa1fc6a5cc2a 47 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 48
dkato 6:aa1fc6a5cc2a 49 /* ->MISRA 8.8 This description is based on the way to fill out OS defined. */
dkato 6:aa1fc6a5cc2a 50 /* ->IPA M2.2.2, MISRA 8.10 This description is based on the way to fill out OS defined. */
dkato 6:aa1fc6a5cc2a 51 osSemaphoreDef(scux_ch0_access);
dkato 6:aa1fc6a5cc2a 52 osSemaphoreDef(scux_ch1_access);
dkato 6:aa1fc6a5cc2a 53 osSemaphoreDef(scux_ch2_access);
dkato 6:aa1fc6a5cc2a 54 osSemaphoreDef(scux_ch3_access);
dkato 6:aa1fc6a5cc2a 55
dkato 6:aa1fc6a5cc2a 56 osSemaphoreDef(scux_ssif_ch0_access);
dkato 6:aa1fc6a5cc2a 57 osSemaphoreDef(scux_ssif_ch1_access);
dkato 6:aa1fc6a5cc2a 58 osSemaphoreDef(scux_ssif_ch2_access);
dkato 6:aa1fc6a5cc2a 59 osSemaphoreDef(scux_ssif_ch3_access);
dkato 6:aa1fc6a5cc2a 60 osSemaphoreDef(scux_ssif_ch4_access);
dkato 6:aa1fc6a5cc2a 61 osSemaphoreDef(scux_ssif_ch5_access);
dkato 6:aa1fc6a5cc2a 62
dkato 6:aa1fc6a5cc2a 63 osSemaphoreDef(scux_shared_access);
dkato 6:aa1fc6a5cc2a 64 /* <-MISRA 8.10, IPA M2.2.2 */
dkato 6:aa1fc6a5cc2a 65 /* <-MISRA 8.8 */
dkato 6:aa1fc6a5cc2a 66
dkato 6:aa1fc6a5cc2a 67 /******************************************************************************
dkato 6:aa1fc6a5cc2a 68 Private global driver management information
dkato 6:aa1fc6a5cc2a 69 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 70
dkato 6:aa1fc6a5cc2a 71 /* driver management infrmation */
dkato 6:aa1fc6a5cc2a 72 static scux_info_drv_t gb_scux_info_drv = {
dkato 6:aa1fc6a5cc2a 73 SCUX_DRV_UNINIT,
dkato 6:aa1fc6a5cc2a 74 {
dkato 6:aa1fc6a5cc2a 75 {SCUX_CH_0, false, 0, SCUX_CH_UNINIT}, /* ch0 */
dkato 6:aa1fc6a5cc2a 76 {SCUX_CH_1, false, 0, SCUX_CH_UNINIT}, /* ch1 */
dkato 6:aa1fc6a5cc2a 77 {SCUX_CH_2, false, 0, SCUX_CH_UNINIT}, /* ch2 */
dkato 6:aa1fc6a5cc2a 78 {SCUX_CH_3, false, 0, SCUX_CH_UNINIT} /* ch3 */
dkato 6:aa1fc6a5cc2a 79 }
dkato 6:aa1fc6a5cc2a 80 };
dkato 6:aa1fc6a5cc2a 81
dkato 6:aa1fc6a5cc2a 82 /* SSIF management information */
dkato 6:aa1fc6a5cc2a 83 static scux_ssif_info_t gb_scux_ssif_info[SCUX_SSIF_CH_NUM];
dkato 6:aa1fc6a5cc2a 84
dkato 6:aa1fc6a5cc2a 85 /* ->MISRA 11.3, 11.4 11.5 This cast is needed for register access. */
dkato 6:aa1fc6a5cc2a 86 /* address table of register set for each SCUX channel */
dkato 6:aa1fc6a5cc2a 87 static scux_reg_info_t p_scux_ch_reg_addr_table[SCUX_CH_NUM] = {
dkato 6:aa1fc6a5cc2a 88 {
dkato 6:aa1fc6a5cc2a 89 &SCUX_FROM_DVUIR_DVU0_0,
dkato 6:aa1fc6a5cc2a 90 &SCUX_FROM_SRCIR0_2SRC0_0,
dkato 6:aa1fc6a5cc2a 91 &SCUX_FROM_FFUIR_FFU0_0,
dkato 6:aa1fc6a5cc2a 92 &SCUX_FROM_FFDIR_FFD0_0,
dkato 6:aa1fc6a5cc2a 93 &SCUX_FROM_OPCIR_OPC0_0,
dkato 6:aa1fc6a5cc2a 94 &SCUX_FROM_IPCIR_IPC0_0,
dkato 6:aa1fc6a5cc2a 95 &SCUXMIXIR_MIX0_0,
dkato 6:aa1fc6a5cc2a 96 &SCUXMADIR_MIX0_0,
dkato 6:aa1fc6a5cc2a 97 &SCUXMIXBR_MIX0_0,
dkato 6:aa1fc6a5cc2a 98 &SCUXMIXMR_MIX0_0,
dkato 6:aa1fc6a5cc2a 99 &SCUXMVPDR_MIX0_0,
dkato 6:aa1fc6a5cc2a 100 &SCUXMDBAR_MIX0_0,
dkato 6:aa1fc6a5cc2a 101 &SCUXMDBER_MIX0_0,
dkato 6:aa1fc6a5cc2a 102 &SCUXMIXSR_MIX0_0,
dkato 6:aa1fc6a5cc2a 103 &SCUXSWRSR_CIM,
dkato 6:aa1fc6a5cc2a 104 &SCUXDMACR_CIM,
dkato 6:aa1fc6a5cc2a 105 &SCUXDMATD0_CIM,
dkato 6:aa1fc6a5cc2a 106 &SCUXDMATU0_CIM,
dkato 6:aa1fc6a5cc2a 107 &SCUXSSIRSEL_CIM,
dkato 6:aa1fc6a5cc2a 108 &SCUXFDTSEL0_CIM,
dkato 6:aa1fc6a5cc2a 109 &SCUXFUTSEL0_CIM,
dkato 6:aa1fc6a5cc2a 110 &SCUXSSIPMD_CIM,
dkato 6:aa1fc6a5cc2a 111 &SCUXSSICTRL_CIM,
dkato 6:aa1fc6a5cc2a 112 &SCUXSRCRSEL0_CIM,
dkato 6:aa1fc6a5cc2a 113 &SCUXMIXRSEL_CIM
dkato 6:aa1fc6a5cc2a 114 },
dkato 6:aa1fc6a5cc2a 115 {
dkato 6:aa1fc6a5cc2a 116 &SCUX_FROM_DVUIR_DVU0_1,
dkato 6:aa1fc6a5cc2a 117 &SCUX_FROM_SRCIR0_2SRC0_0,
dkato 6:aa1fc6a5cc2a 118 &SCUX_FROM_FFUIR_FFU0_1,
dkato 6:aa1fc6a5cc2a 119 &SCUX_FROM_FFDIR_FFD0_1,
dkato 6:aa1fc6a5cc2a 120 &SCUX_FROM_OPCIR_OPC0_1,
dkato 6:aa1fc6a5cc2a 121 &SCUX_FROM_IPCIR_IPC0_1,
dkato 6:aa1fc6a5cc2a 122 &SCUXMIXIR_MIX0_0,
dkato 6:aa1fc6a5cc2a 123 &SCUXMADIR_MIX0_0,
dkato 6:aa1fc6a5cc2a 124 &SCUXMIXBR_MIX0_0,
dkato 6:aa1fc6a5cc2a 125 &SCUXMIXMR_MIX0_0,
dkato 6:aa1fc6a5cc2a 126 &SCUXMVPDR_MIX0_0,
dkato 6:aa1fc6a5cc2a 127 &SCUXMDBBR_MIX0_0,
dkato 6:aa1fc6a5cc2a 128 &SCUXMDBER_MIX0_0,
dkato 6:aa1fc6a5cc2a 129 &SCUXMIXSR_MIX0_0,
dkato 6:aa1fc6a5cc2a 130 &SCUXSWRSR_CIM,
dkato 6:aa1fc6a5cc2a 131 &SCUXDMACR_CIM,
dkato 6:aa1fc6a5cc2a 132 &SCUXDMATD1_CIM,
dkato 6:aa1fc6a5cc2a 133 &SCUXDMATU1_CIM,
dkato 6:aa1fc6a5cc2a 134 &SCUXSSIRSEL_CIM,
dkato 6:aa1fc6a5cc2a 135 &SCUXFDTSEL1_CIM,
dkato 6:aa1fc6a5cc2a 136 &SCUXFUTSEL1_CIM,
dkato 6:aa1fc6a5cc2a 137 &SCUXSSIPMD_CIM,
dkato 6:aa1fc6a5cc2a 138 &SCUXSSICTRL_CIM,
dkato 6:aa1fc6a5cc2a 139 &SCUXSRCRSEL1_CIM,
dkato 6:aa1fc6a5cc2a 140 &SCUXMIXRSEL_CIM
dkato 6:aa1fc6a5cc2a 141 },
dkato 6:aa1fc6a5cc2a 142 {
dkato 6:aa1fc6a5cc2a 143 &SCUX_FROM_DVUIR_DVU0_2,
dkato 6:aa1fc6a5cc2a 144 &SCUX_FROM_SRCIR0_2SRC0_1,
dkato 6:aa1fc6a5cc2a 145 &SCUX_FROM_FFUIR_FFU0_2,
dkato 6:aa1fc6a5cc2a 146 &SCUX_FROM_FFDIR_FFD0_2,
dkato 6:aa1fc6a5cc2a 147 &SCUX_FROM_OPCIR_OPC0_2,
dkato 6:aa1fc6a5cc2a 148 &SCUX_FROM_IPCIR_IPC0_2,
dkato 6:aa1fc6a5cc2a 149 &SCUXMIXIR_MIX0_0,
dkato 6:aa1fc6a5cc2a 150 &SCUXMADIR_MIX0_0,
dkato 6:aa1fc6a5cc2a 151 &SCUXMIXBR_MIX0_0,
dkato 6:aa1fc6a5cc2a 152 &SCUXMIXMR_MIX0_0,
dkato 6:aa1fc6a5cc2a 153 &SCUXMVPDR_MIX0_0,
dkato 6:aa1fc6a5cc2a 154 &SCUXMDBCR_MIX0_0,
dkato 6:aa1fc6a5cc2a 155 &SCUXMDBER_MIX0_0,
dkato 6:aa1fc6a5cc2a 156 &SCUXMIXSR_MIX0_0,
dkato 6:aa1fc6a5cc2a 157 &SCUXSWRSR_CIM,
dkato 6:aa1fc6a5cc2a 158 &SCUXDMACR_CIM,
dkato 6:aa1fc6a5cc2a 159 &SCUXDMATD2_CIM,
dkato 6:aa1fc6a5cc2a 160 &SCUXDMATU2_CIM,
dkato 6:aa1fc6a5cc2a 161 &SCUXSSIRSEL_CIM,
dkato 6:aa1fc6a5cc2a 162 &SCUXFDTSEL2_CIM,
dkato 6:aa1fc6a5cc2a 163 &SCUXFUTSEL2_CIM,
dkato 6:aa1fc6a5cc2a 164 &SCUXSSIPMD_CIM,
dkato 6:aa1fc6a5cc2a 165 &SCUXSSICTRL_CIM,
dkato 6:aa1fc6a5cc2a 166 &SCUXSRCRSEL2_CIM,
dkato 6:aa1fc6a5cc2a 167 &SCUXMIXRSEL_CIM
dkato 6:aa1fc6a5cc2a 168 },
dkato 6:aa1fc6a5cc2a 169 {
dkato 6:aa1fc6a5cc2a 170 &SCUX_FROM_DVUIR_DVU0_3,
dkato 6:aa1fc6a5cc2a 171 &SCUX_FROM_SRCIR0_2SRC0_1,
dkato 6:aa1fc6a5cc2a 172 &SCUX_FROM_FFUIR_FFU0_3,
dkato 6:aa1fc6a5cc2a 173 &SCUX_FROM_FFDIR_FFD0_3,
dkato 6:aa1fc6a5cc2a 174 &SCUX_FROM_OPCIR_OPC0_3,
dkato 6:aa1fc6a5cc2a 175 &SCUX_FROM_IPCIR_IPC0_3,
dkato 6:aa1fc6a5cc2a 176 &SCUXMIXIR_MIX0_0,
dkato 6:aa1fc6a5cc2a 177 &SCUXMADIR_MIX0_0,
dkato 6:aa1fc6a5cc2a 178 &SCUXMIXBR_MIX0_0,
dkato 6:aa1fc6a5cc2a 179 &SCUXMIXMR_MIX0_0,
dkato 6:aa1fc6a5cc2a 180 &SCUXMVPDR_MIX0_0,
dkato 6:aa1fc6a5cc2a 181 &SCUXMDBDR_MIX0_0,
dkato 6:aa1fc6a5cc2a 182 &SCUXMDBER_MIX0_0,
dkato 6:aa1fc6a5cc2a 183 &SCUXMIXSR_MIX0_0,
dkato 6:aa1fc6a5cc2a 184 &SCUXSWRSR_CIM,
dkato 6:aa1fc6a5cc2a 185 &SCUXDMACR_CIM,
dkato 6:aa1fc6a5cc2a 186 &SCUXDMATD3_CIM,
dkato 6:aa1fc6a5cc2a 187 &SCUXDMATU3_CIM,
dkato 6:aa1fc6a5cc2a 188 &SCUXSSIRSEL_CIM,
dkato 6:aa1fc6a5cc2a 189 &SCUXFDTSEL3_CIM,
dkato 6:aa1fc6a5cc2a 190 &SCUXFUTSEL3_CIM,
dkato 6:aa1fc6a5cc2a 191 &SCUXSSIPMD_CIM,
dkato 6:aa1fc6a5cc2a 192 &SCUXSSICTRL_CIM,
dkato 6:aa1fc6a5cc2a 193 &SCUXSRCRSEL3_CIM,
dkato 6:aa1fc6a5cc2a 194 &SCUXMIXRSEL_CIM
dkato 6:aa1fc6a5cc2a 195 }
dkato 6:aa1fc6a5cc2a 196 };
dkato 6:aa1fc6a5cc2a 197 /* <-MISRA 11.3, 11.4 11.5 */
dkato 6:aa1fc6a5cc2a 198
dkato 6:aa1fc6a5cc2a 199 /* ->MISRA 11.3 This cast is needed for register access. */
dkato 6:aa1fc6a5cc2a 200 /* address table of register set for each SSIF channel */
dkato 6:aa1fc6a5cc2a 201 static volatile struct st_ssif * const p_scux_ssif_ch_reg_addr[SCUX_SSIF_CH_NUM] =
dkato 6:aa1fc6a5cc2a 202 {
dkato 6:aa1fc6a5cc2a 203 &SSIF0,
dkato 6:aa1fc6a5cc2a 204 &SSIF1,
dkato 6:aa1fc6a5cc2a 205 &SSIF2,
dkato 6:aa1fc6a5cc2a 206 &SSIF3,
dkato 6:aa1fc6a5cc2a 207 &SSIF4,
dkato 6:aa1fc6a5cc2a 208 &SSIF5
dkato 6:aa1fc6a5cc2a 209 };
dkato 6:aa1fc6a5cc2a 210 /* <-MISRA 11.3 */
dkato 6:aa1fc6a5cc2a 211
dkato 6:aa1fc6a5cc2a 212 /* SCUX semaphore table define */
dkato 6:aa1fc6a5cc2a 213 static const osSemaphoreDef_t * const p_semdef_ch_scux_access[SCUX_CH_NUM] =
dkato 6:aa1fc6a5cc2a 214 {
dkato 6:aa1fc6a5cc2a 215 osSemaphore(scux_ch0_access),
dkato 6:aa1fc6a5cc2a 216 osSemaphore(scux_ch1_access),
dkato 6:aa1fc6a5cc2a 217 osSemaphore(scux_ch2_access),
dkato 6:aa1fc6a5cc2a 218 osSemaphore(scux_ch3_access)
dkato 6:aa1fc6a5cc2a 219 };
dkato 6:aa1fc6a5cc2a 220
dkato 6:aa1fc6a5cc2a 221 /* SSIF semaphore table define */
dkato 6:aa1fc6a5cc2a 222 static const osSemaphoreDef_t * const p_semdef_ch_scux_ssif_access[SCUX_SSIF_CH_NUM] =
dkato 6:aa1fc6a5cc2a 223 {
dkato 6:aa1fc6a5cc2a 224 osSemaphore(scux_ssif_ch0_access),
dkato 6:aa1fc6a5cc2a 225 osSemaphore(scux_ssif_ch1_access),
dkato 6:aa1fc6a5cc2a 226 osSemaphore(scux_ssif_ch2_access),
dkato 6:aa1fc6a5cc2a 227 osSemaphore(scux_ssif_ch3_access),
dkato 6:aa1fc6a5cc2a 228 osSemaphore(scux_ssif_ch4_access),
dkato 6:aa1fc6a5cc2a 229 osSemaphore(scux_ssif_ch5_access)
dkato 6:aa1fc6a5cc2a 230 };
dkato 6:aa1fc6a5cc2a 231
dkato 6:aa1fc6a5cc2a 232 /* write DMA resource define */
dkato 6:aa1fc6a5cc2a 233 static const dma_res_select_t gb_dma_res_select_tx[SCUX_CH_NUM] =
dkato 6:aa1fc6a5cc2a 234 {
dkato 6:aa1fc6a5cc2a 235 DMA_RS_SCUTXI0,
dkato 6:aa1fc6a5cc2a 236 DMA_RS_SCUTXI1,
dkato 6:aa1fc6a5cc2a 237 DMA_RS_SCUTXI2,
dkato 6:aa1fc6a5cc2a 238 DMA_RS_SCUTXI3
dkato 6:aa1fc6a5cc2a 239 };
dkato 6:aa1fc6a5cc2a 240
dkato 6:aa1fc6a5cc2a 241 /* read DMA resource define */
dkato 6:aa1fc6a5cc2a 242 static const dma_res_select_t gb_dma_res_select_rx[SCUX_CH_NUM] =
dkato 6:aa1fc6a5cc2a 243 {
dkato 6:aa1fc6a5cc2a 244 DMA_RS_SCURXI0,
dkato 6:aa1fc6a5cc2a 245 DMA_RS_SCURXI1,
dkato 6:aa1fc6a5cc2a 246 DMA_RS_SCURXI2,
dkato 6:aa1fc6a5cc2a 247 DMA_RS_SCURXI3
dkato 6:aa1fc6a5cc2a 248 };
dkato 6:aa1fc6a5cc2a 249
dkato 6:aa1fc6a5cc2a 250 /* write dummy data buffer */
dkato 6:aa1fc6a5cc2a 251 static uint8_t gb_scux_write_dummy_buf[SCUX_DUMMY_BUF_SIZE];
dkato 6:aa1fc6a5cc2a 252
dkato 6:aa1fc6a5cc2a 253 /* read dummy data buffer */
dkato 6:aa1fc6a5cc2a 254 static uint8_t gb_scux_read_dummy_buf[SCUX_DUMMY_BUF_SIZE];
dkato 6:aa1fc6a5cc2a 255
dkato 6:aa1fc6a5cc2a 256 /******************************************************************************
dkato 6:aa1fc6a5cc2a 257 Function prototypes
dkato 6:aa1fc6a5cc2a 258 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 259
dkato 6:aa1fc6a5cc2a 260 static int_t SCUX_CheckSrcParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT]);
dkato 6:aa1fc6a5cc2a 261 static int_t SCUX_CheckDvuParam(const scux_info_ch_t * const p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 262 static int_t SCUX_CheckSsifParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT], const bool_t use_mix_flag);
dkato 6:aa1fc6a5cc2a 263 static int_t SCUX_CheckMixParam(const scux_info_ch_t * const p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 264 #if(1) /* mbed */
dkato 6:aa1fc6a5cc2a 265 static int_t SCUX_CmnUnInitialize(void);
dkato 6:aa1fc6a5cc2a 266 #endif /* end mbed */
dkato 6:aa1fc6a5cc2a 267
dkato 6:aa1fc6a5cc2a 268 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 269 * Function Name: SCUX_GetDrvInstance
dkato 6:aa1fc6a5cc2a 270 * @brief Get pointer of gb_scux_info_drv.
dkato 6:aa1fc6a5cc2a 271 *
dkato 6:aa1fc6a5cc2a 272 * Description:<br>
dkato 6:aa1fc6a5cc2a 273 *
dkato 6:aa1fc6a5cc2a 274 * @param None.
dkato 6:aa1fc6a5cc2a 275 * @retval pointer of gb_scux_info_drv -
dkato 6:aa1fc6a5cc2a 276 * driver instance.
dkato 6:aa1fc6a5cc2a 277 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 278
dkato 6:aa1fc6a5cc2a 279 scux_info_drv_t *SCUX_GetDrvInstance(void)
dkato 6:aa1fc6a5cc2a 280 {
dkato 6:aa1fc6a5cc2a 281
dkato 6:aa1fc6a5cc2a 282 return &gb_scux_info_drv;
dkato 6:aa1fc6a5cc2a 283 }
dkato 6:aa1fc6a5cc2a 284
dkato 6:aa1fc6a5cc2a 285 /******************************************************************************
dkato 6:aa1fc6a5cc2a 286 End of function SCUX_GetDrv_Instance
dkato 6:aa1fc6a5cc2a 287 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 288
dkato 6:aa1fc6a5cc2a 289 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 290 * Function Name: SCUX_GetDrvChInfo
dkato 6:aa1fc6a5cc2a 291 * @brief gb_scux_info_drv.info_ch[channel].
dkato 6:aa1fc6a5cc2a 292 *
dkato 6:aa1fc6a5cc2a 293 * Description:<br>
dkato 6:aa1fc6a5cc2a 294 *
dkato 6:aa1fc6a5cc2a 295 * @param[in] channel information number.
dkato 6:aa1fc6a5cc2a 296 * @retval pointer of gb_scux_info_drv -
dkato 6:aa1fc6a5cc2a 297 * pointer of channel information.
dkato 6:aa1fc6a5cc2a 298 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 299
dkato 6:aa1fc6a5cc2a 300 scux_info_ch_t *SCUX_GetDrvChInfo(const int_t channel)
dkato 6:aa1fc6a5cc2a 301 {
dkato 6:aa1fc6a5cc2a 302
dkato 6:aa1fc6a5cc2a 303 return &gb_scux_info_drv.info_ch[channel];
dkato 6:aa1fc6a5cc2a 304 }
dkato 6:aa1fc6a5cc2a 305
dkato 6:aa1fc6a5cc2a 306 /******************************************************************************
dkato 6:aa1fc6a5cc2a 307 End of function SCUX_GetDrvChInfo
dkato 6:aa1fc6a5cc2a 308 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 309
dkato 6:aa1fc6a5cc2a 310 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 311 * Function Name: SCUX_GetSsifChInfo
dkato 6:aa1fc6a5cc2a 312 * @brief gb_scux_ssif_info.channel.
dkato 6:aa1fc6a5cc2a 313 *
dkato 6:aa1fc6a5cc2a 314 * Description:<br>
dkato 6:aa1fc6a5cc2a 315 *
dkato 6:aa1fc6a5cc2a 316 * @param[in] SSIF channel number.
dkato 6:aa1fc6a5cc2a 317 * @retval pointer of gb_scux_ssif_info -
dkato 6:aa1fc6a5cc2a 318 * pointer of SSIF information.
dkato 6:aa1fc6a5cc2a 319 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 320
dkato 6:aa1fc6a5cc2a 321 scux_ssif_info_t *SCUX_GetSsifChInfo(const int_t channel)
dkato 6:aa1fc6a5cc2a 322 {
dkato 6:aa1fc6a5cc2a 323
dkato 6:aa1fc6a5cc2a 324 return &gb_scux_ssif_info[channel];
dkato 6:aa1fc6a5cc2a 325 }
dkato 6:aa1fc6a5cc2a 326
dkato 6:aa1fc6a5cc2a 327 /******************************************************************************
dkato 6:aa1fc6a5cc2a 328 End of function SCUX_GetSsifChInfo
dkato 6:aa1fc6a5cc2a 329 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 330
dkato 6:aa1fc6a5cc2a 331 #if(1) /* mbed */
dkato 6:aa1fc6a5cc2a 332 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 333 * Function Name: SCUX_InitializeOne
dkato 6:aa1fc6a5cc2a 334 * @brief Init SCUX driver.
dkato 6:aa1fc6a5cc2a 335 *
dkato 6:aa1fc6a5cc2a 336 * Description:<br>
dkato 6:aa1fc6a5cc2a 337 *
dkato 6:aa1fc6a5cc2a 338 * @param[in] channel :initialize channel number.
dkato 6:aa1fc6a5cc2a 339 * @param[in] p_scux_init_param :Initialize parameter for SCUX.
dkato 6:aa1fc6a5cc2a 340 * @retval ESUCCESS -
dkato 6:aa1fc6a5cc2a 341 * Operation successful.
dkato 6:aa1fc6a5cc2a 342 * EERROR -
dkato 6:aa1fc6a5cc2a 343 * Error occured.
dkato 6:aa1fc6a5cc2a 344 * error code -
dkato 6:aa1fc6a5cc2a 345 * ENOMEM : Making semaphore is failed.
dkato 6:aa1fc6a5cc2a 346 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 347 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 348 int_t SCUX_InitializeOne(const int_t channel, const scux_channel_cfg_t * const p_scux_init_param)
dkato 6:aa1fc6a5cc2a 349 {
dkato 6:aa1fc6a5cc2a 350 int_t retval = ESUCCESS;
dkato 6:aa1fc6a5cc2a 351 osStatus sem_ercd;
dkato 6:aa1fc6a5cc2a 352 int_t scux_ch_count;
dkato 6:aa1fc6a5cc2a 353 int_t audio_ch_count;
dkato 6:aa1fc6a5cc2a 354 scux_ssif_ch_num_t ssif_ch_count;
dkato 6:aa1fc6a5cc2a 355 uint32_t cpg_value;
dkato 6:aa1fc6a5cc2a 356 bool_t init_shared_flag = false;
dkato 6:aa1fc6a5cc2a 357 int_t was_masked;
dkato 6:aa1fc6a5cc2a 358 volatile uint8_t dummy_buf;
dkato 6:aa1fc6a5cc2a 359 uint32_t scux_init_count;
dkato 6:aa1fc6a5cc2a 360 int_t uninit_ercd;
dkato 6:aa1fc6a5cc2a 361 bool_t init_start_flag = false;
dkato 6:aa1fc6a5cc2a 362 bool_t uninit_all_flag = false;
dkato 6:aa1fc6a5cc2a 363 uint32_t i;
dkato 6:aa1fc6a5cc2a 364
dkato 6:aa1fc6a5cc2a 365 if (NULL == p_scux_init_param)
dkato 6:aa1fc6a5cc2a 366 {
dkato 6:aa1fc6a5cc2a 367 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 368 }
dkato 6:aa1fc6a5cc2a 369 else if (false == p_scux_init_param->enabled)
dkato 6:aa1fc6a5cc2a 370 {
dkato 6:aa1fc6a5cc2a 371 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 372 }
dkato 6:aa1fc6a5cc2a 373 else
dkato 6:aa1fc6a5cc2a 374 {
dkato 6:aa1fc6a5cc2a 375 /* init channel management information */
dkato 6:aa1fc6a5cc2a 376 scux_ch_count = channel;
dkato 6:aa1fc6a5cc2a 377
dkato 6:aa1fc6a5cc2a 378 for (i = 0; ((i < INIT_WAIT_NUM) && (false == init_start_flag)); i++)
dkato 6:aa1fc6a5cc2a 379 {
dkato 6:aa1fc6a5cc2a 380 was_masked = __disable_irq();
dkato 6:aa1fc6a5cc2a 381
dkato 6:aa1fc6a5cc2a 382 if (SCUX_DRV_INIT == gb_scux_info_drv.drv_stat)
dkato 6:aa1fc6a5cc2a 383 {
dkato 6:aa1fc6a5cc2a 384 /* already scux driver shared information is initialized */
dkato 6:aa1fc6a5cc2a 385 init_shared_flag = true;
dkato 6:aa1fc6a5cc2a 386
dkato 6:aa1fc6a5cc2a 387 /* enable the channel */
dkato 6:aa1fc6a5cc2a 388 gb_scux_info_drv.info_ch[scux_ch_count].enabled = true;
dkato 6:aa1fc6a5cc2a 389
dkato 6:aa1fc6a5cc2a 390 init_start_flag = true;
dkato 6:aa1fc6a5cc2a 391 }
dkato 6:aa1fc6a5cc2a 392 else if (SCUX_DRV_UNINIT == gb_scux_info_drv.drv_stat)
dkato 6:aa1fc6a5cc2a 393 {
dkato 6:aa1fc6a5cc2a 394 /* change the status to scux initialization running */
dkato 6:aa1fc6a5cc2a 395 gb_scux_info_drv.drv_stat = SCUX_DRV_INIT_RUNNING;
dkato 6:aa1fc6a5cc2a 396
dkato 6:aa1fc6a5cc2a 397 for (scux_init_count = SCUX_CH_0; scux_init_count < SCUX_CH_NUM; scux_init_count++)
dkato 6:aa1fc6a5cc2a 398 {
dkato 6:aa1fc6a5cc2a 399 gb_scux_info_drv.info_ch[scux_init_count].enabled = false;
dkato 6:aa1fc6a5cc2a 400 gb_scux_info_drv.info_ch[scux_init_count].ch_stat = SCUX_CH_UNINIT;
dkato 6:aa1fc6a5cc2a 401
dkato 6:aa1fc6a5cc2a 402 gb_scux_info_drv.info_ch[scux_init_count].sem_ch_scux_access = NULL;
dkato 6:aa1fc6a5cc2a 403 }
dkato 6:aa1fc6a5cc2a 404
dkato 6:aa1fc6a5cc2a 405 for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
dkato 6:aa1fc6a5cc2a 406 {
dkato 6:aa1fc6a5cc2a 407 gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = NULL;
dkato 6:aa1fc6a5cc2a 408 }
dkato 6:aa1fc6a5cc2a 409
dkato 6:aa1fc6a5cc2a 410 gb_scux_info_drv.shared_info.sem_shared_access = NULL;
dkato 6:aa1fc6a5cc2a 411
dkato 6:aa1fc6a5cc2a 412 /* enable the channel */
dkato 6:aa1fc6a5cc2a 413 gb_scux_info_drv.info_ch[scux_ch_count].enabled = true;
dkato 6:aa1fc6a5cc2a 414
dkato 6:aa1fc6a5cc2a 415 init_start_flag = true;
dkato 6:aa1fc6a5cc2a 416 }
dkato 6:aa1fc6a5cc2a 417 else
dkato 6:aa1fc6a5cc2a 418 {
dkato 6:aa1fc6a5cc2a 419 /* do nothing : SCUX_DRV_INIT_RUNNING */
dkato 6:aa1fc6a5cc2a 420 }
dkato 6:aa1fc6a5cc2a 421
dkato 6:aa1fc6a5cc2a 422 if (0 == was_masked)
dkato 6:aa1fc6a5cc2a 423 {
dkato 6:aa1fc6a5cc2a 424 __enable_irq();
dkato 6:aa1fc6a5cc2a 425 }
dkato 6:aa1fc6a5cc2a 426
dkato 6:aa1fc6a5cc2a 427 if (false == init_start_flag)
dkato 6:aa1fc6a5cc2a 428 {
dkato 6:aa1fc6a5cc2a 429 /* wait for the change of drv_stat to SCUX_DRV_INIT */
dkato 6:aa1fc6a5cc2a 430 (void)osDelay(INIT_WAIT_TIME_MSEC);
dkato 6:aa1fc6a5cc2a 431 }
dkato 6:aa1fc6a5cc2a 432 }
dkato 6:aa1fc6a5cc2a 433
dkato 6:aa1fc6a5cc2a 434 if (false == init_start_flag)
dkato 6:aa1fc6a5cc2a 435 {
dkato 6:aa1fc6a5cc2a 436 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 437 }
dkato 6:aa1fc6a5cc2a 438 else
dkato 6:aa1fc6a5cc2a 439 {
dkato 6:aa1fc6a5cc2a 440 {
dkato 6:aa1fc6a5cc2a 441
dkato 6:aa1fc6a5cc2a 442 /* copy parameter */
dkato 6:aa1fc6a5cc2a 443 /* set interrupt parameter */
dkato 6:aa1fc6a5cc2a 444 gb_scux_info_drv.info_ch[scux_ch_count].int_level = p_scux_init_param->int_level;
dkato 6:aa1fc6a5cc2a 445
dkato 6:aa1fc6a5cc2a 446 /* set route parameter */
dkato 6:aa1fc6a5cc2a 447 gb_scux_info_drv.info_ch[scux_ch_count].route_set = p_scux_init_param->route;
dkato 6:aa1fc6a5cc2a 448
dkato 6:aa1fc6a5cc2a 449 /* set SRC paramter */
dkato 6:aa1fc6a5cc2a 450 SCUX_IoctlSetSrcCfg(scux_ch_count, &p_scux_init_param->src_cfg);
dkato 6:aa1fc6a5cc2a 451
dkato 6:aa1fc6a5cc2a 452 /* init SCUX parameter */
dkato 6:aa1fc6a5cc2a 453 if ((SCUX_CH_0 == scux_ch_count) || (SCUX_CH_1 == scux_ch_count))
dkato 6:aa1fc6a5cc2a 454 {
dkato 6:aa1fc6a5cc2a 455 gb_scux_info_drv.info_ch[scux_ch_count].fifo_size = SCUX_FIFO_SIZE_CH0_1;
dkato 6:aa1fc6a5cc2a 456 }
dkato 6:aa1fc6a5cc2a 457 else
dkato 6:aa1fc6a5cc2a 458 {
dkato 6:aa1fc6a5cc2a 459 gb_scux_info_drv.info_ch[scux_ch_count].fifo_size = SCUX_FIFO_SIZE_CH2_3;
dkato 6:aa1fc6a5cc2a 460 }
dkato 6:aa1fc6a5cc2a 461 gb_scux_info_drv.info_ch[scux_ch_count].dma_resource_tx = gb_dma_res_select_tx[scux_ch_count];
dkato 6:aa1fc6a5cc2a 462 gb_scux_info_drv.info_ch[scux_ch_count].dma_resource_rx = gb_dma_res_select_rx[scux_ch_count];
dkato 6:aa1fc6a5cc2a 463 gb_scux_info_drv.info_ch[scux_ch_count].futsel_cim_value = FUTSEL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 464 gb_scux_info_drv.info_ch[scux_ch_count].err_stat_backup = ESUCCESS;
dkato 6:aa1fc6a5cc2a 465
dkato 6:aa1fc6a5cc2a 466 /* init DVU parameter */
dkato 6:aa1fc6a5cc2a 467 for (audio_ch_count = SCUX_AUDIO_CH_0; audio_ch_count < SCUX_AUDIO_CH_MAX; audio_ch_count++)
dkato 6:aa1fc6a5cc2a 468 {
dkato 6:aa1fc6a5cc2a 469 gb_scux_info_drv.info_ch[scux_ch_count].dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch_count] = false;
dkato 6:aa1fc6a5cc2a 470 }
dkato 6:aa1fc6a5cc2a 471 gb_scux_info_drv.info_ch[scux_ch_count].dvu_setup = false;
dkato 6:aa1fc6a5cc2a 472
dkato 6:aa1fc6a5cc2a 473 if (false == init_shared_flag)
dkato 6:aa1fc6a5cc2a 474 {
dkato 6:aa1fc6a5cc2a 475 /* init MIX parameter */
dkato 6:aa1fc6a5cc2a 476 gb_scux_info_drv.shared_info.mix_setup = false;
dkato 6:aa1fc6a5cc2a 477 gb_scux_info_drv.shared_info.mix_run_ch = 0U;
dkato 6:aa1fc6a5cc2a 478 gb_scux_info_drv.shared_info.mix_ssif_ch = 0U;
dkato 6:aa1fc6a5cc2a 479
dkato 6:aa1fc6a5cc2a 480 /* init SSIF parameter */
dkato 6:aa1fc6a5cc2a 481 for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
dkato 6:aa1fc6a5cc2a 482 {
dkato 6:aa1fc6a5cc2a 483 gb_scux_ssif_info[ssif_ch_count].ssif_setup = false;
dkato 6:aa1fc6a5cc2a 484 gb_scux_ssif_info[ssif_ch_count].ssif_cfg.ssif_ch_num = ssif_ch_count;
dkato 6:aa1fc6a5cc2a 485 gb_scux_ssif_info[ssif_ch_count].scux_channel = 0;
dkato 6:aa1fc6a5cc2a 486 gb_scux_ssif_info[ssif_ch_count].pin_mode = SCUX_PIN_MODE_INDEPEND;
dkato 6:aa1fc6a5cc2a 487 }
dkato 6:aa1fc6a5cc2a 488
dkato 6:aa1fc6a5cc2a 489 /* init regsiter store value */
dkato 6:aa1fc6a5cc2a 490 gb_scux_info_drv.shared_info.ssictrl_cim_value = SSICTRL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 491 }
dkato 6:aa1fc6a5cc2a 492
dkato 6:aa1fc6a5cc2a 493 /* set register address */
dkato 6:aa1fc6a5cc2a 494 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg = &p_scux_ch_reg_addr_table[scux_ch_count];
dkato 6:aa1fc6a5cc2a 495
dkato 6:aa1fc6a5cc2a 496 if (false == init_shared_flag) {
dkato 6:aa1fc6a5cc2a 497 #if defined (__ICCARM__)
dkato 6:aa1fc6a5cc2a 498 was_masked = __disable_irq_iar();
dkato 6:aa1fc6a5cc2a 499 #else
dkato 6:aa1fc6a5cc2a 500 was_masked = __disable_irq();
dkato 6:aa1fc6a5cc2a 501 #endif
dkato 6:aa1fc6a5cc2a 502
dkato 6:aa1fc6a5cc2a 503 /* supply clock for SCUX */
dkato 6:aa1fc6a5cc2a 504 cpg_value = (uint32_t)CPG.STBCR8 & ~(CPG_STBCR8_BIT_MSTP81);
dkato 6:aa1fc6a5cc2a 505 CPG.STBCR8 = (uint8_t)cpg_value;
dkato 6:aa1fc6a5cc2a 506 dummy_buf = CPG.STBCR8;
dkato 6:aa1fc6a5cc2a 507
dkato 6:aa1fc6a5cc2a 508 if (0 == was_masked)
dkato 6:aa1fc6a5cc2a 509 {
dkato 6:aa1fc6a5cc2a 510 __enable_irq();
dkato 6:aa1fc6a5cc2a 511 }
dkato 6:aa1fc6a5cc2a 512
dkato 6:aa1fc6a5cc2a 513 /* software reset */
dkato 6:aa1fc6a5cc2a 514 SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
dkato 6:aa1fc6a5cc2a 515 SCUX.SWRSR_CIM |= SWRSR_CIM_SWRST_SET;
dkato 6:aa1fc6a5cc2a 516 }
dkato 6:aa1fc6a5cc2a 517
dkato 6:aa1fc6a5cc2a 518 /* init DVU register */
dkato 6:aa1fc6a5cc2a 519 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 = DVUIR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 520 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = VADIR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 521 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 = DVUBR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 522 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 = DVUCR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 523 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 = ZCMCR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 524 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = VRCTR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 525 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = VRPDR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 526 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = VRDBR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 527 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = VRWTR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 528 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL0R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 529 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL1R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 530 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL2R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 531 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL3R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 532 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL4R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 533 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL5R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 534 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL6R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 535 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL7R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 536 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUER_DVU0_0 = DVUER_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 537 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = VEVMR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 538 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VEVCR_DVU0_0 = VEVCR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 539
dkato 6:aa1fc6a5cc2a 540 /* init SRC register */
dkato 6:aa1fc6a5cc2a 541 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 542 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SADIR0_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 543 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 544 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSCR0_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 545 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSVR0_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 546 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCCR0_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
dkato 6:aa1fc6a5cc2a 547 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->MNFSR0_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 548 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->BFSSR0_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 549 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 550 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 551 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR0_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 552 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 553 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SADIR1_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 554 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 555 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSCR1_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 556 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSVR1_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 557 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCCR1_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
dkato 6:aa1fc6a5cc2a 558 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->MNFSR1_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 559 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->BFSSR1_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 560 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 561 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 562 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 563 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 564 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 = SRCIRR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 565
dkato 6:aa1fc6a5cc2a 566 /* init FFU register */
dkato 6:aa1fc6a5cc2a 567 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 = FFUIR_FFU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 568 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FUAIR_FFU0_0 = FUAIR_FFU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 569 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->URQSR_FFU0_0 = URQSR_FFU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 570 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 571 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 = UEVMR_FFU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 572 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = UEVCR_FFU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 573
dkato 6:aa1fc6a5cc2a 574 /* init FFD register */
dkato 6:aa1fc6a5cc2a 575 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 = FFDIR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 576 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FDAIR_FFD0_0 = FDAIR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 577 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DRQSR_FFD0_0 = DRQSR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 578 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 579 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 = FFDBR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 580 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = DEVMR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 581 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 582
dkato 6:aa1fc6a5cc2a 583 /* init OPC register */
dkato 6:aa1fc6a5cc2a 584 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_opc_reg->OPCIR_OPC0_0 = OPCIR_OPC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 585 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 586
dkato 6:aa1fc6a5cc2a 587 /* init IPC register */
dkato 6:aa1fc6a5cc2a 588 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 = IPCIR_IPC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 589 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 590
dkato 6:aa1fc6a5cc2a 591 /* init MIX register for each channel */
dkato 6:aa1fc6a5cc2a 592 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mdb_n_r_mix0_0) = MDB_N_R_MIX0_0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 593
dkato 6:aa1fc6a5cc2a 594 /* init CIM register for each channel */
dkato 6:aa1fc6a5cc2a 595 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->fdtsel_n_cim) = FDTSEL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 596 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->futsel_n_cim) = FUTSEL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 597 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->srcrsel_n_cim) = SRCRSEL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 598
dkato 6:aa1fc6a5cc2a 599 /* init shared register */
dkato 6:aa1fc6a5cc2a 600 if (false == init_shared_flag)
dkato 6:aa1fc6a5cc2a 601 {
dkato 6:aa1fc6a5cc2a 602 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixir_mix0_0) = MIXIR_MIX0_0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 603 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->madir_mix0_0) = MADIR_MIX0_0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 604 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixbr_mix0_0) = MIXBR_MIX0_0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 605 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixmr_mix0_0) = MIXMR_MIX0_0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 606 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mvpdr_mix0_0) = MVPDR_MIX0_0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 607 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mdber_mix0_0) = MDBER_MIX0_0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 608 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->dmacr_cim) = DMACR_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 609 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssirsel_cim) = SSIRSEL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 610 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssipmd_cim) = SSIPMD_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 611 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssictrl_cim) = SSICTRL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 612 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixrsel_cim) = MIXRSEL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 613 }
dkato 6:aa1fc6a5cc2a 614
dkato 6:aa1fc6a5cc2a 615 if (false == init_shared_flag)
dkato 6:aa1fc6a5cc2a 616 {
dkato 6:aa1fc6a5cc2a 617 /* set SSIF register */
dkato 6:aa1fc6a5cc2a 618 for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
dkato 6:aa1fc6a5cc2a 619 {
dkato 6:aa1fc6a5cc2a 620 gb_scux_ssif_info[ssif_ch_count].p_scux_ssif_reg = p_scux_ssif_ch_reg_addr[ssif_ch_count];
dkato 6:aa1fc6a5cc2a 621 }
dkato 6:aa1fc6a5cc2a 622 }
dkato 6:aa1fc6a5cc2a 623
dkato 6:aa1fc6a5cc2a 624 /* set semaphore parameter */
dkato 6:aa1fc6a5cc2a 625 gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = osSemaphoreCreate(p_semdef_ch_scux_access[scux_ch_count], 1);
dkato 6:aa1fc6a5cc2a 626 if (NULL == gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
dkato 6:aa1fc6a5cc2a 627 {
dkato 6:aa1fc6a5cc2a 628 retval = ENOMEM;
dkato 6:aa1fc6a5cc2a 629 }
dkato 6:aa1fc6a5cc2a 630 if ((ESUCCESS == retval) && (false == init_shared_flag))
dkato 6:aa1fc6a5cc2a 631 {
dkato 6:aa1fc6a5cc2a 632 for (ssif_ch_count = SCUX_SSIF_CH_0; ((ssif_ch_count < SCUX_SSIF_CH_NUM) && (ESUCCESS == retval)); ssif_ch_count++)
dkato 6:aa1fc6a5cc2a 633 {
dkato 6:aa1fc6a5cc2a 634 gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = osSemaphoreCreate(p_semdef_ch_scux_ssif_access[ssif_ch_count], 1);
dkato 6:aa1fc6a5cc2a 635 if (NULL == gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
dkato 6:aa1fc6a5cc2a 636 {
dkato 6:aa1fc6a5cc2a 637 retval = ENOMEM;
dkato 6:aa1fc6a5cc2a 638 }
dkato 6:aa1fc6a5cc2a 639 }
dkato 6:aa1fc6a5cc2a 640 }
dkato 6:aa1fc6a5cc2a 641 if ((ESUCCESS == retval) && (false == init_shared_flag))
dkato 6:aa1fc6a5cc2a 642 {
dkato 6:aa1fc6a5cc2a 643 gb_scux_info_drv.shared_info.sem_shared_access = osSemaphoreCreate(osSemaphore(scux_shared_access), 1);
dkato 6:aa1fc6a5cc2a 644 if (NULL == gb_scux_info_drv.shared_info.sem_shared_access)
dkato 6:aa1fc6a5cc2a 645 {
dkato 6:aa1fc6a5cc2a 646 retval = ENOMEM;
dkato 6:aa1fc6a5cc2a 647 }
dkato 6:aa1fc6a5cc2a 648 }
dkato 6:aa1fc6a5cc2a 649
dkato 6:aa1fc6a5cc2a 650
dkato 6:aa1fc6a5cc2a 651 gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_INIT;
dkato 6:aa1fc6a5cc2a 652 }
dkato 6:aa1fc6a5cc2a 653
dkato 6:aa1fc6a5cc2a 654 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 655 {
dkato 6:aa1fc6a5cc2a 656 /* uninit each resouces */
dkato 6:aa1fc6a5cc2a 657 gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
dkato 6:aa1fc6a5cc2a 658
dkato 6:aa1fc6a5cc2a 659 if (NULL != gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
dkato 6:aa1fc6a5cc2a 660 {
dkato 6:aa1fc6a5cc2a 661 /* semaphore delete */
dkato 6:aa1fc6a5cc2a 662 sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
dkato 6:aa1fc6a5cc2a 663 /* semaphore error check */
dkato 6:aa1fc6a5cc2a 664 if (osOK != sem_ercd)
dkato 6:aa1fc6a5cc2a 665 {
dkato 6:aa1fc6a5cc2a 666 /* set error return value */
dkato 6:aa1fc6a5cc2a 667 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 668 }
dkato 6:aa1fc6a5cc2a 669
dkato 6:aa1fc6a5cc2a 670 gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = NULL;
dkato 6:aa1fc6a5cc2a 671 }
dkato 6:aa1fc6a5cc2a 672
dkato 6:aa1fc6a5cc2a 673 was_masked = __disable_irq();
dkato 6:aa1fc6a5cc2a 674
dkato 6:aa1fc6a5cc2a 675 gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
dkato 6:aa1fc6a5cc2a 676
dkato 6:aa1fc6a5cc2a 677 for (i = SCUX_CH_0; i < SCUX_CH_NUM; i++)
dkato 6:aa1fc6a5cc2a 678 {
dkato 6:aa1fc6a5cc2a 679 if (false != gb_scux_info_drv.info_ch[i].enabled)
dkato 6:aa1fc6a5cc2a 680 {
dkato 6:aa1fc6a5cc2a 681 break;
dkato 6:aa1fc6a5cc2a 682 }
dkato 6:aa1fc6a5cc2a 683 }
dkato 6:aa1fc6a5cc2a 684
dkato 6:aa1fc6a5cc2a 685 if (SCUX_CH_NUM == i)
dkato 6:aa1fc6a5cc2a 686 {
dkato 6:aa1fc6a5cc2a 687 gb_scux_info_drv.drv_stat = SCUX_DRV_INIT_RUNNING;
dkato 6:aa1fc6a5cc2a 688 uninit_all_flag = true;
dkato 6:aa1fc6a5cc2a 689 }
dkato 6:aa1fc6a5cc2a 690
dkato 6:aa1fc6a5cc2a 691 if (0 == was_masked)
dkato 6:aa1fc6a5cc2a 692 {
dkato 6:aa1fc6a5cc2a 693 __enable_irq();
dkato 6:aa1fc6a5cc2a 694 }
dkato 6:aa1fc6a5cc2a 695
dkato 6:aa1fc6a5cc2a 696 if (false != uninit_all_flag)
dkato 6:aa1fc6a5cc2a 697 {
dkato 6:aa1fc6a5cc2a 698 /* uninitialize driver infomation */
dkato 6:aa1fc6a5cc2a 699 uninit_ercd = SCUX_CmnUnInitialize();
dkato 6:aa1fc6a5cc2a 700 if (ESUCCESS != uninit_ercd)
dkato 6:aa1fc6a5cc2a 701 {
dkato 6:aa1fc6a5cc2a 702 retval = uninit_ercd;
dkato 6:aa1fc6a5cc2a 703 }
dkato 6:aa1fc6a5cc2a 704
dkato 6:aa1fc6a5cc2a 705 gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
dkato 6:aa1fc6a5cc2a 706 }
dkato 6:aa1fc6a5cc2a 707 }
dkato 6:aa1fc6a5cc2a 708 else
dkato 6:aa1fc6a5cc2a 709 {
dkato 6:aa1fc6a5cc2a 710 gb_scux_info_drv.drv_stat = SCUX_DRV_INIT;
dkato 6:aa1fc6a5cc2a 711 }
dkato 6:aa1fc6a5cc2a 712 }
dkato 6:aa1fc6a5cc2a 713 }
dkato 6:aa1fc6a5cc2a 714
dkato 6:aa1fc6a5cc2a 715 return retval;
dkato 6:aa1fc6a5cc2a 716 }
dkato 6:aa1fc6a5cc2a 717
dkato 6:aa1fc6a5cc2a 718 /******************************************************************************
dkato 6:aa1fc6a5cc2a 719 End of function SCUX_InitializeOne
dkato 6:aa1fc6a5cc2a 720 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 721
dkato 6:aa1fc6a5cc2a 722 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 723 * Function Name: SCUX_UnInitializeOne
dkato 6:aa1fc6a5cc2a 724 * @brief Uninit SCUX driver.
dkato 6:aa1fc6a5cc2a 725 *
dkato 6:aa1fc6a5cc2a 726 * Description:<br>
dkato 6:aa1fc6a5cc2a 727 *
dkato 6:aa1fc6a5cc2a 728 * @param[in] channel :unInitialize channel number.
dkato 6:aa1fc6a5cc2a 729 * @retval None.
dkato 6:aa1fc6a5cc2a 730 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 731 void SCUX_UnInitializeOne(const int_t channel)
dkato 6:aa1fc6a5cc2a 732 {
dkato 6:aa1fc6a5cc2a 733 osStatus sem_ercd;
dkato 6:aa1fc6a5cc2a 734 int_t ercd;
dkato 6:aa1fc6a5cc2a 735 int_t scux_ch_count;
dkato 6:aa1fc6a5cc2a 736 int_t ssif_ch_count;
dkato 6:aa1fc6a5cc2a 737 bool_t uninit_all_flag = false;
dkato 6:aa1fc6a5cc2a 738 uint32_t i;
dkato 6:aa1fc6a5cc2a 739 int_t was_masked;
dkato 6:aa1fc6a5cc2a 740
dkato 6:aa1fc6a5cc2a 741 scux_ch_count = channel;
dkato 7:30ebba78fff0 742 if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
dkato 6:aa1fc6a5cc2a 743 {
dkato 7:30ebba78fff0 744 /* check ch_stat whether going transfer */
dkato 7:30ebba78fff0 745 if ((SCUX_CH_UNINIT != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat) &&
dkato 7:30ebba78fff0 746 (SCUX_CH_INIT != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat) &&
dkato 7:30ebba78fff0 747 (SCUX_CH_STOP != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat))
dkato 6:aa1fc6a5cc2a 748 {
dkato 7:30ebba78fff0 749 /* The exclusive access control (interrupt disabled) starts */
dkato 6:aa1fc6a5cc2a 750 #if defined (__ICCARM__)
dkato 7:30ebba78fff0 751 was_masked = __disable_irq_iar();
dkato 6:aa1fc6a5cc2a 752 #else
dkato 7:30ebba78fff0 753 was_masked = __disable_irq();
dkato 6:aa1fc6a5cc2a 754 #endif
dkato 6:aa1fc6a5cc2a 755
dkato 7:30ebba78fff0 756 /* This exclusive access control ends in the SCUX_IoctlClearStop */
dkato 7:30ebba78fff0 757 /* call the __enable_irq in the SCUX_IoctlClearStop */
dkato 7:30ebba78fff0 758 ercd = SCUX_IoctlClearStop(scux_ch_count, was_masked);
dkato 7:30ebba78fff0 759 if (ESUCCESS != ercd)
dkato 7:30ebba78fff0 760 {
dkato 7:30ebba78fff0 761 /* NON_NOTICE_ASSERT: SCUX stop failed */
dkato 7:30ebba78fff0 762 }
dkato 7:30ebba78fff0 763
dkato 7:30ebba78fff0 764 ercd = R_DMA_Free(gb_scux_info_drv.info_ch[scux_ch_count].dma_tx_ch, NULL);
dkato 7:30ebba78fff0 765 if (ESUCCESS != ercd)
dkato 7:30ebba78fff0 766 {
dkato 7:30ebba78fff0 767 /* NON_NOTICE_ASSERT: DMA release failed */
dkato 6:aa1fc6a5cc2a 768 }
dkato 6:aa1fc6a5cc2a 769 }
dkato 6:aa1fc6a5cc2a 770 }
dkato 6:aa1fc6a5cc2a 771
dkato 7:30ebba78fff0 772 if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
dkato 6:aa1fc6a5cc2a 773 {
dkato 7:30ebba78fff0 774 if (gb_scux_info_drv.info_ch[scux_ch_count].ch_stat == SCUX_CH_UNINIT)
dkato 6:aa1fc6a5cc2a 775 {
dkato 7:30ebba78fff0 776 /* NON_NOTICE_ASSERT: abnormal status */
dkato 7:30ebba78fff0 777 }
dkato 7:30ebba78fff0 778
dkato 7:30ebba78fff0 779 /* uninit each resouces */
dkato 7:30ebba78fff0 780 gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
dkato 7:30ebba78fff0 781
dkato 7:30ebba78fff0 782 if (NULL != gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
dkato 7:30ebba78fff0 783 {
dkato 6:aa1fc6a5cc2a 784 /* delete each semaphore */
dkato 6:aa1fc6a5cc2a 785 sem_ercd = osSemaphoreRelease(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
dkato 6:aa1fc6a5cc2a 786 /* semaphore error check */
dkato 6:aa1fc6a5cc2a 787 if (osOK != sem_ercd)
dkato 6:aa1fc6a5cc2a 788 {
dkato 6:aa1fc6a5cc2a 789 /* NON_NOTICE_ASSERT: semaphore error */
dkato 6:aa1fc6a5cc2a 790 }
dkato 7:30ebba78fff0 791
dkato 6:aa1fc6a5cc2a 792 sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
dkato 6:aa1fc6a5cc2a 793 /* semaphore error check */
dkato 6:aa1fc6a5cc2a 794 if (osOK != sem_ercd)
dkato 6:aa1fc6a5cc2a 795 {
dkato 6:aa1fc6a5cc2a 796 /* NON_NOTICE_ASSERT: semaphore error */
dkato 6:aa1fc6a5cc2a 797 }
dkato 7:30ebba78fff0 798
dkato 6:aa1fc6a5cc2a 799 gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = NULL;
dkato 6:aa1fc6a5cc2a 800 }
dkato 7:30ebba78fff0 801
dkato 7:30ebba78fff0 802 /* delete queue */
dkato 7:30ebba78fff0 803 ahf_cancelall(&gb_scux_info_drv.info_ch[scux_ch_count].tx_que);
dkato 7:30ebba78fff0 804 ahf_destroy(&gb_scux_info_drv.info_ch[scux_ch_count].tx_que);
dkato 7:30ebba78fff0 805 ahf_cancelall(&gb_scux_info_drv.info_ch[scux_ch_count].rx_que);
dkato 7:30ebba78fff0 806 ahf_destroy(&gb_scux_info_drv.info_ch[scux_ch_count].rx_que);
dkato 6:aa1fc6a5cc2a 807 }
dkato 6:aa1fc6a5cc2a 808
dkato 6:aa1fc6a5cc2a 809 was_masked = __disable_irq();
dkato 6:aa1fc6a5cc2a 810
dkato 6:aa1fc6a5cc2a 811 gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
dkato 6:aa1fc6a5cc2a 812
dkato 6:aa1fc6a5cc2a 813 for (i = SCUX_CH_0; i < SCUX_CH_NUM; i++)
dkato 6:aa1fc6a5cc2a 814 {
dkato 6:aa1fc6a5cc2a 815 if (false != gb_scux_info_drv.info_ch[i].enabled)
dkato 6:aa1fc6a5cc2a 816 {
dkato 6:aa1fc6a5cc2a 817 break;
dkato 6:aa1fc6a5cc2a 818 }
dkato 6:aa1fc6a5cc2a 819 }
dkato 6:aa1fc6a5cc2a 820
dkato 6:aa1fc6a5cc2a 821 if (SCUX_CH_NUM == i)
dkato 6:aa1fc6a5cc2a 822 {
dkato 6:aa1fc6a5cc2a 823 if (SCUX_DRV_INIT == gb_scux_info_drv.drv_stat)
dkato 6:aa1fc6a5cc2a 824 {
dkato 6:aa1fc6a5cc2a 825 gb_scux_info_drv.drv_stat = SCUX_DRV_INIT_RUNNING;
dkato 6:aa1fc6a5cc2a 826 uninit_all_flag = true;
dkato 6:aa1fc6a5cc2a 827 }
dkato 6:aa1fc6a5cc2a 828 }
dkato 6:aa1fc6a5cc2a 829
dkato 6:aa1fc6a5cc2a 830 if (0 == was_masked)
dkato 6:aa1fc6a5cc2a 831 {
dkato 6:aa1fc6a5cc2a 832 __enable_irq();
dkato 6:aa1fc6a5cc2a 833 }
dkato 6:aa1fc6a5cc2a 834
dkato 6:aa1fc6a5cc2a 835 if (false != uninit_all_flag)
dkato 6:aa1fc6a5cc2a 836 {
dkato 6:aa1fc6a5cc2a 837 for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
dkato 6:aa1fc6a5cc2a 838 {
dkato 6:aa1fc6a5cc2a 839 if (NULL != gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
dkato 6:aa1fc6a5cc2a 840 {
dkato 6:aa1fc6a5cc2a 841 sem_ercd = osSemaphoreRelease(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
dkato 6:aa1fc6a5cc2a 842 /* semaphore error check */
dkato 6:aa1fc6a5cc2a 843 if (osOK != sem_ercd)
dkato 6:aa1fc6a5cc2a 844 {
dkato 6:aa1fc6a5cc2a 845 /* NON_NOTICE_ASSERT: semaphore error */
dkato 6:aa1fc6a5cc2a 846 }
dkato 6:aa1fc6a5cc2a 847 }
dkato 6:aa1fc6a5cc2a 848 }
dkato 6:aa1fc6a5cc2a 849
dkato 6:aa1fc6a5cc2a 850 if (NULL != gb_scux_info_drv.shared_info.sem_shared_access)
dkato 6:aa1fc6a5cc2a 851 {
dkato 6:aa1fc6a5cc2a 852 sem_ercd = osSemaphoreRelease(gb_scux_info_drv.shared_info.sem_shared_access);
dkato 6:aa1fc6a5cc2a 853 /* semaphore error check */
dkato 6:aa1fc6a5cc2a 854 if (osOK != sem_ercd)
dkato 6:aa1fc6a5cc2a 855 {
dkato 6:aa1fc6a5cc2a 856 /* NON_NOTICE_ASSERT: semaphore error */
dkato 6:aa1fc6a5cc2a 857 }
dkato 6:aa1fc6a5cc2a 858 }
dkato 6:aa1fc6a5cc2a 859
dkato 6:aa1fc6a5cc2a 860 /* uninitialize driver infomation */
dkato 6:aa1fc6a5cc2a 861 (void)SCUX_CmnUnInitialize();
dkato 6:aa1fc6a5cc2a 862
dkato 6:aa1fc6a5cc2a 863 gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
dkato 6:aa1fc6a5cc2a 864 }
dkato 7:30ebba78fff0 865 }
dkato 7:30ebba78fff0 866
dkato 7:30ebba78fff0 867 /******************************************************************************
dkato 7:30ebba78fff0 868 End of function SCUX_UnInitializeOne
dkato 7:30ebba78fff0 869 ******************************************************************************/
dkato 7:30ebba78fff0 870 #endif /* end mbed */
dkato 7:30ebba78fff0 871
dkato 7:30ebba78fff0 872 /**************************************************************************//**
dkato 7:30ebba78fff0 873 * Function Name: SCUX_Initialize
dkato 7:30ebba78fff0 874 * @brief Init SCUX driver.
dkato 7:30ebba78fff0 875 *
dkato 7:30ebba78fff0 876 * Description:<br>
dkato 7:30ebba78fff0 877 *
dkato 7:30ebba78fff0 878 * @param[in] p_scux_init_param :Initialize parameter for SCUX.
dkato 7:30ebba78fff0 879 * @retval ESUCCESS -
dkato 7:30ebba78fff0 880 * Operation successful.
dkato 7:30ebba78fff0 881 * EERROR -
dkato 7:30ebba78fff0 882 * Error occured.
dkato 7:30ebba78fff0 883 * error code -
dkato 7:30ebba78fff0 884 * ENOMEM : Making semaphore is failed.
dkato 7:30ebba78fff0 885 * EFAULT : Internal error is occured.
dkato 7:30ebba78fff0 886 ******************************************************************************/
dkato 7:30ebba78fff0 887 int_t SCUX_Initialize(const scux_channel_cfg_t * const p_scux_init_param)
dkato 7:30ebba78fff0 888 {
dkato 7:30ebba78fff0 889 int_t retval = ESUCCESS;
dkato 7:30ebba78fff0 890 osStatus sem_ercd;
dkato 7:30ebba78fff0 891 int_t scux_ch_count;
dkato 7:30ebba78fff0 892 int_t audio_ch_count;
dkato 7:30ebba78fff0 893 scux_ssif_ch_num_t ssif_ch_count;
dkato 7:30ebba78fff0 894 uint32_t cpg_value;
dkato 7:30ebba78fff0 895 bool_t init_shared_flag = false;
dkato 7:30ebba78fff0 896 int_t was_masked;
dkato 7:30ebba78fff0 897 volatile uint8_t dummy_buf;
dkato 7:30ebba78fff0 898
dkato 7:30ebba78fff0 899 if (NULL == p_scux_init_param)
dkato 7:30ebba78fff0 900 {
dkato 7:30ebba78fff0 901 retval = EFAULT;
dkato 7:30ebba78fff0 902 }
dkato 7:30ebba78fff0 903 else
dkato 7:30ebba78fff0 904 {
dkato 7:30ebba78fff0 905 /* init channel management information */
dkato 7:30ebba78fff0 906 for (scux_ch_count = 0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
dkato 7:30ebba78fff0 907 {
dkato 7:30ebba78fff0 908 if (false == p_scux_init_param[scux_ch_count].enabled)
dkato 7:30ebba78fff0 909 {
dkato 7:30ebba78fff0 910 /* set disable parameter */
dkato 7:30ebba78fff0 911 gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
dkato 7:30ebba78fff0 912 gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
dkato 7:30ebba78fff0 913 }
dkato 7:30ebba78fff0 914 else
dkato 7:30ebba78fff0 915 {
dkato 7:30ebba78fff0 916 gb_scux_info_drv.info_ch[scux_ch_count].enabled = true;
dkato 7:30ebba78fff0 917
dkato 7:30ebba78fff0 918 /* copy parameter */
dkato 7:30ebba78fff0 919 /* set interrupt parameter */
dkato 7:30ebba78fff0 920 gb_scux_info_drv.info_ch[scux_ch_count].int_level = p_scux_init_param[scux_ch_count].int_level;
dkato 7:30ebba78fff0 921
dkato 7:30ebba78fff0 922 /* set route parameter */
dkato 7:30ebba78fff0 923 gb_scux_info_drv.info_ch[scux_ch_count].route_set = p_scux_init_param[scux_ch_count].route;
dkato 7:30ebba78fff0 924
dkato 7:30ebba78fff0 925 /* set SRC paramter */
dkato 7:30ebba78fff0 926 SCUX_IoctlSetSrcCfg(scux_ch_count, &p_scux_init_param[scux_ch_count].src_cfg);
dkato 7:30ebba78fff0 927
dkato 7:30ebba78fff0 928 /* init SCUX parameter */
dkato 7:30ebba78fff0 929 if ((SCUX_CH_0 == scux_ch_count) || (SCUX_CH_1 == scux_ch_count))
dkato 7:30ebba78fff0 930 {
dkato 7:30ebba78fff0 931 gb_scux_info_drv.info_ch[scux_ch_count].fifo_size = SCUX_FIFO_SIZE_CH0_1;
dkato 7:30ebba78fff0 932 }
dkato 7:30ebba78fff0 933 else
dkato 7:30ebba78fff0 934 {
dkato 7:30ebba78fff0 935 gb_scux_info_drv.info_ch[scux_ch_count].fifo_size = SCUX_FIFO_SIZE_CH2_3;
dkato 7:30ebba78fff0 936 }
dkato 7:30ebba78fff0 937 gb_scux_info_drv.info_ch[scux_ch_count].dma_resource_tx = gb_dma_res_select_tx[scux_ch_count];
dkato 7:30ebba78fff0 938 gb_scux_info_drv.info_ch[scux_ch_count].dma_resource_rx = gb_dma_res_select_rx[scux_ch_count];
dkato 7:30ebba78fff0 939 gb_scux_info_drv.info_ch[scux_ch_count].futsel_cim_value = FUTSEL_CIM_INIT_VALUE;
dkato 7:30ebba78fff0 940 gb_scux_info_drv.info_ch[scux_ch_count].err_stat_backup = ESUCCESS;
dkato 7:30ebba78fff0 941
dkato 7:30ebba78fff0 942 /* init DVU parameter */
dkato 7:30ebba78fff0 943 for (audio_ch_count = SCUX_AUDIO_CH_0; audio_ch_count < SCUX_AUDIO_CH_MAX; audio_ch_count++)
dkato 7:30ebba78fff0 944 {
dkato 7:30ebba78fff0 945 gb_scux_info_drv.info_ch[scux_ch_count].dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch_count] = false;
dkato 7:30ebba78fff0 946 }
dkato 7:30ebba78fff0 947 gb_scux_info_drv.info_ch[scux_ch_count].dvu_setup = false;
dkato 7:30ebba78fff0 948
dkato 7:30ebba78fff0 949 if (false == init_shared_flag)
dkato 7:30ebba78fff0 950 {
dkato 7:30ebba78fff0 951 /* init MIX parameter */
dkato 7:30ebba78fff0 952 gb_scux_info_drv.shared_info.mix_setup = false;
dkato 7:30ebba78fff0 953 gb_scux_info_drv.shared_info.mix_run_ch = 0U;
dkato 7:30ebba78fff0 954 gb_scux_info_drv.shared_info.mix_ssif_ch = 0U;
dkato 7:30ebba78fff0 955
dkato 7:30ebba78fff0 956 /* init SSIF parameter */
dkato 7:30ebba78fff0 957 for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
dkato 7:30ebba78fff0 958 {
dkato 7:30ebba78fff0 959 gb_scux_ssif_info[ssif_ch_count].ssif_setup = false;
dkato 7:30ebba78fff0 960 gb_scux_ssif_info[ssif_ch_count].ssif_cfg.ssif_ch_num = ssif_ch_count;
dkato 7:30ebba78fff0 961 gb_scux_ssif_info[ssif_ch_count].scux_channel = 0;
dkato 7:30ebba78fff0 962 gb_scux_ssif_info[ssif_ch_count].pin_mode = SCUX_PIN_MODE_INDEPEND;
dkato 7:30ebba78fff0 963 }
dkato 7:30ebba78fff0 964
dkato 7:30ebba78fff0 965 /* init regsiter store value */
dkato 7:30ebba78fff0 966 gb_scux_info_drv.shared_info.ssictrl_cim_value = SSICTRL_CIM_INIT_VALUE;
dkato 7:30ebba78fff0 967 }
dkato 7:30ebba78fff0 968
dkato 7:30ebba78fff0 969 /* set register address */
dkato 7:30ebba78fff0 970 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg = &p_scux_ch_reg_addr_table[scux_ch_count];
dkato 7:30ebba78fff0 971
dkato 7:30ebba78fff0 972 if (false == init_shared_flag) {
dkato 7:30ebba78fff0 973 #if defined (__ICCARM__)
dkato 7:30ebba78fff0 974 was_masked = __disable_irq_iar();
dkato 7:30ebba78fff0 975 #else
dkato 7:30ebba78fff0 976 was_masked = __disable_irq();
dkato 7:30ebba78fff0 977 #endif
dkato 7:30ebba78fff0 978
dkato 7:30ebba78fff0 979 /* supply clock for SCUX */
dkato 7:30ebba78fff0 980 cpg_value = (uint32_t)CPG.STBCR8 & ~(CPG_STBCR8_BIT_MSTP81);
dkato 7:30ebba78fff0 981 CPG.STBCR8 = (uint8_t)cpg_value;
dkato 7:30ebba78fff0 982 dummy_buf = CPG.STBCR8;
dkato 7:30ebba78fff0 983
dkato 7:30ebba78fff0 984 if (0 == was_masked)
dkato 7:30ebba78fff0 985 {
dkato 7:30ebba78fff0 986 __enable_irq();
dkato 7:30ebba78fff0 987 }
dkato 7:30ebba78fff0 988
dkato 7:30ebba78fff0 989 /* software reset */
dkato 7:30ebba78fff0 990 SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
dkato 7:30ebba78fff0 991 SCUX.SWRSR_CIM |= SWRSR_CIM_SWRST_SET;
dkato 7:30ebba78fff0 992 }
dkato 7:30ebba78fff0 993
dkato 7:30ebba78fff0 994 /* init DVU register */
dkato 7:30ebba78fff0 995 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 = DVUIR_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 996 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = VADIR_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 997 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 = DVUBR_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 998 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 = DVUCR_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 999 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 = ZCMCR_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1000 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = VRCTR_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1001 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = VRPDR_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1002 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = VRDBR_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1003 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = VRWTR_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1004 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL0R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1005 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL1R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1006 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL2R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1007 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL3R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1008 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL4R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1009 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL5R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1010 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL6R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1011 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL7R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1012 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUER_DVU0_0 = DVUER_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1013 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = VEVMR_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1014 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VEVCR_DVU0_0 = VEVCR_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1015
dkato 7:30ebba78fff0 1016 /* init SRC register */
dkato 7:30ebba78fff0 1017 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1018 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SADIR0_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1019 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1020 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSCR0_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1021 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSVR0_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1022 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCCR0_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
dkato 7:30ebba78fff0 1023 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->MNFSR0_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1024 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->BFSSR0_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1025 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1026 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1027 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR0_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1028 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1029 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SADIR1_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1030 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1031 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSCR1_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1032 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSVR1_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1033 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCCR1_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
dkato 7:30ebba78fff0 1034 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->MNFSR1_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1035 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->BFSSR1_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1036 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1037 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1038 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1039 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1040 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 = SRCIRR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1041
dkato 7:30ebba78fff0 1042 /* init FFU register */
dkato 7:30ebba78fff0 1043 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 = FFUIR_FFU0_INIT_VALUE;
dkato 7:30ebba78fff0 1044 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FUAIR_FFU0_0 = FUAIR_FFU0_INIT_VALUE;
dkato 7:30ebba78fff0 1045 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->URQSR_FFU0_0 = URQSR_FFU0_INIT_VALUE;
dkato 7:30ebba78fff0 1046 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_INIT_VALUE;
dkato 7:30ebba78fff0 1047 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 = UEVMR_FFU0_INIT_VALUE;
dkato 7:30ebba78fff0 1048 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = UEVCR_FFU0_INIT_VALUE;
dkato 7:30ebba78fff0 1049
dkato 7:30ebba78fff0 1050 /* init FFD register */
dkato 7:30ebba78fff0 1051 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 = FFDIR_FFD0_INIT_VALUE;
dkato 7:30ebba78fff0 1052 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FDAIR_FFD0_0 = FDAIR_FFD0_INIT_VALUE;
dkato 7:30ebba78fff0 1053 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DRQSR_FFD0_0 = DRQSR_FFD0_INIT_VALUE;
dkato 7:30ebba78fff0 1054 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_INIT_VALUE;
dkato 7:30ebba78fff0 1055 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 = FFDBR_FFD0_INIT_VALUE;
dkato 7:30ebba78fff0 1056 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = DEVMR_FFD0_INIT_VALUE;
dkato 7:30ebba78fff0 1057 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
dkato 7:30ebba78fff0 1058
dkato 7:30ebba78fff0 1059 /* init OPC register */
dkato 7:30ebba78fff0 1060 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_opc_reg->OPCIR_OPC0_0 = OPCIR_OPC0_INIT_VALUE;
dkato 7:30ebba78fff0 1061 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC0_INIT_VALUE;
dkato 7:30ebba78fff0 1062
dkato 7:30ebba78fff0 1063 /* init IPC register */
dkato 7:30ebba78fff0 1064 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 = IPCIR_IPC0_INIT_VALUE;
dkato 7:30ebba78fff0 1065 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC0_INIT_VALUE;
dkato 7:30ebba78fff0 1066
dkato 7:30ebba78fff0 1067 /* init MIX register for each channel */
dkato 7:30ebba78fff0 1068 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mdb_n_r_mix0_0) = MDB_N_R_MIX0_0_INIT_VALUE;
dkato 7:30ebba78fff0 1069
dkato 7:30ebba78fff0 1070 /* init CIM register for each channel */
dkato 7:30ebba78fff0 1071 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->fdtsel_n_cim) = FDTSEL_CIM_INIT_VALUE;
dkato 7:30ebba78fff0 1072 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->futsel_n_cim) = FUTSEL_CIM_INIT_VALUE;
dkato 7:30ebba78fff0 1073 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->srcrsel_n_cim) = SRCRSEL_CIM_INIT_VALUE;
dkato 7:30ebba78fff0 1074
dkato 7:30ebba78fff0 1075 /* init shared register */
dkato 7:30ebba78fff0 1076 if (false == init_shared_flag)
dkato 7:30ebba78fff0 1077 {
dkato 7:30ebba78fff0 1078 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixir_mix0_0) = MIXIR_MIX0_0_INIT_VALUE;
dkato 7:30ebba78fff0 1079 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->madir_mix0_0) = MADIR_MIX0_0_INIT_VALUE;
dkato 7:30ebba78fff0 1080 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixbr_mix0_0) = MIXBR_MIX0_0_INIT_VALUE;
dkato 7:30ebba78fff0 1081 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixmr_mix0_0) = MIXMR_MIX0_0_INIT_VALUE;
dkato 7:30ebba78fff0 1082 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mvpdr_mix0_0) = MVPDR_MIX0_0_INIT_VALUE;
dkato 7:30ebba78fff0 1083 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mdber_mix0_0) = MDBER_MIX0_0_INIT_VALUE;
dkato 7:30ebba78fff0 1084 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->dmacr_cim) = DMACR_CIM_INIT_VALUE;
dkato 7:30ebba78fff0 1085 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssirsel_cim) = SSIRSEL_CIM_INIT_VALUE;
dkato 7:30ebba78fff0 1086 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssipmd_cim) = SSIPMD_CIM_INIT_VALUE;
dkato 7:30ebba78fff0 1087 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssictrl_cim) = SSICTRL_CIM_INIT_VALUE;
dkato 7:30ebba78fff0 1088 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixrsel_cim) = MIXRSEL_CIM_INIT_VALUE;
dkato 7:30ebba78fff0 1089 }
dkato 7:30ebba78fff0 1090
dkato 7:30ebba78fff0 1091 if (false == init_shared_flag)
dkato 7:30ebba78fff0 1092 {
dkato 7:30ebba78fff0 1093 /* set SSIF register */
dkato 7:30ebba78fff0 1094 for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
dkato 7:30ebba78fff0 1095 {
dkato 7:30ebba78fff0 1096 gb_scux_ssif_info[ssif_ch_count].p_scux_ssif_reg = p_scux_ssif_ch_reg_addr[ssif_ch_count];
dkato 7:30ebba78fff0 1097 }
dkato 7:30ebba78fff0 1098 }
dkato 7:30ebba78fff0 1099
dkato 7:30ebba78fff0 1100 /* set semaphore parameter */
dkato 7:30ebba78fff0 1101 gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = osSemaphoreCreate(p_semdef_ch_scux_access[scux_ch_count], 1);
dkato 7:30ebba78fff0 1102 if (NULL == gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
dkato 7:30ebba78fff0 1103 {
dkato 7:30ebba78fff0 1104 retval = ENOMEM;
dkato 7:30ebba78fff0 1105 }
dkato 7:30ebba78fff0 1106 if ((ESUCCESS == retval) && (false == init_shared_flag))
dkato 7:30ebba78fff0 1107 {
dkato 7:30ebba78fff0 1108 for (ssif_ch_count = SCUX_SSIF_CH_0; ((ssif_ch_count < SCUX_SSIF_CH_NUM) && (ESUCCESS == retval)); ssif_ch_count++)
dkato 7:30ebba78fff0 1109 {
dkato 7:30ebba78fff0 1110 gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = osSemaphoreCreate(p_semdef_ch_scux_ssif_access[ssif_ch_count], 1);
dkato 7:30ebba78fff0 1111 if (NULL == gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
dkato 7:30ebba78fff0 1112 {
dkato 7:30ebba78fff0 1113 retval = ENOMEM;
dkato 7:30ebba78fff0 1114 }
dkato 7:30ebba78fff0 1115 }
dkato 7:30ebba78fff0 1116 }
dkato 7:30ebba78fff0 1117 if ((ESUCCESS == retval) && (false == init_shared_flag))
dkato 7:30ebba78fff0 1118 {
dkato 7:30ebba78fff0 1119 gb_scux_info_drv.shared_info.sem_shared_access = osSemaphoreCreate(osSemaphore(scux_shared_access), 1);
dkato 7:30ebba78fff0 1120 if (NULL == gb_scux_info_drv.shared_info.sem_shared_access)
dkato 7:30ebba78fff0 1121 {
dkato 7:30ebba78fff0 1122 retval = ENOMEM;
dkato 7:30ebba78fff0 1123 }
dkato 7:30ebba78fff0 1124 }
dkato 7:30ebba78fff0 1125
dkato 7:30ebba78fff0 1126 if (false == init_shared_flag)
dkato 7:30ebba78fff0 1127 {
dkato 7:30ebba78fff0 1128 init_shared_flag = true;
dkato 7:30ebba78fff0 1129 }
dkato 7:30ebba78fff0 1130
dkato 7:30ebba78fff0 1131 gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_INIT;
dkato 7:30ebba78fff0 1132 }
dkato 7:30ebba78fff0 1133 }
dkato 7:30ebba78fff0 1134 }
dkato 7:30ebba78fff0 1135
dkato 7:30ebba78fff0 1136 if (ESUCCESS != retval)
dkato 7:30ebba78fff0 1137 {
dkato 7:30ebba78fff0 1138 for (scux_ch_count = SCUX_SSIF_CH_0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
dkato 7:30ebba78fff0 1139 {
dkato 7:30ebba78fff0 1140 if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
dkato 7:30ebba78fff0 1141 {
dkato 7:30ebba78fff0 1142 /* semaphore delete */
dkato 7:30ebba78fff0 1143 sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
dkato 7:30ebba78fff0 1144 /* semaphore error check */
dkato 7:30ebba78fff0 1145 if (osOK != sem_ercd)
dkato 7:30ebba78fff0 1146 {
dkato 7:30ebba78fff0 1147 /* set error return value */
dkato 7:30ebba78fff0 1148 retval = EFAULT;
dkato 7:30ebba78fff0 1149 }
dkato 7:30ebba78fff0 1150
dkato 7:30ebba78fff0 1151 gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
dkato 7:30ebba78fff0 1152 gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
dkato 7:30ebba78fff0 1153 }
dkato 7:30ebba78fff0 1154 }
dkato 7:30ebba78fff0 1155
dkato 7:30ebba78fff0 1156 for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
dkato 7:30ebba78fff0 1157 {
dkato 7:30ebba78fff0 1158 sem_ercd = osSemaphoreDelete(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
dkato 7:30ebba78fff0 1159 /* semaphore error check */
dkato 7:30ebba78fff0 1160 if (osOK != sem_ercd)
dkato 7:30ebba78fff0 1161 {
dkato 7:30ebba78fff0 1162 /* set error return value */
dkato 7:30ebba78fff0 1163 retval = EFAULT;
dkato 7:30ebba78fff0 1164 }
dkato 7:30ebba78fff0 1165 }
dkato 7:30ebba78fff0 1166
dkato 7:30ebba78fff0 1167 sem_ercd = osSemaphoreDelete(gb_scux_info_drv.shared_info.sem_shared_access);
dkato 7:30ebba78fff0 1168 /* semaphore error check */
dkato 7:30ebba78fff0 1169 if (osOK != sem_ercd)
dkato 7:30ebba78fff0 1170 {
dkato 7:30ebba78fff0 1171 /* set error return value */
dkato 7:30ebba78fff0 1172 retval = EFAULT;
dkato 7:30ebba78fff0 1173 }
dkato 7:30ebba78fff0 1174
dkato 7:30ebba78fff0 1175 gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
dkato 7:30ebba78fff0 1176 }
dkato 7:30ebba78fff0 1177 else
dkato 7:30ebba78fff0 1178 {
dkato 7:30ebba78fff0 1179 gb_scux_info_drv.drv_stat = SCUX_DRV_INIT;
dkato 7:30ebba78fff0 1180 }
dkato 7:30ebba78fff0 1181
dkato 7:30ebba78fff0 1182 return retval;
dkato 7:30ebba78fff0 1183 }
dkato 7:30ebba78fff0 1184
dkato 7:30ebba78fff0 1185 /******************************************************************************
dkato 7:30ebba78fff0 1186 End of function SCUX_Initialize
dkato 7:30ebba78fff0 1187 ******************************************************************************/
dkato 7:30ebba78fff0 1188
dkato 7:30ebba78fff0 1189 /**************************************************************************//**
dkato 7:30ebba78fff0 1190 * Function Name: SCUX_UnInitialize
dkato 7:30ebba78fff0 1191 * @brief Uninit SCUX driver.
dkato 7:30ebba78fff0 1192 *
dkato 7:30ebba78fff0 1193 * Description:<br>
dkato 7:30ebba78fff0 1194 *
dkato 7:30ebba78fff0 1195 * @param[in] None.
dkato 7:30ebba78fff0 1196 * @retval None.
dkato 7:30ebba78fff0 1197 ******************************************************************************/
dkato 7:30ebba78fff0 1198 void SCUX_UnInitialize(void)
dkato 7:30ebba78fff0 1199 {
dkato 7:30ebba78fff0 1200 osStatus sem_ercd;
dkato 7:30ebba78fff0 1201 int_t ercd;
dkato 7:30ebba78fff0 1202 int_t scux_ch_count;
dkato 7:30ebba78fff0 1203 int_t ssif_ch_count;
dkato 7:30ebba78fff0 1204 uint32_t cpg_value;
dkato 7:30ebba78fff0 1205 int_t was_masked;
dkato 7:30ebba78fff0 1206
dkato 7:30ebba78fff0 1207 for (scux_ch_count = 0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
dkato 7:30ebba78fff0 1208 {
dkato 7:30ebba78fff0 1209 if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
dkato 7:30ebba78fff0 1210 {
dkato 7:30ebba78fff0 1211 /* check ch_stat whether going transfer */
dkato 7:30ebba78fff0 1212 if ((SCUX_CH_UNINIT != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat) &&
dkato 7:30ebba78fff0 1213 (SCUX_CH_INIT != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat) &&
dkato 7:30ebba78fff0 1214 (SCUX_CH_STOP != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat))
dkato 7:30ebba78fff0 1215 {
dkato 7:30ebba78fff0 1216 #if defined (__ICCARM__)
dkato 7:30ebba78fff0 1217 was_masked = __disable_irq_iar();
dkato 7:30ebba78fff0 1218 #else
dkato 7:30ebba78fff0 1219 was_masked = __disable_irq();
dkato 7:30ebba78fff0 1220 #endif
dkato 7:30ebba78fff0 1221
dkato 7:30ebba78fff0 1222 /* This exclusive access control ends in the SCUX_IoctlClearStop */
dkato 7:30ebba78fff0 1223 ercd = SCUX_IoctlClearStop(scux_ch_count, was_masked);
dkato 7:30ebba78fff0 1224 if (ESUCCESS != ercd)
dkato 7:30ebba78fff0 1225 {
dkato 7:30ebba78fff0 1226 /* NON_NOTICE_ASSERT: SCUX stop failed */
dkato 7:30ebba78fff0 1227 }
dkato 7:30ebba78fff0 1228
dkato 7:30ebba78fff0 1229 ercd = R_DMA_Free(gb_scux_info_drv.info_ch[scux_ch_count].dma_tx_ch, NULL);
dkato 7:30ebba78fff0 1230 if (ESUCCESS != ercd)
dkato 7:30ebba78fff0 1231 {
dkato 7:30ebba78fff0 1232 /* NON_NOTICE_ASSERT: DMA release failed */
dkato 7:30ebba78fff0 1233 }
dkato 7:30ebba78fff0 1234 }
dkato 7:30ebba78fff0 1235 }
dkato 7:30ebba78fff0 1236 }
dkato 7:30ebba78fff0 1237
dkato 7:30ebba78fff0 1238 /* software reset */
dkato 7:30ebba78fff0 1239 SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
dkato 7:30ebba78fff0 1240
dkato 7:30ebba78fff0 1241 for (scux_ch_count = 0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
dkato 7:30ebba78fff0 1242 {
dkato 7:30ebba78fff0 1243 if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
dkato 7:30ebba78fff0 1244 {
dkato 7:30ebba78fff0 1245 if (gb_scux_info_drv.info_ch[scux_ch_count].ch_stat == SCUX_CH_UNINIT)
dkato 7:30ebba78fff0 1246 {
dkato 7:30ebba78fff0 1247 /* NON_NOTICE_ASSERT: abnormal status */
dkato 7:30ebba78fff0 1248 }
dkato 7:30ebba78fff0 1249
dkato 7:30ebba78fff0 1250 /* uninit each resouces */
dkato 7:30ebba78fff0 1251 gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
dkato 7:30ebba78fff0 1252
dkato 7:30ebba78fff0 1253 /* delete each semaphore */
dkato 7:30ebba78fff0 1254 sem_ercd = osSemaphoreRelease(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
dkato 7:30ebba78fff0 1255 /* semaphore error check */
dkato 7:30ebba78fff0 1256 if (osOK != sem_ercd)
dkato 7:30ebba78fff0 1257 {
dkato 7:30ebba78fff0 1258 /* NON_NOTICE_ASSERT: semaphore error */
dkato 7:30ebba78fff0 1259 }
dkato 7:30ebba78fff0 1260
dkato 7:30ebba78fff0 1261 sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
dkato 7:30ebba78fff0 1262 /* semaphore error check */
dkato 7:30ebba78fff0 1263 if (osOK != sem_ercd)
dkato 7:30ebba78fff0 1264 {
dkato 7:30ebba78fff0 1265 /* NON_NOTICE_ASSERT: semaphore error */
dkato 7:30ebba78fff0 1266 }
dkato 7:30ebba78fff0 1267
dkato 7:30ebba78fff0 1268 gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = NULL;
dkato 7:30ebba78fff0 1269
dkato 7:30ebba78fff0 1270 /* delete queue */
dkato 7:30ebba78fff0 1271 ahf_cancelall(&gb_scux_info_drv.info_ch[scux_ch_count].tx_que);
dkato 7:30ebba78fff0 1272 ahf_destroy(&gb_scux_info_drv.info_ch[scux_ch_count].tx_que);
dkato 7:30ebba78fff0 1273 ahf_cancelall(&gb_scux_info_drv.info_ch[scux_ch_count].rx_que);
dkato 7:30ebba78fff0 1274 ahf_destroy(&gb_scux_info_drv.info_ch[scux_ch_count].rx_que);
dkato 7:30ebba78fff0 1275 }
dkato 7:30ebba78fff0 1276 }
dkato 7:30ebba78fff0 1277
dkato 6:aa1fc6a5cc2a 1278 for (ssif_ch_count = 0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
dkato 6:aa1fc6a5cc2a 1279 {
dkato 6:aa1fc6a5cc2a 1280 sem_ercd = osSemaphoreRelease(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
dkato 6:aa1fc6a5cc2a 1281 /* semaphore error check */
dkato 6:aa1fc6a5cc2a 1282 if (osOK != sem_ercd)
dkato 6:aa1fc6a5cc2a 1283 {
dkato 6:aa1fc6a5cc2a 1284 /* NON_NOTICE_ASSERT: semaphore error */
dkato 6:aa1fc6a5cc2a 1285 }
dkato 6:aa1fc6a5cc2a 1286
dkato 6:aa1fc6a5cc2a 1287 sem_ercd = osSemaphoreDelete(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
dkato 6:aa1fc6a5cc2a 1288 /* semaphore error check */
dkato 6:aa1fc6a5cc2a 1289 if (osOK != sem_ercd)
dkato 6:aa1fc6a5cc2a 1290 {
dkato 6:aa1fc6a5cc2a 1291 /* NON_NOTICE_ASSERT: semaphore error */
dkato 6:aa1fc6a5cc2a 1292 }
dkato 6:aa1fc6a5cc2a 1293
dkato 6:aa1fc6a5cc2a 1294 gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = NULL;
dkato 6:aa1fc6a5cc2a 1295 }
dkato 6:aa1fc6a5cc2a 1296
dkato 6:aa1fc6a5cc2a 1297 sem_ercd = osSemaphoreRelease(gb_scux_info_drv.shared_info.sem_shared_access);
dkato 6:aa1fc6a5cc2a 1298 /* semaphore error check */
dkato 6:aa1fc6a5cc2a 1299 if (osOK != sem_ercd)
dkato 6:aa1fc6a5cc2a 1300 {
dkato 6:aa1fc6a5cc2a 1301 /* NON_NOTICE_ASSERT: semaphore error */
dkato 6:aa1fc6a5cc2a 1302 }
dkato 6:aa1fc6a5cc2a 1303
dkato 6:aa1fc6a5cc2a 1304 sem_ercd = osSemaphoreDelete(gb_scux_info_drv.shared_info.sem_shared_access);
dkato 6:aa1fc6a5cc2a 1305 /* semaphore error check */
dkato 6:aa1fc6a5cc2a 1306 if (osOK != sem_ercd)
dkato 6:aa1fc6a5cc2a 1307 {
dkato 6:aa1fc6a5cc2a 1308 /* NON_NOTICE_ASSERT: semaphore error */
dkato 6:aa1fc6a5cc2a 1309 }
dkato 6:aa1fc6a5cc2a 1310
dkato 6:aa1fc6a5cc2a 1311 gb_scux_info_drv.shared_info.sem_shared_access = NULL;
dkato 6:aa1fc6a5cc2a 1312
dkato 6:aa1fc6a5cc2a 1313 #if defined (__ICCARM__)
dkato 6:aa1fc6a5cc2a 1314 was_masked = __disable_irq_iar();
dkato 6:aa1fc6a5cc2a 1315 #else
dkato 6:aa1fc6a5cc2a 1316 was_masked = __disable_irq();
dkato 6:aa1fc6a5cc2a 1317 #endif
dkato 6:aa1fc6a5cc2a 1318
dkato 6:aa1fc6a5cc2a 1319 /* stop clock for SCUX */
dkato 6:aa1fc6a5cc2a 1320 cpg_value = ((uint32_t)CPG.STBCR8 | CPG_STBCR8_BIT_MSTP81);
dkato 6:aa1fc6a5cc2a 1321 CPG.STBCR8 = (uint8_t)cpg_value;
dkato 6:aa1fc6a5cc2a 1322
dkato 6:aa1fc6a5cc2a 1323 if (0 == was_masked)
dkato 6:aa1fc6a5cc2a 1324 {
dkato 6:aa1fc6a5cc2a 1325 /* enable all irq */
dkato 6:aa1fc6a5cc2a 1326 __enable_irq();
dkato 6:aa1fc6a5cc2a 1327 }
dkato 6:aa1fc6a5cc2a 1328
dkato 6:aa1fc6a5cc2a 1329 gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
dkato 6:aa1fc6a5cc2a 1330 }
dkato 6:aa1fc6a5cc2a 1331
dkato 6:aa1fc6a5cc2a 1332 /******************************************************************************
dkato 6:aa1fc6a5cc2a 1333 End of function SCUX_UnInitialize
dkato 6:aa1fc6a5cc2a 1334 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 1335
dkato 6:aa1fc6a5cc2a 1336 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 1337 * Function Name: SCUX_OpenChannel
dkato 6:aa1fc6a5cc2a 1338 * @brief Open SCUX driver channel.
dkato 6:aa1fc6a5cc2a 1339 *
dkato 6:aa1fc6a5cc2a 1340 * Description:<br>
dkato 6:aa1fc6a5cc2a 1341 *
dkato 6:aa1fc6a5cc2a 1342 * @param[in] channel:open channel number.
dkato 6:aa1fc6a5cc2a 1343 * @param[in] flags:specifies the access mode whether the channel is
dkato 6:aa1fc6a5cc2a 1344 * opened for a read or a write
dkato 6:aa1fc6a5cc2a 1345 * @retval ESUCCESS: Operation successful.
dkato 6:aa1fc6a5cc2a 1346 * ENOMEM: Create queue is failed.
dkato 6:aa1fc6a5cc2a 1347 * EMFILE: Allocate DMA ch for write is failed.
dkato 6:aa1fc6a5cc2a 1348 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 1349
dkato 6:aa1fc6a5cc2a 1350 int_t SCUX_OpenChannel(const int_t channel, const int_t flags)
dkato 6:aa1fc6a5cc2a 1351 {
dkato 6:aa1fc6a5cc2a 1352 int_t retval;
dkato 6:aa1fc6a5cc2a 1353
dkato 6:aa1fc6a5cc2a 1354 /* create write request queue */
dkato 6:aa1fc6a5cc2a 1355 retval = ahf_create(&gb_scux_info_drv.info_ch[channel].tx_que, AHF_LOCKINT);
dkato 6:aa1fc6a5cc2a 1356 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 1357 {
dkato 6:aa1fc6a5cc2a 1358 retval = ENOMEM;
dkato 6:aa1fc6a5cc2a 1359 }
dkato 6:aa1fc6a5cc2a 1360 else
dkato 6:aa1fc6a5cc2a 1361 {
dkato 6:aa1fc6a5cc2a 1362 /* create read request queue */
dkato 6:aa1fc6a5cc2a 1363 retval = ahf_create(&gb_scux_info_drv.info_ch[channel].rx_que, AHF_LOCKINT);
dkato 6:aa1fc6a5cc2a 1364 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 1365 {
dkato 6:aa1fc6a5cc2a 1366 retval = ENOMEM;
dkato 6:aa1fc6a5cc2a 1367 }
dkato 6:aa1fc6a5cc2a 1368 }
dkato 6:aa1fc6a5cc2a 1369
dkato 6:aa1fc6a5cc2a 1370 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1371 {
dkato 6:aa1fc6a5cc2a 1372 SCUX_InterruptInit(channel);
dkato 6:aa1fc6a5cc2a 1373
dkato 6:aa1fc6a5cc2a 1374 /* init channel information parameter */
dkato 6:aa1fc6a5cc2a 1375 gb_scux_info_drv.info_ch[channel].open_flags = flags;
dkato 6:aa1fc6a5cc2a 1376 gb_scux_info_drv.info_ch[channel].p_tx_aio = NULL;
dkato 6:aa1fc6a5cc2a 1377 gb_scux_info_drv.info_ch[channel].p_tx_next_aio = NULL;
dkato 6:aa1fc6a5cc2a 1378 gb_scux_info_drv.info_ch[channel].p_rx_aio = NULL;
dkato 6:aa1fc6a5cc2a 1379 gb_scux_info_drv.info_ch[channel].p_rx_next_aio = NULL;
dkato 6:aa1fc6a5cc2a 1380 gb_scux_info_drv.info_ch[channel].p_ssif_info1 = NULL;
dkato 6:aa1fc6a5cc2a 1381 gb_scux_info_drv.info_ch[channel].p_ssif_info2 = NULL;
dkato 6:aa1fc6a5cc2a 1382 gb_scux_info_drv.info_ch[channel].p_ssif_info3 = NULL;
dkato 6:aa1fc6a5cc2a 1383 gb_scux_info_drv.info_ch[channel].p_flush_callback = NULL;
dkato 6:aa1fc6a5cc2a 1384 gb_scux_info_drv.info_ch[channel].p_tx_dummy_data = &gb_scux_write_dummy_buf[0];
dkato 6:aa1fc6a5cc2a 1385 gb_scux_info_drv.info_ch[channel].p_rx_dummy_data = &gb_scux_read_dummy_buf[0];
dkato 6:aa1fc6a5cc2a 1386
dkato 6:aa1fc6a5cc2a 1387 /* get DMA channel for write */
dkato 6:aa1fc6a5cc2a 1388 gb_scux_info_drv.info_ch[channel].dma_tx_ch = R_DMA_Alloc(DMA_ALLOC_CH, NULL);
dkato 6:aa1fc6a5cc2a 1389 if (EERROR == gb_scux_info_drv.info_ch[channel].dma_tx_ch)
dkato 6:aa1fc6a5cc2a 1390 {
dkato 6:aa1fc6a5cc2a 1391 retval = EMFILE;
dkato 6:aa1fc6a5cc2a 1392 }
dkato 6:aa1fc6a5cc2a 1393 else
dkato 6:aa1fc6a5cc2a 1394 {
dkato 6:aa1fc6a5cc2a 1395 gb_scux_info_drv.info_ch[channel].ch_stat = SCUX_CH_STOP;
dkato 6:aa1fc6a5cc2a 1396 }
dkato 6:aa1fc6a5cc2a 1397
dkato 6:aa1fc6a5cc2a 1398 }
dkato 6:aa1fc6a5cc2a 1399
dkato 6:aa1fc6a5cc2a 1400 return retval;
dkato 6:aa1fc6a5cc2a 1401 }
dkato 6:aa1fc6a5cc2a 1402
dkato 6:aa1fc6a5cc2a 1403 /******************************************************************************
dkato 6:aa1fc6a5cc2a 1404 End of function SCUX_OpenChannel
dkato 6:aa1fc6a5cc2a 1405 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 1406
dkato 6:aa1fc6a5cc2a 1407 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 1408 * Function Name: SCUX_CloseChannel
dkato 6:aa1fc6a5cc2a 1409 * @brief Close SCUX driver channel.
dkato 6:aa1fc6a5cc2a 1410 *
dkato 6:aa1fc6a5cc2a 1411 * Description:<br>
dkato 6:aa1fc6a5cc2a 1412 *
dkato 6:aa1fc6a5cc2a 1413 * @param[in] channel: SCUX channel number.
dkato 6:aa1fc6a5cc2a 1414 * @retval ESUCCESS : Operation successful.
dkato 6:aa1fc6a5cc2a 1415 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 1416 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 1417
dkato 6:aa1fc6a5cc2a 1418 int_t SCUX_CloseChannel(const int_t channel)
dkato 6:aa1fc6a5cc2a 1419 {
dkato 6:aa1fc6a5cc2a 1420 int_t retval = ESUCCESS;
dkato 6:aa1fc6a5cc2a 1421 int_t ercd;
dkato 6:aa1fc6a5cc2a 1422 int_t was_masked;
dkato 6:aa1fc6a5cc2a 1423
dkato 6:aa1fc6a5cc2a 1424 /* check ch_stat whether going transfer */
dkato 6:aa1fc6a5cc2a 1425 if ((SCUX_CH_UNINIT != gb_scux_info_drv.info_ch[channel].ch_stat) &&
dkato 6:aa1fc6a5cc2a 1426 (SCUX_CH_INIT != gb_scux_info_drv.info_ch[channel].ch_stat) &&
dkato 6:aa1fc6a5cc2a 1427 (SCUX_CH_STOP != gb_scux_info_drv.info_ch[channel].ch_stat))
dkato 6:aa1fc6a5cc2a 1428 {
dkato 6:aa1fc6a5cc2a 1429 #if defined (__ICCARM__)
dkato 6:aa1fc6a5cc2a 1430 was_masked = __disable_irq_iar();
dkato 6:aa1fc6a5cc2a 1431 #else
dkato 6:aa1fc6a5cc2a 1432 was_masked = __disable_irq();
dkato 6:aa1fc6a5cc2a 1433 #endif
dkato 6:aa1fc6a5cc2a 1434
dkato 6:aa1fc6a5cc2a 1435 /* This exclusive access control ends in the SCUX_IoctlClearStop */
dkato 6:aa1fc6a5cc2a 1436 ercd = SCUX_IoctlClearStop(channel, was_masked);
dkato 6:aa1fc6a5cc2a 1437 if (ESUCCESS != ercd)
dkato 6:aa1fc6a5cc2a 1438 {
dkato 6:aa1fc6a5cc2a 1439 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 1440 }
dkato 6:aa1fc6a5cc2a 1441 }
dkato 6:aa1fc6a5cc2a 1442
dkato 6:aa1fc6a5cc2a 1443 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1444 {
dkato 6:aa1fc6a5cc2a 1445 /* delete queue */
dkato 6:aa1fc6a5cc2a 1446 ahf_cancelall(&gb_scux_info_drv.info_ch[channel].tx_que);
dkato 6:aa1fc6a5cc2a 1447 ahf_destroy(&gb_scux_info_drv.info_ch[channel].tx_que);
dkato 6:aa1fc6a5cc2a 1448 ahf_cancelall(&gb_scux_info_drv.info_ch[channel].rx_que);
dkato 6:aa1fc6a5cc2a 1449 ahf_destroy(&gb_scux_info_drv.info_ch[channel].rx_que);
dkato 6:aa1fc6a5cc2a 1450
dkato 6:aa1fc6a5cc2a 1451 SCUX_InterruptUninit(channel);
dkato 6:aa1fc6a5cc2a 1452
dkato 6:aa1fc6a5cc2a 1453 ercd = R_DMA_Free(gb_scux_info_drv.info_ch[channel].dma_tx_ch, NULL);
dkato 6:aa1fc6a5cc2a 1454 if (ESUCCESS != ercd)
dkato 6:aa1fc6a5cc2a 1455 {
dkato 6:aa1fc6a5cc2a 1456 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 1457 }
dkato 6:aa1fc6a5cc2a 1458 else
dkato 6:aa1fc6a5cc2a 1459 {
dkato 6:aa1fc6a5cc2a 1460 /* reset error status */
dkato 6:aa1fc6a5cc2a 1461 gb_scux_info_drv.info_ch[channel].err_stat_backup = ESUCCESS;
dkato 6:aa1fc6a5cc2a 1462 /* set channel status to open */
dkato 6:aa1fc6a5cc2a 1463 gb_scux_info_drv.info_ch[channel].ch_stat = SCUX_CH_INIT;
dkato 6:aa1fc6a5cc2a 1464 }
dkato 6:aa1fc6a5cc2a 1465 }
dkato 6:aa1fc6a5cc2a 1466
dkato 6:aa1fc6a5cc2a 1467 return retval;
dkato 6:aa1fc6a5cc2a 1468 }
dkato 6:aa1fc6a5cc2a 1469
dkato 6:aa1fc6a5cc2a 1470 /******************************************************************************
dkato 6:aa1fc6a5cc2a 1471 End of function SCUX_CloseChannel
dkato 6:aa1fc6a5cc2a 1472 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 1473
dkato 6:aa1fc6a5cc2a 1474
dkato 6:aa1fc6a5cc2a 1475 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 1476 * Function Name: SCUX_CheckParam
dkato 6:aa1fc6a5cc2a 1477 * @brief Check SCUX parameter.
dkato 6:aa1fc6a5cc2a 1478 *
dkato 6:aa1fc6a5cc2a 1479 * Description:<br>
dkato 6:aa1fc6a5cc2a 1480 *
dkato 6:aa1fc6a5cc2a 1481 * @param[in] *p_scux_info_ch:SCUX channel information.
dkato 6:aa1fc6a5cc2a 1482 * @retval ESUCCESS : Parameter is no problems.
dkato 6:aa1fc6a5cc2a 1483 * EACCES : DVU setting isn't performed when DVU is used.
dkato 6:aa1fc6a5cc2a 1484 * EACCES : MIX setting isn't performed when MIX is used.
dkato 6:aa1fc6a5cc2a 1485 * EACCES : SSIF setting isn't performed when SSIF is used.
dkato 6:aa1fc6a5cc2a 1486 * EPERM : Parameter is unexpected value.
dkato 6:aa1fc6a5cc2a 1487 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 1488 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 1489
dkato 6:aa1fc6a5cc2a 1490 int_t SCUX_CheckParam(scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 1491 {
dkato 6:aa1fc6a5cc2a 1492 int_t retval = ESUCCESS;
dkato 6:aa1fc6a5cc2a 1493 uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT] = {SCUX_SSIF_NO_USE_CH, SCUX_SSIF_NO_USE_CH, SCUX_SSIF_NO_USE_CH};
dkato 6:aa1fc6a5cc2a 1494 bool_t use_mix_flag = false;
dkato 6:aa1fc6a5cc2a 1495
dkato 6:aa1fc6a5cc2a 1496 if (NULL == p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 1497 {
dkato 6:aa1fc6a5cc2a 1498 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 1499 }
dkato 6:aa1fc6a5cc2a 1500 else
dkato 6:aa1fc6a5cc2a 1501 {
dkato 6:aa1fc6a5cc2a 1502 /* check route parameter */
dkato 6:aa1fc6a5cc2a 1503 if (((SCUX_ROUTE_SRC_MEM_MIN >= p_scux_info_ch->route_set) || (SCUX_ROUTE_SRC_MEM_MAX <= p_scux_info_ch->route_set)) &&
dkato 6:aa1fc6a5cc2a 1504 ((SCUX_ROUTE_SRC_SSIF_MIN >= p_scux_info_ch->route_set) || (SCUX_ROUTE_SRC_SSIF_MAX <= p_scux_info_ch->route_set)) &&
dkato 6:aa1fc6a5cc2a 1505 ((SCUX_ROUTE_SRC_MIX_SSIF_MIN >= p_scux_info_ch->route_set) || (SCUX_ROUTE_SRC_MIX_SSIF_MAX <= p_scux_info_ch->route_set)))
dkato 6:aa1fc6a5cc2a 1506 {
dkato 6:aa1fc6a5cc2a 1507 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1508 }
dkato 6:aa1fc6a5cc2a 1509 else
dkato 6:aa1fc6a5cc2a 1510 {
dkato 6:aa1fc6a5cc2a 1511 /* check route whether include SCUX channel */
dkato 6:aa1fc6a5cc2a 1512 switch (p_scux_info_ch->channel)
dkato 6:aa1fc6a5cc2a 1513 {
dkato 6:aa1fc6a5cc2a 1514 case SCUX_CH_0:
dkato 6:aa1fc6a5cc2a 1515 if ((SCUX_ROUTE_SRC0_MEM != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1516 (SCUX_ROUTE_SRC0_SSIF0 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1517 (SCUX_ROUTE_SRC0_MIX_SSIF0 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1518 (SCUX_ROUTE_SRC0_SSIF3 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1519 (SCUX_ROUTE_SRC0_MIX_SSIF3 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1520 (SCUX_ROUTE_SRC0_SSIF012 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1521 (SCUX_ROUTE_SRC0_MIX_SSIF012 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1522 (SCUX_ROUTE_SRC0_SSIF345 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1523 (SCUX_ROUTE_SRC0_MIX_SSIF345 != p_scux_info_ch->route_set))
dkato 6:aa1fc6a5cc2a 1524 {
dkato 6:aa1fc6a5cc2a 1525 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1526 }
dkato 6:aa1fc6a5cc2a 1527 break;
dkato 6:aa1fc6a5cc2a 1528
dkato 6:aa1fc6a5cc2a 1529 case SCUX_CH_1:
dkato 6:aa1fc6a5cc2a 1530 if ((SCUX_ROUTE_SRC1_MEM != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1531 (SCUX_ROUTE_SRC1_SSIF0 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1532 (SCUX_ROUTE_SRC1_MIX_SSIF0 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1533 (SCUX_ROUTE_SRC1_SSIF3 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1534 (SCUX_ROUTE_SRC1_MIX_SSIF3 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1535 (SCUX_ROUTE_SRC1_SSIF012 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1536 (SCUX_ROUTE_SRC1_MIX_SSIF012 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1537 (SCUX_ROUTE_SRC1_SSIF345 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1538 (SCUX_ROUTE_SRC1_MIX_SSIF345 != p_scux_info_ch->route_set))
dkato 6:aa1fc6a5cc2a 1539 {
dkato 6:aa1fc6a5cc2a 1540 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1541 }
dkato 6:aa1fc6a5cc2a 1542 break;
dkato 6:aa1fc6a5cc2a 1543
dkato 6:aa1fc6a5cc2a 1544 case SCUX_CH_2:
dkato 6:aa1fc6a5cc2a 1545 if ((SCUX_ROUTE_SRC2_MEM != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1546 (SCUX_ROUTE_SRC2_MIX_SSIF0 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1547 (SCUX_ROUTE_SRC2_SSIF1 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1548 (SCUX_ROUTE_SRC2_MIX_SSIF3 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1549 (SCUX_ROUTE_SRC2_SSIF4 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1550 (SCUX_ROUTE_SRC2_MIX_SSIF012 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1551 (SCUX_ROUTE_SRC2_MIX_SSIF345 != p_scux_info_ch->route_set))
dkato 6:aa1fc6a5cc2a 1552 {
dkato 6:aa1fc6a5cc2a 1553 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1554 }
dkato 6:aa1fc6a5cc2a 1555 break;
dkato 6:aa1fc6a5cc2a 1556
dkato 6:aa1fc6a5cc2a 1557 case SCUX_CH_3:
dkato 6:aa1fc6a5cc2a 1558 if ((SCUX_ROUTE_SRC3_MEM != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1559 (SCUX_ROUTE_SRC3_MIX_SSIF0 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1560 (SCUX_ROUTE_SRC3_SSIF2 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1561 (SCUX_ROUTE_SRC3_MIX_SSIF3 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1562 (SCUX_ROUTE_SRC3_SSIF5 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1563 (SCUX_ROUTE_SRC3_MIX_SSIF012 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1564 (SCUX_ROUTE_SRC3_MIX_SSIF345 != p_scux_info_ch->route_set))
dkato 6:aa1fc6a5cc2a 1565 {
dkato 6:aa1fc6a5cc2a 1566 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1567 }
dkato 6:aa1fc6a5cc2a 1568 break;
dkato 6:aa1fc6a5cc2a 1569
dkato 6:aa1fc6a5cc2a 1570 default :
dkato 6:aa1fc6a5cc2a 1571 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 1572 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 1573 break;
dkato 6:aa1fc6a5cc2a 1574
dkato 6:aa1fc6a5cc2a 1575 }
dkato 6:aa1fc6a5cc2a 1576 }
dkato 6:aa1fc6a5cc2a 1577
dkato 6:aa1fc6a5cc2a 1578 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1579 {
dkato 6:aa1fc6a5cc2a 1580 /* set using SSIF channel and MIX information */
dkato 6:aa1fc6a5cc2a 1581 switch (p_scux_info_ch->route_set)
dkato 6:aa1fc6a5cc2a 1582 {
dkato 6:aa1fc6a5cc2a 1583 case SCUX_ROUTE_SRC0_MEM :
dkato 6:aa1fc6a5cc2a 1584 /* fall through */
dkato 6:aa1fc6a5cc2a 1585 case SCUX_ROUTE_SRC1_MEM :
dkato 6:aa1fc6a5cc2a 1586 /* fall through */
dkato 6:aa1fc6a5cc2a 1587 case SCUX_ROUTE_SRC2_MEM :
dkato 6:aa1fc6a5cc2a 1588 /* fall through */
dkato 6:aa1fc6a5cc2a 1589 case SCUX_ROUTE_SRC3_MEM :
dkato 6:aa1fc6a5cc2a 1590 /* do nothing, when mem to mem route is setting */
dkato 6:aa1fc6a5cc2a 1591 break;
dkato 6:aa1fc6a5cc2a 1592
dkato 6:aa1fc6a5cc2a 1593 case SCUX_ROUTE_SRC0_SSIF0 :
dkato 6:aa1fc6a5cc2a 1594 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
dkato 6:aa1fc6a5cc2a 1595 break;
dkato 6:aa1fc6a5cc2a 1596
dkato 6:aa1fc6a5cc2a 1597 case SCUX_ROUTE_SRC0_SSIF012 :
dkato 6:aa1fc6a5cc2a 1598 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
dkato 6:aa1fc6a5cc2a 1599 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_1;
dkato 6:aa1fc6a5cc2a 1600 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_2;
dkato 6:aa1fc6a5cc2a 1601 break;
dkato 6:aa1fc6a5cc2a 1602
dkato 6:aa1fc6a5cc2a 1603 case SCUX_ROUTE_SRC0_SSIF3 :
dkato 6:aa1fc6a5cc2a 1604 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
dkato 6:aa1fc6a5cc2a 1605 break;
dkato 6:aa1fc6a5cc2a 1606
dkato 6:aa1fc6a5cc2a 1607 case SCUX_ROUTE_SRC0_SSIF345 :
dkato 6:aa1fc6a5cc2a 1608 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
dkato 6:aa1fc6a5cc2a 1609 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_4;
dkato 6:aa1fc6a5cc2a 1610 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_5;
dkato 6:aa1fc6a5cc2a 1611 break;
dkato 6:aa1fc6a5cc2a 1612
dkato 6:aa1fc6a5cc2a 1613 case SCUX_ROUTE_SRC1_SSIF0 :
dkato 6:aa1fc6a5cc2a 1614 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
dkato 6:aa1fc6a5cc2a 1615 break;
dkato 6:aa1fc6a5cc2a 1616
dkato 6:aa1fc6a5cc2a 1617 case SCUX_ROUTE_SRC1_SSIF012 :
dkato 6:aa1fc6a5cc2a 1618 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
dkato 6:aa1fc6a5cc2a 1619 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_1;
dkato 6:aa1fc6a5cc2a 1620 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_2;
dkato 6:aa1fc6a5cc2a 1621 break;
dkato 6:aa1fc6a5cc2a 1622
dkato 6:aa1fc6a5cc2a 1623 case SCUX_ROUTE_SRC1_SSIF3 :
dkato 6:aa1fc6a5cc2a 1624 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
dkato 6:aa1fc6a5cc2a 1625 break;
dkato 6:aa1fc6a5cc2a 1626
dkato 6:aa1fc6a5cc2a 1627 case SCUX_ROUTE_SRC1_SSIF345 :
dkato 6:aa1fc6a5cc2a 1628 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
dkato 6:aa1fc6a5cc2a 1629 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_4;
dkato 6:aa1fc6a5cc2a 1630 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_5;
dkato 6:aa1fc6a5cc2a 1631 break;
dkato 6:aa1fc6a5cc2a 1632
dkato 6:aa1fc6a5cc2a 1633 case SCUX_ROUTE_SRC2_SSIF1 :
dkato 6:aa1fc6a5cc2a 1634 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_1;
dkato 6:aa1fc6a5cc2a 1635 break;
dkato 6:aa1fc6a5cc2a 1636
dkato 6:aa1fc6a5cc2a 1637 case SCUX_ROUTE_SRC2_SSIF4 :
dkato 6:aa1fc6a5cc2a 1638 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_4;
dkato 6:aa1fc6a5cc2a 1639 break;
dkato 6:aa1fc6a5cc2a 1640
dkato 6:aa1fc6a5cc2a 1641 case SCUX_ROUTE_SRC3_SSIF2 :
dkato 6:aa1fc6a5cc2a 1642 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_2;
dkato 6:aa1fc6a5cc2a 1643 break;
dkato 6:aa1fc6a5cc2a 1644
dkato 6:aa1fc6a5cc2a 1645 case SCUX_ROUTE_SRC3_SSIF5 :
dkato 6:aa1fc6a5cc2a 1646 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_5;
dkato 6:aa1fc6a5cc2a 1647 break;
dkato 6:aa1fc6a5cc2a 1648
dkato 6:aa1fc6a5cc2a 1649 case SCUX_ROUTE_SRC0_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 1650 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
dkato 6:aa1fc6a5cc2a 1651 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1652 break;
dkato 6:aa1fc6a5cc2a 1653
dkato 6:aa1fc6a5cc2a 1654 case SCUX_ROUTE_SRC0_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 1655 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
dkato 6:aa1fc6a5cc2a 1656 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
dkato 6:aa1fc6a5cc2a 1657 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
dkato 6:aa1fc6a5cc2a 1658 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1659 break;
dkato 6:aa1fc6a5cc2a 1660
dkato 6:aa1fc6a5cc2a 1661 case SCUX_ROUTE_SRC0_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 1662 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
dkato 6:aa1fc6a5cc2a 1663 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1664 break;
dkato 6:aa1fc6a5cc2a 1665
dkato 6:aa1fc6a5cc2a 1666 case SCUX_ROUTE_SRC0_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 1667 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
dkato 6:aa1fc6a5cc2a 1668 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
dkato 6:aa1fc6a5cc2a 1669 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
dkato 6:aa1fc6a5cc2a 1670 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1671 break;
dkato 6:aa1fc6a5cc2a 1672
dkato 6:aa1fc6a5cc2a 1673 case SCUX_ROUTE_SRC1_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 1674 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
dkato 6:aa1fc6a5cc2a 1675 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1676 break;
dkato 6:aa1fc6a5cc2a 1677
dkato 6:aa1fc6a5cc2a 1678 case SCUX_ROUTE_SRC1_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 1679 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
dkato 6:aa1fc6a5cc2a 1680 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
dkato 6:aa1fc6a5cc2a 1681 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
dkato 6:aa1fc6a5cc2a 1682 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1683 break;
dkato 6:aa1fc6a5cc2a 1684
dkato 6:aa1fc6a5cc2a 1685 case SCUX_ROUTE_SRC1_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 1686 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
dkato 6:aa1fc6a5cc2a 1687 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1688 break;
dkato 6:aa1fc6a5cc2a 1689
dkato 6:aa1fc6a5cc2a 1690 case SCUX_ROUTE_SRC1_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 1691 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
dkato 6:aa1fc6a5cc2a 1692 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
dkato 6:aa1fc6a5cc2a 1693 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
dkato 6:aa1fc6a5cc2a 1694 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1695 break;
dkato 6:aa1fc6a5cc2a 1696
dkato 6:aa1fc6a5cc2a 1697 case SCUX_ROUTE_SRC2_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 1698 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
dkato 6:aa1fc6a5cc2a 1699 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1700 break;
dkato 6:aa1fc6a5cc2a 1701
dkato 6:aa1fc6a5cc2a 1702 case SCUX_ROUTE_SRC2_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 1703 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
dkato 6:aa1fc6a5cc2a 1704 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
dkato 6:aa1fc6a5cc2a 1705 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
dkato 6:aa1fc6a5cc2a 1706 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1707 break;
dkato 6:aa1fc6a5cc2a 1708
dkato 6:aa1fc6a5cc2a 1709 case SCUX_ROUTE_SRC2_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 1710 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
dkato 6:aa1fc6a5cc2a 1711 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1712 break;
dkato 6:aa1fc6a5cc2a 1713
dkato 6:aa1fc6a5cc2a 1714 case SCUX_ROUTE_SRC2_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 1715 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
dkato 6:aa1fc6a5cc2a 1716 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
dkato 6:aa1fc6a5cc2a 1717 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
dkato 6:aa1fc6a5cc2a 1718 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1719 break;
dkato 6:aa1fc6a5cc2a 1720
dkato 6:aa1fc6a5cc2a 1721 case SCUX_ROUTE_SRC3_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 1722 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
dkato 6:aa1fc6a5cc2a 1723 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1724 break;
dkato 6:aa1fc6a5cc2a 1725
dkato 6:aa1fc6a5cc2a 1726 case SCUX_ROUTE_SRC3_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 1727 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
dkato 6:aa1fc6a5cc2a 1728 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
dkato 6:aa1fc6a5cc2a 1729 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
dkato 6:aa1fc6a5cc2a 1730 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1731 break;
dkato 6:aa1fc6a5cc2a 1732
dkato 6:aa1fc6a5cc2a 1733 case SCUX_ROUTE_SRC3_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 1734 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
dkato 6:aa1fc6a5cc2a 1735 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1736 break;
dkato 6:aa1fc6a5cc2a 1737
dkato 6:aa1fc6a5cc2a 1738 case SCUX_ROUTE_SRC3_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 1739 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
dkato 6:aa1fc6a5cc2a 1740 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
dkato 6:aa1fc6a5cc2a 1741 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
dkato 6:aa1fc6a5cc2a 1742 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1743 break;
dkato 6:aa1fc6a5cc2a 1744
dkato 6:aa1fc6a5cc2a 1745 default :
dkato 6:aa1fc6a5cc2a 1746 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 1747 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1748 break;
dkato 6:aa1fc6a5cc2a 1749 }
dkato 6:aa1fc6a5cc2a 1750 }
dkato 6:aa1fc6a5cc2a 1751
dkato 6:aa1fc6a5cc2a 1752 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1753 {
dkato 6:aa1fc6a5cc2a 1754 if (false != p_scux_info_ch->src_cfg.src_enable)
dkato 6:aa1fc6a5cc2a 1755 {
dkato 6:aa1fc6a5cc2a 1756 retval = SCUX_CheckSrcParam(p_scux_info_ch, ssif_ch);
dkato 6:aa1fc6a5cc2a 1757 }
dkato 6:aa1fc6a5cc2a 1758 else
dkato 6:aa1fc6a5cc2a 1759 {
dkato 6:aa1fc6a5cc2a 1760 if (false != p_scux_info_ch->src_cfg.mode_sync)
dkato 6:aa1fc6a5cc2a 1761 {
dkato 6:aa1fc6a5cc2a 1762 /* src disable is async mode only */
dkato 6:aa1fc6a5cc2a 1763 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1764 }
dkato 6:aa1fc6a5cc2a 1765 }
dkato 6:aa1fc6a5cc2a 1766 }
dkato 6:aa1fc6a5cc2a 1767
dkato 6:aa1fc6a5cc2a 1768 if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1])
dkato 6:aa1fc6a5cc2a 1769 {
dkato 6:aa1fc6a5cc2a 1770 /* check parameter for SSIF direct route */
dkato 6:aa1fc6a5cc2a 1771 if ((ESUCCESS == retval) && (false != p_scux_info_ch->dvu_cfg.dvu_enable))
dkato 6:aa1fc6a5cc2a 1772 {
dkato 6:aa1fc6a5cc2a 1773 retval = SCUX_CheckDvuParam(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 1774 }
dkato 6:aa1fc6a5cc2a 1775
dkato 6:aa1fc6a5cc2a 1776 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1777 {
dkato 6:aa1fc6a5cc2a 1778 retval = SCUX_CheckSsifParam(p_scux_info_ch, ssif_ch, use_mix_flag);
dkato 6:aa1fc6a5cc2a 1779 }
dkato 6:aa1fc6a5cc2a 1780
dkato 6:aa1fc6a5cc2a 1781 if ((ESUCCESS == retval) && (false != use_mix_flag))
dkato 6:aa1fc6a5cc2a 1782 {
dkato 6:aa1fc6a5cc2a 1783 retval = SCUX_CheckMixParam(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 1784 }
dkato 6:aa1fc6a5cc2a 1785 }
dkato 6:aa1fc6a5cc2a 1786 }
dkato 6:aa1fc6a5cc2a 1787
dkato 6:aa1fc6a5cc2a 1788 return retval;
dkato 6:aa1fc6a5cc2a 1789 }
dkato 6:aa1fc6a5cc2a 1790
dkato 6:aa1fc6a5cc2a 1791 /******************************************************************************
dkato 6:aa1fc6a5cc2a 1792 End of function SCUX_CheckParam
dkato 6:aa1fc6a5cc2a 1793 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 1794
dkato 6:aa1fc6a5cc2a 1795 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 1796 * Function Name: SCUX_CheckSrcParam
dkato 6:aa1fc6a5cc2a 1797 * @brief Check SRC parameter and set rate parameter to SCUX information.
dkato 6:aa1fc6a5cc2a 1798 *
dkato 6:aa1fc6a5cc2a 1799 * Description:<br>
dkato 6:aa1fc6a5cc2a 1800 *
dkato 6:aa1fc6a5cc2a 1801 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 1802 * @param[in] ssif_ch : Used ssif channel number.
dkato 6:aa1fc6a5cc2a 1803 * @param[in] use_mix_flag : Flag of Using MIX .
dkato 6:aa1fc6a5cc2a 1804 * @retval ESUCCESS : Parameter is no problems.
dkato 6:aa1fc6a5cc2a 1805 * EPERM : Parameter is unexpected value.
dkato 6:aa1fc6a5cc2a 1806 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 1807 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 1808
dkato 6:aa1fc6a5cc2a 1809 static int_t SCUX_CheckSrcParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT])
dkato 6:aa1fc6a5cc2a 1810 {
dkato 6:aa1fc6a5cc2a 1811 int_t retval = ESUCCESS;
dkato 6:aa1fc6a5cc2a 1812 uint32_t ssif_arrange_num;
dkato 6:aa1fc6a5cc2a 1813 uint32_t rate_sample_ratio;
dkato 6:aa1fc6a5cc2a 1814 uint32_t max_conv_rate;
dkato 6:aa1fc6a5cc2a 1815 uint32_t min_conv_rate = 0;
dkato 6:aa1fc6a5cc2a 1816 uint32_t freq_value = 0;
dkato 6:aa1fc6a5cc2a 1817 int_t audio_ch;
dkato 6:aa1fc6a5cc2a 1818 uint32_t max_rate;
dkato 6:aa1fc6a5cc2a 1819
dkato 6:aa1fc6a5cc2a 1820 if ((NULL == p_scux_info_ch) || (NULL == ssif_ch))
dkato 6:aa1fc6a5cc2a 1821 {
dkato 6:aa1fc6a5cc2a 1822 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 1823 }
dkato 6:aa1fc6a5cc2a 1824 else
dkato 6:aa1fc6a5cc2a 1825 {
dkato 6:aa1fc6a5cc2a 1826 /* check use ch */
dkato 6:aa1fc6a5cc2a 1827 if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_1 == p_scux_info_ch->channel))
dkato 6:aa1fc6a5cc2a 1828 {
dkato 6:aa1fc6a5cc2a 1829 if ((SCUX_USE_CH_1 != p_scux_info_ch->src_cfg.use_ch) &&
dkato 6:aa1fc6a5cc2a 1830 (SCUX_USE_CH_2 != p_scux_info_ch->src_cfg.use_ch) &&
dkato 6:aa1fc6a5cc2a 1831 (SCUX_USE_CH_4 != p_scux_info_ch->src_cfg.use_ch) &&
dkato 6:aa1fc6a5cc2a 1832 (SCUX_USE_CH_6 != p_scux_info_ch->src_cfg.use_ch) &&
dkato 6:aa1fc6a5cc2a 1833 (SCUX_USE_CH_8 != p_scux_info_ch->src_cfg.use_ch))
dkato 6:aa1fc6a5cc2a 1834 {
dkato 6:aa1fc6a5cc2a 1835 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1836 }
dkato 6:aa1fc6a5cc2a 1837 }
dkato 6:aa1fc6a5cc2a 1838 else
dkato 6:aa1fc6a5cc2a 1839 {
dkato 6:aa1fc6a5cc2a 1840 /* on SCUX2, SCUX3, enable audio channel is only 1ch and 2ch */
dkato 6:aa1fc6a5cc2a 1841 if ((SCUX_USE_CH_1 != p_scux_info_ch->src_cfg.use_ch) && (SCUX_USE_CH_2 != p_scux_info_ch->src_cfg.use_ch))
dkato 6:aa1fc6a5cc2a 1842 {
dkato 6:aa1fc6a5cc2a 1843 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1844 }
dkato 6:aa1fc6a5cc2a 1845 }
dkato 6:aa1fc6a5cc2a 1846
dkato 6:aa1fc6a5cc2a 1847 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1848 {
dkato 6:aa1fc6a5cc2a 1849 /* if using SSIF, 1ch audio channel is disabled */
dkato 6:aa1fc6a5cc2a 1850 if ((SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]) && (SCUX_USE_CH_1 == p_scux_info_ch->src_cfg.use_ch))
dkato 6:aa1fc6a5cc2a 1851 {
dkato 6:aa1fc6a5cc2a 1852 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1853 }
dkato 6:aa1fc6a5cc2a 1854 }
dkato 6:aa1fc6a5cc2a 1855
dkato 6:aa1fc6a5cc2a 1856 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1857 {
dkato 6:aa1fc6a5cc2a 1858 /* if mutiple SSIF channel and enable TDM mode, only 2ch audio channel is enabled */
dkato 6:aa1fc6a5cc2a 1859 for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
dkato 6:aa1fc6a5cc2a 1860 {
dkato 6:aa1fc6a5cc2a 1861 if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
dkato 6:aa1fc6a5cc2a 1862 {
dkato 6:aa1fc6a5cc2a 1863 if (false != gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.use_tdm)
dkato 6:aa1fc6a5cc2a 1864 {
dkato 6:aa1fc6a5cc2a 1865 if (SCUX_USE_CH_2 == p_scux_info_ch->src_cfg.use_ch)
dkato 6:aa1fc6a5cc2a 1866 {
dkato 6:aa1fc6a5cc2a 1867 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1868 }
dkato 6:aa1fc6a5cc2a 1869 }
dkato 6:aa1fc6a5cc2a 1870 }
dkato 6:aa1fc6a5cc2a 1871 }
dkato 6:aa1fc6a5cc2a 1872 }
dkato 6:aa1fc6a5cc2a 1873
dkato 6:aa1fc6a5cc2a 1874 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1875 {
dkato 6:aa1fc6a5cc2a 1876 /* multiple SSIF ch check (multiple SSIF is used SSIF2) */
dkato 6:aa1fc6a5cc2a 1877 if ((SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]) && (SCUX_USE_CH_6 != p_scux_info_ch->src_cfg.use_ch))
dkato 6:aa1fc6a5cc2a 1878 {
dkato 6:aa1fc6a5cc2a 1879 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1880 }
dkato 6:aa1fc6a5cc2a 1881 }
dkato 6:aa1fc6a5cc2a 1882
dkato 6:aa1fc6a5cc2a 1883 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1884 {
dkato 6:aa1fc6a5cc2a 1885 /* check word length */
dkato 6:aa1fc6a5cc2a 1886 if ((SCUX_DATA_LEN_MIN >= p_scux_info_ch->src_cfg.word_len) || (SCUX_DATA_LEN_MAX <= p_scux_info_ch->src_cfg.word_len))
dkato 6:aa1fc6a5cc2a 1887 {
dkato 6:aa1fc6a5cc2a 1888 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1889 }
dkato 6:aa1fc6a5cc2a 1890 }
dkato 6:aa1fc6a5cc2a 1891
dkato 6:aa1fc6a5cc2a 1892 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1893 {
dkato 6:aa1fc6a5cc2a 1894 /* check delay mode */
dkato 6:aa1fc6a5cc2a 1895 if ((SCUX_DELAY_MIN >= p_scux_info_ch->src_cfg.delay_mode) || (SCUX_DELAY_MAX <= p_scux_info_ch->src_cfg.delay_mode))
dkato 6:aa1fc6a5cc2a 1896 {
dkato 6:aa1fc6a5cc2a 1897 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1898 }
dkato 6:aa1fc6a5cc2a 1899 else
dkato 6:aa1fc6a5cc2a 1900 {
dkato 6:aa1fc6a5cc2a 1901 /* enable audio channel is less than 2ch when delay mode is enabled */
dkato 6:aa1fc6a5cc2a 1902 if ((SCUX_DELAY_NORMAL != p_scux_info_ch->src_cfg.delay_mode) && (SCUX_USE_CH_2 < p_scux_info_ch->src_cfg.use_ch))
dkato 6:aa1fc6a5cc2a 1903 {
dkato 6:aa1fc6a5cc2a 1904 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1905 }
dkato 6:aa1fc6a5cc2a 1906 }
dkato 6:aa1fc6a5cc2a 1907 }
dkato 6:aa1fc6a5cc2a 1908
dkato 6:aa1fc6a5cc2a 1909 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1910 {
dkato 6:aa1fc6a5cc2a 1911 /* check rate setting */
dkato 6:aa1fc6a5cc2a 1912 if (false != p_scux_info_ch->src_cfg.mode_sync)
dkato 6:aa1fc6a5cc2a 1913 {
dkato 6:aa1fc6a5cc2a 1914 /* check input rate */
dkato 6:aa1fc6a5cc2a 1915 if ((SCUX_SYNC_RATE_8 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1916 (SCUX_SYNC_RATE_11_025 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1917 (SCUX_SYNC_RATE_12 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1918 (SCUX_SYNC_RATE_16 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1919 (SCUX_SYNC_RATE_22_05 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1920 (SCUX_SYNC_RATE_24 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1921 (SCUX_SYNC_RATE_32 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1922 (SCUX_SYNC_RATE_44_1 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1923 (SCUX_SYNC_RATE_48 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1924 (SCUX_SYNC_RATE_64 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1925 (SCUX_SYNC_RATE_88_2 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1926 (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.input_rate_sync))
dkato 6:aa1fc6a5cc2a 1927 {
dkato 6:aa1fc6a5cc2a 1928 /* enable rate is less than 66KHz on 6ch */
dkato 6:aa1fc6a5cc2a 1929 if ((SCUX_USE_CH_6 == p_scux_info_ch->src_cfg.use_ch) &&
dkato 6:aa1fc6a5cc2a 1930 ((SCUX_SYNC_RATE_88_2 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1931 (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.input_rate_sync)))
dkato 6:aa1fc6a5cc2a 1932 {
dkato 6:aa1fc6a5cc2a 1933 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1934 }
dkato 6:aa1fc6a5cc2a 1935
dkato 6:aa1fc6a5cc2a 1936 /* enable rate is less than 49KHz on 8ch */
dkato 6:aa1fc6a5cc2a 1937 if ((SCUX_USE_CH_8 == p_scux_info_ch->src_cfg.use_ch) &&
dkato 6:aa1fc6a5cc2a 1938 ((SCUX_SYNC_RATE_64 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1939 (SCUX_SYNC_RATE_88_2 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1940 (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.input_rate_sync)))
dkato 6:aa1fc6a5cc2a 1941 {
dkato 6:aa1fc6a5cc2a 1942 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1943 }
dkato 6:aa1fc6a5cc2a 1944 }
dkato 6:aa1fc6a5cc2a 1945 else
dkato 6:aa1fc6a5cc2a 1946 {
dkato 6:aa1fc6a5cc2a 1947 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1948 }
dkato 6:aa1fc6a5cc2a 1949
dkato 6:aa1fc6a5cc2a 1950 if (ESUCCESS == retval) {
dkato 6:aa1fc6a5cc2a 1951 /* check output rate */
dkato 6:aa1fc6a5cc2a 1952 if ((SCUX_SYNC_RATE_8 == p_scux_info_ch->src_cfg.output_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1953 (SCUX_SYNC_RATE_16 == p_scux_info_ch->src_cfg.output_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1954 (SCUX_SYNC_RATE_24 == p_scux_info_ch->src_cfg.output_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1955 (SCUX_SYNC_RATE_32 == p_scux_info_ch->src_cfg.output_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1956 (SCUX_SYNC_RATE_44_1 == p_scux_info_ch->src_cfg.output_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1957 (SCUX_SYNC_RATE_48 == p_scux_info_ch->src_cfg.output_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1958 (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.output_rate_sync))
dkato 6:aa1fc6a5cc2a 1959 {
dkato 6:aa1fc6a5cc2a 1960 /* enable rate is less than 66KHz on 6ch, enable rate is less than 49KHz on 8ch */
dkato 6:aa1fc6a5cc2a 1961 if ((SCUX_USE_CH_6 <= p_scux_info_ch->src_cfg.use_ch) &&
dkato 6:aa1fc6a5cc2a 1962 (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.output_rate_sync))
dkato 6:aa1fc6a5cc2a 1963 {
dkato 6:aa1fc6a5cc2a 1964 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1965 }
dkato 6:aa1fc6a5cc2a 1966 }
dkato 6:aa1fc6a5cc2a 1967 else
dkato 6:aa1fc6a5cc2a 1968 {
dkato 6:aa1fc6a5cc2a 1969 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1970 }
dkato 6:aa1fc6a5cc2a 1971 }
dkato 6:aa1fc6a5cc2a 1972
dkato 6:aa1fc6a5cc2a 1973 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1974 {
dkato 6:aa1fc6a5cc2a 1975 p_scux_info_ch->input_rate = p_scux_info_ch->src_cfg.input_rate_sync;
dkato 6:aa1fc6a5cc2a 1976 p_scux_info_ch->output_rate = p_scux_info_ch->src_cfg.output_rate_sync;
dkato 6:aa1fc6a5cc2a 1977 }
dkato 6:aa1fc6a5cc2a 1978 }
dkato 6:aa1fc6a5cc2a 1979 else
dkato 6:aa1fc6a5cc2a 1980 {
dkato 6:aa1fc6a5cc2a 1981 /* async mode */
dkato 6:aa1fc6a5cc2a 1982 /* check input rate */
dkato 6:aa1fc6a5cc2a 1983 /* get input source clock */
dkato 6:aa1fc6a5cc2a 1984 switch (p_scux_info_ch->src_cfg.input_clk_async)
dkato 6:aa1fc6a5cc2a 1985 {
dkato 6:aa1fc6a5cc2a 1986 case SCUX_CLK_AUDIO_CLK :
dkato 6:aa1fc6a5cc2a 1987 freq_value = SCUX_AUDIO_CLK;
dkato 6:aa1fc6a5cc2a 1988 break;
dkato 6:aa1fc6a5cc2a 1989
dkato 6:aa1fc6a5cc2a 1990 case SCUX_CLK_AUDIO_X1 :
dkato 6:aa1fc6a5cc2a 1991 freq_value = SCUX_AUDIO_X1;
dkato 6:aa1fc6a5cc2a 1992 break;
dkato 6:aa1fc6a5cc2a 1993
dkato 6:aa1fc6a5cc2a 1994 case SCUX_CLK_MLB_CLK :
dkato 6:aa1fc6a5cc2a 1995 freq_value = SCUX_MLB_CLK;
dkato 6:aa1fc6a5cc2a 1996 break;
dkato 6:aa1fc6a5cc2a 1997
dkato 6:aa1fc6a5cc2a 1998 case SCUX_CLK_USB_X1 :
dkato 6:aa1fc6a5cc2a 1999 freq_value = SCUX_USB_X1;
dkato 6:aa1fc6a5cc2a 2000 break;
dkato 6:aa1fc6a5cc2a 2001
dkato 6:aa1fc6a5cc2a 2002 case SCUX_CLK_CLKP1_2 :
dkato 6:aa1fc6a5cc2a 2003 freq_value = SCUX_CLKLP1_DIV2;
dkato 6:aa1fc6a5cc2a 2004 break;
dkato 6:aa1fc6a5cc2a 2005
dkato 6:aa1fc6a5cc2a 2006 case SCUX_CLK_MTU_TIOC3A :
dkato 6:aa1fc6a5cc2a 2007 freq_value = p_scux_info_ch->src_cfg.freq_tioc3a;
dkato 6:aa1fc6a5cc2a 2008 if (0U == freq_value)
dkato 6:aa1fc6a5cc2a 2009 {
dkato 6:aa1fc6a5cc2a 2010 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2011 }
dkato 6:aa1fc6a5cc2a 2012 break;
dkato 6:aa1fc6a5cc2a 2013
dkato 6:aa1fc6a5cc2a 2014 case SCUX_CLK_MTU_TIOC4A :
dkato 6:aa1fc6a5cc2a 2015 freq_value = p_scux_info_ch->src_cfg.freq_tioc4a;
dkato 6:aa1fc6a5cc2a 2016 if (0U == freq_value)
dkato 6:aa1fc6a5cc2a 2017 {
dkato 6:aa1fc6a5cc2a 2018 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2019 }
dkato 6:aa1fc6a5cc2a 2020 break;
dkato 6:aa1fc6a5cc2a 2021
dkato 6:aa1fc6a5cc2a 2022 case SCUX_CLK_SSIF0_WS :
dkato 6:aa1fc6a5cc2a 2023 /* fall through */
dkato 6:aa1fc6a5cc2a 2024 case SCUX_CLK_SSIF1_WS :
dkato 6:aa1fc6a5cc2a 2025 /* fall through */
dkato 6:aa1fc6a5cc2a 2026 case SCUX_CLK_SSIF2_WS :
dkato 6:aa1fc6a5cc2a 2027 /* fall through */
dkato 6:aa1fc6a5cc2a 2028 case SCUX_CLK_SSIF3_WS :
dkato 6:aa1fc6a5cc2a 2029 /* fall through */
dkato 6:aa1fc6a5cc2a 2030 case SCUX_CLK_SSIF4_WS :
dkato 6:aa1fc6a5cc2a 2031 /* fall through */
dkato 6:aa1fc6a5cc2a 2032 case SCUX_CLK_SSIF5_WS :
dkato 6:aa1fc6a5cc2a 2033 freq_value = p_scux_info_ch->src_cfg.input_ws;
dkato 6:aa1fc6a5cc2a 2034 if (0U == freq_value)
dkato 6:aa1fc6a5cc2a 2035 {
dkato 6:aa1fc6a5cc2a 2036 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2037 }
dkato 6:aa1fc6a5cc2a 2038 break;
dkato 6:aa1fc6a5cc2a 2039
dkato 6:aa1fc6a5cc2a 2040 default :
dkato 6:aa1fc6a5cc2a 2041 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 2042 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2043 break;
dkato 6:aa1fc6a5cc2a 2044 }
dkato 6:aa1fc6a5cc2a 2045
dkato 6:aa1fc6a5cc2a 2046 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2047 {
dkato 6:aa1fc6a5cc2a 2048 /* check devide rate and devide source clock */
dkato 6:aa1fc6a5cc2a 2049 /* check source clock isn't SSIF WS signal */
dkato 6:aa1fc6a5cc2a 2050 if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 2051 (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 2052 (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 2053 (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 2054 (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 2055 (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.input_clk_async))
dkato 6:aa1fc6a5cc2a 2056 {
dkato 6:aa1fc6a5cc2a 2057 if ((0U != (p_scux_info_ch->src_cfg.input_div_async % SCUX_EVEN_VALUE_DIV)) ||
dkato 6:aa1fc6a5cc2a 2058 (SCUX_MAX_DIV_CLK < p_scux_info_ch->src_cfg.input_div_async))
dkato 6:aa1fc6a5cc2a 2059 {
dkato 6:aa1fc6a5cc2a 2060 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2061 }
dkato 6:aa1fc6a5cc2a 2062 else
dkato 6:aa1fc6a5cc2a 2063 {
dkato 6:aa1fc6a5cc2a 2064 if (0U == p_scux_info_ch->src_cfg.input_div_async)
dkato 6:aa1fc6a5cc2a 2065 {
dkato 6:aa1fc6a5cc2a 2066 /* 0 is a same size */
dkato 6:aa1fc6a5cc2a 2067 p_scux_info_ch->input_rate = freq_value;
dkato 6:aa1fc6a5cc2a 2068 }
dkato 6:aa1fc6a5cc2a 2069 else{
dkato 6:aa1fc6a5cc2a 2070 p_scux_info_ch->input_rate = freq_value / p_scux_info_ch->src_cfg.input_div_async;
dkato 6:aa1fc6a5cc2a 2071 }
dkato 6:aa1fc6a5cc2a 2072 }
dkato 6:aa1fc6a5cc2a 2073 }
dkato 6:aa1fc6a5cc2a 2074 else
dkato 6:aa1fc6a5cc2a 2075 {
dkato 6:aa1fc6a5cc2a 2076 p_scux_info_ch->input_rate = freq_value;
dkato 6:aa1fc6a5cc2a 2077 }
dkato 6:aa1fc6a5cc2a 2078
dkato 6:aa1fc6a5cc2a 2079 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2080 {
dkato 6:aa1fc6a5cc2a 2081 /* check input frequency is enable range */
dkato 6:aa1fc6a5cc2a 2082 if (SCUX_USE_CH_6 == p_scux_info_ch->src_cfg.use_ch)
dkato 6:aa1fc6a5cc2a 2083 {
dkato 6:aa1fc6a5cc2a 2084 max_rate = SCUX_MAX_FREQ_CH6;
dkato 6:aa1fc6a5cc2a 2085 }
dkato 6:aa1fc6a5cc2a 2086 else if (SCUX_USE_CH_8 == p_scux_info_ch->src_cfg.use_ch)
dkato 6:aa1fc6a5cc2a 2087 {
dkato 6:aa1fc6a5cc2a 2088 max_rate = SCUX_MAX_FREQ_CH8;
dkato 6:aa1fc6a5cc2a 2089 }
dkato 6:aa1fc6a5cc2a 2090 else
dkato 6:aa1fc6a5cc2a 2091 {
dkato 6:aa1fc6a5cc2a 2092 max_rate = SCUX_MAX_FREQ_CH1_4;
dkato 6:aa1fc6a5cc2a 2093 }
dkato 6:aa1fc6a5cc2a 2094
dkato 6:aa1fc6a5cc2a 2095 if ((SCUX_MIN_FREQ > p_scux_info_ch->input_rate) ||
dkato 6:aa1fc6a5cc2a 2096 (max_rate < p_scux_info_ch->input_rate))
dkato 6:aa1fc6a5cc2a 2097 {
dkato 6:aa1fc6a5cc2a 2098 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2099 }
dkato 6:aa1fc6a5cc2a 2100 }
dkato 6:aa1fc6a5cc2a 2101 }
dkato 6:aa1fc6a5cc2a 2102
dkato 6:aa1fc6a5cc2a 2103 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2104 {
dkato 6:aa1fc6a5cc2a 2105 /* if output route is SSIF direct route ,WS signal frequency is used */
dkato 6:aa1fc6a5cc2a 2106 if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1])
dkato 6:aa1fc6a5cc2a 2107 {
dkato 6:aa1fc6a5cc2a 2108 if ((SCUX_SYNC_RATE_8 == p_scux_info_ch->src_cfg.output_ws) ||
dkato 6:aa1fc6a5cc2a 2109 (SCUX_SYNC_RATE_11_025 == p_scux_info_ch->src_cfg.output_ws) ||
dkato 6:aa1fc6a5cc2a 2110 (SCUX_SYNC_RATE_12 == p_scux_info_ch->src_cfg.output_ws) ||
dkato 6:aa1fc6a5cc2a 2111 (SCUX_SYNC_RATE_16 == p_scux_info_ch->src_cfg.output_ws) ||
dkato 6:aa1fc6a5cc2a 2112 (SCUX_SYNC_RATE_22_05 == p_scux_info_ch->src_cfg.output_ws) ||
dkato 6:aa1fc6a5cc2a 2113 (SCUX_SYNC_RATE_24 == p_scux_info_ch->src_cfg.output_ws) ||
dkato 6:aa1fc6a5cc2a 2114 (SCUX_SYNC_RATE_32 == p_scux_info_ch->src_cfg.output_ws) ||
dkato 6:aa1fc6a5cc2a 2115 (SCUX_SYNC_RATE_44_1 == p_scux_info_ch->src_cfg.output_ws) ||
dkato 6:aa1fc6a5cc2a 2116 (SCUX_SYNC_RATE_48 == p_scux_info_ch->src_cfg.output_ws) ||
dkato 6:aa1fc6a5cc2a 2117 (SCUX_SYNC_RATE_64 == p_scux_info_ch->src_cfg.output_ws) ||
dkato 6:aa1fc6a5cc2a 2118 (SCUX_SYNC_RATE_88_2 == p_scux_info_ch->src_cfg.output_ws) ||
dkato 6:aa1fc6a5cc2a 2119 (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.output_ws))
dkato 6:aa1fc6a5cc2a 2120 {
dkato 6:aa1fc6a5cc2a 2121 p_scux_info_ch->output_rate = p_scux_info_ch->src_cfg.output_ws;
dkato 6:aa1fc6a5cc2a 2122 }
dkato 6:aa1fc6a5cc2a 2123 else
dkato 6:aa1fc6a5cc2a 2124 {
dkato 6:aa1fc6a5cc2a 2125 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2126 }
dkato 6:aa1fc6a5cc2a 2127 }
dkato 6:aa1fc6a5cc2a 2128 else
dkato 6:aa1fc6a5cc2a 2129 {
dkato 6:aa1fc6a5cc2a 2130 /* check output rate (mem to mem)*/
dkato 6:aa1fc6a5cc2a 2131 /* get output source clock */
dkato 6:aa1fc6a5cc2a 2132 switch (p_scux_info_ch->src_cfg.output_clk_async)
dkato 6:aa1fc6a5cc2a 2133 {
dkato 6:aa1fc6a5cc2a 2134 case SCUX_CLK_AUDIO_CLK :
dkato 6:aa1fc6a5cc2a 2135 freq_value = SCUX_AUDIO_CLK;
dkato 6:aa1fc6a5cc2a 2136 break;
dkato 6:aa1fc6a5cc2a 2137
dkato 6:aa1fc6a5cc2a 2138 case SCUX_CLK_AUDIO_X1 :
dkato 6:aa1fc6a5cc2a 2139 freq_value = SCUX_AUDIO_X1;
dkato 6:aa1fc6a5cc2a 2140 break;
dkato 6:aa1fc6a5cc2a 2141
dkato 6:aa1fc6a5cc2a 2142 case SCUX_CLK_MLB_CLK :
dkato 6:aa1fc6a5cc2a 2143 freq_value = SCUX_MLB_CLK;
dkato 6:aa1fc6a5cc2a 2144 break;
dkato 6:aa1fc6a5cc2a 2145
dkato 6:aa1fc6a5cc2a 2146 case SCUX_CLK_USB_X1 :
dkato 6:aa1fc6a5cc2a 2147 freq_value = SCUX_USB_X1;
dkato 6:aa1fc6a5cc2a 2148 break;
dkato 6:aa1fc6a5cc2a 2149
dkato 6:aa1fc6a5cc2a 2150 case SCUX_CLK_CLKP1_2 :
dkato 6:aa1fc6a5cc2a 2151 freq_value = SCUX_CLKLP1_DIV2;
dkato 6:aa1fc6a5cc2a 2152 break;
dkato 6:aa1fc6a5cc2a 2153
dkato 6:aa1fc6a5cc2a 2154 case SCUX_CLK_MTU_TIOC3A :
dkato 6:aa1fc6a5cc2a 2155 freq_value = p_scux_info_ch->src_cfg.freq_tioc3a;
dkato 6:aa1fc6a5cc2a 2156 if (0U == freq_value)
dkato 6:aa1fc6a5cc2a 2157 {
dkato 6:aa1fc6a5cc2a 2158 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2159 }
dkato 6:aa1fc6a5cc2a 2160 break;
dkato 6:aa1fc6a5cc2a 2161
dkato 6:aa1fc6a5cc2a 2162 case SCUX_CLK_MTU_TIOC4A :
dkato 6:aa1fc6a5cc2a 2163 freq_value = p_scux_info_ch->src_cfg.freq_tioc4a;
dkato 6:aa1fc6a5cc2a 2164 if (0U == freq_value)
dkato 6:aa1fc6a5cc2a 2165 {
dkato 6:aa1fc6a5cc2a 2166 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2167 }
dkato 6:aa1fc6a5cc2a 2168 break;
dkato 6:aa1fc6a5cc2a 2169
dkato 6:aa1fc6a5cc2a 2170 case SCUX_CLK_SSIF0_WS :
dkato 6:aa1fc6a5cc2a 2171 /* fall through */
dkato 6:aa1fc6a5cc2a 2172 case SCUX_CLK_SSIF1_WS :
dkato 6:aa1fc6a5cc2a 2173 /* fall through */
dkato 6:aa1fc6a5cc2a 2174 case SCUX_CLK_SSIF2_WS :
dkato 6:aa1fc6a5cc2a 2175 /* fall through */
dkato 6:aa1fc6a5cc2a 2176 case SCUX_CLK_SSIF3_WS :
dkato 6:aa1fc6a5cc2a 2177 /* fall through */
dkato 6:aa1fc6a5cc2a 2178 case SCUX_CLK_SSIF4_WS :
dkato 6:aa1fc6a5cc2a 2179 /* fall through */
dkato 6:aa1fc6a5cc2a 2180 case SCUX_CLK_SSIF5_WS :
dkato 6:aa1fc6a5cc2a 2181 freq_value = p_scux_info_ch->src_cfg.output_ws;
dkato 6:aa1fc6a5cc2a 2182 if (0U == freq_value)
dkato 6:aa1fc6a5cc2a 2183 {
dkato 6:aa1fc6a5cc2a 2184 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2185 }
dkato 6:aa1fc6a5cc2a 2186 break;
dkato 6:aa1fc6a5cc2a 2187
dkato 6:aa1fc6a5cc2a 2188 default :
dkato 6:aa1fc6a5cc2a 2189 /* error check is gone when route is other than SSIF */
dkato 6:aa1fc6a5cc2a 2190 if (SCUX_ROUTE_SSIF != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
dkato 6:aa1fc6a5cc2a 2191 {
dkato 6:aa1fc6a5cc2a 2192 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2193 }
dkato 6:aa1fc6a5cc2a 2194 break;
dkato 6:aa1fc6a5cc2a 2195 }
dkato 6:aa1fc6a5cc2a 2196 }
dkato 6:aa1fc6a5cc2a 2197
dkato 6:aa1fc6a5cc2a 2198 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2199 {
dkato 6:aa1fc6a5cc2a 2200 /* check devide rate on only except for SSIF route, MISRA R1.1 mesure */
dkato 6:aa1fc6a5cc2a 2201 if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
dkato 6:aa1fc6a5cc2a 2202 (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
dkato 6:aa1fc6a5cc2a 2203 (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
dkato 6:aa1fc6a5cc2a 2204 (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
dkato 6:aa1fc6a5cc2a 2205 (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
dkato 6:aa1fc6a5cc2a 2206 (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.output_clk_async))
dkato 6:aa1fc6a5cc2a 2207 {
dkato 6:aa1fc6a5cc2a 2208 if ((0U != (p_scux_info_ch->src_cfg.output_div_async % SCUX_EVEN_VALUE_DIV)) ||
dkato 6:aa1fc6a5cc2a 2209 (SCUX_MAX_DIV_CLK < p_scux_info_ch->src_cfg.output_div_async))
dkato 6:aa1fc6a5cc2a 2210 {
dkato 6:aa1fc6a5cc2a 2211 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2212 }
dkato 6:aa1fc6a5cc2a 2213 }
dkato 6:aa1fc6a5cc2a 2214 }
dkato 6:aa1fc6a5cc2a 2215
dkato 6:aa1fc6a5cc2a 2216 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2217 {
dkato 6:aa1fc6a5cc2a 2218 /* check source clock isn't SSIF WS signal */
dkato 6:aa1fc6a5cc2a 2219 if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
dkato 6:aa1fc6a5cc2a 2220 (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
dkato 6:aa1fc6a5cc2a 2221 (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
dkato 6:aa1fc6a5cc2a 2222 (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
dkato 6:aa1fc6a5cc2a 2223 (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
dkato 6:aa1fc6a5cc2a 2224 (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.output_clk_async))
dkato 6:aa1fc6a5cc2a 2225 {
dkato 6:aa1fc6a5cc2a 2226 if (0U == p_scux_info_ch->src_cfg.output_div_async)
dkato 6:aa1fc6a5cc2a 2227 {
dkato 6:aa1fc6a5cc2a 2228 /* 0 is a same size */
dkato 6:aa1fc6a5cc2a 2229 p_scux_info_ch->output_rate = freq_value;
dkato 6:aa1fc6a5cc2a 2230 }
dkato 6:aa1fc6a5cc2a 2231 else
dkato 6:aa1fc6a5cc2a 2232 {
dkato 6:aa1fc6a5cc2a 2233 p_scux_info_ch->output_rate = freq_value / p_scux_info_ch->src_cfg.output_div_async;
dkato 6:aa1fc6a5cc2a 2234 }
dkato 6:aa1fc6a5cc2a 2235 }
dkato 6:aa1fc6a5cc2a 2236 else
dkato 6:aa1fc6a5cc2a 2237 {
dkato 6:aa1fc6a5cc2a 2238 p_scux_info_ch->output_rate = freq_value;
dkato 6:aa1fc6a5cc2a 2239 }
dkato 6:aa1fc6a5cc2a 2240 /* check input frequency is enable range */
dkato 6:aa1fc6a5cc2a 2241 if (SCUX_USE_CH_6 == p_scux_info_ch->src_cfg.use_ch)
dkato 6:aa1fc6a5cc2a 2242 {
dkato 6:aa1fc6a5cc2a 2243 max_rate = SCUX_MAX_FREQ_CH6;
dkato 6:aa1fc6a5cc2a 2244 }
dkato 6:aa1fc6a5cc2a 2245 else if (SCUX_USE_CH_8 == p_scux_info_ch->src_cfg.use_ch)
dkato 6:aa1fc6a5cc2a 2246 {
dkato 6:aa1fc6a5cc2a 2247 max_rate = SCUX_MAX_FREQ_CH8;
dkato 6:aa1fc6a5cc2a 2248 }
dkato 6:aa1fc6a5cc2a 2249 else
dkato 6:aa1fc6a5cc2a 2250 {
dkato 6:aa1fc6a5cc2a 2251 max_rate = SCUX_MAX_FREQ_CH1_4;
dkato 6:aa1fc6a5cc2a 2252 }
dkato 6:aa1fc6a5cc2a 2253
dkato 6:aa1fc6a5cc2a 2254 if ((SCUX_MIN_FREQ > p_scux_info_ch->output_rate) ||
dkato 6:aa1fc6a5cc2a 2255 (max_rate < p_scux_info_ch->output_rate))
dkato 6:aa1fc6a5cc2a 2256 {
dkato 6:aa1fc6a5cc2a 2257 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2258 }
dkato 6:aa1fc6a5cc2a 2259
dkato 6:aa1fc6a5cc2a 2260 }
dkato 6:aa1fc6a5cc2a 2261 }
dkato 6:aa1fc6a5cc2a 2262 }
dkato 6:aa1fc6a5cc2a 2263
dkato 6:aa1fc6a5cc2a 2264 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2265 {
dkato 6:aa1fc6a5cc2a 2266 /* check convert rate range */
dkato 6:aa1fc6a5cc2a 2267 max_conv_rate = SCUX_MAX_CONV_RATE;
dkato 6:aa1fc6a5cc2a 2268 switch (p_scux_info_ch->src_cfg.delay_mode)
dkato 6:aa1fc6a5cc2a 2269 {
dkato 6:aa1fc6a5cc2a 2270 case SCUX_DELAY_NORMAL :
dkato 6:aa1fc6a5cc2a 2271 switch (p_scux_info_ch->src_cfg.use_ch)
dkato 6:aa1fc6a5cc2a 2272 {
dkato 6:aa1fc6a5cc2a 2273 case SCUX_USE_CH_1 :
dkato 6:aa1fc6a5cc2a 2274 /* fall through */
dkato 6:aa1fc6a5cc2a 2275 case SCUX_USE_CH_2 :
dkato 6:aa1fc6a5cc2a 2276 min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH1_2;
dkato 6:aa1fc6a5cc2a 2277 break;
dkato 6:aa1fc6a5cc2a 2278
dkato 6:aa1fc6a5cc2a 2279 case SCUX_USE_CH_4 :
dkato 6:aa1fc6a5cc2a 2280 min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH4;
dkato 6:aa1fc6a5cc2a 2281 break;
dkato 6:aa1fc6a5cc2a 2282
dkato 6:aa1fc6a5cc2a 2283 case SCUX_USE_CH_6 :
dkato 6:aa1fc6a5cc2a 2284 min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH6;
dkato 6:aa1fc6a5cc2a 2285 break;
dkato 6:aa1fc6a5cc2a 2286
dkato 6:aa1fc6a5cc2a 2287 case SCUX_USE_CH_8 :
dkato 6:aa1fc6a5cc2a 2288 min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH8;
dkato 6:aa1fc6a5cc2a 2289 break;
dkato 6:aa1fc6a5cc2a 2290
dkato 6:aa1fc6a5cc2a 2291 default :
dkato 6:aa1fc6a5cc2a 2292 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 2293 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2294 break;
dkato 6:aa1fc6a5cc2a 2295 }
dkato 6:aa1fc6a5cc2a 2296 break;
dkato 6:aa1fc6a5cc2a 2297
dkato 6:aa1fc6a5cc2a 2298 case SCUX_DELAY_LOW_DELAY1 :
dkato 6:aa1fc6a5cc2a 2299 min_conv_rate = SCUX_MIN_CONV_RATE_DELAY1;
dkato 6:aa1fc6a5cc2a 2300 break;
dkato 6:aa1fc6a5cc2a 2301
dkato 6:aa1fc6a5cc2a 2302 case SCUX_DELAY_LOW_DELAY2 :
dkato 6:aa1fc6a5cc2a 2303 min_conv_rate = SCUX_MIN_CONV_RATE_DELAY2;
dkato 6:aa1fc6a5cc2a 2304 break;
dkato 6:aa1fc6a5cc2a 2305
dkato 6:aa1fc6a5cc2a 2306 default :
dkato 6:aa1fc6a5cc2a 2307 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 2308 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2309 break;
dkato 6:aa1fc6a5cc2a 2310 }
dkato 6:aa1fc6a5cc2a 2311
dkato 6:aa1fc6a5cc2a 2312 rate_sample_ratio = ((p_scux_info_ch->output_rate * SCUX_RATE_INT_CONV_VALUE) / p_scux_info_ch->input_rate);
dkato 6:aa1fc6a5cc2a 2313 if ((min_conv_rate > rate_sample_ratio) || (max_conv_rate < rate_sample_ratio))
dkato 6:aa1fc6a5cc2a 2314 {
dkato 6:aa1fc6a5cc2a 2315 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2316 }
dkato 6:aa1fc6a5cc2a 2317 }
dkato 6:aa1fc6a5cc2a 2318 }
dkato 6:aa1fc6a5cc2a 2319
dkato 6:aa1fc6a5cc2a 2320 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2321 {
dkato 6:aa1fc6a5cc2a 2322 /* check wait time */
dkato 6:aa1fc6a5cc2a 2323 if (SCUX_MAX_WAIT_TIME < p_scux_info_ch->src_cfg.wait_sample)
dkato 6:aa1fc6a5cc2a 2324 {
dkato 6:aa1fc6a5cc2a 2325 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2326 }
dkato 6:aa1fc6a5cc2a 2327 }
dkato 6:aa1fc6a5cc2a 2328
dkato 6:aa1fc6a5cc2a 2329 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2330 {
dkato 6:aa1fc6a5cc2a 2331 /* check min rate ratio */
dkato 6:aa1fc6a5cc2a 2332 if ((SCUX_MIN_RATE_MIN_PAERCENTAGE > (uint32_t)p_scux_info_ch->src_cfg.min_rate_percentage) ||
dkato 6:aa1fc6a5cc2a 2333 (SCUX_MIN_RATE_MAX_PAERCENTAGE < (uint32_t)p_scux_info_ch->src_cfg.min_rate_percentage))
dkato 6:aa1fc6a5cc2a 2334 {
dkato 6:aa1fc6a5cc2a 2335 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2336 }
dkato 6:aa1fc6a5cc2a 2337 }
dkato 6:aa1fc6a5cc2a 2338
dkato 6:aa1fc6a5cc2a 2339 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2340 {
dkato 6:aa1fc6a5cc2a 2341 /* check input data position */
dkato 6:aa1fc6a5cc2a 2342 for (audio_ch = 0; ((ESUCCESS == retval) && (audio_ch < p_scux_info_ch->src_cfg.use_ch)); audio_ch++)
dkato 6:aa1fc6a5cc2a 2343 {
dkato 6:aa1fc6a5cc2a 2344 if ((SCUX_AUDIO_CH_MIN >= p_scux_info_ch->src_cfg.select_in_data_ch[audio_ch]) ||
dkato 6:aa1fc6a5cc2a 2345 (SCUX_AUDIO_CH_MAX <= p_scux_info_ch->src_cfg.select_in_data_ch[audio_ch]))
dkato 6:aa1fc6a5cc2a 2346 {
dkato 6:aa1fc6a5cc2a 2347 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2348 }
dkato 6:aa1fc6a5cc2a 2349 }
dkato 6:aa1fc6a5cc2a 2350 }
dkato 6:aa1fc6a5cc2a 2351 }
dkato 6:aa1fc6a5cc2a 2352
dkato 6:aa1fc6a5cc2a 2353 return retval;
dkato 6:aa1fc6a5cc2a 2354 }
dkato 6:aa1fc6a5cc2a 2355
dkato 6:aa1fc6a5cc2a 2356 /******************************************************************************
dkato 6:aa1fc6a5cc2a 2357 End of function SCUX_CheckSrcParam
dkato 6:aa1fc6a5cc2a 2358 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2359
dkato 6:aa1fc6a5cc2a 2360 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 2361 * Function Name: SCUX_CheckDvuParam
dkato 6:aa1fc6a5cc2a 2362 * @brief Check DVU parameter.
dkato 6:aa1fc6a5cc2a 2363 *
dkato 6:aa1fc6a5cc2a 2364 * Description:<br>
dkato 6:aa1fc6a5cc2a 2365 *
dkato 6:aa1fc6a5cc2a 2366 * @param[in] *p_scux_info_ch:SCUX channel information.
dkato 6:aa1fc6a5cc2a 2367 * @retval ESUCCESS : Parameter is no problems.
dkato 6:aa1fc6a5cc2a 2368 * EACCES : DVU setting isn't performed when DVU is used.
dkato 6:aa1fc6a5cc2a 2369 * EPERM : Parameter is unexpected value.
dkato 6:aa1fc6a5cc2a 2370 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 2371 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2372
dkato 6:aa1fc6a5cc2a 2373 static int_t SCUX_CheckDvuParam(const scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 2374 {
dkato 6:aa1fc6a5cc2a 2375 int_t retval = ESUCCESS;
dkato 6:aa1fc6a5cc2a 2376 int_t audio_ch;
dkato 6:aa1fc6a5cc2a 2377 uint32_t enable_ch_flag = false;
dkato 6:aa1fc6a5cc2a 2378
dkato 6:aa1fc6a5cc2a 2379 if (NULL == p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 2380 {
dkato 6:aa1fc6a5cc2a 2381 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 2382 }
dkato 6:aa1fc6a5cc2a 2383 else
dkato 6:aa1fc6a5cc2a 2384 {
dkato 6:aa1fc6a5cc2a 2385 if (false == p_scux_info_ch->dvu_setup)
dkato 6:aa1fc6a5cc2a 2386 {
dkato 6:aa1fc6a5cc2a 2387 retval = EACCES;
dkato 6:aa1fc6a5cc2a 2388 }
dkato 6:aa1fc6a5cc2a 2389 else
dkato 6:aa1fc6a5cc2a 2390 {
dkato 6:aa1fc6a5cc2a 2391 if (false != p_scux_info_ch->dvu_cfg.dvu_enable)
dkato 6:aa1fc6a5cc2a 2392 {
dkato 6:aa1fc6a5cc2a 2393 /* check digital volume value */
dkato 6:aa1fc6a5cc2a 2394 if (false != p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol_enable)
dkato 6:aa1fc6a5cc2a 2395 {
dkato 6:aa1fc6a5cc2a 2396 /* check digital volume value */
dkato 6:aa1fc6a5cc2a 2397 for (audio_ch = 0; ((ESUCCESS == retval) && (audio_ch < p_scux_info_ch->src_cfg.use_ch)); audio_ch++)
dkato 6:aa1fc6a5cc2a 2398 {
dkato 6:aa1fc6a5cc2a 2399 if (SCUX_MAX_DIGITAL_VOLUME < p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch])
dkato 6:aa1fc6a5cc2a 2400 {
dkato 6:aa1fc6a5cc2a 2401 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2402 }
dkato 6:aa1fc6a5cc2a 2403 }
dkato 6:aa1fc6a5cc2a 2404 }
dkato 6:aa1fc6a5cc2a 2405
dkato 6:aa1fc6a5cc2a 2406 /* check ramp volume value */
dkato 6:aa1fc6a5cc2a 2407 for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
dkato 6:aa1fc6a5cc2a 2408 {
dkato 6:aa1fc6a5cc2a 2409 enable_ch_flag |= (uint32_t)p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol_enable[audio_ch];
dkato 6:aa1fc6a5cc2a 2410 }
dkato 6:aa1fc6a5cc2a 2411
dkato 6:aa1fc6a5cc2a 2412 if ((ESUCCESS == retval) && (false != (bool_t)enable_ch_flag))
dkato 6:aa1fc6a5cc2a 2413 {
dkato 6:aa1fc6a5cc2a 2414 /* check ramp up period */
dkato 6:aa1fc6a5cc2a 2415 if ((p_scux_info_ch->dvu_cfg.dvu_ramp_vol.up_period <= SCUX_DVU_TIME_MIN) ||
dkato 6:aa1fc6a5cc2a 2416 (p_scux_info_ch->dvu_cfg.dvu_ramp_vol.up_period >= SCUX_DVU_TIME_MAX))
dkato 6:aa1fc6a5cc2a 2417 {
dkato 6:aa1fc6a5cc2a 2418 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2419 }
dkato 6:aa1fc6a5cc2a 2420
dkato 6:aa1fc6a5cc2a 2421 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2422 {
dkato 6:aa1fc6a5cc2a 2423 /* check ramp down period */
dkato 6:aa1fc6a5cc2a 2424 if ((p_scux_info_ch->dvu_cfg.dvu_ramp_vol.down_period <= SCUX_DVU_TIME_MIN) ||
dkato 6:aa1fc6a5cc2a 2425 (p_scux_info_ch->dvu_cfg.dvu_ramp_vol.down_period >= SCUX_DVU_TIME_MAX))
dkato 6:aa1fc6a5cc2a 2426 {
dkato 6:aa1fc6a5cc2a 2427 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2428 }
dkato 6:aa1fc6a5cc2a 2429 }
dkato 6:aa1fc6a5cc2a 2430
dkato 6:aa1fc6a5cc2a 2431 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2432 {
dkato 6:aa1fc6a5cc2a 2433 /* check ramp volume */
dkato 6:aa1fc6a5cc2a 2434 if (SCUX_MAX_RAMP_VOLUME < p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol)
dkato 6:aa1fc6a5cc2a 2435 {
dkato 6:aa1fc6a5cc2a 2436 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2437 }
dkato 6:aa1fc6a5cc2a 2438 }
dkato 6:aa1fc6a5cc2a 2439
dkato 6:aa1fc6a5cc2a 2440 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 2441 {
dkato 6:aa1fc6a5cc2a 2442 /* check wait time */
dkato 6:aa1fc6a5cc2a 2443 if (SCUX_MAX_WAIT_TIME < p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time)
dkato 6:aa1fc6a5cc2a 2444 {
dkato 6:aa1fc6a5cc2a 2445 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2446 }
dkato 6:aa1fc6a5cc2a 2447 }
dkato 6:aa1fc6a5cc2a 2448 }
dkato 6:aa1fc6a5cc2a 2449 }
dkato 6:aa1fc6a5cc2a 2450 }
dkato 6:aa1fc6a5cc2a 2451 }
dkato 6:aa1fc6a5cc2a 2452
dkato 6:aa1fc6a5cc2a 2453 return retval;
dkato 6:aa1fc6a5cc2a 2454 }
dkato 6:aa1fc6a5cc2a 2455
dkato 6:aa1fc6a5cc2a 2456 /******************************************************************************
dkato 6:aa1fc6a5cc2a 2457 End of function SCUX_CheckDvuParam
dkato 6:aa1fc6a5cc2a 2458 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2459
dkato 6:aa1fc6a5cc2a 2460 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 2461 * Function Name: SCUX_CheckSsifParam
dkato 6:aa1fc6a5cc2a 2462 * @brief Check SSIF parameter.
dkato 6:aa1fc6a5cc2a 2463 *
dkato 6:aa1fc6a5cc2a 2464 * Description:<br>
dkato 6:aa1fc6a5cc2a 2465 *
dkato 6:aa1fc6a5cc2a 2466 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 2467 * @param[in] ssif_ch : Used ssif channel number.
dkato 6:aa1fc6a5cc2a 2468 * @param[in] use_mix_flag : Flag of Using MIX .
dkato 6:aa1fc6a5cc2a 2469 * @retval ESUCCESS : Parameter is no problems.
dkato 6:aa1fc6a5cc2a 2470 * EACCES : SSIF setting isn't performed when SSIF is used.
dkato 6:aa1fc6a5cc2a 2471 * EACCES : SSIF channel is already used.
dkato 6:aa1fc6a5cc2a 2472 * EACCES : When use MIX, it is a setup which does not agree in a route setup.
dkato 6:aa1fc6a5cc2a 2473 * EPERM : Parameter is unexpected value.
dkato 6:aa1fc6a5cc2a 2474 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 2475 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2476
dkato 6:aa1fc6a5cc2a 2477 static int_t SCUX_CheckSsifParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT], const bool_t use_mix_flag)
dkato 6:aa1fc6a5cc2a 2478 {
dkato 6:aa1fc6a5cc2a 2479 int_t retval = ESUCCESS;
dkato 6:aa1fc6a5cc2a 2480 uint32_t ssif_arrange_num;
dkato 6:aa1fc6a5cc2a 2481 uint32_t mix_ssif_ch_bit = 0;
dkato 6:aa1fc6a5cc2a 2482 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
dkato 6:aa1fc6a5cc2a 2483
dkato 6:aa1fc6a5cc2a 2484 if ((NULL == p_info_drv) || (NULL == p_scux_info_ch) || (NULL == ssif_ch))
dkato 6:aa1fc6a5cc2a 2485 {
dkato 6:aa1fc6a5cc2a 2486 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 2487 }
dkato 6:aa1fc6a5cc2a 2488 else
dkato 6:aa1fc6a5cc2a 2489 {
dkato 6:aa1fc6a5cc2a 2490 if (false == use_mix_flag)
dkato 6:aa1fc6a5cc2a 2491 {
dkato 6:aa1fc6a5cc2a 2492 /* used SSIF channel check no used MIX route */
dkato 6:aa1fc6a5cc2a 2493 for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
dkato 6:aa1fc6a5cc2a 2494 {
dkato 6:aa1fc6a5cc2a 2495 if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
dkato 6:aa1fc6a5cc2a 2496 {
dkato 6:aa1fc6a5cc2a 2497 /* check SSIF is already setup */
dkato 6:aa1fc6a5cc2a 2498 if (false == gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_setup)
dkato 6:aa1fc6a5cc2a 2499 {
dkato 6:aa1fc6a5cc2a 2500 retval = EACCES;
dkato 6:aa1fc6a5cc2a 2501 }
dkato 6:aa1fc6a5cc2a 2502 else
dkato 6:aa1fc6a5cc2a 2503 {
dkato 6:aa1fc6a5cc2a 2504 /* used SSIF channel is checked by other SCUX channel */
dkato 6:aa1fc6a5cc2a 2505 if (0 != gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].scux_channel)
dkato 6:aa1fc6a5cc2a 2506 {
dkato 6:aa1fc6a5cc2a 2507 retval = EACCES;
dkato 6:aa1fc6a5cc2a 2508 }
dkato 6:aa1fc6a5cc2a 2509 }
dkato 6:aa1fc6a5cc2a 2510 }
dkato 6:aa1fc6a5cc2a 2511 }
dkato 6:aa1fc6a5cc2a 2512 }
dkato 6:aa1fc6a5cc2a 2513 else
dkato 6:aa1fc6a5cc2a 2514 {
dkato 6:aa1fc6a5cc2a 2515 /* used SSIF channel check on MIX route */
dkato 6:aa1fc6a5cc2a 2516 for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
dkato 6:aa1fc6a5cc2a 2517 {
dkato 6:aa1fc6a5cc2a 2518 if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
dkato 6:aa1fc6a5cc2a 2519 {
dkato 6:aa1fc6a5cc2a 2520 /* clear SCUX_SSIF_use_mix_flag and get SSIF channel number */
dkato 6:aa1fc6a5cc2a 2521 mix_ssif_ch_bit |= (1U << ssif_ch[ssif_arrange_num]);
dkato 6:aa1fc6a5cc2a 2522 /* check SSIF is already setup */
dkato 6:aa1fc6a5cc2a 2523 if (false == gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_setup)
dkato 6:aa1fc6a5cc2a 2524 {
dkato 6:aa1fc6a5cc2a 2525 retval = EACCES;
dkato 6:aa1fc6a5cc2a 2526 }
dkato 6:aa1fc6a5cc2a 2527 }
dkato 6:aa1fc6a5cc2a 2528 }
dkato 6:aa1fc6a5cc2a 2529 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2530 {
dkato 6:aa1fc6a5cc2a 2531 /* used SSIF channel check, on MIX route check */
dkato 6:aa1fc6a5cc2a 2532 if (0U != p_info_drv->shared_info.mix_ssif_ch)
dkato 6:aa1fc6a5cc2a 2533 {
dkato 6:aa1fc6a5cc2a 2534 /* In the MIX setup for the and after 2times, it is checked that same SSIF ch on 1st setting is set up */
dkato 6:aa1fc6a5cc2a 2535 if (p_info_drv->shared_info.mix_ssif_ch != mix_ssif_ch_bit)
dkato 6:aa1fc6a5cc2a 2536 {
dkato 6:aa1fc6a5cc2a 2537 retval = EACCES;
dkato 6:aa1fc6a5cc2a 2538 }
dkato 6:aa1fc6a5cc2a 2539 }
dkato 6:aa1fc6a5cc2a 2540 else
dkato 6:aa1fc6a5cc2a 2541 {
dkato 6:aa1fc6a5cc2a 2542 /*It checks that SSIF channel is not used once on first MIX setup */
dkato 6:aa1fc6a5cc2a 2543 if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2])
dkato 6:aa1fc6a5cc2a 2544 {
dkato 6:aa1fc6a5cc2a 2545 if ((0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]].scux_channel) ||
dkato 6:aa1fc6a5cc2a 2546 (0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]].scux_channel) ||
dkato 6:aa1fc6a5cc2a 2547 (0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3]].scux_channel))
dkato 6:aa1fc6a5cc2a 2548 {
dkato 6:aa1fc6a5cc2a 2549 retval = EACCES;
dkato 6:aa1fc6a5cc2a 2550 }
dkato 6:aa1fc6a5cc2a 2551 }
dkato 6:aa1fc6a5cc2a 2552 else
dkato 6:aa1fc6a5cc2a 2553 {
dkato 6:aa1fc6a5cc2a 2554 if (0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]].scux_channel)
dkato 6:aa1fc6a5cc2a 2555 {
dkato 6:aa1fc6a5cc2a 2556 retval = EACCES;
dkato 6:aa1fc6a5cc2a 2557 }
dkato 6:aa1fc6a5cc2a 2558 }
dkato 6:aa1fc6a5cc2a 2559 }
dkato 6:aa1fc6a5cc2a 2560 }
dkato 6:aa1fc6a5cc2a 2561 }
dkato 6:aa1fc6a5cc2a 2562
dkato 6:aa1fc6a5cc2a 2563 /* each SSIF parameter check */
dkato 6:aa1fc6a5cc2a 2564 for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
dkato 6:aa1fc6a5cc2a 2565 {
dkato 6:aa1fc6a5cc2a 2566 /* used SSIF channel check, on SSIF direct route check */
dkato 6:aa1fc6a5cc2a 2567 if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
dkato 6:aa1fc6a5cc2a 2568 {
dkato 6:aa1fc6a5cc2a 2569
dkato 6:aa1fc6a5cc2a 2570 /* check system word */
dkato 6:aa1fc6a5cc2a 2571 if ((gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.system_word <= SCUX_SSIF_SYSTEM_LEN_MIN) ||
dkato 6:aa1fc6a5cc2a 2572 (gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.system_word >= SCUX_SSIF_SYSTEM_LEN_MAX))
dkato 6:aa1fc6a5cc2a 2573 {
dkato 6:aa1fc6a5cc2a 2574 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2575 }
dkato 6:aa1fc6a5cc2a 2576 else
dkato 6:aa1fc6a5cc2a 2577 {
dkato 6:aa1fc6a5cc2a 2578 /* check system word >= data word */
dkato 6:aa1fc6a5cc2a 2579 /* The combination applicable to error only of data word of 24bit and system word of 16bit */
dkato 6:aa1fc6a5cc2a 2580 if ((SCUX_DATA_LEN_16 != p_scux_info_ch->src_cfg.word_len) &&
dkato 6:aa1fc6a5cc2a 2581 (SCUX_SSIF_SYSTEM_LEN_16 == gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.system_word))
dkato 6:aa1fc6a5cc2a 2582 {
dkato 6:aa1fc6a5cc2a 2583 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2584 }
dkato 6:aa1fc6a5cc2a 2585 }
dkato 6:aa1fc6a5cc2a 2586
dkato 6:aa1fc6a5cc2a 2587 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2588 {
dkato 6:aa1fc6a5cc2a 2589 /* if multiple channel is used, TDM is disable */
dkato 6:aa1fc6a5cc2a 2590 if ((SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]) &&
dkato 6:aa1fc6a5cc2a 2591 (false != gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.use_tdm))
dkato 6:aa1fc6a5cc2a 2592 {
dkato 6:aa1fc6a5cc2a 2593 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2594 }
dkato 6:aa1fc6a5cc2a 2595 }
dkato 6:aa1fc6a5cc2a 2596 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2597 {
dkato 6:aa1fc6a5cc2a 2598 retval = SCUX_CheckSsifClockDiv(p_scux_info_ch, ssif_ch[ssif_arrange_num]);
dkato 6:aa1fc6a5cc2a 2599 }
dkato 6:aa1fc6a5cc2a 2600
dkato 6:aa1fc6a5cc2a 2601 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2602 {
dkato 6:aa1fc6a5cc2a 2603 gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].scux_channel
dkato 6:aa1fc6a5cc2a 2604 = (int_t)((uint32_t)gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].scux_channel | (1U << p_scux_info_ch->channel));
dkato 6:aa1fc6a5cc2a 2605 }
dkato 6:aa1fc6a5cc2a 2606 }
dkato 6:aa1fc6a5cc2a 2607 }
dkato 6:aa1fc6a5cc2a 2608
dkato 6:aa1fc6a5cc2a 2609 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2610 {
dkato 6:aa1fc6a5cc2a 2611 /* set SSIF information structure pointer */
dkato 6:aa1fc6a5cc2a 2612 if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2])
dkato 6:aa1fc6a5cc2a 2613 {
dkato 6:aa1fc6a5cc2a 2614 p_scux_info_ch->p_ssif_info1 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]];
dkato 6:aa1fc6a5cc2a 2615 p_scux_info_ch->p_ssif_info2 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]];
dkato 6:aa1fc6a5cc2a 2616 p_scux_info_ch->p_ssif_info3 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3]];
dkato 6:aa1fc6a5cc2a 2617 }
dkato 6:aa1fc6a5cc2a 2618 else
dkato 6:aa1fc6a5cc2a 2619 {
dkato 6:aa1fc6a5cc2a 2620 p_scux_info_ch->p_ssif_info1 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]];
dkato 6:aa1fc6a5cc2a 2621 p_scux_info_ch->p_ssif_info2 = NULL;
dkato 6:aa1fc6a5cc2a 2622 p_scux_info_ch->p_ssif_info3 = NULL;
dkato 6:aa1fc6a5cc2a 2623 }
dkato 6:aa1fc6a5cc2a 2624 }
dkato 6:aa1fc6a5cc2a 2625 }
dkato 6:aa1fc6a5cc2a 2626
dkato 6:aa1fc6a5cc2a 2627 return retval;
dkato 6:aa1fc6a5cc2a 2628 }
dkato 6:aa1fc6a5cc2a 2629
dkato 6:aa1fc6a5cc2a 2630 /******************************************************************************
dkato 6:aa1fc6a5cc2a 2631 End of function SCUX_CheckSsifParam
dkato 6:aa1fc6a5cc2a 2632 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2633
dkato 6:aa1fc6a5cc2a 2634 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 2635 * Function Name: SCUX_CheckMixParam
dkato 6:aa1fc6a5cc2a 2636 * @brief Check MIX parameter.
dkato 6:aa1fc6a5cc2a 2637 *
dkato 6:aa1fc6a5cc2a 2638 * Description:<br>
dkato 6:aa1fc6a5cc2a 2639 *
dkato 6:aa1fc6a5cc2a 2640 * @param[in] *p_scux_info_ch:SCUX channel information.
dkato 6:aa1fc6a5cc2a 2641 * @retval ESUCCESS : Parameter is no problems.
dkato 6:aa1fc6a5cc2a 2642 * EACCES : MIX setting isn't performed when MIX is used.
dkato 6:aa1fc6a5cc2a 2643 * EPERM : Parameter is unexpected value.
dkato 6:aa1fc6a5cc2a 2644 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 2645 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2646
dkato 6:aa1fc6a5cc2a 2647 static int_t SCUX_CheckMixParam(const scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 2648 {
dkato 6:aa1fc6a5cc2a 2649 int_t retval = ESUCCESS;
dkato 6:aa1fc6a5cc2a 2650 int_t scux_ch;
dkato 6:aa1fc6a5cc2a 2651 int_t audio_ch;
dkato 6:aa1fc6a5cc2a 2652 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
dkato 6:aa1fc6a5cc2a 2653
dkato 6:aa1fc6a5cc2a 2654 if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
dkato 6:aa1fc6a5cc2a 2655 {
dkato 6:aa1fc6a5cc2a 2656 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 2657 }
dkato 6:aa1fc6a5cc2a 2658 else
dkato 6:aa1fc6a5cc2a 2659 {
dkato 6:aa1fc6a5cc2a 2660 if (false == p_info_drv->shared_info.mix_setup)
dkato 6:aa1fc6a5cc2a 2661 {
dkato 6:aa1fc6a5cc2a 2662 retval = EACCES;
dkato 6:aa1fc6a5cc2a 2663 }
dkato 6:aa1fc6a5cc2a 2664 else
dkato 6:aa1fc6a5cc2a 2665 {
dkato 6:aa1fc6a5cc2a 2666 if (false != p_info_drv->shared_info.mixmode_ramp)
dkato 6:aa1fc6a5cc2a 2667 {
dkato 6:aa1fc6a5cc2a 2668 /* check ramp up time */
dkato 6:aa1fc6a5cc2a 2669 if ((SCUX_MIX_TIME_MIN >= p_info_drv->shared_info.up_period) ||
dkato 6:aa1fc6a5cc2a 2670 (SCUX_MIX_TIME_MAX <= p_info_drv->shared_info.up_period))
dkato 6:aa1fc6a5cc2a 2671 {
dkato 6:aa1fc6a5cc2a 2672 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2673 }
dkato 6:aa1fc6a5cc2a 2674
dkato 6:aa1fc6a5cc2a 2675 /* check ramp down time */
dkato 6:aa1fc6a5cc2a 2676 if ((SCUX_MIX_TIME_MIN >= p_info_drv->shared_info.down_period) ||
dkato 6:aa1fc6a5cc2a 2677 (SCUX_MIX_TIME_MAX <= p_info_drv->shared_info.down_period))
dkato 6:aa1fc6a5cc2a 2678 {
dkato 6:aa1fc6a5cc2a 2679 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2680 }
dkato 6:aa1fc6a5cc2a 2681 }
dkato 6:aa1fc6a5cc2a 2682
dkato 6:aa1fc6a5cc2a 2683 /* check MIX volume */
dkato 6:aa1fc6a5cc2a 2684 for (scux_ch = SCUX_CH_0; ((ESUCCESS == retval) && (SCUX_CH_NUM > scux_ch)); scux_ch++)
dkato 6:aa1fc6a5cc2a 2685 {
dkato 6:aa1fc6a5cc2a 2686 /* register set on the channel itself which sets up or channel which has already MIX operated */
dkato 6:aa1fc6a5cc2a 2687 if ((scux_ch == p_scux_info_ch->channel) ||
dkato 6:aa1fc6a5cc2a 2688 (0U != (p_info_drv->shared_info.mix_run_ch & (1U << scux_ch))))
dkato 6:aa1fc6a5cc2a 2689 {
dkato 6:aa1fc6a5cc2a 2690 if (SCUX_MAX_RAMP_VOLUME < p_info_drv->shared_info.mix_vol[scux_ch])
dkato 6:aa1fc6a5cc2a 2691 {
dkato 6:aa1fc6a5cc2a 2692 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2693 }
dkato 6:aa1fc6a5cc2a 2694 }
dkato 6:aa1fc6a5cc2a 2695 }
dkato 6:aa1fc6a5cc2a 2696
dkato 6:aa1fc6a5cc2a 2697 /* check output data position */
dkato 6:aa1fc6a5cc2a 2698 for (audio_ch = 0; ((ESUCCESS == retval) && (audio_ch < p_scux_info_ch->src_cfg.use_ch)); audio_ch++)
dkato 6:aa1fc6a5cc2a 2699 {
dkato 6:aa1fc6a5cc2a 2700 /* check min rate ratio */
dkato 6:aa1fc6a5cc2a 2701 if ((SCUX_AUDIO_CH_MIN >= p_info_drv->shared_info.select_out_data_ch[audio_ch]) ||
dkato 6:aa1fc6a5cc2a 2702 (SCUX_AUDIO_CH_MAX <= p_info_drv->shared_info.select_out_data_ch[audio_ch]))
dkato 6:aa1fc6a5cc2a 2703 {
dkato 6:aa1fc6a5cc2a 2704 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2705 }
dkato 6:aa1fc6a5cc2a 2706 }
dkato 6:aa1fc6a5cc2a 2707 }
dkato 6:aa1fc6a5cc2a 2708 }
dkato 6:aa1fc6a5cc2a 2709
dkato 6:aa1fc6a5cc2a 2710 return retval;
dkato 6:aa1fc6a5cc2a 2711 }
dkato 6:aa1fc6a5cc2a 2712
dkato 6:aa1fc6a5cc2a 2713 /******************************************************************************
dkato 6:aa1fc6a5cc2a 2714 End of function SCUX_CheckMixParam
dkato 6:aa1fc6a5cc2a 2715 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2716
dkato 6:aa1fc6a5cc2a 2717 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 2718 * Function Name: SCUX_StrNLen
dkato 6:aa1fc6a5cc2a 2719 * @brief computes the length of the string
dkato 6:aa1fc6a5cc2a 2720 *
dkato 6:aa1fc6a5cc2a 2721 * Description:<br>
dkato 6:aa1fc6a5cc2a 2722 * if string is longer than maxlen, this function return maxlen
dkato 6:aa1fc6a5cc2a 2723 * @param[in] p_str :pointer of string
dkato 6:aa1fc6a5cc2a 2724 * @param[in] maxlen :maximum length of inspection
dkato 6:aa1fc6a5cc2a 2725 * @retval 'number of characters in the string' or 'maxlen'
dkato 6:aa1fc6a5cc2a 2726 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2727 size_t SCUX_StrNLen(const char_t* p_str, size_t maxlen)
dkato 6:aa1fc6a5cc2a 2728 {
dkato 6:aa1fc6a5cc2a 2729 size_t ret_len;
dkato 6:aa1fc6a5cc2a 2730
dkato 6:aa1fc6a5cc2a 2731 if (NULL == p_str)
dkato 6:aa1fc6a5cc2a 2732 {
dkato 6:aa1fc6a5cc2a 2733 /* character string does not exist */
dkato 6:aa1fc6a5cc2a 2734 ret_len = 0;
dkato 6:aa1fc6a5cc2a 2735 }
dkato 6:aa1fc6a5cc2a 2736 else
dkato 6:aa1fc6a5cc2a 2737 {
dkato 6:aa1fc6a5cc2a 2738 /* ->IPA P1.3.1 Even if a sign is positive, even a negative is no problem. */
dkato 6:aa1fc6a5cc2a 2739 for (ret_len = 0; (maxlen != 0U) && (*p_str != '\0'); ret_len++)
dkato 6:aa1fc6a5cc2a 2740 /* <-IPA P1.3.1 */
dkato 6:aa1fc6a5cc2a 2741 {
dkato 6:aa1fc6a5cc2a 2742 maxlen--;
dkato 6:aa1fc6a5cc2a 2743 p_str++;
dkato 6:aa1fc6a5cc2a 2744 }
dkato 6:aa1fc6a5cc2a 2745 }
dkato 6:aa1fc6a5cc2a 2746
dkato 6:aa1fc6a5cc2a 2747 return ret_len;
dkato 6:aa1fc6a5cc2a 2748 }
dkato 6:aa1fc6a5cc2a 2749
dkato 6:aa1fc6a5cc2a 2750 /******************************************************************************
dkato 6:aa1fc6a5cc2a 2751 End of function SCUX_StrNLen
dkato 6:aa1fc6a5cc2a 2752 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2753 #if(1) /* mbed */
dkato 6:aa1fc6a5cc2a 2754 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 2755 * Function Name: SCUX_CmnUnInitialize
dkato 6:aa1fc6a5cc2a 2756 * @brief uninitialize driver infomation.
dkato 6:aa1fc6a5cc2a 2757 *
dkato 6:aa1fc6a5cc2a 2758 * Description:<br>
dkato 6:aa1fc6a5cc2a 2759 *
dkato 6:aa1fc6a5cc2a 2760 * @param[in] None.
dkato 6:aa1fc6a5cc2a 2761 * @retval ESUCCESS : Parameter is no problems.
dkato 6:aa1fc6a5cc2a 2762 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 2763 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2764 static int_t SCUX_CmnUnInitialize(void)
dkato 6:aa1fc6a5cc2a 2765 {
dkato 6:aa1fc6a5cc2a 2766 int_t retval = ESUCCESS;
dkato 6:aa1fc6a5cc2a 2767 osStatus sem_ercd;
dkato 6:aa1fc6a5cc2a 2768 int_t ssif_ch_count;
dkato 6:aa1fc6a5cc2a 2769 uint32_t cpg_value;
dkato 6:aa1fc6a5cc2a 2770 uint32_t was_masked;
dkato 6:aa1fc6a5cc2a 2771 volatile uint8_t dummy_buf;
dkato 6:aa1fc6a5cc2a 2772
dkato 6:aa1fc6a5cc2a 2773 /* software reset */
dkato 6:aa1fc6a5cc2a 2774 SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
dkato 6:aa1fc6a5cc2a 2775
dkato 6:aa1fc6a5cc2a 2776 for (ssif_ch_count = 0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
dkato 6:aa1fc6a5cc2a 2777 {
dkato 6:aa1fc6a5cc2a 2778 if (NULL != gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
dkato 6:aa1fc6a5cc2a 2779 {
dkato 6:aa1fc6a5cc2a 2780 sem_ercd = osSemaphoreDelete(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
dkato 6:aa1fc6a5cc2a 2781 /* semaphore error check */
dkato 6:aa1fc6a5cc2a 2782 if (osOK != sem_ercd)
dkato 6:aa1fc6a5cc2a 2783 {
dkato 6:aa1fc6a5cc2a 2784 /* set error return value */
dkato 6:aa1fc6a5cc2a 2785 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 2786 }
dkato 6:aa1fc6a5cc2a 2787
dkato 6:aa1fc6a5cc2a 2788 gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = NULL;
dkato 6:aa1fc6a5cc2a 2789 }
dkato 6:aa1fc6a5cc2a 2790 }
dkato 6:aa1fc6a5cc2a 2791
dkato 6:aa1fc6a5cc2a 2792 if (NULL != gb_scux_info_drv.shared_info.sem_shared_access)
dkato 6:aa1fc6a5cc2a 2793 {
dkato 6:aa1fc6a5cc2a 2794 sem_ercd = osSemaphoreDelete(gb_scux_info_drv.shared_info.sem_shared_access);
dkato 6:aa1fc6a5cc2a 2795 /* semaphore error check */
dkato 6:aa1fc6a5cc2a 2796 if (osOK != sem_ercd)
dkato 6:aa1fc6a5cc2a 2797 {
dkato 6:aa1fc6a5cc2a 2798 /* set error return value */
dkato 6:aa1fc6a5cc2a 2799 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 2800 }
dkato 6:aa1fc6a5cc2a 2801
dkato 6:aa1fc6a5cc2a 2802 gb_scux_info_drv.shared_info.sem_shared_access = NULL;
dkato 6:aa1fc6a5cc2a 2803 }
dkato 6:aa1fc6a5cc2a 2804
dkato 6:aa1fc6a5cc2a 2805 was_masked = __disable_irq();
dkato 6:aa1fc6a5cc2a 2806
dkato 6:aa1fc6a5cc2a 2807 /* stop clock for SCUX */
dkato 6:aa1fc6a5cc2a 2808 cpg_value = ((uint32_t)CPG.STBCR8 | CPG_STBCR8_BIT_MSTP81);
dkato 6:aa1fc6a5cc2a 2809 CPG.STBCR8 = (uint8_t)cpg_value;
dkato 6:aa1fc6a5cc2a 2810 dummy_buf = CPG.STBCR8;
dkato 6:aa1fc6a5cc2a 2811
dkato 6:aa1fc6a5cc2a 2812 if (0U == was_masked)
dkato 6:aa1fc6a5cc2a 2813 {
dkato 6:aa1fc6a5cc2a 2814 /* enable all irq */
dkato 6:aa1fc6a5cc2a 2815 __enable_irq();
dkato 6:aa1fc6a5cc2a 2816 }
dkato 6:aa1fc6a5cc2a 2817
dkato 6:aa1fc6a5cc2a 2818 return retval;
dkato 6:aa1fc6a5cc2a 2819 }
dkato 6:aa1fc6a5cc2a 2820
dkato 6:aa1fc6a5cc2a 2821 /******************************************************************************
dkato 6:aa1fc6a5cc2a 2822 End of function SCUX_CmnUnInitialize
dkato 6:aa1fc6a5cc2a 2823 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2824 #endif /* end mbed */