RZ/A1H CMSIS-RTOS RTX BSP for GR-PEACH.

Dependents:   GR-PEACH_Azure_Speech ImageZoomInout_Sample ImageRotaion_Sample ImageScroll_Sample ... more

Fork of R_BSP by Daiki Kato

SSIF

The SSIF driver implements transmission and reception functionality which uses the SSIF in the RZ/A Series.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Ssif.h"
00003 #include "sine_data_tbl.h"
00004 
00005 //I2S send only, The upper limit of write buffer is 8.
00006 R_BSP_Ssif ssif(P4_4, P4_5, P4_7, P4_6, 0x80, 8, 0);
00007 
00008 static void callback_ssif_write_end(void * p_data, int32_t result, void * p_app_data) {
00009     if (result < 0) {
00010         printf("ssif write callback error %d\n", result);
00011     }
00012 }
00013 
00014 int main() {
00015     rbsp_data_conf_t   ssif_write_end_conf = {&callback_ssif_write_end, NULL};
00016     ssif_channel_cfg_t ssif_cfg;
00017     int32_t            result;
00018 
00019     //I2S Master, 44.1kHz, 16bit, 2ch
00020     ssif_cfg.enabled                = true;
00021     ssif_cfg.int_level              = 0x78;
00022     ssif_cfg.slave_mode             = false;
00023     ssif_cfg.sample_freq            = 44100u;
00024     ssif_cfg.clk_select             = SSIF_CFG_CKS_AUDIO_X1;
00025     ssif_cfg.multi_ch               = SSIF_CFG_MULTI_CH_1;
00026     ssif_cfg.data_word              = SSIF_CFG_DATA_WORD_16;
00027     ssif_cfg.system_word            = SSIF_CFG_SYSTEM_WORD_32;
00028     ssif_cfg.bclk_pol               = SSIF_CFG_FALLING;
00029     ssif_cfg.ws_pol                 = SSIF_CFG_WS_LOW;
00030     ssif_cfg.padding_pol            = SSIF_CFG_PADDING_LOW;
00031     ssif_cfg.serial_alignment       = SSIF_CFG_DATA_FIRST;
00032     ssif_cfg.parallel_alignment     = SSIF_CFG_LEFT;
00033     ssif_cfg.ws_delay               = SSIF_CFG_DELAY;
00034     ssif_cfg.noise_cancel           = SSIF_CFG_DISABLE_NOISE_CANCEL;
00035     ssif_cfg.tdm_mode               = SSIF_CFG_DISABLE_TDM;
00036     ssif_cfg.romdec_direct.mode     = SSIF_CFG_DISABLE_ROMDEC_DIRECT;
00037     ssif_cfg.romdec_direct.p_cbfunc = NULL;
00038     result = ssif.ConfigChannel(&ssif_cfg);
00039     if (result < 0) {
00040         printf("ssif config error %d\n", result);
00041     }
00042 
00043     while (1) {
00044         //The upper limit of write buffer is 8.
00045         result = ssif.write((void *)sin_data_44100Hz_16bit_2ch, 
00046                             sizeof(sin_data_44100Hz_16bit_2ch), &ssif_write_end_conf);
00047         if (result < 0) {
00048             printf("ssif write api error %d\n", result);
00049         }
00050     }
00051 }

API

Import library

Public Member Functions

R_BSP_Ssif (PinName sck, PinName ws, PinName tx, PinName rx, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor.
virtual ~R_BSP_Ssif ()
Destructor.
int32_t GetSsifChNo (void)
Get a value of SSIF channel number.
bool ConfigChannel (const ssif_channel_cfg_t *const p_ch_cfg)
Save configuration to the SSIF driver.
bool GetStatus (uint32_t *const p_status)
Get a value of SSISR register.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Interface

See the Pinout page for more details


SCUX

The SCUX module consists of a sampling rate converter, a digital volume unit, and a mixer.
The SCUX driver can perform asynchronous and synchronous sampling rate conversions using the sampling rate converter. The SCUX driver uses the DMA transfer mode to input and output audio data.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Scux.h"
00003 #include "USBHostMSD.h"
00004 
00005 R_BSP_Scux scux(SCUX_CH_0);
00006 
00007 #define WRITE_SAMPLE_NUM (128)
00008 #define READ_SAMPLE_NUM  (2048)
00009 
00010 const short sin_data[WRITE_SAMPLE_NUM] = {
00011  0x0000,0x0000,0x0C8C,0x0C8C,0x18F9,0x18F9,0x2528,0x2528
00012 ,0x30FB,0x30FB,0x3C56,0x3C56,0x471C,0x471C,0x5133,0x5133
00013 ,0x5A82,0x5A82,0x62F1,0x62F1,0x6A6D,0x6A6D,0x70E2,0x70E2
00014 ,0x7641,0x7641,0x7A7C,0x7A7C,0x7D89,0x7D89,0x7F61,0x7F61
00015 ,0x7FFF,0x7FFF,0x7F61,0x7F61,0x7D89,0x7D89,0x7A7C,0x7A7C
00016 ,0x7641,0x7641,0x70E2,0x70E2,0x6A6D,0x6A6D,0x62F1,0x62F1
00017 ,0x5A82,0x5A82,0x5133,0x5133,0x471C,0x471C,0x3C56,0x3C56
00018 ,0x30FB,0x30FB,0x2528,0x2528,0x18F9,0x18F9,0x0C8C,0x0C8C
00019 ,0x0000,0x0000,0xF374,0xF374,0xE707,0xE707,0xDAD8,0xDAD8
00020 ,0xCF05,0xCF05,0xC3AA,0xC3AA,0xB8E4,0xB8E4,0xAECD,0xAECD
00021 ,0xA57E,0xA57E,0x9D0F,0x9D0F,0x9593,0x9593,0x8F1E,0x8F1E
00022 ,0x89BF,0x89BF,0x8584,0x8584,0x8277,0x8277,0x809F,0x809F
00023 ,0x8001,0x8001,0x809F,0x809F,0x8277,0x8277,0x8584,0x8584
00024 ,0x89BF,0x89BF,0x8F1E,0x8F1E,0x9593,0x9593,0x9D0F,0x9D0F
00025 ,0xA57E,0xA57E,0xAECD,0xAECD,0xB8E4,0xB8E4,0xC3AA,0xC3AA
00026 ,0xCF05,0xCF05,0xDAD8,0xDAD8,0xE707,0xE707,0xF374,0xF374
00027 };
00028 
00029 #if defined(__ICCARM__)
00030 #pragma data_alignment=4
00031 short write_buff[WRITE_SAMPLE_NUM]@ ".mirrorram";
00032 #pragma data_alignment=4
00033 short read_buff[READ_SAMPLE_NUM]@ ".mirrorram";
00034 #else
00035 short write_buff[WRITE_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00036 short read_buff[READ_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00037 #endif
00038 
00039 void scux_setup(void);
00040 void write_task(void const*);
00041 void file_output_to_usb(void);
00042 
00043 int main(void) {
00044     // set up SRC parameters.
00045     scux_setup();
00046 
00047     printf("Sampling rate conversion Start.\n");
00048     // start accepting transmit/receive requests.
00049     scux.TransStart();
00050 
00051     // create a new thread to write to SCUX.
00052     Thread writeTask(write_task, NULL, osPriorityNormal, 1024 * 4);
00053 
00054     // receive request to the SCUX driver.
00055     scux.read(read_buff, sizeof(read_buff));
00056     printf("Sampling rate conversion End.\n");
00057 
00058     // output binary file to USB port 0.
00059     file_output_to_usb();
00060 }
00061 
00062 void scux_setup(void) {
00063     scux_src_usr_cfg_t src_cfg;
00064 
00065     src_cfg.src_enable           = true;
00066     src_cfg.word_len             = SCUX_DATA_LEN_16;
00067     src_cfg.mode_sync            = true;
00068     src_cfg.input_rate           = SAMPLING_RATE_48000HZ;
00069     src_cfg.output_rate          = SAMPLING_RATE_96000HZ;
00070     src_cfg.select_in_data_ch[0] = SELECT_IN_DATA_CH_0;
00071     src_cfg.select_in_data_ch[1] = SELECT_IN_DATA_CH_1;
00072 
00073     scux.SetSrcCfg(&src_cfg);
00074 }
00075 
00076 void scux_flush_callback(int scux_ch) {
00077     // do nothing
00078 }
00079 
00080 void write_task(void const*) {
00081     memcpy(write_buff, sin_data, sizeof(write_buff));
00082     // send request to the SCUX driver.
00083     scux.write(write_buff, sizeof(write_buff));
00084 
00085     // stop the acceptance of transmit/receive requests.
00086     scux.FlushStop(&scux_flush_callback);
00087 }
00088 
00089 void file_output_to_usb(void) {
00090     FILE * fp = NULL;
00091     int i;
00092 
00093     USBHostMSD msd("usb");
00094 
00095     // try to connect a MSD device
00096     for(i = 0; i < 10; i++) {
00097         if (msd.connect()) {
00098             break;
00099         }
00100         wait(0.5);
00101     }
00102 
00103     if (msd.connected()) {
00104         fp = fopen("/usb/scux_input.dat", "rb");
00105         if (fp == NULL) {
00106             fp = fopen("/usb/scux_input.dat", "wb");
00107             if (fp != NULL) {
00108                 fwrite(write_buff, sizeof(short), WRITE_SAMPLE_NUM, fp);
00109                 fclose(fp);
00110                 printf("Output binary file(Input data) to USB.\n");
00111             } else {
00112                 printf("Failed to output binary file(Input data).\n");
00113             }
00114         } else {
00115             printf("Binary file(Input data) exists.\n");
00116             fclose(fp);
00117         }
00118 
00119         fp = fopen("/usb/scux_output.dat", "rb");
00120         if (fp == NULL) {
00121             fp = fopen("/usb/scux_output.dat", "wb");
00122             if (fp != NULL) {
00123                 fwrite(read_buff, sizeof(short), READ_SAMPLE_NUM, fp);
00124                 fclose(fp);
00125                 printf("Output binary file(Output data) to USB.\n");
00126             } else {
00127                 printf("Failed to output binary file(Output data).\n");
00128             }
00129         } else {
00130             printf("Binary file(Output data) exists.\n");
00131             fclose(fp);
00132         }
00133     } else {
00134         printf("Failed to connect to the USB device.\n");
00135     }
00136 } 

API

Import library

Public Member Functions

R_BSP_Scux ( scux_ch_num_t channel, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor: Initializes and opens the channel designated by the SCUX driver.
virtual ~R_BSP_Scux (void)
Destructor: Closes the channel designated by the SCUX driver and exits.
bool TransStart (void)
Sets up the SCUX HW and starts operation, then starts accepting write/read requests.
bool FlushStop (void(*const callback)(int32_t))
Stops accepting write/read requests, flushes out all data in the SCUX that is requested for transfer, then stops the HW operation.
bool ClearStop (void)
Discards all data in the SCUX that is requested for transfer before stopping the hardware operation and stops accepting write/read requests.
bool SetSrcCfg (const scux_src_usr_cfg_t *const p_src_param)
Sets up SRC parameters.
bool GetWriteStat (uint32_t *const p_write_stat)
Obtains the state information of the write request.
bool GetReadStat (uint32_t *const p_read_stat)
Obtains the state information of the read request.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Write request state transition diagram

/media/uploads/dkato/scux_write_state_transition.png

Read request state transition diagram

/media/uploads/dkato/scux_read_state_transition.png

Committer:
dkato
Date:
Mon Jun 01 08:33:21 2015 +0000
Revision:
0:702bf7b2b7d8
Child:
5:1390bfcb667c
first comit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:702bf7b2b7d8 1 /*******************************************************************************
dkato 0:702bf7b2b7d8 2 * DISCLAIMER
dkato 0:702bf7b2b7d8 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:702bf7b2b7d8 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:702bf7b2b7d8 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:702bf7b2b7d8 6 * all applicable laws, including copyright laws.
dkato 0:702bf7b2b7d8 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:702bf7b2b7d8 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:702bf7b2b7d8 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:702bf7b2b7d8 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:702bf7b2b7d8 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:702bf7b2b7d8 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:702bf7b2b7d8 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:702bf7b2b7d8 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:702bf7b2b7d8 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:702bf7b2b7d8 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:702bf7b2b7d8 17 * and to discontinue the availability of this software. By using this software,
dkato 0:702bf7b2b7d8 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:702bf7b2b7d8 19 * following link:
dkato 0:702bf7b2b7d8 20 * http://www.renesas.com/disclaimer*
dkato 0:702bf7b2b7d8 21 * Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
dkato 0:702bf7b2b7d8 22 *******************************************************************************/
dkato 0:702bf7b2b7d8 23
dkato 0:702bf7b2b7d8 24 /**************************************************************************//**
dkato 0:702bf7b2b7d8 25 * @file dma.c
dkato 0:702bf7b2b7d8 26 * $Rev: 1133 $
dkato 0:702bf7b2b7d8 27 * $Date:: 2014-09-08 14:33:59 +0900#$
dkato 0:702bf7b2b7d8 28 * @brief DMA Driver internal functions
dkato 0:702bf7b2b7d8 29 ******************************************************************************/
dkato 0:702bf7b2b7d8 30
dkato 0:702bf7b2b7d8 31 /*****************************************************************************
dkato 0:702bf7b2b7d8 32 * History : DD.MM.YYYY Version Description
dkato 0:702bf7b2b7d8 33 * : 15.01.2013 1.00 First Release
dkato 0:702bf7b2b7d8 34 ******************************************************************************/
dkato 0:702bf7b2b7d8 35
dkato 0:702bf7b2b7d8 36 /*******************************************************************************
dkato 0:702bf7b2b7d8 37 Includes <System Includes>, "Project Includes"
dkato 0:702bf7b2b7d8 38 *******************************************************************************/
dkato 0:702bf7b2b7d8 39
dkato 0:702bf7b2b7d8 40 #include "dma.h"
dkato 0:702bf7b2b7d8 41 #include "aioif.h"
dkato 0:702bf7b2b7d8 42 #include "iodefine.h"
dkato 0:702bf7b2b7d8 43 #include "gic.h"
dkato 0:702bf7b2b7d8 44 #include "bsp_util.h"
dkato 0:702bf7b2b7d8 45
dkato 0:702bf7b2b7d8 46 /******************************************************************************
dkato 0:702bf7b2b7d8 47 Private global driver management information
dkato 0:702bf7b2b7d8 48 ******************************************************************************/
dkato 0:702bf7b2b7d8 49
dkato 0:702bf7b2b7d8 50 /* driver management infrmation */
dkato 0:702bf7b2b7d8 51 static dma_info_drv_t gb_info_drv;
dkato 0:702bf7b2b7d8 52
dkato 0:702bf7b2b7d8 53 /******************************************************************************
dkato 0:702bf7b2b7d8 54 Private global channel semaphore information
dkato 0:702bf7b2b7d8 55 ******************************************************************************/
dkato 0:702bf7b2b7d8 56
dkato 0:702bf7b2b7d8 57 /* driver semaphore name define */
dkato 0:702bf7b2b7d8 58 /* ->MISRA 8.8, 8.10, IPA M2.2.2 There is no problem in the description of declaration of
dkato 0:702bf7b2b7d8 59 OS resource itself */
dkato 0:702bf7b2b7d8 60 osSemaphoreDef(sem_dma_ch0);
dkato 0:702bf7b2b7d8 61 osSemaphoreDef(sem_dma_ch1);
dkato 0:702bf7b2b7d8 62 osSemaphoreDef(sem_dma_ch2);
dkato 0:702bf7b2b7d8 63 osSemaphoreDef(sem_dma_ch3);
dkato 0:702bf7b2b7d8 64 osSemaphoreDef(sem_dma_ch4);
dkato 0:702bf7b2b7d8 65 osSemaphoreDef(sem_dma_ch5);
dkato 0:702bf7b2b7d8 66 osSemaphoreDef(sem_dma_ch6);
dkato 0:702bf7b2b7d8 67 osSemaphoreDef(sem_dma_ch7);
dkato 0:702bf7b2b7d8 68 osSemaphoreDef(sem_dma_ch8);
dkato 0:702bf7b2b7d8 69 osSemaphoreDef(sem_dma_ch9);
dkato 0:702bf7b2b7d8 70 osSemaphoreDef(sem_dma_ch10);
dkato 0:702bf7b2b7d8 71 osSemaphoreDef(sem_dma_ch11);
dkato 0:702bf7b2b7d8 72 osSemaphoreDef(sem_dma_ch12);
dkato 0:702bf7b2b7d8 73 osSemaphoreDef(sem_dma_ch13);
dkato 0:702bf7b2b7d8 74 osSemaphoreDef(sem_dma_ch14);
dkato 0:702bf7b2b7d8 75 osSemaphoreDef(sem_dma_ch15);
dkato 0:702bf7b2b7d8 76 /* <-MISRA 8.8, 8.10, IPA M2.2.2 */
dkato 0:702bf7b2b7d8 77
dkato 0:702bf7b2b7d8 78 /******************************************************************************
dkato 0:702bf7b2b7d8 79 Private function define (interrupt handler)
dkato 0:702bf7b2b7d8 80 ******************************************************************************/
dkato 0:702bf7b2b7d8 81
dkato 0:702bf7b2b7d8 82 static void R_DMA_End0InterruptHandler(void);
dkato 0:702bf7b2b7d8 83 static void R_DMA_End1InterruptHandler(void);
dkato 0:702bf7b2b7d8 84 static void R_DMA_End2InterruptHandler(void);
dkato 0:702bf7b2b7d8 85 static void R_DMA_End3InterruptHandler(void);
dkato 0:702bf7b2b7d8 86 static void R_DMA_End4InterruptHandler(void);
dkato 0:702bf7b2b7d8 87 static void R_DMA_End5InterruptHandler(void);
dkato 0:702bf7b2b7d8 88 static void R_DMA_End6InterruptHandler(void);
dkato 0:702bf7b2b7d8 89 static void R_DMA_End7InterruptHandler(void);
dkato 0:702bf7b2b7d8 90 static void R_DMA_End8InterruptHandler(void);
dkato 0:702bf7b2b7d8 91 static void R_DMA_End9InterruptHandler(void);
dkato 0:702bf7b2b7d8 92 static void R_DMA_End10InterruptHandler(void);
dkato 0:702bf7b2b7d8 93 static void R_DMA_End11InterruptHandler(void);
dkato 0:702bf7b2b7d8 94 static void R_DMA_End12InterruptHandler(void);
dkato 0:702bf7b2b7d8 95 static void R_DMA_End13InterruptHandler(void);
dkato 0:702bf7b2b7d8 96 static void R_DMA_End14InterruptHandler(void);
dkato 0:702bf7b2b7d8 97 static void R_DMA_End15InterruptHandler(void);
dkato 0:702bf7b2b7d8 98 static void R_DMA_ErrInterruptHandler(void);
dkato 0:702bf7b2b7d8 99 static void R_DMA_EndHandlerProcess(const int_t channel);
dkato 0:702bf7b2b7d8 100
dkato 0:702bf7b2b7d8 101 /******************************************************************************
dkato 0:702bf7b2b7d8 102 Function prototypes
dkato 0:702bf7b2b7d8 103 *****************************************************************************/
dkato 0:702bf7b2b7d8 104
dkato 0:702bf7b2b7d8 105 static void DMA_OpenChannel(const int_t channel);
dkato 0:702bf7b2b7d8 106
dkato 0:702bf7b2b7d8 107 /******************************************************************************
dkato 0:702bf7b2b7d8 108 * Function Name: DMA_GetDrvInstance
dkato 0:702bf7b2b7d8 109 * Description : Get pointer of gb_info_drv.
dkato 0:702bf7b2b7d8 110 * Arguments : *p_dma_info_drv -
dkato 0:702bf7b2b7d8 111 * Pointer of gb_info_drv is returned.
dkato 0:702bf7b2b7d8 112 * Return Value : None
dkato 0:702bf7b2b7d8 113 ******************************************************************************/
dkato 0:702bf7b2b7d8 114
dkato 0:702bf7b2b7d8 115 dma_info_drv_t *DMA_GetDrvInstance(void)
dkato 0:702bf7b2b7d8 116 {
dkato 0:702bf7b2b7d8 117
dkato 0:702bf7b2b7d8 118 return &gb_info_drv;
dkato 0:702bf7b2b7d8 119 }
dkato 0:702bf7b2b7d8 120
dkato 0:702bf7b2b7d8 121 /******************************************************************************
dkato 0:702bf7b2b7d8 122 End of function DMA_GetDrv_Instance
dkato 0:702bf7b2b7d8 123 ******************************************************************************/
dkato 0:702bf7b2b7d8 124
dkato 0:702bf7b2b7d8 125 /******************************************************************************
dkato 0:702bf7b2b7d8 126 * Function Name: DMA_GetDrvChInfo
dkato 0:702bf7b2b7d8 127 * Description : Get pointer of gb_info_drv.info_ch[channel].
dkato 0:702bf7b2b7d8 128 * Arguments : *p_dma_info_drv -
dkato 0:702bf7b2b7d8 129 * Pointer of gb_info_drv is returned.
dkato 0:702bf7b2b7d8 130 * Return Value : None
dkato 0:702bf7b2b7d8 131 ******************************************************************************/
dkato 0:702bf7b2b7d8 132
dkato 0:702bf7b2b7d8 133 dma_info_ch_t *DMA_GetDrvChInfo(const int_t channel)
dkato 0:702bf7b2b7d8 134 {
dkato 0:702bf7b2b7d8 135
dkato 0:702bf7b2b7d8 136 return &gb_info_drv.info_ch[channel];
dkato 0:702bf7b2b7d8 137 }
dkato 0:702bf7b2b7d8 138
dkato 0:702bf7b2b7d8 139 /******************************************************************************
dkato 0:702bf7b2b7d8 140 End of function DMA_GetDrvChInfo
dkato 0:702bf7b2b7d8 141 ******************************************************************************/
dkato 0:702bf7b2b7d8 142
dkato 0:702bf7b2b7d8 143 /******************************************************************************
dkato 0:702bf7b2b7d8 144 * Function Name: DMA_Initialize
dkato 0:702bf7b2b7d8 145 * Description : Initialize DMA driver.
dkato 0:702bf7b2b7d8 146 * Arguments : *p_dma_init_param -
dkato 0:702bf7b2b7d8 147 * Pointer of init parameters.
dkato 0:702bf7b2b7d8 148 * sem_drv -
dkato 0:702bf7b2b7d8 149 * Driver semaphore ID.
dkato 0:702bf7b2b7d8 150 * Return Value : ESUCCESS -
dkato 0:702bf7b2b7d8 151 * Operation successful.
dkato 0:702bf7b2b7d8 152 * OS error num -
dkato 0:702bf7b2b7d8 153 * Registering handler failed.
dkato 0:702bf7b2b7d8 154 * ENOMEM -
dkato 0:702bf7b2b7d8 155 * Making semaphore failed.
dkato 0:702bf7b2b7d8 156 ******************************************************************************/
dkato 0:702bf7b2b7d8 157
dkato 0:702bf7b2b7d8 158 int_t DMA_Initialize(const dma_drv_init_t * const p_dma_init_param, const osSemaphoreId sem_drv)
dkato 0:702bf7b2b7d8 159 {
dkato 0:702bf7b2b7d8 160 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 161 int_t ch_count;
dkato 0:702bf7b2b7d8 162 uint32_t error_code;
dkato 0:702bf7b2b7d8 163 bool_t init_check_flag;
dkato 0:702bf7b2b7d8 164
dkato 0:702bf7b2b7d8 165 /* ->MISRA 11.3, 11.4, IPA R3.6.2 This cast is needed for register access. */
dkato 0:702bf7b2b7d8 166 /* address table of register set for each channel */
dkato 0:702bf7b2b7d8 167 static volatile struct st_dmac_n *gb_dma_ch_register_addr_table[DMA_CH_NUM] =
dkato 0:702bf7b2b7d8 168 { &DMAC0,
dkato 0:702bf7b2b7d8 169 &DMAC1,
dkato 0:702bf7b2b7d8 170 &DMAC2,
dkato 0:702bf7b2b7d8 171 &DMAC3,
dkato 0:702bf7b2b7d8 172 &DMAC4,
dkato 0:702bf7b2b7d8 173 &DMAC5,
dkato 0:702bf7b2b7d8 174 &DMAC6,
dkato 0:702bf7b2b7d8 175 &DMAC7,
dkato 0:702bf7b2b7d8 176 &DMAC8,
dkato 0:702bf7b2b7d8 177 &DMAC9,
dkato 0:702bf7b2b7d8 178 &DMAC10,
dkato 0:702bf7b2b7d8 179 &DMAC11,
dkato 0:702bf7b2b7d8 180 &DMAC12,
dkato 0:702bf7b2b7d8 181 &DMAC13,
dkato 0:702bf7b2b7d8 182 &DMAC14,
dkato 0:702bf7b2b7d8 183 &DMAC15
dkato 0:702bf7b2b7d8 184 };
dkato 0:702bf7b2b7d8 185 /* <-MISRA 11.3, 11.4, IPA R3.6.2*/
dkato 0:702bf7b2b7d8 186
dkato 0:702bf7b2b7d8 187 /* ->MISRA 11.3, 11.4, IPA R3.6.2 This cast is needed for register access. */
dkato 0:702bf7b2b7d8 188 /* address table of register set for common register */
dkato 0:702bf7b2b7d8 189 static volatile struct st_dmaccommon_n *gb_dma_common_register_addr_table[DMA_CH_NUM] =
dkato 0:702bf7b2b7d8 190 { &DMAC07,
dkato 0:702bf7b2b7d8 191 &DMAC07,
dkato 0:702bf7b2b7d8 192 &DMAC07,
dkato 0:702bf7b2b7d8 193 &DMAC07,
dkato 0:702bf7b2b7d8 194 &DMAC07,
dkato 0:702bf7b2b7d8 195 &DMAC07,
dkato 0:702bf7b2b7d8 196 &DMAC07,
dkato 0:702bf7b2b7d8 197 &DMAC07,
dkato 0:702bf7b2b7d8 198 &DMAC815,
dkato 0:702bf7b2b7d8 199 &DMAC815,
dkato 0:702bf7b2b7d8 200 &DMAC815,
dkato 0:702bf7b2b7d8 201 &DMAC815,
dkato 0:702bf7b2b7d8 202 &DMAC815,
dkato 0:702bf7b2b7d8 203 &DMAC815,
dkato 0:702bf7b2b7d8 204 &DMAC815,
dkato 0:702bf7b2b7d8 205 &DMAC815
dkato 0:702bf7b2b7d8 206 };
dkato 0:702bf7b2b7d8 207 /* <-MISRA 11.3, 11.4, IPA R3.6.2*/
dkato 0:702bf7b2b7d8 208
dkato 0:702bf7b2b7d8 209 /* ->MISRA 11.3, 11.4 This cast is needed for register access. */
dkato 0:702bf7b2b7d8 210 /* address table of register set for DMARS */
dkato 0:702bf7b2b7d8 211 static volatile uint32_t *gb_dmars_register_addr_table[DMA_CH_NUM] =
dkato 0:702bf7b2b7d8 212 { &DMACDMARS0,
dkato 0:702bf7b2b7d8 213 &DMACDMARS0,
dkato 0:702bf7b2b7d8 214 &DMACDMARS1,
dkato 0:702bf7b2b7d8 215 &DMACDMARS1,
dkato 0:702bf7b2b7d8 216 &DMACDMARS2,
dkato 0:702bf7b2b7d8 217 &DMACDMARS2,
dkato 0:702bf7b2b7d8 218 &DMACDMARS3,
dkato 0:702bf7b2b7d8 219 &DMACDMARS3,
dkato 0:702bf7b2b7d8 220 &DMACDMARS4,
dkato 0:702bf7b2b7d8 221 &DMACDMARS4,
dkato 0:702bf7b2b7d8 222 &DMACDMARS5,
dkato 0:702bf7b2b7d8 223 &DMACDMARS5,
dkato 0:702bf7b2b7d8 224 &DMACDMARS6,
dkato 0:702bf7b2b7d8 225 &DMACDMARS6,
dkato 0:702bf7b2b7d8 226 &DMACDMARS7,
dkato 0:702bf7b2b7d8 227 &DMACDMARS7
dkato 0:702bf7b2b7d8 228 };
dkato 0:702bf7b2b7d8 229 /* <-MISRA 11.3, 11.4 */
dkato 0:702bf7b2b7d8 230
dkato 0:702bf7b2b7d8 231 /* Interrpt handlers table */
dkato 0:702bf7b2b7d8 232 static const IRQHandler gb_dma_int_handler_table[DMA_CH_NUM] =
dkato 0:702bf7b2b7d8 233 { &R_DMA_End0InterruptHandler, /* DMA end interrupt for ch0 - ch15 */
dkato 0:702bf7b2b7d8 234 &R_DMA_End1InterruptHandler,
dkato 0:702bf7b2b7d8 235 &R_DMA_End2InterruptHandler,
dkato 0:702bf7b2b7d8 236 &R_DMA_End3InterruptHandler,
dkato 0:702bf7b2b7d8 237 &R_DMA_End4InterruptHandler,
dkato 0:702bf7b2b7d8 238 &R_DMA_End5InterruptHandler,
dkato 0:702bf7b2b7d8 239 &R_DMA_End6InterruptHandler,
dkato 0:702bf7b2b7d8 240 &R_DMA_End7InterruptHandler,
dkato 0:702bf7b2b7d8 241 &R_DMA_End8InterruptHandler,
dkato 0:702bf7b2b7d8 242 &R_DMA_End9InterruptHandler,
dkato 0:702bf7b2b7d8 243 &R_DMA_End10InterruptHandler,
dkato 0:702bf7b2b7d8 244 &R_DMA_End11InterruptHandler,
dkato 0:702bf7b2b7d8 245 &R_DMA_End12InterruptHandler,
dkato 0:702bf7b2b7d8 246 &R_DMA_End13InterruptHandler,
dkato 0:702bf7b2b7d8 247 &R_DMA_End14InterruptHandler,
dkato 0:702bf7b2b7d8 248 &R_DMA_End15InterruptHandler
dkato 0:702bf7b2b7d8 249 };
dkato 0:702bf7b2b7d8 250
dkato 0:702bf7b2b7d8 251 /* Interrupt numbers table */
dkato 0:702bf7b2b7d8 252 static const IRQn_Type gb_dma_int_num_table[DMA_CH_NUM] =
dkato 0:702bf7b2b7d8 253 { DMAINT0_IRQn, /* DMA end interrupt for ch0 - ch15 */
dkato 0:702bf7b2b7d8 254 DMAINT1_IRQn,
dkato 0:702bf7b2b7d8 255 DMAINT2_IRQn,
dkato 0:702bf7b2b7d8 256 DMAINT3_IRQn,
dkato 0:702bf7b2b7d8 257 DMAINT4_IRQn,
dkato 0:702bf7b2b7d8 258 DMAINT5_IRQn,
dkato 0:702bf7b2b7d8 259 DMAINT6_IRQn,
dkato 0:702bf7b2b7d8 260 DMAINT7_IRQn,
dkato 0:702bf7b2b7d8 261 DMAINT8_IRQn,
dkato 0:702bf7b2b7d8 262 DMAINT9_IRQn,
dkato 0:702bf7b2b7d8 263 DMAINT10_IRQn,
dkato 0:702bf7b2b7d8 264 DMAINT11_IRQn,
dkato 0:702bf7b2b7d8 265 DMAINT12_IRQn,
dkato 0:702bf7b2b7d8 266 DMAINT13_IRQn,
dkato 0:702bf7b2b7d8 267 DMAINT14_IRQn,
dkato 0:702bf7b2b7d8 268 DMAINT15_IRQn
dkato 0:702bf7b2b7d8 269 };
dkato 0:702bf7b2b7d8 270
dkato 0:702bf7b2b7d8 271 /* driver semaphore table define */
dkato 0:702bf7b2b7d8 272 static const osSemaphoreDef_t *p_gb_semdef_ch[DMA_CH_NUM] =
dkato 0:702bf7b2b7d8 273 {
dkato 0:702bf7b2b7d8 274 osSemaphore(sem_dma_ch0),
dkato 0:702bf7b2b7d8 275 osSemaphore(sem_dma_ch1),
dkato 0:702bf7b2b7d8 276 osSemaphore(sem_dma_ch2),
dkato 0:702bf7b2b7d8 277 osSemaphore(sem_dma_ch3),
dkato 0:702bf7b2b7d8 278 osSemaphore(sem_dma_ch4),
dkato 0:702bf7b2b7d8 279 osSemaphore(sem_dma_ch5),
dkato 0:702bf7b2b7d8 280 osSemaphore(sem_dma_ch6),
dkato 0:702bf7b2b7d8 281 osSemaphore(sem_dma_ch7),
dkato 0:702bf7b2b7d8 282 osSemaphore(sem_dma_ch8),
dkato 0:702bf7b2b7d8 283 osSemaphore(sem_dma_ch9),
dkato 0:702bf7b2b7d8 284 osSemaphore(sem_dma_ch10),
dkato 0:702bf7b2b7d8 285 osSemaphore(sem_dma_ch11),
dkato 0:702bf7b2b7d8 286 osSemaphore(sem_dma_ch12),
dkato 0:702bf7b2b7d8 287 osSemaphore(sem_dma_ch13),
dkato 0:702bf7b2b7d8 288 osSemaphore(sem_dma_ch14),
dkato 0:702bf7b2b7d8 289 osSemaphore(sem_dma_ch15)
dkato 0:702bf7b2b7d8 290 };
dkato 0:702bf7b2b7d8 291
dkato 0:702bf7b2b7d8 292 /* element of p_dma_init_param is copied to element of gb_info_drv */
dkato 0:702bf7b2b7d8 293 gb_info_drv.p_err_aio = p_dma_init_param->p_aio;
dkato 0:702bf7b2b7d8 294
dkato 0:702bf7b2b7d8 295 /* set driver semaphore ID */
dkato 0:702bf7b2b7d8 296 gb_info_drv.sem_drv = sem_drv;
dkato 0:702bf7b2b7d8 297
dkato 0:702bf7b2b7d8 298 /* set DMA error interrupt number */
dkato 0:702bf7b2b7d8 299 gb_info_drv.err_irq_num = DMAERR_IRQn;
dkato 0:702bf7b2b7d8 300
dkato 0:702bf7b2b7d8 301 /* init channel management information */
dkato 0:702bf7b2b7d8 302 for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
dkato 0:702bf7b2b7d8 303 {
dkato 0:702bf7b2b7d8 304 /* set channel number */
dkato 0:702bf7b2b7d8 305 gb_info_drv.info_ch[ch_count].ch = ch_count;
dkato 0:702bf7b2b7d8 306
dkato 0:702bf7b2b7d8 307 /* set DMA end interrupt number */
dkato 0:702bf7b2b7d8 308 gb_info_drv.info_ch[ch_count].end_irq_num = gb_dma_int_num_table[ch_count];
dkato 0:702bf7b2b7d8 309
dkato 0:702bf7b2b7d8 310 /* init next DMA setting flag */
dkato 0:702bf7b2b7d8 311 gb_info_drv.info_ch[ch_count].next_dma_flag = false;
dkato 0:702bf7b2b7d8 312
dkato 0:702bf7b2b7d8 313 if (1U == ((uint32_t)ch_count & CHECK_ODD_EVEN_MASK))
dkato 0:702bf7b2b7d8 314 {
dkato 0:702bf7b2b7d8 315 /* set shift number when channel is odd value */
dkato 0:702bf7b2b7d8 316 gb_info_drv.info_ch[ch_count].shift_dmars = SHIFT_DMARS_ODD_CH;
dkato 0:702bf7b2b7d8 317 /* set mask value when channel is odd value */
dkato 0:702bf7b2b7d8 318 gb_info_drv.info_ch[ch_count].mask_dmars = MASK_DMARS_ODD_CH;
dkato 0:702bf7b2b7d8 319 }
dkato 0:702bf7b2b7d8 320 else
dkato 0:702bf7b2b7d8 321 {
dkato 0:702bf7b2b7d8 322 /* set shift number when channel is even value */
dkato 0:702bf7b2b7d8 323 gb_info_drv.info_ch[ch_count].shift_dmars = SHIFT_DMARS_EVEN_CH;
dkato 0:702bf7b2b7d8 324 /* set mask value when channel is even value */
dkato 0:702bf7b2b7d8 325 gb_info_drv.info_ch[ch_count].mask_dmars = MASK_DMARS_EVEN_CH;
dkato 0:702bf7b2b7d8 326 }
dkato 0:702bf7b2b7d8 327
dkato 0:702bf7b2b7d8 328 /* init DMA setup flag */
dkato 0:702bf7b2b7d8 329 gb_info_drv.info_ch[ch_count].setup_flag = false;
dkato 0:702bf7b2b7d8 330
dkato 0:702bf7b2b7d8 331 /* ->MISRA 11.4 This cast is needed for register access. */
dkato 0:702bf7b2b7d8 332 /* set DMA register address for each channel */
dkato 0:702bf7b2b7d8 333 gb_info_drv.info_ch[ch_count].p_dma_ch_reg = gb_dma_ch_register_addr_table[ch_count];
dkato 0:702bf7b2b7d8 334 /* set common resgiter for channel 0 - 7 */
dkato 0:702bf7b2b7d8 335 gb_info_drv.info_ch[ch_count].p_dma_common_reg = gb_dma_common_register_addr_table[ch_count];
dkato 0:702bf7b2b7d8 336 /* <-MISRA 11.4 */
dkato 0:702bf7b2b7d8 337
dkato 0:702bf7b2b7d8 338 /* set DMARS register for each channel */
dkato 0:702bf7b2b7d8 339 gb_info_drv.info_ch[ch_count].p_dma_dmars_reg = gb_dmars_register_addr_table[ch_count];
dkato 0:702bf7b2b7d8 340 }
dkato 0:702bf7b2b7d8 341
dkato 0:702bf7b2b7d8 342 /* init DMA registers */
dkato 0:702bf7b2b7d8 343 for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
dkato 0:702bf7b2b7d8 344 {
dkato 0:702bf7b2b7d8 345 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0SA_n = N0SA_INIT_VALUE;
dkato 0:702bf7b2b7d8 346 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1SA_n = N1SA_INIT_VALUE;
dkato 0:702bf7b2b7d8 347 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0DA_n = N0DA_INIT_VALUE;
dkato 0:702bf7b2b7d8 348 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1DA_n = N1DA_INIT_VALUE;
dkato 0:702bf7b2b7d8 349 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0TB_n = N0TB_INIT_VALUE;
dkato 0:702bf7b2b7d8 350 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1TB_n = N1TB_INIT_VALUE;
dkato 0:702bf7b2b7d8 351 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCTRL_n = CHCTRL_INIT_VALUE;
dkato 0:702bf7b2b7d8 352 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCFG_n = CHCFG_INIT_VALUE;
dkato 0:702bf7b2b7d8 353 /* set DMA interval = 0 */
dkato 0:702bf7b2b7d8 354 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHITVL_n = CHITVL_INIT_VALUE;
dkato 0:702bf7b2b7d8 355 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHEXT_n = CHEXT_INIT_VALUE;
dkato 0:702bf7b2b7d8 356 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->NXLA_n = NXLA_INIT_VALUE;
dkato 0:702bf7b2b7d8 357 *(gb_info_drv.info_ch[ch_count].p_dma_dmars_reg) = DMARS_INIT_VALUE;
dkato 0:702bf7b2b7d8 358 }
dkato 0:702bf7b2b7d8 359 /* init common resgiter for channel 0 - 7 */
dkato 0:702bf7b2b7d8 360 /* set interrupt output : pulse,
dkato 0:702bf7b2b7d8 361 set round robin mode */
dkato 0:702bf7b2b7d8 362 gb_info_drv.info_ch[DMA_CH_0].p_dma_common_reg->DCTRL_0_7 = DCTRL_INIT_VALUE;
dkato 0:702bf7b2b7d8 363 /* init common resgiter for channel 8 - 15 */
dkato 0:702bf7b2b7d8 364 /* set interrupt output : pulse,
dkato 0:702bf7b2b7d8 365 set round robin mode */
dkato 0:702bf7b2b7d8 366 gb_info_drv.info_ch[HIGH_COMMON_REG_OFFSET].p_dma_common_reg->DCTRL_0_7 = DCTRL_INIT_VALUE;
dkato 0:702bf7b2b7d8 367
dkato 0:702bf7b2b7d8 368 /* making channel semaphore */
dkato 0:702bf7b2b7d8 369 init_check_flag = false;
dkato 0:702bf7b2b7d8 370 ch_count = 0;
dkato 0:702bf7b2b7d8 371 while (false == init_check_flag)
dkato 0:702bf7b2b7d8 372 {
dkato 0:702bf7b2b7d8 373 /* make semaphore */
dkato 0:702bf7b2b7d8 374 gb_info_drv.info_ch[ch_count].sem_ch = osSemaphoreCreate(p_gb_semdef_ch[ch_count], 1);
dkato 0:702bf7b2b7d8 375 if (NULL == gb_info_drv.info_ch[ch_count].sem_ch)
dkato 0:702bf7b2b7d8 376 {
dkato 0:702bf7b2b7d8 377 /* set error return value */
dkato 0:702bf7b2b7d8 378 retval = ENOMEM;
dkato 0:702bf7b2b7d8 379 init_check_flag = true;
dkato 0:702bf7b2b7d8 380 }
dkato 0:702bf7b2b7d8 381
dkato 0:702bf7b2b7d8 382 if ((DMA_CH_NUM - 1) == ch_count)
dkato 0:702bf7b2b7d8 383 {
dkato 0:702bf7b2b7d8 384 init_check_flag = true;
dkato 0:702bf7b2b7d8 385 }
dkato 0:702bf7b2b7d8 386 ch_count++;
dkato 0:702bf7b2b7d8 387 }
dkato 0:702bf7b2b7d8 388
dkato 0:702bf7b2b7d8 389 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 390 {
dkato 0:702bf7b2b7d8 391 /* DMA end interrupt handler register */
dkato 0:702bf7b2b7d8 392 init_check_flag = false;
dkato 0:702bf7b2b7d8 393 ch_count = 0;
dkato 0:702bf7b2b7d8 394 while (false == init_check_flag)
dkato 0:702bf7b2b7d8 395 {
dkato 0:702bf7b2b7d8 396 error_code = InterruptHandlerRegister(gb_info_drv.info_ch[ch_count].end_irq_num,
dkato 0:702bf7b2b7d8 397 gb_dma_int_handler_table[ch_count]
dkato 0:702bf7b2b7d8 398 );
dkato 0:702bf7b2b7d8 399 /* 0 is no error on InterruptHandlerRegister() */
dkato 0:702bf7b2b7d8 400 if (0U != error_code)
dkato 0:702bf7b2b7d8 401 {
dkato 0:702bf7b2b7d8 402 retval = (int_t)error_code;
dkato 0:702bf7b2b7d8 403 init_check_flag = true;
dkato 0:702bf7b2b7d8 404 }
dkato 0:702bf7b2b7d8 405 if ((DMA_CH_NUM - 1) == ch_count)
dkato 0:702bf7b2b7d8 406 {
dkato 0:702bf7b2b7d8 407 init_check_flag = true;
dkato 0:702bf7b2b7d8 408 }
dkato 0:702bf7b2b7d8 409 ch_count++;
dkato 0:702bf7b2b7d8 410 }
dkato 0:702bf7b2b7d8 411
dkato 0:702bf7b2b7d8 412 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 413 {
dkato 0:702bf7b2b7d8 414 /* DMA error interrupt handler register */
dkato 0:702bf7b2b7d8 415 error_code = InterruptHandlerRegister(gb_info_drv.err_irq_num,
dkato 0:702bf7b2b7d8 416 &R_DMA_ErrInterruptHandler
dkato 0:702bf7b2b7d8 417 );
dkato 0:702bf7b2b7d8 418 /* 0 is no error on InterruptHandlerRegister() */
dkato 0:702bf7b2b7d8 419 if (0U != error_code)
dkato 0:702bf7b2b7d8 420 {
dkato 0:702bf7b2b7d8 421 retval = (int_t)error_code;
dkato 0:702bf7b2b7d8 422 }
dkato 0:702bf7b2b7d8 423 }
dkato 0:702bf7b2b7d8 424 }
dkato 0:702bf7b2b7d8 425
dkato 0:702bf7b2b7d8 426 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 427 {
dkato 0:702bf7b2b7d8 428 /* set DMA end interrupt level & priority */
dkato 0:702bf7b2b7d8 429 for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
dkato 0:702bf7b2b7d8 430 {
dkato 0:702bf7b2b7d8 431 /* set interrupt level (set edge trigger, 1-N model) */
dkato 0:702bf7b2b7d8 432 GIC_SetLevelModel(gb_info_drv.info_ch[ch_count].end_irq_num, 1, 1);
dkato 0:702bf7b2b7d8 433 }
dkato 0:702bf7b2b7d8 434 /* set DMA error interrupt level (set edge trgger, 1-N model) */
dkato 0:702bf7b2b7d8 435 GIC_SetLevelModel(gb_info_drv.err_irq_num, 1, 1);
dkato 0:702bf7b2b7d8 436 /* DMA error interrupt enable */
dkato 0:702bf7b2b7d8 437 GIC_EnableIRQ(gb_info_drv.err_irq_num);
dkato 0:702bf7b2b7d8 438 }
dkato 0:702bf7b2b7d8 439
dkato 0:702bf7b2b7d8 440 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 441 {
dkato 0:702bf7b2b7d8 442 /* set channel status */
dkato 0:702bf7b2b7d8 443 for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
dkato 0:702bf7b2b7d8 444 {
dkato 0:702bf7b2b7d8 445 if ((bool_t)false != p_dma_init_param->channel[ch_count])
dkato 0:702bf7b2b7d8 446 {
dkato 0:702bf7b2b7d8 447 gb_info_drv.info_ch[ch_count].ch_stat = DMA_CH_INIT;
dkato 0:702bf7b2b7d8 448 }
dkato 0:702bf7b2b7d8 449 else
dkato 0:702bf7b2b7d8 450 {
dkato 0:702bf7b2b7d8 451 gb_info_drv.info_ch[ch_count].ch_stat = DMA_CH_UNINIT;
dkato 0:702bf7b2b7d8 452 }
dkato 0:702bf7b2b7d8 453 }
dkato 0:702bf7b2b7d8 454 /* set driver status to DMA_DRV_INIT */
dkato 0:702bf7b2b7d8 455 gb_info_drv.drv_stat = DMA_DRV_INIT;
dkato 0:702bf7b2b7d8 456 }
dkato 0:702bf7b2b7d8 457
dkato 0:702bf7b2b7d8 458 return retval;
dkato 0:702bf7b2b7d8 459 }
dkato 0:702bf7b2b7d8 460
dkato 0:702bf7b2b7d8 461 /******************************************************************************
dkato 0:702bf7b2b7d8 462 End of function DMA_Initialize
dkato 0:702bf7b2b7d8 463 ******************************************************************************/
dkato 0:702bf7b2b7d8 464
dkato 0:702bf7b2b7d8 465 /******************************************************************************
dkato 0:702bf7b2b7d8 466 * Function Name: DMA_UnInitialize
dkato 0:702bf7b2b7d8 467 * Description : UnInitialize DMA driver.
dkato 0:702bf7b2b7d8 468 * Arguments : None.
dkato 0:702bf7b2b7d8 469 * Return Value : ESUCCESS -
dkato 0:702bf7b2b7d8 470 * Operation successful.
dkato 0:702bf7b2b7d8 471 * OS error num -
dkato 0:702bf7b2b7d8 472 * Unregistering handler failed,
dkato 0:702bf7b2b7d8 473 * or Semaphore release failed.
dkato 0:702bf7b2b7d8 474 ******************************************************************************/
dkato 0:702bf7b2b7d8 475
dkato 0:702bf7b2b7d8 476 int_t DMA_UnInitialize(void)
dkato 0:702bf7b2b7d8 477 {
dkato 0:702bf7b2b7d8 478 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 479 int_t ch_count;
dkato 0:702bf7b2b7d8 480 uint32_t error_code;
dkato 0:702bf7b2b7d8 481 osStatus sem_status;
dkato 0:702bf7b2b7d8 482 bool_t uninit_check_flag;
dkato 0:702bf7b2b7d8 483
dkato 0:702bf7b2b7d8 484 /* init DMA registers */
dkato 0:702bf7b2b7d8 485 for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
dkato 0:702bf7b2b7d8 486 {
dkato 0:702bf7b2b7d8 487 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCTRL_n = 0;
dkato 0:702bf7b2b7d8 488 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCFG_n = 0;
dkato 0:702bf7b2b7d8 489 *(gb_info_drv.info_ch[ch_count].p_dma_dmars_reg) = 0;
dkato 0:702bf7b2b7d8 490 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0SA_n = 0;
dkato 0:702bf7b2b7d8 491 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1SA_n = 0;
dkato 0:702bf7b2b7d8 492 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0DA_n = 0;
dkato 0:702bf7b2b7d8 493 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1DA_n = 0;
dkato 0:702bf7b2b7d8 494 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0TB_n = 0;
dkato 0:702bf7b2b7d8 495 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1TB_n = 0;
dkato 0:702bf7b2b7d8 496 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHITVL_n = 0;
dkato 0:702bf7b2b7d8 497 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHEXT_n = 0;
dkato 0:702bf7b2b7d8 498 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->NXLA_n = 0;
dkato 0:702bf7b2b7d8 499 }
dkato 0:702bf7b2b7d8 500 /* init common resgiter for channel 0 - 7 */
dkato 0:702bf7b2b7d8 501 gb_info_drv.info_ch[DMA_CH_0].p_dma_common_reg->DCTRL_0_7 = 0;
dkato 0:702bf7b2b7d8 502 /* init common resgiter for channel 8 - 15 */
dkato 0:702bf7b2b7d8 503 gb_info_drv.info_ch[HIGH_COMMON_REG_OFFSET].p_dma_common_reg->DCTRL_0_7 = 0;
dkato 0:702bf7b2b7d8 504
dkato 0:702bf7b2b7d8 505 /* uninit DMA interrupt */
dkato 0:702bf7b2b7d8 506 ch_count = 0;
dkato 0:702bf7b2b7d8 507 uninit_check_flag = false;
dkato 0:702bf7b2b7d8 508 while (false == uninit_check_flag)
dkato 0:702bf7b2b7d8 509 {
dkato 0:702bf7b2b7d8 510 /* disable DMA end interrupt */
dkato 0:702bf7b2b7d8 511 GIC_DisableIRQ(gb_info_drv.info_ch[ch_count].end_irq_num);
dkato 0:702bf7b2b7d8 512
dkato 0:702bf7b2b7d8 513 /* unregister DMA end interrupt handler */
dkato 0:702bf7b2b7d8 514 error_code = InterruptHandlerUnregister(gb_info_drv.info_ch[ch_count].end_irq_num);
dkato 0:702bf7b2b7d8 515 /* 0 is no error on InterruptHandlerUnRegister() */
dkato 0:702bf7b2b7d8 516 if (0U != error_code)
dkato 0:702bf7b2b7d8 517 {
dkato 0:702bf7b2b7d8 518 retval = (int_t)error_code;
dkato 0:702bf7b2b7d8 519 uninit_check_flag = true;
dkato 0:702bf7b2b7d8 520 }
dkato 0:702bf7b2b7d8 521 if ((DMA_CH_NUM - 1) == ch_count)
dkato 0:702bf7b2b7d8 522 {
dkato 0:702bf7b2b7d8 523 uninit_check_flag = true;
dkato 0:702bf7b2b7d8 524 }
dkato 0:702bf7b2b7d8 525 ch_count++;
dkato 0:702bf7b2b7d8 526 }
dkato 0:702bf7b2b7d8 527 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 528 {
dkato 0:702bf7b2b7d8 529 /* disable DMA error interrupt */
dkato 0:702bf7b2b7d8 530 GIC_DisableIRQ(gb_info_drv.err_irq_num);
dkato 0:702bf7b2b7d8 531
dkato 0:702bf7b2b7d8 532 /* unregister DMA interrupt error handler */
dkato 0:702bf7b2b7d8 533 error_code = InterruptHandlerUnregister(gb_info_drv.err_irq_num);
dkato 0:702bf7b2b7d8 534 /* 0 is no error on InterruptHandlerUnRegister() */
dkato 0:702bf7b2b7d8 535 if (0U != error_code)
dkato 0:702bf7b2b7d8 536 {
dkato 0:702bf7b2b7d8 537 retval = (int_t)error_code;
dkato 0:702bf7b2b7d8 538 }
dkato 0:702bf7b2b7d8 539 }
dkato 0:702bf7b2b7d8 540
dkato 0:702bf7b2b7d8 541 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 542 {
dkato 0:702bf7b2b7d8 543 /* delete channel semaphore */
dkato 0:702bf7b2b7d8 544 ch_count = 0;
dkato 0:702bf7b2b7d8 545 uninit_check_flag = false;
dkato 0:702bf7b2b7d8 546 while (false == uninit_check_flag)
dkato 0:702bf7b2b7d8 547 {
dkato 0:702bf7b2b7d8 548 /* semaphore delete */
dkato 0:702bf7b2b7d8 549 sem_status = osSemaphoreDelete(gb_info_drv.info_ch[ch_count].sem_ch);
dkato 0:702bf7b2b7d8 550 if (osOK != sem_status)
dkato 0:702bf7b2b7d8 551 {
dkato 0:702bf7b2b7d8 552 /* set error return value */
dkato 0:702bf7b2b7d8 553 retval = (int_t)sem_status;
dkato 0:702bf7b2b7d8 554 uninit_check_flag = true;
dkato 0:702bf7b2b7d8 555 }
dkato 0:702bf7b2b7d8 556 if ((DMA_CH_NUM - 1) == ch_count)
dkato 0:702bf7b2b7d8 557 {
dkato 0:702bf7b2b7d8 558 uninit_check_flag = true;
dkato 0:702bf7b2b7d8 559 }
dkato 0:702bf7b2b7d8 560 ch_count++;
dkato 0:702bf7b2b7d8 561 }
dkato 0:702bf7b2b7d8 562 }
dkato 0:702bf7b2b7d8 563
dkato 0:702bf7b2b7d8 564 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 565 {
dkato 0:702bf7b2b7d8 566 /* set channel status to DMA_CH_UNINIT */
dkato 0:702bf7b2b7d8 567 for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
dkato 0:702bf7b2b7d8 568 {
dkato 0:702bf7b2b7d8 569 gb_info_drv.info_ch[ch_count].ch_stat = DMA_CH_UNINIT;
dkato 0:702bf7b2b7d8 570 }
dkato 0:702bf7b2b7d8 571 /* set driver status to DMA_DRV_UNINIT*/
dkato 0:702bf7b2b7d8 572 gb_info_drv.drv_stat = DMA_DRV_UNINIT;
dkato 0:702bf7b2b7d8 573 }
dkato 0:702bf7b2b7d8 574
dkato 0:702bf7b2b7d8 575 return retval;
dkato 0:702bf7b2b7d8 576 }
dkato 0:702bf7b2b7d8 577
dkato 0:702bf7b2b7d8 578 /******************************************************************************
dkato 0:702bf7b2b7d8 579 End of function DMA_UnInitialize
dkato 0:702bf7b2b7d8 580 ******************************************************************************/
dkato 0:702bf7b2b7d8 581
dkato 0:702bf7b2b7d8 582 /******************************************************************************
dkato 0:702bf7b2b7d8 583 * Function Name: DMA_OpenChannel
dkato 0:702bf7b2b7d8 584 * Description : DMA channel open.
dkato 0:702bf7b2b7d8 585 * Set DMA channel status to DMA_CH_OPEN.
dkato 0:702bf7b2b7d8 586 * Arguments : channel -
dkato 0:702bf7b2b7d8 587 * Open channel number.
dkato 0:702bf7b2b7d8 588 * Return Value : None.
dkato 0:702bf7b2b7d8 589 ******************************************************************************/
dkato 0:702bf7b2b7d8 590
dkato 0:702bf7b2b7d8 591 static void DMA_OpenChannel(const int_t channel)
dkato 0:702bf7b2b7d8 592 {
dkato 0:702bf7b2b7d8 593 /* set channel status to DMA_CH_OPEN */
dkato 0:702bf7b2b7d8 594 gb_info_drv.info_ch[channel].ch_stat = DMA_CH_OPEN;
dkato 0:702bf7b2b7d8 595
dkato 0:702bf7b2b7d8 596 return;
dkato 0:702bf7b2b7d8 597 }
dkato 0:702bf7b2b7d8 598
dkato 0:702bf7b2b7d8 599 /******************************************************************************
dkato 0:702bf7b2b7d8 600 End of function DMA_OpenChannel
dkato 0:702bf7b2b7d8 601 ******************************************************************************/
dkato 0:702bf7b2b7d8 602
dkato 0:702bf7b2b7d8 603 /******************************************************************************
dkato 0:702bf7b2b7d8 604 * Function Name: DMA_GetFreeChannel
dkato 0:702bf7b2b7d8 605 * Description : Find free DMA channel and Get DMA channel.
dkato 0:702bf7b2b7d8 606 * Arguments : None
dkato 0:702bf7b2b7d8 607 * Return Value : channel -
dkato 0:702bf7b2b7d8 608 * Open channel number.
dkato 0:702bf7b2b7d8 609 * error code -
dkato 0:702bf7b2b7d8 610 * OS error num : Semaphore release failed.
dkato 0:702bf7b2b7d8 611 * EMFILE : When looking for a free channel, but a free channel
dkato 0:702bf7b2b7d8 612 * didn't exist.
dkato 0:702bf7b2b7d8 613 * EFAULT: Wait semaphore failed.
dkato 0:702bf7b2b7d8 614 ******************************************************************************/
dkato 0:702bf7b2b7d8 615
dkato 0:702bf7b2b7d8 616 int_t DMA_GetFreeChannel(void)
dkato 0:702bf7b2b7d8 617 {
dkato 0:702bf7b2b7d8 618 int_t retval = EFAULT;
dkato 0:702bf7b2b7d8 619 dma_info_ch_t *dma_info_ch;
dkato 0:702bf7b2b7d8 620 int_t ch_alloc;
dkato 0:702bf7b2b7d8 621 int_t sem_wait_status;
dkato 0:702bf7b2b7d8 622 osStatus sem_release_status;
dkato 0:702bf7b2b7d8 623 bool_t ch_stat_check_flag;
dkato 0:702bf7b2b7d8 624
dkato 0:702bf7b2b7d8 625 /* looking for free channel */
dkato 0:702bf7b2b7d8 626 ch_stat_check_flag = false;
dkato 0:702bf7b2b7d8 627 ch_alloc = 0;
dkato 0:702bf7b2b7d8 628 while (false == ch_stat_check_flag)
dkato 0:702bf7b2b7d8 629 {
dkato 0:702bf7b2b7d8 630 dma_info_ch = DMA_GetDrvChInfo(ch_alloc);
dkato 0:702bf7b2b7d8 631 /* start semaphore wait forever */
dkato 0:702bf7b2b7d8 632 /* check carrying out on the task (0) */
dkato 0:702bf7b2b7d8 633 if (0 == R_ExceptionalMode())
dkato 0:702bf7b2b7d8 634 {
dkato 0:702bf7b2b7d8 635 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
dkato 0:702bf7b2b7d8 636 sem_wait_status = osSemaphoreWait(dma_info_ch->sem_ch, osWaitForever);
dkato 0:702bf7b2b7d8 637 /* <-MISRA 10.6 */
dkato 0:702bf7b2b7d8 638 /* semaphore error check */
dkato 0:702bf7b2b7d8 639 if ((-1) == sem_wait_status)
dkato 0:702bf7b2b7d8 640 {
dkato 0:702bf7b2b7d8 641 /* set error return value */
dkato 0:702bf7b2b7d8 642 retval = EFAULT;
dkato 0:702bf7b2b7d8 643 ch_stat_check_flag = true;
dkato 0:702bf7b2b7d8 644 }
dkato 0:702bf7b2b7d8 645 }
dkato 0:702bf7b2b7d8 646
dkato 0:702bf7b2b7d8 647 if (false == ch_stat_check_flag)
dkato 0:702bf7b2b7d8 648 {
dkato 0:702bf7b2b7d8 649 if (DMA_CH_INIT == dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 650 {
dkato 0:702bf7b2b7d8 651 DMA_OpenChannel(ch_alloc);
dkato 0:702bf7b2b7d8 652 retval = ch_alloc;
dkato 0:702bf7b2b7d8 653 /* semaphore release */
dkato 0:702bf7b2b7d8 654 /* check carrying out on the task (0) */
dkato 0:702bf7b2b7d8 655 if (0 == R_ExceptionalMode())
dkato 0:702bf7b2b7d8 656 {
dkato 0:702bf7b2b7d8 657 sem_release_status = osSemaphoreRelease(dma_info_ch->sem_ch);
dkato 0:702bf7b2b7d8 658 /* semaphore error check */
dkato 0:702bf7b2b7d8 659 if (osOK != sem_release_status)
dkato 0:702bf7b2b7d8 660 {
dkato 0:702bf7b2b7d8 661 /* set error return value */
dkato 0:702bf7b2b7d8 662 retval = (int_t)sem_release_status;
dkato 0:702bf7b2b7d8 663 }
dkato 0:702bf7b2b7d8 664 }
dkato 0:702bf7b2b7d8 665 ch_stat_check_flag = true;
dkato 0:702bf7b2b7d8 666 }
dkato 0:702bf7b2b7d8 667 else
dkato 0:702bf7b2b7d8 668 {
dkato 0:702bf7b2b7d8 669 /* semaphore release */
dkato 0:702bf7b2b7d8 670 /* check carrying out on the task (0) */
dkato 0:702bf7b2b7d8 671 if (0 == R_ExceptionalMode())
dkato 0:702bf7b2b7d8 672 {
dkato 0:702bf7b2b7d8 673 sem_release_status = osSemaphoreRelease(dma_info_ch->sem_ch);
dkato 0:702bf7b2b7d8 674 /* semaphore error check */
dkato 0:702bf7b2b7d8 675 if (osOK != sem_release_status)
dkato 0:702bf7b2b7d8 676 {
dkato 0:702bf7b2b7d8 677 /* set error return value */
dkato 0:702bf7b2b7d8 678 retval = (int_t)sem_release_status;
dkato 0:702bf7b2b7d8 679 ch_stat_check_flag = true;
dkato 0:702bf7b2b7d8 680 }
dkato 0:702bf7b2b7d8 681 }
dkato 0:702bf7b2b7d8 682 }
dkato 0:702bf7b2b7d8 683 if (false == ch_stat_check_flag)
dkato 0:702bf7b2b7d8 684 {
dkato 0:702bf7b2b7d8 685 ch_alloc++;
dkato 0:702bf7b2b7d8 686 /* not detected free channel */
dkato 0:702bf7b2b7d8 687 if (DMA_CH_NUM == ch_alloc)
dkato 0:702bf7b2b7d8 688 {
dkato 0:702bf7b2b7d8 689 /* set error return value */
dkato 0:702bf7b2b7d8 690 retval = EMFILE;
dkato 0:702bf7b2b7d8 691 ch_stat_check_flag = true;
dkato 0:702bf7b2b7d8 692 }
dkato 0:702bf7b2b7d8 693 }
dkato 0:702bf7b2b7d8 694 }
dkato 0:702bf7b2b7d8 695 }
dkato 0:702bf7b2b7d8 696
dkato 0:702bf7b2b7d8 697 return retval;
dkato 0:702bf7b2b7d8 698 }
dkato 0:702bf7b2b7d8 699
dkato 0:702bf7b2b7d8 700 /******************************************************************************
dkato 0:702bf7b2b7d8 701 End of function DMA_GetFreeChannel
dkato 0:702bf7b2b7d8 702 ******************************************************************************/
dkato 0:702bf7b2b7d8 703
dkato 0:702bf7b2b7d8 704 /******************************************************************************
dkato 0:702bf7b2b7d8 705 * Function Name: DMA_GetFixedChannel
dkato 0:702bf7b2b7d8 706 * Description : Get specified DMA channel number.
dkato 0:702bf7b2b7d8 707 * Arguments : channel -
dkato 0:702bf7b2b7d8 708 * Open channel number.
dkato 0:702bf7b2b7d8 709 * Return Value : channel -
dkato 0:702bf7b2b7d8 710 * Open channel number.
dkato 0:702bf7b2b7d8 711 * error code -
dkato 0:702bf7b2b7d8 712 * OS error num : Semaphore release failed.
dkato 0:702bf7b2b7d8 713 * EBUSY : It has been allocated already in channel.
dkato 0:702bf7b2b7d8 714 * ENOTSUP : Channel status is DMA_CH_UNINIT.
dkato 0:702bf7b2b7d8 715 * EFAULT: Channel status is besides the status definded in
dkato 0:702bf7b2b7d8 716 * dma_stat_ch_t.
dkato 0:702bf7b2b7d8 717 * Wait semaphore failed.
dkato 0:702bf7b2b7d8 718 ******************************************************************************/
dkato 0:702bf7b2b7d8 719
dkato 0:702bf7b2b7d8 720 int_t DMA_GetFixedChannel(const int_t channel)
dkato 0:702bf7b2b7d8 721 {
dkato 0:702bf7b2b7d8 722 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 723 dma_info_ch_t *dma_info_ch;
dkato 0:702bf7b2b7d8 724 int_t sem_wait_status;
dkato 0:702bf7b2b7d8 725 osStatus sem_release_status;
dkato 0:702bf7b2b7d8 726
dkato 0:702bf7b2b7d8 727 /* allocate the specified number */
dkato 0:702bf7b2b7d8 728 dma_info_ch = DMA_GetDrvChInfo(channel);
dkato 0:702bf7b2b7d8 729 /* start semaphore wait forever */
dkato 0:702bf7b2b7d8 730 /* check carrying out on the task (0) */
dkato 0:702bf7b2b7d8 731 if (0 == R_ExceptionalMode())
dkato 0:702bf7b2b7d8 732 {
dkato 0:702bf7b2b7d8 733 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
dkato 0:702bf7b2b7d8 734 sem_wait_status = osSemaphoreWait(dma_info_ch->sem_ch, osWaitForever);
dkato 0:702bf7b2b7d8 735 /* <-MISRA 10.6 */
dkato 0:702bf7b2b7d8 736 /* semaphore error check */
dkato 0:702bf7b2b7d8 737 if ((-1) == sem_wait_status)
dkato 0:702bf7b2b7d8 738 {
dkato 0:702bf7b2b7d8 739 /* set error return value */
dkato 0:702bf7b2b7d8 740 retval = EFAULT;
dkato 0:702bf7b2b7d8 741 }
dkato 0:702bf7b2b7d8 742 }
dkato 0:702bf7b2b7d8 743
dkato 0:702bf7b2b7d8 744 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 745 {
dkato 0:702bf7b2b7d8 746 if (DMA_CH_INIT == dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 747 {
dkato 0:702bf7b2b7d8 748 DMA_OpenChannel(channel);
dkato 0:702bf7b2b7d8 749 /* return alloc channel number */
dkato 0:702bf7b2b7d8 750 retval = channel;
dkato 0:702bf7b2b7d8 751 }
dkato 0:702bf7b2b7d8 752 else
dkato 0:702bf7b2b7d8 753 {
dkato 0:702bf7b2b7d8 754 /* set error return value */
dkato 0:702bf7b2b7d8 755 switch (dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 756 {
dkato 0:702bf7b2b7d8 757 case DMA_CH_UNINIT:
dkato 0:702bf7b2b7d8 758 retval = ENOTSUP;
dkato 0:702bf7b2b7d8 759 break;
dkato 0:702bf7b2b7d8 760 /* These 2 cases are intentionally combined. */
dkato 0:702bf7b2b7d8 761 case DMA_CH_OPEN:
dkato 0:702bf7b2b7d8 762 case DMA_CH_TRANSFER:
dkato 0:702bf7b2b7d8 763 retval = EBUSY;
dkato 0:702bf7b2b7d8 764 break;
dkato 0:702bf7b2b7d8 765
dkato 0:702bf7b2b7d8 766 default:
dkato 0:702bf7b2b7d8 767 retval = EFAULT;
dkato 0:702bf7b2b7d8 768 break;
dkato 0:702bf7b2b7d8 769
dkato 0:702bf7b2b7d8 770 }
dkato 0:702bf7b2b7d8 771 }
dkato 0:702bf7b2b7d8 772 /* semaphore release */
dkato 0:702bf7b2b7d8 773 /* check carrying out on the task (0) */
dkato 0:702bf7b2b7d8 774 if (0 == R_ExceptionalMode())
dkato 0:702bf7b2b7d8 775 {
dkato 0:702bf7b2b7d8 776 sem_release_status = osSemaphoreRelease(dma_info_ch->sem_ch);
dkato 0:702bf7b2b7d8 777 /* semaphore error check */
dkato 0:702bf7b2b7d8 778 if (osOK != sem_release_status)
dkato 0:702bf7b2b7d8 779 {
dkato 0:702bf7b2b7d8 780 /* set error return value */
dkato 0:702bf7b2b7d8 781 retval = (int_t)sem_release_status;
dkato 0:702bf7b2b7d8 782 }
dkato 0:702bf7b2b7d8 783 }
dkato 0:702bf7b2b7d8 784 }
dkato 0:702bf7b2b7d8 785
dkato 0:702bf7b2b7d8 786 return retval;
dkato 0:702bf7b2b7d8 787 }
dkato 0:702bf7b2b7d8 788
dkato 0:702bf7b2b7d8 789 /******************************************************************************
dkato 0:702bf7b2b7d8 790 End of function DMA_GetFixedChannel
dkato 0:702bf7b2b7d8 791 ******************************************************************************/
dkato 0:702bf7b2b7d8 792
dkato 0:702bf7b2b7d8 793 /******************************************************************************
dkato 0:702bf7b2b7d8 794 * Function Name: DMA_CloseChannel
dkato 0:702bf7b2b7d8 795 * Description : DMA channel close.
dkato 0:702bf7b2b7d8 796 * Set DMA channel status to DMA_CH_INIT.
dkato 0:702bf7b2b7d8 797 * Arguments : channel -
dkato 0:702bf7b2b7d8 798 * Close channel number.
dkato 0:702bf7b2b7d8 799 * Return Value : None.
dkato 0:702bf7b2b7d8 800 ******************************************************************************/
dkato 0:702bf7b2b7d8 801
dkato 0:702bf7b2b7d8 802 void DMA_CloseChannel(const int_t channel)
dkato 0:702bf7b2b7d8 803 {
dkato 0:702bf7b2b7d8 804 int_t was_masked;
dkato 0:702bf7b2b7d8 805
dkato 0:702bf7b2b7d8 806 /* disable all irq */
dkato 0:702bf7b2b7d8 807 was_masked = __disable_irq();
dkato 0:702bf7b2b7d8 808 /* clear DMARS register */
dkato 0:702bf7b2b7d8 809 *(gb_info_drv.info_ch[channel].p_dma_dmars_reg) &= gb_info_drv.info_ch[channel].mask_dmars;
dkato 0:702bf7b2b7d8 810 if (0 == was_masked)
dkato 0:702bf7b2b7d8 811 {
dkato 0:702bf7b2b7d8 812 /* enable all irq */
dkato 0:702bf7b2b7d8 813 __enable_irq();
dkato 0:702bf7b2b7d8 814
dkato 0:702bf7b2b7d8 815 }
dkato 0:702bf7b2b7d8 816 /* set channel status to DMA_CH_INIT */
dkato 0:702bf7b2b7d8 817 gb_info_drv.info_ch[channel].ch_stat = DMA_CH_INIT;
dkato 0:702bf7b2b7d8 818
dkato 0:702bf7b2b7d8 819 return;
dkato 0:702bf7b2b7d8 820 }
dkato 0:702bf7b2b7d8 821
dkato 0:702bf7b2b7d8 822 /******************************************************************************
dkato 0:702bf7b2b7d8 823 End of function DMA_CloseChannel
dkato 0:702bf7b2b7d8 824 ******************************************************************************/
dkato 0:702bf7b2b7d8 825
dkato 0:702bf7b2b7d8 826 /******************************************************************************
dkato 0:702bf7b2b7d8 827 * Function Name: DMA_Setparam
dkato 0:702bf7b2b7d8 828 * Description : Set DMA transfer parameter to Register.
dkato 0:702bf7b2b7d8 829 * Arguments : channel -
dkato 0:702bf7b2b7d8 830 * Set up channel number.
dkato 0:702bf7b2b7d8 831 * *p_ch_setup -
dkato 0:702bf7b2b7d8 832 * Set up parameters.
dkato 0:702bf7b2b7d8 833 * *p_ch_cfg -
dkato 0:702bf7b2b7d8 834 * DMA channel config table parameters.
dkato 0:702bf7b2b7d8 835 * *reqd
dkato 0:702bf7b2b7d8 836 * set vaule for REQD bit on CHCFG
dkato 0:702bf7b2b7d8 837 * Return Value : None.
dkato 0:702bf7b2b7d8 838 ******************************************************************************/
dkato 0:702bf7b2b7d8 839
dkato 0:702bf7b2b7d8 840 void DMA_SetParam(const int_t channel, const dma_ch_setup_t *const p_ch_setup,
dkato 0:702bf7b2b7d8 841 const dma_ch_cfg_t * const p_ch_cfg, const uint32_t reqd)
dkato 0:702bf7b2b7d8 842 {
dkato 0:702bf7b2b7d8 843 uint32_t chcfg_sel;
dkato 0:702bf7b2b7d8 844 uint32_t value_dmars;
dkato 0:702bf7b2b7d8 845 int_t was_masked;
dkato 0:702bf7b2b7d8 846
dkato 0:702bf7b2b7d8 847 /* set DMA transfer parameter to DMA channel infomation */
dkato 0:702bf7b2b7d8 848 gb_info_drv.info_ch[channel].resource = p_ch_setup->resource;
dkato 0:702bf7b2b7d8 849 gb_info_drv.info_ch[channel].direction = p_ch_setup->direction;
dkato 0:702bf7b2b7d8 850 gb_info_drv.info_ch[channel].src_width = p_ch_setup->src_width;
dkato 0:702bf7b2b7d8 851 gb_info_drv.info_ch[channel].src_cnt = p_ch_setup->src_cnt;
dkato 0:702bf7b2b7d8 852 gb_info_drv.info_ch[channel].dst_width = p_ch_setup->dst_width;
dkato 0:702bf7b2b7d8 853 gb_info_drv.info_ch[channel].dst_cnt = p_ch_setup->dst_cnt;
dkato 0:702bf7b2b7d8 854 gb_info_drv.info_ch[channel].p_end_aio = p_ch_setup->p_aio;
dkato 0:702bf7b2b7d8 855
dkato 0:702bf7b2b7d8 856 /* disable all irq */
dkato 0:702bf7b2b7d8 857 was_masked = __disable_irq();
dkato 0:702bf7b2b7d8 858 /* set DMARS value and protect non change bit */
dkato 0:702bf7b2b7d8 859 value_dmars = *(gb_info_drv.info_ch[channel].p_dma_dmars_reg);
dkato 0:702bf7b2b7d8 860 value_dmars = ((value_dmars & gb_info_drv.info_ch[channel].mask_dmars) |
dkato 0:702bf7b2b7d8 861 (uint32_t)(p_ch_cfg->dmars << gb_info_drv.info_ch[channel].shift_dmars));
dkato 0:702bf7b2b7d8 862 /* set DMARS register value */
dkato 0:702bf7b2b7d8 863 *(gb_info_drv.info_ch[channel].p_dma_dmars_reg) = value_dmars;
dkato 0:702bf7b2b7d8 864 if (0 == was_masked)
dkato 0:702bf7b2b7d8 865 {
dkato 0:702bf7b2b7d8 866 /* enable all irq */
dkato 0:702bf7b2b7d8 867 __enable_irq();
dkato 0:702bf7b2b7d8 868 }
dkato 0:702bf7b2b7d8 869
dkato 0:702bf7b2b7d8 870 /* set CHCFG regsiter */
dkato 0:702bf7b2b7d8 871 if (channel < HIGH_COMMON_REG_OFFSET)
dkato 0:702bf7b2b7d8 872 {
dkato 0:702bf7b2b7d8 873 chcfg_sel = (uint32_t)channel;
dkato 0:702bf7b2b7d8 874 }
dkato 0:702bf7b2b7d8 875 else
dkato 0:702bf7b2b7d8 876 {
dkato 0:702bf7b2b7d8 877 chcfg_sel = (uint32_t)(channel - HIGH_COMMON_REG_OFFSET);
dkato 0:702bf7b2b7d8 878 }
dkato 0:702bf7b2b7d8 879 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n
dkato 0:702bf7b2b7d8 880 = ((uint32_t)CHCFG_FIXED_VALUE |
dkato 0:702bf7b2b7d8 881 /* ->MISRA 21.1 ,IPA R2.4.1 The value of every parameter won't be minus.
dkato 0:702bf7b2b7d8 882 and the value after a shift will be less than 0x80000000 certainly.
dkato 0:702bf7b2b7d8 883 */
dkato 0:702bf7b2b7d8 884 (((uint32_t)p_ch_setup->dst_cnt << CHCFG_SHIFT_DAD) & CHCFG_MASK_DAD) |
dkato 0:702bf7b2b7d8 885 (((uint32_t)p_ch_setup->src_cnt << CHCFG_SHIFT_SAD) & CHCFG_MASK_SAD) |
dkato 0:702bf7b2b7d8 886 (((uint32_t)p_ch_setup->dst_width << CHCFG_SHIFT_DDS) & CHCFG_MASK_DDS) |
dkato 0:702bf7b2b7d8 887 (((uint32_t)p_ch_setup->src_width << CHCFG_SHIFT_SDS) & CHCFG_MASK_SDS) |
dkato 0:702bf7b2b7d8 888 /* <-MISRA 21.1, IPA R2.4.1 */
dkato 0:702bf7b2b7d8 889 p_ch_cfg->tm |
dkato 0:702bf7b2b7d8 890 p_ch_cfg->lvl |
dkato 0:702bf7b2b7d8 891 reqd |
dkato 0:702bf7b2b7d8 892 chcfg_sel);
dkato 0:702bf7b2b7d8 893
dkato 0:702bf7b2b7d8 894 /* set setup flag */
dkato 0:702bf7b2b7d8 895 gb_info_drv.info_ch[channel].setup_flag = true;
dkato 0:702bf7b2b7d8 896
dkato 0:702bf7b2b7d8 897 return;
dkato 0:702bf7b2b7d8 898 }
dkato 0:702bf7b2b7d8 899
dkato 0:702bf7b2b7d8 900 /******************************************************************************
dkato 0:702bf7b2b7d8 901 End of function DMA_SetParam
dkato 0:702bf7b2b7d8 902 ******************************************************************************/
dkato 0:702bf7b2b7d8 903
dkato 0:702bf7b2b7d8 904 /******************************************************************************
dkato 0:702bf7b2b7d8 905 * Function Name: DMA_BusParam
dkato 0:702bf7b2b7d8 906 * Description : Set bus parameter for DMA.
dkato 0:702bf7b2b7d8 907 * Arguments : channel -
dkato 0:702bf7b2b7d8 908 * Set address channel number.
dkato 0:702bf7b2b7d8 909 * *p_dma_data -
dkato 0:702bf7b2b7d8 910 * DMA transfer address parameter set.
dkato 0:702bf7b2b7d8 911 * Return Value : None.
dkato 0:702bf7b2b7d8 912 ******************************************************************************/
dkato 0:702bf7b2b7d8 913
dkato 0:702bf7b2b7d8 914 void DMA_BusParam(const int_t channel, const dma_trans_data_t * const p_dma_data)
dkato 0:702bf7b2b7d8 915 {
dkato 0:702bf7b2b7d8 916 uint32_t src_bus_addr = (uint32_t)p_dma_data->src_addr;
dkato 0:702bf7b2b7d8 917 uint32_t dst_bus_addr = (uint32_t)p_dma_data->dst_addr;
dkato 0:702bf7b2b7d8 918 uint32_t chext_value = (CHEXT_SET_DPR_NON_SECURE | CHEXT_SET_SPR_NON_SECURE);
dkato 0:702bf7b2b7d8 919
dkato 0:702bf7b2b7d8 920 /* set bus parameter for SRC */
dkato 0:702bf7b2b7d8 921 if ((DMA_EXTERNAL_BUS_END >= src_bus_addr) ||
dkato 0:702bf7b2b7d8 922 ((DMA_EXTERNAL_BUS_MIRROR_START <= src_bus_addr) &&
dkato 0:702bf7b2b7d8 923 (DMA_EXTERNAL_BUS_MIRROR_END >= src_bus_addr)))
dkato 0:702bf7b2b7d8 924
dkato 0:702bf7b2b7d8 925 {
dkato 0:702bf7b2b7d8 926 chext_value |= CHEXT_SET_SCA_NORMAL;
dkato 0:702bf7b2b7d8 927 }
dkato 0:702bf7b2b7d8 928 else
dkato 0:702bf7b2b7d8 929 {
dkato 0:702bf7b2b7d8 930 chext_value |= CHEXT_SET_SCA_STRONG;
dkato 0:702bf7b2b7d8 931 }
dkato 0:702bf7b2b7d8 932
dkato 0:702bf7b2b7d8 933 /* set bus parameter for DST */
dkato 0:702bf7b2b7d8 934 if ((DMA_EXTERNAL_BUS_END >= dst_bus_addr) ||
dkato 0:702bf7b2b7d8 935 ((DMA_EXTERNAL_BUS_MIRROR_START <= dst_bus_addr) &&
dkato 0:702bf7b2b7d8 936 (DMA_EXTERNAL_BUS_MIRROR_END >= dst_bus_addr)))
dkato 0:702bf7b2b7d8 937
dkato 0:702bf7b2b7d8 938 {
dkato 0:702bf7b2b7d8 939 chext_value |= CHEXT_SET_DCA_NORMAL;
dkato 0:702bf7b2b7d8 940 }
dkato 0:702bf7b2b7d8 941 else
dkato 0:702bf7b2b7d8 942 {
dkato 0:702bf7b2b7d8 943 chext_value |= CHEXT_SET_DCA_STRONG;
dkato 0:702bf7b2b7d8 944 }
dkato 0:702bf7b2b7d8 945
dkato 0:702bf7b2b7d8 946 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHEXT_n = chext_value;
dkato 0:702bf7b2b7d8 947
dkato 0:702bf7b2b7d8 948 return;
dkato 0:702bf7b2b7d8 949 }
dkato 0:702bf7b2b7d8 950
dkato 0:702bf7b2b7d8 951 /******************************************************************************
dkato 0:702bf7b2b7d8 952 End of function DMA_BusParam
dkato 0:702bf7b2b7d8 953 ******************************************************************************/
dkato 0:702bf7b2b7d8 954
dkato 0:702bf7b2b7d8 955 /******************************************************************************
dkato 0:702bf7b2b7d8 956 * Function Name: DMA_SetData
dkato 0:702bf7b2b7d8 957 * Description : Set DMA transfer address to Register.
dkato 0:702bf7b2b7d8 958 * Arguments : channel -
dkato 0:702bf7b2b7d8 959 * Set address channel number.
dkato 0:702bf7b2b7d8 960 * *p_dma_data -
dkato 0:702bf7b2b7d8 961 * DMA transfer address parameter set.
dkato 0:702bf7b2b7d8 962 * next_register_set -
dkato 0:702bf7b2b7d8 963 * Number of next register set.
dkato 0:702bf7b2b7d8 964 * Return Value : None.
dkato 0:702bf7b2b7d8 965 ******************************************************************************/
dkato 0:702bf7b2b7d8 966
dkato 0:702bf7b2b7d8 967 void DMA_SetData(const int_t channel, const dma_trans_data_t * const p_dma_data,
dkato 0:702bf7b2b7d8 968 const uint32_t next_register_set)
dkato 0:702bf7b2b7d8 969 {
dkato 0:702bf7b2b7d8 970 if (0U == next_register_set)
dkato 0:702bf7b2b7d8 971 {
dkato 0:702bf7b2b7d8 972 /* set DMA transfer address parameters to next register set0 */
dkato 0:702bf7b2b7d8 973 gb_info_drv.info_ch[channel].src_addr0 = p_dma_data->src_addr;
dkato 0:702bf7b2b7d8 974 gb_info_drv.info_ch[channel].dst_addr0 = p_dma_data->dst_addr;
dkato 0:702bf7b2b7d8 975 gb_info_drv.info_ch[channel].count0 = p_dma_data->count;
dkato 0:702bf7b2b7d8 976
dkato 0:702bf7b2b7d8 977 /* ->MISRA 11.3 This cast is needed for setting address to register. */
dkato 0:702bf7b2b7d8 978 /* set DAM transfer addres to register */
dkato 0:702bf7b2b7d8 979 gb_info_drv.info_ch[channel].p_dma_ch_reg->N0SA_n = (uint32_t)p_dma_data->src_addr;
dkato 0:702bf7b2b7d8 980 gb_info_drv.info_ch[channel].p_dma_ch_reg->N0DA_n = (uint32_t)p_dma_data->dst_addr;
dkato 0:702bf7b2b7d8 981 /* <-MISRA 11.3 */
dkato 0:702bf7b2b7d8 982 gb_info_drv.info_ch[channel].p_dma_ch_reg->N0TB_n = p_dma_data->count;
dkato 0:702bf7b2b7d8 983 }
dkato 0:702bf7b2b7d8 984 else
dkato 0:702bf7b2b7d8 985 {
dkato 0:702bf7b2b7d8 986 /* set DMA transfer address parameters to next regiter set1 */
dkato 0:702bf7b2b7d8 987 gb_info_drv.info_ch[channel].src_addr1 = p_dma_data->src_addr;
dkato 0:702bf7b2b7d8 988 gb_info_drv.info_ch[channel].dst_addr1 = p_dma_data->dst_addr;
dkato 0:702bf7b2b7d8 989 gb_info_drv.info_ch[channel].count1 = p_dma_data->count;
dkato 0:702bf7b2b7d8 990
dkato 0:702bf7b2b7d8 991 /* ->MISRA 11.3 This cast is needed for setting address to register. */
dkato 0:702bf7b2b7d8 992 /* set DAM transfer addres to register */
dkato 0:702bf7b2b7d8 993 gb_info_drv.info_ch[channel].p_dma_ch_reg->N1SA_n = (uint32_t)p_dma_data->src_addr;
dkato 0:702bf7b2b7d8 994 gb_info_drv.info_ch[channel].p_dma_ch_reg->N1DA_n = (uint32_t)p_dma_data->dst_addr;
dkato 0:702bf7b2b7d8 995 /* <-MISRA 11.3 */
dkato 0:702bf7b2b7d8 996 gb_info_drv.info_ch[channel].p_dma_ch_reg->N1TB_n = p_dma_data->count;
dkato 0:702bf7b2b7d8 997 }
dkato 0:702bf7b2b7d8 998
dkato 0:702bf7b2b7d8 999 return;
dkato 0:702bf7b2b7d8 1000 }
dkato 0:702bf7b2b7d8 1001
dkato 0:702bf7b2b7d8 1002 /******************************************************************************
dkato 0:702bf7b2b7d8 1003 End of function DMA_SetData
dkato 0:702bf7b2b7d8 1004 ******************************************************************************/
dkato 0:702bf7b2b7d8 1005
dkato 0:702bf7b2b7d8 1006 /******************************************************************************
dkato 0:702bf7b2b7d8 1007 * Function Name: DMA_SetNextData
dkato 0:702bf7b2b7d8 1008 * Description : Set continuous DMA transfer setting.
dkato 0:702bf7b2b7d8 1009 * Arguments : channel -
dkato 0:702bf7b2b7d8 1010 * Set continuous DMA transfer channel number.
dkato 0:702bf7b2b7d8 1011 * *p_dma_data -
dkato 0:702bf7b2b7d8 1012 * DMA transfer address parameter set.
dkato 0:702bf7b2b7d8 1013 * Return Value : None.
dkato 0:702bf7b2b7d8 1014 ******************************************************************************/
dkato 0:702bf7b2b7d8 1015
dkato 0:702bf7b2b7d8 1016 void DMA_SetNextData(const int_t channel, const dma_trans_data_t * const p_dma_data)
dkato 0:702bf7b2b7d8 1017 {
dkato 0:702bf7b2b7d8 1018 uint32_t next_register_set;
dkato 0:702bf7b2b7d8 1019
dkato 0:702bf7b2b7d8 1020 /* check number of next register set for next DMA transfer */
dkato 0:702bf7b2b7d8 1021 /* The reverse number in current number is set in next regsiter set of next DMA. */
dkato 0:702bf7b2b7d8 1022 if (0U == (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_SR))
dkato 0:702bf7b2b7d8 1023 {
dkato 0:702bf7b2b7d8 1024 next_register_set = 1U;
dkato 0:702bf7b2b7d8 1025 }
dkato 0:702bf7b2b7d8 1026 else
dkato 0:702bf7b2b7d8 1027 {
dkato 0:702bf7b2b7d8 1028 next_register_set = 0U;
dkato 0:702bf7b2b7d8 1029 }
dkato 0:702bf7b2b7d8 1030
dkato 0:702bf7b2b7d8 1031 /* set DMA transfer address for next DMA */
dkato 0:702bf7b2b7d8 1032 DMA_SetData(channel, p_dma_data, next_register_set);
dkato 0:702bf7b2b7d8 1033
dkato 0:702bf7b2b7d8 1034 /* start setting for next DMA */
dkato 0:702bf7b2b7d8 1035 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n |= (uint32_t)(CHCFG_SET_REN | CHCFG_SET_RSW);
dkato 0:702bf7b2b7d8 1036
dkato 0:702bf7b2b7d8 1037 /* set flag wich indicates that next DMA transfer set already */
dkato 0:702bf7b2b7d8 1038 gb_info_drv.info_ch[channel].next_dma_flag = true;
dkato 0:702bf7b2b7d8 1039
dkato 0:702bf7b2b7d8 1040 /* auto restart continous DMA */
dkato 0:702bf7b2b7d8 1041 if ((0U == (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_EN)) &&
dkato 0:702bf7b2b7d8 1042 (false == gb_info_drv.info_ch[channel].setup_flag))
dkato 0:702bf7b2b7d8 1043 {
dkato 0:702bf7b2b7d8 1044 /* auto restart DMA */
dkato 0:702bf7b2b7d8 1045 DMA_SetData(channel, p_dma_data, 0);
dkato 0:702bf7b2b7d8 1046 DMA_Start(channel, true);
dkato 0:702bf7b2b7d8 1047 }
dkato 0:702bf7b2b7d8 1048
dkato 0:702bf7b2b7d8 1049 return;
dkato 0:702bf7b2b7d8 1050 }
dkato 0:702bf7b2b7d8 1051
dkato 0:702bf7b2b7d8 1052 /******************************************************************************
dkato 0:702bf7b2b7d8 1053 End of function DMA_Nextdata
dkato 0:702bf7b2b7d8 1054 ******************************************************************************/
dkato 0:702bf7b2b7d8 1055
dkato 0:702bf7b2b7d8 1056 /******************************************************************************
dkato 0:702bf7b2b7d8 1057 * Function Name: DMA_Start
dkato 0:702bf7b2b7d8 1058 * Description : Start DMA transfer.
dkato 0:702bf7b2b7d8 1059 * Arguments : channel -
dkato 0:702bf7b2b7d8 1060 * DMA transfer start channel number.
dkato 0:702bf7b2b7d8 1061 * :restart_flag -
dkato 0:702bf7b2b7d8 1062 * Flag of DMA continous transfer auto restart.
dkato 0:702bf7b2b7d8 1063 * Return Value : None.
dkato 0:702bf7b2b7d8 1064 ******************************************************************************/
dkato 0:702bf7b2b7d8 1065
dkato 0:702bf7b2b7d8 1066 void DMA_Start(const int_t channel, const bool_t restart_flag)
dkato 0:702bf7b2b7d8 1067 {
dkato 0:702bf7b2b7d8 1068 if (false != restart_flag)
dkato 0:702bf7b2b7d8 1069 {
dkato 0:702bf7b2b7d8 1070 /* clear continous DMA setting */
dkato 0:702bf7b2b7d8 1071 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &=
dkato 0:702bf7b2b7d8 1072 ~(uint32_t)(CHCFG_SET_RSW | CHCFG_SET_RSEL | CHCFG_SET_REN);
dkato 0:702bf7b2b7d8 1073 gb_info_drv.info_ch[channel].next_dma_flag = false;
dkato 0:702bf7b2b7d8 1074 }
dkato 0:702bf7b2b7d8 1075
dkato 0:702bf7b2b7d8 1076 /* clear setup flag */
dkato 0:702bf7b2b7d8 1077 gb_info_drv.info_ch[channel].setup_flag = false;
dkato 0:702bf7b2b7d8 1078
dkato 0:702bf7b2b7d8 1079 /* reset DMA */
dkato 0:702bf7b2b7d8 1080 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = CHCTRL_SET_SWRST;
dkato 0:702bf7b2b7d8 1081
dkato 0:702bf7b2b7d8 1082 /* clear mask of DMA transfer end */
dkato 0:702bf7b2b7d8 1083 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &= ~((uint32_t)CHCFG_SET_DEM);
dkato 0:702bf7b2b7d8 1084
dkato 0:702bf7b2b7d8 1085 GIC_EnableIRQ(gb_info_drv.info_ch[channel].end_irq_num);
dkato 0:702bf7b2b7d8 1086
dkato 0:702bf7b2b7d8 1087 /* start DMA transfer */
dkato 0:702bf7b2b7d8 1088 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = CHCTRL_SET_SETEN;
dkato 0:702bf7b2b7d8 1089
dkato 0:702bf7b2b7d8 1090 /* set channel status to DMA_CH_TRANSFER */
dkato 0:702bf7b2b7d8 1091 gb_info_drv.info_ch[channel].ch_stat = DMA_CH_TRANSFER;
dkato 0:702bf7b2b7d8 1092
dkato 0:702bf7b2b7d8 1093 return;
dkato 0:702bf7b2b7d8 1094 }
dkato 0:702bf7b2b7d8 1095
dkato 0:702bf7b2b7d8 1096 /******************************************************************************
dkato 0:702bf7b2b7d8 1097 End of function DMA_Start
dkato 0:702bf7b2b7d8 1098 ******************************************************************************/
dkato 0:702bf7b2b7d8 1099
dkato 0:702bf7b2b7d8 1100 /******************************************************************************
dkato 0:702bf7b2b7d8 1101 * Function Name: DMA_Stop
dkato 0:702bf7b2b7d8 1102 * Description : Stop DMA transfer.
dkato 0:702bf7b2b7d8 1103 * Arguments : channel -
dkato 0:702bf7b2b7d8 1104 * DMA transfer start channel number.
dkato 0:702bf7b2b7d8 1105 * *p_remain -
dkato 0:702bf7b2b7d8 1106 * Remain data size of DMA transfer.
dkato 0:702bf7b2b7d8 1107 * Return Value : None.
dkato 0:702bf7b2b7d8 1108 ******************************************************************************/
dkato 0:702bf7b2b7d8 1109
dkato 0:702bf7b2b7d8 1110 void DMA_Stop(const int_t channel, uint32_t * const p_remain)
dkato 0:702bf7b2b7d8 1111 {
dkato 0:702bf7b2b7d8 1112 uint32_t stop_wait_cnt;
dkato 0:702bf7b2b7d8 1113
dkato 0:702bf7b2b7d8 1114 /* disable DMA end interrupt */
dkato 0:702bf7b2b7d8 1115 GIC_DisableIRQ(gb_info_drv.info_ch[channel].end_irq_num);
dkato 0:702bf7b2b7d8 1116
dkato 0:702bf7b2b7d8 1117 /* stop DMA transfer */
dkato 0:702bf7b2b7d8 1118 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = CHCTRL_SET_CLREN;
dkato 0:702bf7b2b7d8 1119
dkato 0:702bf7b2b7d8 1120 /* wait DMA stop */
dkato 0:702bf7b2b7d8 1121 stop_wait_cnt = 0;
dkato 0:702bf7b2b7d8 1122 while ((0 != (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_TACT)) &&
dkato 0:702bf7b2b7d8 1123 (DMA_STOP_WAIT_MAX_CNT > stop_wait_cnt))
dkato 0:702bf7b2b7d8 1124 {
dkato 0:702bf7b2b7d8 1125 stop_wait_cnt++;
dkato 0:702bf7b2b7d8 1126 }
dkato 0:702bf7b2b7d8 1127
dkato 0:702bf7b2b7d8 1128 if (DMA_STOP_WAIT_MAX_CNT <= stop_wait_cnt)
dkato 0:702bf7b2b7d8 1129 {
dkato 0:702bf7b2b7d8 1130 /* NON_NOTICE_ASSERT: wait count is abnormal value (usually, a count is set to 0 or 1) */
dkato 0:702bf7b2b7d8 1131 }
dkato 0:702bf7b2b7d8 1132
dkato 0:702bf7b2b7d8 1133 /* get remain data size */
dkato 0:702bf7b2b7d8 1134 *p_remain = gb_info_drv.info_ch[channel].p_dma_ch_reg->CRTB_n;
dkato 0:702bf7b2b7d8 1135
dkato 0:702bf7b2b7d8 1136 /* set mask of DMA transfer end */
dkato 0:702bf7b2b7d8 1137 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n |= (uint32_t)CHCFG_SET_DEM;
dkato 0:702bf7b2b7d8 1138
dkato 0:702bf7b2b7d8 1139 /* clear setting of continuous DMA */
dkato 0:702bf7b2b7d8 1140 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &= ~(uint32_t)(CHCFG_SET_RSW | CHCFG_SET_RSEL);
dkato 0:702bf7b2b7d8 1141
dkato 0:702bf7b2b7d8 1142 /* clear TC, END bit */
dkato 0:702bf7b2b7d8 1143 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = (CHCTRL_SET_CLRTC | CHCTRL_SET_CLREND);
dkato 0:702bf7b2b7d8 1144
dkato 0:702bf7b2b7d8 1145 /* clear flag wich indicates that next DMA transfer set already */
dkato 0:702bf7b2b7d8 1146 gb_info_drv.info_ch[channel].next_dma_flag = false;
dkato 0:702bf7b2b7d8 1147
dkato 0:702bf7b2b7d8 1148 /* interrupt clear, if interrupt occured already */
dkato 0:702bf7b2b7d8 1149 GIC_ClearPendingIRQ(gb_info_drv.info_ch[channel].end_irq_num);
dkato 0:702bf7b2b7d8 1150
dkato 0:702bf7b2b7d8 1151 /* set channel status to DMA_CH_OPEN */
dkato 0:702bf7b2b7d8 1152 gb_info_drv.info_ch[channel].ch_stat = DMA_CH_OPEN;
dkato 0:702bf7b2b7d8 1153
dkato 0:702bf7b2b7d8 1154 return;
dkato 0:702bf7b2b7d8 1155 }
dkato 0:702bf7b2b7d8 1156
dkato 0:702bf7b2b7d8 1157 /******************************************************************************
dkato 0:702bf7b2b7d8 1158 End of function DMA_Stop
dkato 0:702bf7b2b7d8 1159 ******************************************************************************/
dkato 0:702bf7b2b7d8 1160
dkato 0:702bf7b2b7d8 1161 /******************************************************************************
dkato 0:702bf7b2b7d8 1162 * Function Name: DMA_SetErrCode
dkato 0:702bf7b2b7d8 1163 * Description : Set error code to error code pointer.
dkato 0:702bf7b2b7d8 1164 * If error code pointer is NULL, nothing is done.
dkato 0:702bf7b2b7d8 1165 * Arguments : error_code -
dkato 0:702bf7b2b7d8 1166 * Error code.
dkato 0:702bf7b2b7d8 1167 * *p_errno -
dkato 0:702bf7b2b7d8 1168 * Pointer of set error code.
dkato 0:702bf7b2b7d8 1169 * Return Value : None.
dkato 0:702bf7b2b7d8 1170 ******************************************************************************/
dkato 0:702bf7b2b7d8 1171
dkato 0:702bf7b2b7d8 1172 void DMA_SetErrCode(const int_t error_code, int32_t * const p_errno)
dkato 0:702bf7b2b7d8 1173 {
dkato 0:702bf7b2b7d8 1174 if (NULL != p_errno)
dkato 0:702bf7b2b7d8 1175 {
dkato 0:702bf7b2b7d8 1176 *p_errno = error_code;
dkato 0:702bf7b2b7d8 1177 }
dkato 0:702bf7b2b7d8 1178
dkato 0:702bf7b2b7d8 1179 return;
dkato 0:702bf7b2b7d8 1180 }
dkato 0:702bf7b2b7d8 1181
dkato 0:702bf7b2b7d8 1182 /******************************************************************************
dkato 0:702bf7b2b7d8 1183 End of function DMA_SetErrCode
dkato 0:702bf7b2b7d8 1184 ******************************************************************************/
dkato 0:702bf7b2b7d8 1185
dkato 0:702bf7b2b7d8 1186 /******************************************************************************
dkato 0:702bf7b2b7d8 1187 * Function Name: R_DMA_ErrInterruptHandler
dkato 0:702bf7b2b7d8 1188 * Description : DMA error interrupt handler.
dkato 0:702bf7b2b7d8 1189 * Notify error information to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1190 * Arguments : None.
dkato 0:702bf7b2b7d8 1191 * Return Value : None.
dkato 0:702bf7b2b7d8 1192 * Note: store error code (EIO) to AIOCB member.
dkato 0:702bf7b2b7d8 1193 ******************************************************************************/
dkato 0:702bf7b2b7d8 1194
dkato 0:702bf7b2b7d8 1195 static void R_DMA_ErrInterruptHandler(void)
dkato 0:702bf7b2b7d8 1196 {
dkato 0:702bf7b2b7d8 1197 uint32_t dstat_er_0_7;
dkato 0:702bf7b2b7d8 1198 uint32_t dstat_er_8_15;
dkato 0:702bf7b2b7d8 1199
dkato 0:702bf7b2b7d8 1200 if (NULL != gb_info_drv.p_err_aio)
dkato 0:702bf7b2b7d8 1201 {
dkato 0:702bf7b2b7d8 1202 /* get error channel number */
dkato 0:702bf7b2b7d8 1203 dstat_er_0_7 = gb_info_drv.info_ch[DMA_CH_0].p_dma_common_reg->DSTAT_ER_0_7;
dkato 0:702bf7b2b7d8 1204 dstat_er_8_15 = gb_info_drv.info_ch[HIGH_COMMON_REG_OFFSET].p_dma_common_reg->DSTAT_ER_0_7;
dkato 0:702bf7b2b7d8 1205
dkato 0:702bf7b2b7d8 1206 /* set error infrmation */
dkato 0:702bf7b2b7d8 1207 gb_info_drv.p_err_aio->aio_sigevent.sigev_value.sival_int = (int_t)(dstat_er_0_7 | (dstat_er_8_15 << HIGH_COMMON_REG_OFFSET));
dkato 0:702bf7b2b7d8 1208
dkato 0:702bf7b2b7d8 1209 /* set error code (EIO) */
dkato 0:702bf7b2b7d8 1210 gb_info_drv.p_err_aio->aio_return = EIO;
dkato 0:702bf7b2b7d8 1211
dkato 0:702bf7b2b7d8 1212 /* call back to the module function which called DMA driver */
dkato 0:702bf7b2b7d8 1213 ahf_complete(NULL, gb_info_drv.p_err_aio);
dkato 0:702bf7b2b7d8 1214 }
dkato 0:702bf7b2b7d8 1215 else
dkato 0:702bf7b2b7d8 1216 {
dkato 0:702bf7b2b7d8 1217 ;
dkato 0:702bf7b2b7d8 1218 /* NON_NOTICE_ASSERT:<callback pointer is NULL> */
dkato 0:702bf7b2b7d8 1219 }
dkato 0:702bf7b2b7d8 1220
dkato 0:702bf7b2b7d8 1221 }
dkato 0:702bf7b2b7d8 1222
dkato 0:702bf7b2b7d8 1223 /******************************************************************************
dkato 0:702bf7b2b7d8 1224 End of function R_DMA_ErrInteruuptHandler
dkato 0:702bf7b2b7d8 1225 ******************************************************************************/
dkato 0:702bf7b2b7d8 1226
dkato 0:702bf7b2b7d8 1227 /******************************************************************************
dkato 0:702bf7b2b7d8 1228 * Function Name: R_DMA_End0InterruptHandler
dkato 0:702bf7b2b7d8 1229 * Description : DMA end interrupt handler for channel 0.
dkato 0:702bf7b2b7d8 1230 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1231 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1232 * Arguments : None.
dkato 0:702bf7b2b7d8 1233 * Return Value : None.
dkato 0:702bf7b2b7d8 1234 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1235 * ESUCCESS -
dkato 0:702bf7b2b7d8 1236 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1237 * EIO -
dkato 0:702bf7b2b7d8 1238 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1239 ******************************************************************************/
dkato 0:702bf7b2b7d8 1240
dkato 0:702bf7b2b7d8 1241 static void R_DMA_End0InterruptHandler(void)
dkato 0:702bf7b2b7d8 1242 {
dkato 0:702bf7b2b7d8 1243
dkato 0:702bf7b2b7d8 1244 R_DMA_EndHandlerProcess(DMA_CH_0);
dkato 0:702bf7b2b7d8 1245
dkato 0:702bf7b2b7d8 1246 }
dkato 0:702bf7b2b7d8 1247
dkato 0:702bf7b2b7d8 1248 /******************************************************************************
dkato 0:702bf7b2b7d8 1249 End of function R_DMA_End0InterruptHandler
dkato 0:702bf7b2b7d8 1250 ******************************************************************************/
dkato 0:702bf7b2b7d8 1251
dkato 0:702bf7b2b7d8 1252 /******************************************************************************
dkato 0:702bf7b2b7d8 1253 * Function Name: R_DMA_End1InterruptHandler
dkato 0:702bf7b2b7d8 1254 * Description : DMA end interrupt handler for channel 1.
dkato 0:702bf7b2b7d8 1255 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1256 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1257 * Arguments : None.
dkato 0:702bf7b2b7d8 1258 * Return Value : None.
dkato 0:702bf7b2b7d8 1259 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1260 * ESUCCESS -
dkato 0:702bf7b2b7d8 1261 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1262 * EIO -
dkato 0:702bf7b2b7d8 1263 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1264 ******************************************************************************/
dkato 0:702bf7b2b7d8 1265
dkato 0:702bf7b2b7d8 1266 static void R_DMA_End1InterruptHandler(void)
dkato 0:702bf7b2b7d8 1267 {
dkato 0:702bf7b2b7d8 1268
dkato 0:702bf7b2b7d8 1269 R_DMA_EndHandlerProcess(DMA_CH_1);
dkato 0:702bf7b2b7d8 1270
dkato 0:702bf7b2b7d8 1271 }
dkato 0:702bf7b2b7d8 1272
dkato 0:702bf7b2b7d8 1273 /******************************************************************************
dkato 0:702bf7b2b7d8 1274 End of function R_DMA_End1InterruptHandler
dkato 0:702bf7b2b7d8 1275 ******************************************************************************/
dkato 0:702bf7b2b7d8 1276
dkato 0:702bf7b2b7d8 1277 /******************************************************************************
dkato 0:702bf7b2b7d8 1278 * Function Name: R_DMA_End2InterruptHandler
dkato 0:702bf7b2b7d8 1279 * Description : DMA end interrupt handler for channel 2.
dkato 0:702bf7b2b7d8 1280 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1281 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1282 * Arguments : None.
dkato 0:702bf7b2b7d8 1283 * Return Value : None.
dkato 0:702bf7b2b7d8 1284 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1285 * ESUCCESS -
dkato 0:702bf7b2b7d8 1286 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1287 * EIO -
dkato 0:702bf7b2b7d8 1288 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1289 ******************************************************************************/
dkato 0:702bf7b2b7d8 1290
dkato 0:702bf7b2b7d8 1291 static void R_DMA_End2InterruptHandler(void)
dkato 0:702bf7b2b7d8 1292 {
dkato 0:702bf7b2b7d8 1293
dkato 0:702bf7b2b7d8 1294 R_DMA_EndHandlerProcess(DMA_CH_2);
dkato 0:702bf7b2b7d8 1295
dkato 0:702bf7b2b7d8 1296 }
dkato 0:702bf7b2b7d8 1297
dkato 0:702bf7b2b7d8 1298 /******************************************************************************
dkato 0:702bf7b2b7d8 1299 End of function R_DMA_End2InterruptHandler
dkato 0:702bf7b2b7d8 1300 ******************************************************************************/
dkato 0:702bf7b2b7d8 1301
dkato 0:702bf7b2b7d8 1302 /******************************************************************************
dkato 0:702bf7b2b7d8 1303 * Function Name: R_DMA_End3InterruptHandler
dkato 0:702bf7b2b7d8 1304 * Description : DMA end interrupt handler for channel 3.
dkato 0:702bf7b2b7d8 1305 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1306 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1307 * Arguments : None.
dkato 0:702bf7b2b7d8 1308 * Return Value : None.
dkato 0:702bf7b2b7d8 1309 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1310 * ESUCCESS -
dkato 0:702bf7b2b7d8 1311 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1312 * EIO -
dkato 0:702bf7b2b7d8 1313 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1314 ******************************************************************************/
dkato 0:702bf7b2b7d8 1315
dkato 0:702bf7b2b7d8 1316 static void R_DMA_End3InterruptHandler(void)
dkato 0:702bf7b2b7d8 1317 {
dkato 0:702bf7b2b7d8 1318
dkato 0:702bf7b2b7d8 1319 R_DMA_EndHandlerProcess(DMA_CH_3);
dkato 0:702bf7b2b7d8 1320
dkato 0:702bf7b2b7d8 1321 }
dkato 0:702bf7b2b7d8 1322
dkato 0:702bf7b2b7d8 1323 /******************************************************************************
dkato 0:702bf7b2b7d8 1324 End of function R_DMA_End3InterruptHandler
dkato 0:702bf7b2b7d8 1325 ******************************************************************************/
dkato 0:702bf7b2b7d8 1326
dkato 0:702bf7b2b7d8 1327 /******************************************************************************
dkato 0:702bf7b2b7d8 1328 * Function Name: R_DMA_End4InterruptHandler
dkato 0:702bf7b2b7d8 1329 * Description : DMA end interrupt handler for channel 4.
dkato 0:702bf7b2b7d8 1330 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1331 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1332 * Arguments : None.
dkato 0:702bf7b2b7d8 1333 * Return Value : None.
dkato 0:702bf7b2b7d8 1334 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1335 * ESUCCESS -
dkato 0:702bf7b2b7d8 1336 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1337 * EIO -
dkato 0:702bf7b2b7d8 1338 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1339 ******************************************************************************/
dkato 0:702bf7b2b7d8 1340
dkato 0:702bf7b2b7d8 1341 static void R_DMA_End4InterruptHandler(void)
dkato 0:702bf7b2b7d8 1342 {
dkato 0:702bf7b2b7d8 1343
dkato 0:702bf7b2b7d8 1344 R_DMA_EndHandlerProcess(DMA_CH_4);
dkato 0:702bf7b2b7d8 1345
dkato 0:702bf7b2b7d8 1346 }
dkato 0:702bf7b2b7d8 1347
dkato 0:702bf7b2b7d8 1348 /******************************************************************************
dkato 0:702bf7b2b7d8 1349 End of function R_DMA_End4InterruptHandler
dkato 0:702bf7b2b7d8 1350 ******************************************************************************/
dkato 0:702bf7b2b7d8 1351
dkato 0:702bf7b2b7d8 1352 /******************************************************************************
dkato 0:702bf7b2b7d8 1353 * Function Name: R_DMA_End5InterruptHandler
dkato 0:702bf7b2b7d8 1354 * Description : DMA end interrupt handler for channel 5.
dkato 0:702bf7b2b7d8 1355 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1356 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1357 * Arguments : None.
dkato 0:702bf7b2b7d8 1358 * Return Value : None.
dkato 0:702bf7b2b7d8 1359 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1360 * ESUCCESS -
dkato 0:702bf7b2b7d8 1361 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1362 * EIO -
dkato 0:702bf7b2b7d8 1363 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1364 ******************************************************************************/
dkato 0:702bf7b2b7d8 1365
dkato 0:702bf7b2b7d8 1366 static void R_DMA_End5InterruptHandler(void)
dkato 0:702bf7b2b7d8 1367 {
dkato 0:702bf7b2b7d8 1368
dkato 0:702bf7b2b7d8 1369 R_DMA_EndHandlerProcess(DMA_CH_5);
dkato 0:702bf7b2b7d8 1370
dkato 0:702bf7b2b7d8 1371 }
dkato 0:702bf7b2b7d8 1372
dkato 0:702bf7b2b7d8 1373 /******************************************************************************
dkato 0:702bf7b2b7d8 1374 End of function R_DMA_End5InterruptHandler
dkato 0:702bf7b2b7d8 1375 ******************************************************************************/
dkato 0:702bf7b2b7d8 1376
dkato 0:702bf7b2b7d8 1377 /******************************************************************************
dkato 0:702bf7b2b7d8 1378 * Function Name: R_DMA_End6InterruptHandler
dkato 0:702bf7b2b7d8 1379 * Description : DMA end interrupt handler for channel 6.
dkato 0:702bf7b2b7d8 1380 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1381 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1382 * Arguments : None.
dkato 0:702bf7b2b7d8 1383 * Return Value : None.
dkato 0:702bf7b2b7d8 1384 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1385 * ESUCCESS -
dkato 0:702bf7b2b7d8 1386 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1387 * EIO -
dkato 0:702bf7b2b7d8 1388 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1389 ******************************************************************************/
dkato 0:702bf7b2b7d8 1390
dkato 0:702bf7b2b7d8 1391 static void R_DMA_End6InterruptHandler(void)
dkato 0:702bf7b2b7d8 1392 {
dkato 0:702bf7b2b7d8 1393
dkato 0:702bf7b2b7d8 1394 R_DMA_EndHandlerProcess(DMA_CH_6);
dkato 0:702bf7b2b7d8 1395
dkato 0:702bf7b2b7d8 1396 }
dkato 0:702bf7b2b7d8 1397
dkato 0:702bf7b2b7d8 1398 /******************************************************************************
dkato 0:702bf7b2b7d8 1399 End of function R_DMA_End6InterruptHandler
dkato 0:702bf7b2b7d8 1400 ******************************************************************************/
dkato 0:702bf7b2b7d8 1401
dkato 0:702bf7b2b7d8 1402 /******************************************************************************
dkato 0:702bf7b2b7d8 1403 * Function Name: R_DMA_End7InterruptHandler
dkato 0:702bf7b2b7d8 1404 * Description : DMA end interrupt handler for channel 7.
dkato 0:702bf7b2b7d8 1405 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1406 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1407 * Arguments : None.
dkato 0:702bf7b2b7d8 1408 * Return Value : None.
dkato 0:702bf7b2b7d8 1409 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1410 * ESUCCESS -
dkato 0:702bf7b2b7d8 1411 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1412 * EIO -
dkato 0:702bf7b2b7d8 1413 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1414 ******************************************************************************/
dkato 0:702bf7b2b7d8 1415
dkato 0:702bf7b2b7d8 1416 static void R_DMA_End7InterruptHandler(void)
dkato 0:702bf7b2b7d8 1417 {
dkato 0:702bf7b2b7d8 1418
dkato 0:702bf7b2b7d8 1419 R_DMA_EndHandlerProcess(DMA_CH_7);
dkato 0:702bf7b2b7d8 1420
dkato 0:702bf7b2b7d8 1421 }
dkato 0:702bf7b2b7d8 1422
dkato 0:702bf7b2b7d8 1423 /******************************************************************************
dkato 0:702bf7b2b7d8 1424 End of function R_DMA_End7InterruptHandler
dkato 0:702bf7b2b7d8 1425 ******************************************************************************/
dkato 0:702bf7b2b7d8 1426
dkato 0:702bf7b2b7d8 1427 /******************************************************************************
dkato 0:702bf7b2b7d8 1428 * Function Name: R_DMA_End8InterruptHandler
dkato 0:702bf7b2b7d8 1429 * Description : DMA end interrupt handler for channel 8.
dkato 0:702bf7b2b7d8 1430 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1431 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1432 * Arguments : None.
dkato 0:702bf7b2b7d8 1433 * Return Value : None.
dkato 0:702bf7b2b7d8 1434 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1435 * ESUCCESS -
dkato 0:702bf7b2b7d8 1436 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1437 * EIO -
dkato 0:702bf7b2b7d8 1438 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1439 ******************************************************************************/
dkato 0:702bf7b2b7d8 1440
dkato 0:702bf7b2b7d8 1441 static void R_DMA_End8InterruptHandler(void)
dkato 0:702bf7b2b7d8 1442 {
dkato 0:702bf7b2b7d8 1443
dkato 0:702bf7b2b7d8 1444 R_DMA_EndHandlerProcess(DMA_CH_8);
dkato 0:702bf7b2b7d8 1445
dkato 0:702bf7b2b7d8 1446 }
dkato 0:702bf7b2b7d8 1447
dkato 0:702bf7b2b7d8 1448 /******************************************************************************
dkato 0:702bf7b2b7d8 1449 End of function R_DMA_End8InterruptHandler
dkato 0:702bf7b2b7d8 1450 ******************************************************************************/
dkato 0:702bf7b2b7d8 1451
dkato 0:702bf7b2b7d8 1452 /******************************************************************************
dkato 0:702bf7b2b7d8 1453 * Function Name: R_DMA_End9InterruptHandler
dkato 0:702bf7b2b7d8 1454 * Description : DMA end interrupt handler for channel 9.
dkato 0:702bf7b2b7d8 1455 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1456 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1457 * Arguments : None.
dkato 0:702bf7b2b7d8 1458 * Return Value : None.
dkato 0:702bf7b2b7d8 1459 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1460 * ESUCCESS -
dkato 0:702bf7b2b7d8 1461 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1462 * EIO -
dkato 0:702bf7b2b7d8 1463 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1464 ******************************************************************************/
dkato 0:702bf7b2b7d8 1465
dkato 0:702bf7b2b7d8 1466 static void R_DMA_End9InterruptHandler(void)
dkato 0:702bf7b2b7d8 1467 {
dkato 0:702bf7b2b7d8 1468
dkato 0:702bf7b2b7d8 1469 R_DMA_EndHandlerProcess(DMA_CH_9);
dkato 0:702bf7b2b7d8 1470
dkato 0:702bf7b2b7d8 1471 }
dkato 0:702bf7b2b7d8 1472
dkato 0:702bf7b2b7d8 1473 /******************************************************************************
dkato 0:702bf7b2b7d8 1474 End of function R_DMA_End9InterruptHandler
dkato 0:702bf7b2b7d8 1475 ******************************************************************************/
dkato 0:702bf7b2b7d8 1476
dkato 0:702bf7b2b7d8 1477 /******************************************************************************
dkato 0:702bf7b2b7d8 1478 * Function Name: R_DMA_End10InterruptHandler
dkato 0:702bf7b2b7d8 1479 * Description : DMA end interrupt handler for channel 10.
dkato 0:702bf7b2b7d8 1480 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1481 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1482 * Arguments : None.
dkato 0:702bf7b2b7d8 1483 * Return Value : None.
dkato 0:702bf7b2b7d8 1484 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1485 * ESUCCESS -
dkato 0:702bf7b2b7d8 1486 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1487 * EIO -
dkato 0:702bf7b2b7d8 1488 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1489 ******************************************************************************/
dkato 0:702bf7b2b7d8 1490
dkato 0:702bf7b2b7d8 1491 static void R_DMA_End10InterruptHandler(void)
dkato 0:702bf7b2b7d8 1492 {
dkato 0:702bf7b2b7d8 1493
dkato 0:702bf7b2b7d8 1494 R_DMA_EndHandlerProcess(DMA_CH_10);
dkato 0:702bf7b2b7d8 1495
dkato 0:702bf7b2b7d8 1496 }
dkato 0:702bf7b2b7d8 1497
dkato 0:702bf7b2b7d8 1498 /******************************************************************************
dkato 0:702bf7b2b7d8 1499 End of function R_DMA_End10InterruptHandler
dkato 0:702bf7b2b7d8 1500 ******************************************************************************/
dkato 0:702bf7b2b7d8 1501
dkato 0:702bf7b2b7d8 1502 /******************************************************************************
dkato 0:702bf7b2b7d8 1503 * Function Name: R_DMA_End11InterruptHandler
dkato 0:702bf7b2b7d8 1504 * Description : DMA end interrupt handler for channel 11.
dkato 0:702bf7b2b7d8 1505 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1506 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1507 * Arguments : None.
dkato 0:702bf7b2b7d8 1508 * Return Value : None.
dkato 0:702bf7b2b7d8 1509 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1510 * ESUCCESS -
dkato 0:702bf7b2b7d8 1511 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1512 * EIO -
dkato 0:702bf7b2b7d8 1513 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1514 ******************************************************************************/
dkato 0:702bf7b2b7d8 1515
dkato 0:702bf7b2b7d8 1516 static void R_DMA_End11InterruptHandler(void)
dkato 0:702bf7b2b7d8 1517 {
dkato 0:702bf7b2b7d8 1518
dkato 0:702bf7b2b7d8 1519 R_DMA_EndHandlerProcess(DMA_CH_11);
dkato 0:702bf7b2b7d8 1520
dkato 0:702bf7b2b7d8 1521 }
dkato 0:702bf7b2b7d8 1522
dkato 0:702bf7b2b7d8 1523 /******************************************************************************
dkato 0:702bf7b2b7d8 1524 End of function R_DMA_End11InterruptHandler
dkato 0:702bf7b2b7d8 1525 ******************************************************************************/
dkato 0:702bf7b2b7d8 1526
dkato 0:702bf7b2b7d8 1527 /******************************************************************************
dkato 0:702bf7b2b7d8 1528 * Function Name: R_DMA_End12InterruptHandler
dkato 0:702bf7b2b7d8 1529 * Description : DMA end interrupt handler for channel 12.
dkato 0:702bf7b2b7d8 1530 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1531 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1532 * Arguments : None.
dkato 0:702bf7b2b7d8 1533 * Return Value : None.
dkato 0:702bf7b2b7d8 1534 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1535 * ESUCCESS -
dkato 0:702bf7b2b7d8 1536 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1537 * EIO -
dkato 0:702bf7b2b7d8 1538 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1539 ******************************************************************************/
dkato 0:702bf7b2b7d8 1540
dkato 0:702bf7b2b7d8 1541 static void R_DMA_End12InterruptHandler(void)
dkato 0:702bf7b2b7d8 1542 {
dkato 0:702bf7b2b7d8 1543
dkato 0:702bf7b2b7d8 1544 R_DMA_EndHandlerProcess(DMA_CH_12);
dkato 0:702bf7b2b7d8 1545
dkato 0:702bf7b2b7d8 1546 }
dkato 0:702bf7b2b7d8 1547
dkato 0:702bf7b2b7d8 1548 /******************************************************************************
dkato 0:702bf7b2b7d8 1549 End of function R_DMA_End12InterruptHandler
dkato 0:702bf7b2b7d8 1550 ******************************************************************************/
dkato 0:702bf7b2b7d8 1551
dkato 0:702bf7b2b7d8 1552 /******************************************************************************
dkato 0:702bf7b2b7d8 1553 * Function Name: R_DMA_End13InterruptHandler
dkato 0:702bf7b2b7d8 1554 * Description : DMA end interrupt handler for channel 13.
dkato 0:702bf7b2b7d8 1555 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1556 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1557 * Arguments : None.
dkato 0:702bf7b2b7d8 1558 * Return Value : None.
dkato 0:702bf7b2b7d8 1559 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1560 * ESUCCESS -
dkato 0:702bf7b2b7d8 1561 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1562 * EIO -
dkato 0:702bf7b2b7d8 1563 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1564 ******************************************************************************/
dkato 0:702bf7b2b7d8 1565
dkato 0:702bf7b2b7d8 1566 static void R_DMA_End13InterruptHandler(void)
dkato 0:702bf7b2b7d8 1567 {
dkato 0:702bf7b2b7d8 1568
dkato 0:702bf7b2b7d8 1569 R_DMA_EndHandlerProcess(DMA_CH_13);
dkato 0:702bf7b2b7d8 1570
dkato 0:702bf7b2b7d8 1571 }
dkato 0:702bf7b2b7d8 1572
dkato 0:702bf7b2b7d8 1573 /******************************************************************************
dkato 0:702bf7b2b7d8 1574 End of function R_DMA_End13InterruptHandler
dkato 0:702bf7b2b7d8 1575 ******************************************************************************/
dkato 0:702bf7b2b7d8 1576
dkato 0:702bf7b2b7d8 1577 /******************************************************************************
dkato 0:702bf7b2b7d8 1578 * Function Name: R_DMA_End14InterruptHandler
dkato 0:702bf7b2b7d8 1579 * Description : DMA end interrupt handler for channel 14.
dkato 0:702bf7b2b7d8 1580 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1581 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1582 * Arguments : None.
dkato 0:702bf7b2b7d8 1583 * Return Value : None.
dkato 0:702bf7b2b7d8 1584 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1585 * ESUCCESS -
dkato 0:702bf7b2b7d8 1586 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1587 * EIO -
dkato 0:702bf7b2b7d8 1588 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1589 ******************************************************************************/
dkato 0:702bf7b2b7d8 1590
dkato 0:702bf7b2b7d8 1591 static void R_DMA_End14InterruptHandler(void)
dkato 0:702bf7b2b7d8 1592 {
dkato 0:702bf7b2b7d8 1593
dkato 0:702bf7b2b7d8 1594 R_DMA_EndHandlerProcess(DMA_CH_14);
dkato 0:702bf7b2b7d8 1595
dkato 0:702bf7b2b7d8 1596 }
dkato 0:702bf7b2b7d8 1597
dkato 0:702bf7b2b7d8 1598 /******************************************************************************
dkato 0:702bf7b2b7d8 1599 End of function R_DMA_End14InterruptHandler
dkato 0:702bf7b2b7d8 1600 ******************************************************************************/
dkato 0:702bf7b2b7d8 1601
dkato 0:702bf7b2b7d8 1602 /******************************************************************************
dkato 0:702bf7b2b7d8 1603 * Function Name: R_DMA_End15InterruptHandler
dkato 0:702bf7b2b7d8 1604 * Description : DMA end interrupt handler for channel 15.
dkato 0:702bf7b2b7d8 1605 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1606 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1607 * Arguments : None.
dkato 0:702bf7b2b7d8 1608 * Return Value : None.
dkato 0:702bf7b2b7d8 1609 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1610 * ESUCCESS -
dkato 0:702bf7b2b7d8 1611 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1612 * EIO -
dkato 0:702bf7b2b7d8 1613 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1614 ******************************************************************************/
dkato 0:702bf7b2b7d8 1615
dkato 0:702bf7b2b7d8 1616 static void R_DMA_End15InterruptHandler(void)
dkato 0:702bf7b2b7d8 1617 {
dkato 0:702bf7b2b7d8 1618
dkato 0:702bf7b2b7d8 1619 R_DMA_EndHandlerProcess(DMA_CH_15);
dkato 0:702bf7b2b7d8 1620
dkato 0:702bf7b2b7d8 1621 }
dkato 0:702bf7b2b7d8 1622
dkato 0:702bf7b2b7d8 1623 /******************************************************************************
dkato 0:702bf7b2b7d8 1624 End of function R_DMA_End15InterruptHandler
dkato 0:702bf7b2b7d8 1625 ******************************************************************************/
dkato 0:702bf7b2b7d8 1626
dkato 0:702bf7b2b7d8 1627 /******************************************************************************
dkato 0:702bf7b2b7d8 1628 * Function Name: R_DMA_EndHandlerProcess
dkato 0:702bf7b2b7d8 1629 * Description : DMA end interrupt handler process carry out.
dkato 0:702bf7b2b7d8 1630 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1631 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1632 * Arguments : channel -
dkato 0:702bf7b2b7d8 1633 * Open channel number.
dkato 0:702bf7b2b7d8 1634 * Return Value : None.
dkato 0:702bf7b2b7d8 1635 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1636 * ESUCCESS -
dkato 0:702bf7b2b7d8 1637 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1638 * EIO -
dkato 0:702bf7b2b7d8 1639 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1640 ******************************************************************************/
dkato 0:702bf7b2b7d8 1641
dkato 0:702bf7b2b7d8 1642 __inline static void R_DMA_EndHandlerProcess(const int_t channel)
dkato 0:702bf7b2b7d8 1643 {
dkato 0:702bf7b2b7d8 1644 bool_t store_next_dma_flag;
dkato 0:702bf7b2b7d8 1645
dkato 0:702bf7b2b7d8 1646 if (NULL != gb_info_drv.info_ch[channel].p_end_aio)
dkato 0:702bf7b2b7d8 1647 {
dkato 0:702bf7b2b7d8 1648
dkato 0:702bf7b2b7d8 1649 /* store next_dma_flag */
dkato 0:702bf7b2b7d8 1650 store_next_dma_flag = gb_info_drv.info_ch[channel].next_dma_flag;
dkato 0:702bf7b2b7d8 1651
dkato 0:702bf7b2b7d8 1652 /* clear flag wich indicates that next DMA transfer set already */
dkato 0:702bf7b2b7d8 1653 gb_info_drv.info_ch[channel].next_dma_flag = false;
dkato 0:702bf7b2b7d8 1654
dkato 0:702bf7b2b7d8 1655 if (false == store_next_dma_flag)
dkato 0:702bf7b2b7d8 1656 {
dkato 0:702bf7b2b7d8 1657 /* DMA transfer complete */
dkato 0:702bf7b2b7d8 1658 /* mask DMA end interrupt */
dkato 0:702bf7b2b7d8 1659 GIC_DisableIRQ(gb_info_drv.info_ch[channel].end_irq_num);
dkato 0:702bf7b2b7d8 1660
dkato 0:702bf7b2b7d8 1661 /* set channel status to DMA_CH_OPEN */
dkato 0:702bf7b2b7d8 1662 gb_info_drv.info_ch[channel].ch_stat = DMA_CH_OPEN;
dkato 0:702bf7b2b7d8 1663
dkato 0:702bf7b2b7d8 1664 /* set mask of DMA transfer end */
dkato 0:702bf7b2b7d8 1665 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n |= (uint32_t)CHCFG_SET_DEM;
dkato 0:702bf7b2b7d8 1666
dkato 0:702bf7b2b7d8 1667 /* clear setting of continuous DMA */
dkato 0:702bf7b2b7d8 1668 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &= ~(uint32_t)(CHCFG_SET_RSW | CHCFG_SET_RSEL);
dkato 0:702bf7b2b7d8 1669
dkato 0:702bf7b2b7d8 1670 /* check EN bit is clear */
dkato 0:702bf7b2b7d8 1671 if (0U == (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_EN))
dkato 0:702bf7b2b7d8 1672 {
dkato 0:702bf7b2b7d8 1673 /* set error code (ESUCCESS) */
dkato 0:702bf7b2b7d8 1674 gb_info_drv.info_ch[channel].p_end_aio->aio_return = ESUCCESS;
dkato 0:702bf7b2b7d8 1675 }
dkato 0:702bf7b2b7d8 1676 else
dkato 0:702bf7b2b7d8 1677 {
dkato 0:702bf7b2b7d8 1678 /* set error code (EIO) */
dkato 0:702bf7b2b7d8 1679 gb_info_drv.info_ch[channel].p_end_aio->aio_return = EIO;
dkato 0:702bf7b2b7d8 1680 }
dkato 0:702bf7b2b7d8 1681 }
dkato 0:702bf7b2b7d8 1682 else
dkato 0:702bf7b2b7d8 1683 {
dkato 0:702bf7b2b7d8 1684 /* set next DMA already */
dkato 0:702bf7b2b7d8 1685 /* set error code (ESUCCESS) */
dkato 0:702bf7b2b7d8 1686 gb_info_drv.info_ch[channel].p_end_aio->aio_return = ESUCCESS;
dkato 0:702bf7b2b7d8 1687 }
dkato 0:702bf7b2b7d8 1688
dkato 0:702bf7b2b7d8 1689 /* clear TC, END bit */
dkato 0:702bf7b2b7d8 1690 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = (CHCTRL_SET_CLRTC | CHCTRL_SET_CLREND);
dkato 0:702bf7b2b7d8 1691
dkato 0:702bf7b2b7d8 1692 /* call back to the module function which called DMA driver */
dkato 0:702bf7b2b7d8 1693 ahf_complete(NULL, gb_info_drv.info_ch[channel].p_end_aio);
dkato 0:702bf7b2b7d8 1694
dkato 0:702bf7b2b7d8 1695 }
dkato 0:702bf7b2b7d8 1696 else
dkato 0:702bf7b2b7d8 1697 {
dkato 0:702bf7b2b7d8 1698 ;
dkato 0:702bf7b2b7d8 1699 /* NON_NOTICE_ASSERT:<callback pointer is NULL> */
dkato 0:702bf7b2b7d8 1700 }
dkato 0:702bf7b2b7d8 1701
dkato 0:702bf7b2b7d8 1702 }
dkato 0:702bf7b2b7d8 1703
dkato 0:702bf7b2b7d8 1704 /******************************************************************************
dkato 0:702bf7b2b7d8 1705 End of function R_DMA_EndHandlerProcess
dkato 0:702bf7b2b7d8 1706 ******************************************************************************/
dkato 0:702bf7b2b7d8 1707