RZ/A1H CMSIS-RTOS RTX BSP for GR-PEACH.

Dependents:   GR-PEACH_Azure_Speech ImageZoomInout_Sample ImageRotaion_Sample ImageScroll_Sample ... more

Fork of R_BSP by Daiki Kato

SSIF

The SSIF driver implements transmission and reception functionality which uses the SSIF in the RZ/A Series.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Ssif.h"
00003 #include "sine_data_tbl.h"
00004 
00005 //I2S send only, The upper limit of write buffer is 8.
00006 R_BSP_Ssif ssif(P4_4, P4_5, P4_7, P4_6, 0x80, 8, 0);
00007 
00008 static void callback_ssif_write_end(void * p_data, int32_t result, void * p_app_data) {
00009     if (result < 0) {
00010         printf("ssif write callback error %d\n", result);
00011     }
00012 }
00013 
00014 int main() {
00015     rbsp_data_conf_t   ssif_write_end_conf = {&callback_ssif_write_end, NULL};
00016     ssif_channel_cfg_t ssif_cfg;
00017     int32_t            result;
00018 
00019     //I2S Master, 44.1kHz, 16bit, 2ch
00020     ssif_cfg.enabled                = true;
00021     ssif_cfg.int_level              = 0x78;
00022     ssif_cfg.slave_mode             = false;
00023     ssif_cfg.sample_freq            = 44100u;
00024     ssif_cfg.clk_select             = SSIF_CFG_CKS_AUDIO_X1;
00025     ssif_cfg.multi_ch               = SSIF_CFG_MULTI_CH_1;
00026     ssif_cfg.data_word              = SSIF_CFG_DATA_WORD_16;
00027     ssif_cfg.system_word            = SSIF_CFG_SYSTEM_WORD_32;
00028     ssif_cfg.bclk_pol               = SSIF_CFG_FALLING;
00029     ssif_cfg.ws_pol                 = SSIF_CFG_WS_LOW;
00030     ssif_cfg.padding_pol            = SSIF_CFG_PADDING_LOW;
00031     ssif_cfg.serial_alignment       = SSIF_CFG_DATA_FIRST;
00032     ssif_cfg.parallel_alignment     = SSIF_CFG_LEFT;
00033     ssif_cfg.ws_delay               = SSIF_CFG_DELAY;
00034     ssif_cfg.noise_cancel           = SSIF_CFG_DISABLE_NOISE_CANCEL;
00035     ssif_cfg.tdm_mode               = SSIF_CFG_DISABLE_TDM;
00036     ssif_cfg.romdec_direct.mode     = SSIF_CFG_DISABLE_ROMDEC_DIRECT;
00037     ssif_cfg.romdec_direct.p_cbfunc = NULL;
00038     result = ssif.ConfigChannel(&ssif_cfg);
00039     if (result < 0) {
00040         printf("ssif config error %d\n", result);
00041     }
00042 
00043     while (1) {
00044         //The upper limit of write buffer is 8.
00045         result = ssif.write((void *)sin_data_44100Hz_16bit_2ch, 
00046                             sizeof(sin_data_44100Hz_16bit_2ch), &ssif_write_end_conf);
00047         if (result < 0) {
00048             printf("ssif write api error %d\n", result);
00049         }
00050     }
00051 }

API

Import library

Public Member Functions

R_BSP_Ssif (PinName sck, PinName ws, PinName tx, PinName rx, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor.
virtual ~R_BSP_Ssif ()
Destructor.
int32_t GetSsifChNo (void)
Get a value of SSIF channel number.
bool ConfigChannel (const ssif_channel_cfg_t *const p_ch_cfg)
Save configuration to the SSIF driver.
bool GetStatus (uint32_t *const p_status)
Get a value of SSISR register.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Interface

See the Pinout page for more details


SCUX

The SCUX module consists of a sampling rate converter, a digital volume unit, and a mixer.
The SCUX driver can perform asynchronous and synchronous sampling rate conversions using the sampling rate converter. The SCUX driver uses the DMA transfer mode to input and output audio data.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Scux.h"
00003 #include "USBHostMSD.h"
00004 
00005 R_BSP_Scux scux(SCUX_CH_0);
00006 
00007 #define WRITE_SAMPLE_NUM (128)
00008 #define READ_SAMPLE_NUM  (2048)
00009 
00010 const short sin_data[WRITE_SAMPLE_NUM] = {
00011  0x0000,0x0000,0x0C8C,0x0C8C,0x18F9,0x18F9,0x2528,0x2528
00012 ,0x30FB,0x30FB,0x3C56,0x3C56,0x471C,0x471C,0x5133,0x5133
00013 ,0x5A82,0x5A82,0x62F1,0x62F1,0x6A6D,0x6A6D,0x70E2,0x70E2
00014 ,0x7641,0x7641,0x7A7C,0x7A7C,0x7D89,0x7D89,0x7F61,0x7F61
00015 ,0x7FFF,0x7FFF,0x7F61,0x7F61,0x7D89,0x7D89,0x7A7C,0x7A7C
00016 ,0x7641,0x7641,0x70E2,0x70E2,0x6A6D,0x6A6D,0x62F1,0x62F1
00017 ,0x5A82,0x5A82,0x5133,0x5133,0x471C,0x471C,0x3C56,0x3C56
00018 ,0x30FB,0x30FB,0x2528,0x2528,0x18F9,0x18F9,0x0C8C,0x0C8C
00019 ,0x0000,0x0000,0xF374,0xF374,0xE707,0xE707,0xDAD8,0xDAD8
00020 ,0xCF05,0xCF05,0xC3AA,0xC3AA,0xB8E4,0xB8E4,0xAECD,0xAECD
00021 ,0xA57E,0xA57E,0x9D0F,0x9D0F,0x9593,0x9593,0x8F1E,0x8F1E
00022 ,0x89BF,0x89BF,0x8584,0x8584,0x8277,0x8277,0x809F,0x809F
00023 ,0x8001,0x8001,0x809F,0x809F,0x8277,0x8277,0x8584,0x8584
00024 ,0x89BF,0x89BF,0x8F1E,0x8F1E,0x9593,0x9593,0x9D0F,0x9D0F
00025 ,0xA57E,0xA57E,0xAECD,0xAECD,0xB8E4,0xB8E4,0xC3AA,0xC3AA
00026 ,0xCF05,0xCF05,0xDAD8,0xDAD8,0xE707,0xE707,0xF374,0xF374
00027 };
00028 
00029 #if defined(__ICCARM__)
00030 #pragma data_alignment=4
00031 short write_buff[WRITE_SAMPLE_NUM]@ ".mirrorram";
00032 #pragma data_alignment=4
00033 short read_buff[READ_SAMPLE_NUM]@ ".mirrorram";
00034 #else
00035 short write_buff[WRITE_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00036 short read_buff[READ_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00037 #endif
00038 
00039 void scux_setup(void);
00040 void write_task(void const*);
00041 void file_output_to_usb(void);
00042 
00043 int main(void) {
00044     // set up SRC parameters.
00045     scux_setup();
00046 
00047     printf("Sampling rate conversion Start.\n");
00048     // start accepting transmit/receive requests.
00049     scux.TransStart();
00050 
00051     // create a new thread to write to SCUX.
00052     Thread writeTask(write_task, NULL, osPriorityNormal, 1024 * 4);
00053 
00054     // receive request to the SCUX driver.
00055     scux.read(read_buff, sizeof(read_buff));
00056     printf("Sampling rate conversion End.\n");
00057 
00058     // output binary file to USB port 0.
00059     file_output_to_usb();
00060 }
00061 
00062 void scux_setup(void) {
00063     scux_src_usr_cfg_t src_cfg;
00064 
00065     src_cfg.src_enable           = true;
00066     src_cfg.word_len             = SCUX_DATA_LEN_16;
00067     src_cfg.mode_sync            = true;
00068     src_cfg.input_rate           = SAMPLING_RATE_48000HZ;
00069     src_cfg.output_rate          = SAMPLING_RATE_96000HZ;
00070     src_cfg.select_in_data_ch[0] = SELECT_IN_DATA_CH_0;
00071     src_cfg.select_in_data_ch[1] = SELECT_IN_DATA_CH_1;
00072 
00073     scux.SetSrcCfg(&src_cfg);
00074 }
00075 
00076 void scux_flush_callback(int scux_ch) {
00077     // do nothing
00078 }
00079 
00080 void write_task(void const*) {
00081     memcpy(write_buff, sin_data, sizeof(write_buff));
00082     // send request to the SCUX driver.
00083     scux.write(write_buff, sizeof(write_buff));
00084 
00085     // stop the acceptance of transmit/receive requests.
00086     scux.FlushStop(&scux_flush_callback);
00087 }
00088 
00089 void file_output_to_usb(void) {
00090     FILE * fp = NULL;
00091     int i;
00092 
00093     USBHostMSD msd("usb");
00094 
00095     // try to connect a MSD device
00096     for(i = 0; i < 10; i++) {
00097         if (msd.connect()) {
00098             break;
00099         }
00100         wait(0.5);
00101     }
00102 
00103     if (msd.connected()) {
00104         fp = fopen("/usb/scux_input.dat", "rb");
00105         if (fp == NULL) {
00106             fp = fopen("/usb/scux_input.dat", "wb");
00107             if (fp != NULL) {
00108                 fwrite(write_buff, sizeof(short), WRITE_SAMPLE_NUM, fp);
00109                 fclose(fp);
00110                 printf("Output binary file(Input data) to USB.\n");
00111             } else {
00112                 printf("Failed to output binary file(Input data).\n");
00113             }
00114         } else {
00115             printf("Binary file(Input data) exists.\n");
00116             fclose(fp);
00117         }
00118 
00119         fp = fopen("/usb/scux_output.dat", "rb");
00120         if (fp == NULL) {
00121             fp = fopen("/usb/scux_output.dat", "wb");
00122             if (fp != NULL) {
00123                 fwrite(read_buff, sizeof(short), READ_SAMPLE_NUM, fp);
00124                 fclose(fp);
00125                 printf("Output binary file(Output data) to USB.\n");
00126             } else {
00127                 printf("Failed to output binary file(Output data).\n");
00128             }
00129         } else {
00130             printf("Binary file(Output data) exists.\n");
00131             fclose(fp);
00132         }
00133     } else {
00134         printf("Failed to connect to the USB device.\n");
00135     }
00136 } 

API

Import library

Public Member Functions

R_BSP_Scux ( scux_ch_num_t channel, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor: Initializes and opens the channel designated by the SCUX driver.
virtual ~R_BSP_Scux (void)
Destructor: Closes the channel designated by the SCUX driver and exits.
bool TransStart (void)
Sets up the SCUX HW and starts operation, then starts accepting write/read requests.
bool FlushStop (void(*const callback)(int32_t))
Stops accepting write/read requests, flushes out all data in the SCUX that is requested for transfer, then stops the HW operation.
bool ClearStop (void)
Discards all data in the SCUX that is requested for transfer before stopping the hardware operation and stops accepting write/read requests.
bool SetSrcCfg (const scux_src_usr_cfg_t *const p_src_param)
Sets up SRC parameters.
bool GetWriteStat (uint32_t *const p_write_stat)
Obtains the state information of the write request.
bool GetReadStat (uint32_t *const p_read_stat)
Obtains the state information of the read request.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Write request state transition diagram

/media/uploads/dkato/scux_write_state_transition.png

Read request state transition diagram

/media/uploads/dkato/scux_read_state_transition.png

Committer:
dkato
Date:
Tue Aug 18 04:00:49 2015 +0000
Revision:
5:1390bfcb667c
Parent:
0:702bf7b2b7d8
Update BSP V.203

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:702bf7b2b7d8 1 /*******************************************************************************
dkato 0:702bf7b2b7d8 2 * DISCLAIMER
dkato 0:702bf7b2b7d8 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:702bf7b2b7d8 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:702bf7b2b7d8 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:702bf7b2b7d8 6 * all applicable laws, including copyright laws.
dkato 0:702bf7b2b7d8 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:702bf7b2b7d8 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:702bf7b2b7d8 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:702bf7b2b7d8 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:702bf7b2b7d8 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:702bf7b2b7d8 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:702bf7b2b7d8 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:702bf7b2b7d8 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:702bf7b2b7d8 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:702bf7b2b7d8 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:702bf7b2b7d8 17 * and to discontinue the availability of this software. By using this software,
dkato 0:702bf7b2b7d8 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:702bf7b2b7d8 19 * following link:
dkato 0:702bf7b2b7d8 20 * http://www.renesas.com/disclaimer*
dkato 0:702bf7b2b7d8 21 * Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
dkato 0:702bf7b2b7d8 22 *******************************************************************************/
dkato 0:702bf7b2b7d8 23
dkato 0:702bf7b2b7d8 24 /**************************************************************************//**
dkato 0:702bf7b2b7d8 25 * @file dma.c
dkato 5:1390bfcb667c 26 * $Rev: 1674 $
dkato 5:1390bfcb667c 27 * $Date:: 2015-05-29 16:35:57 +0900#$
dkato 0:702bf7b2b7d8 28 * @brief DMA Driver internal functions
dkato 0:702bf7b2b7d8 29 ******************************************************************************/
dkato 0:702bf7b2b7d8 30
dkato 0:702bf7b2b7d8 31 /*****************************************************************************
dkato 0:702bf7b2b7d8 32 * History : DD.MM.YYYY Version Description
dkato 0:702bf7b2b7d8 33 * : 15.01.2013 1.00 First Release
dkato 0:702bf7b2b7d8 34 ******************************************************************************/
dkato 0:702bf7b2b7d8 35
dkato 0:702bf7b2b7d8 36 /*******************************************************************************
dkato 0:702bf7b2b7d8 37 Includes <System Includes>, "Project Includes"
dkato 0:702bf7b2b7d8 38 *******************************************************************************/
dkato 0:702bf7b2b7d8 39
dkato 0:702bf7b2b7d8 40 #include "dma.h"
dkato 0:702bf7b2b7d8 41 #include "aioif.h"
dkato 0:702bf7b2b7d8 42 #include "iodefine.h"
dkato 0:702bf7b2b7d8 43 #include "gic.h"
dkato 0:702bf7b2b7d8 44
dkato 0:702bf7b2b7d8 45 /******************************************************************************
dkato 0:702bf7b2b7d8 46 Private global driver management information
dkato 0:702bf7b2b7d8 47 ******************************************************************************/
dkato 0:702bf7b2b7d8 48
dkato 0:702bf7b2b7d8 49 /* driver management infrmation */
dkato 0:702bf7b2b7d8 50 static dma_info_drv_t gb_info_drv;
dkato 0:702bf7b2b7d8 51
dkato 0:702bf7b2b7d8 52 /******************************************************************************
dkato 0:702bf7b2b7d8 53 Private function define (interrupt handler)
dkato 0:702bf7b2b7d8 54 ******************************************************************************/
dkato 0:702bf7b2b7d8 55
dkato 0:702bf7b2b7d8 56 static void R_DMA_End0InterruptHandler(void);
dkato 0:702bf7b2b7d8 57 static void R_DMA_End1InterruptHandler(void);
dkato 0:702bf7b2b7d8 58 static void R_DMA_End2InterruptHandler(void);
dkato 0:702bf7b2b7d8 59 static void R_DMA_End3InterruptHandler(void);
dkato 0:702bf7b2b7d8 60 static void R_DMA_End4InterruptHandler(void);
dkato 0:702bf7b2b7d8 61 static void R_DMA_End5InterruptHandler(void);
dkato 0:702bf7b2b7d8 62 static void R_DMA_End6InterruptHandler(void);
dkato 0:702bf7b2b7d8 63 static void R_DMA_End7InterruptHandler(void);
dkato 0:702bf7b2b7d8 64 static void R_DMA_End8InterruptHandler(void);
dkato 0:702bf7b2b7d8 65 static void R_DMA_End9InterruptHandler(void);
dkato 0:702bf7b2b7d8 66 static void R_DMA_End10InterruptHandler(void);
dkato 0:702bf7b2b7d8 67 static void R_DMA_End11InterruptHandler(void);
dkato 0:702bf7b2b7d8 68 static void R_DMA_End12InterruptHandler(void);
dkato 0:702bf7b2b7d8 69 static void R_DMA_End13InterruptHandler(void);
dkato 0:702bf7b2b7d8 70 static void R_DMA_End14InterruptHandler(void);
dkato 0:702bf7b2b7d8 71 static void R_DMA_End15InterruptHandler(void);
dkato 0:702bf7b2b7d8 72 static void R_DMA_ErrInterruptHandler(void);
dkato 0:702bf7b2b7d8 73 static void R_DMA_EndHandlerProcess(const int_t channel);
dkato 0:702bf7b2b7d8 74
dkato 0:702bf7b2b7d8 75 /******************************************************************************
dkato 0:702bf7b2b7d8 76 Function prototypes
dkato 0:702bf7b2b7d8 77 *****************************************************************************/
dkato 0:702bf7b2b7d8 78
dkato 0:702bf7b2b7d8 79 static void DMA_OpenChannel(const int_t channel);
dkato 0:702bf7b2b7d8 80
dkato 0:702bf7b2b7d8 81 /******************************************************************************
dkato 0:702bf7b2b7d8 82 * Function Name: DMA_GetDrvInstance
dkato 0:702bf7b2b7d8 83 * Description : Get pointer of gb_info_drv.
dkato 0:702bf7b2b7d8 84 * Arguments : *p_dma_info_drv -
dkato 0:702bf7b2b7d8 85 * Pointer of gb_info_drv is returned.
dkato 0:702bf7b2b7d8 86 * Return Value : None
dkato 0:702bf7b2b7d8 87 ******************************************************************************/
dkato 0:702bf7b2b7d8 88
dkato 0:702bf7b2b7d8 89 dma_info_drv_t *DMA_GetDrvInstance(void)
dkato 0:702bf7b2b7d8 90 {
dkato 0:702bf7b2b7d8 91
dkato 0:702bf7b2b7d8 92 return &gb_info_drv;
dkato 0:702bf7b2b7d8 93 }
dkato 0:702bf7b2b7d8 94
dkato 0:702bf7b2b7d8 95 /******************************************************************************
dkato 0:702bf7b2b7d8 96 End of function DMA_GetDrv_Instance
dkato 0:702bf7b2b7d8 97 ******************************************************************************/
dkato 0:702bf7b2b7d8 98
dkato 0:702bf7b2b7d8 99 /******************************************************************************
dkato 0:702bf7b2b7d8 100 * Function Name: DMA_GetDrvChInfo
dkato 0:702bf7b2b7d8 101 * Description : Get pointer of gb_info_drv.info_ch[channel].
dkato 0:702bf7b2b7d8 102 * Arguments : *p_dma_info_drv -
dkato 0:702bf7b2b7d8 103 * Pointer of gb_info_drv is returned.
dkato 0:702bf7b2b7d8 104 * Return Value : None
dkato 0:702bf7b2b7d8 105 ******************************************************************************/
dkato 0:702bf7b2b7d8 106
dkato 0:702bf7b2b7d8 107 dma_info_ch_t *DMA_GetDrvChInfo(const int_t channel)
dkato 0:702bf7b2b7d8 108 {
dkato 0:702bf7b2b7d8 109
dkato 0:702bf7b2b7d8 110 return &gb_info_drv.info_ch[channel];
dkato 0:702bf7b2b7d8 111 }
dkato 0:702bf7b2b7d8 112
dkato 0:702bf7b2b7d8 113 /******************************************************************************
dkato 0:702bf7b2b7d8 114 End of function DMA_GetDrvChInfo
dkato 0:702bf7b2b7d8 115 ******************************************************************************/
dkato 0:702bf7b2b7d8 116
dkato 0:702bf7b2b7d8 117 /******************************************************************************
dkato 0:702bf7b2b7d8 118 * Function Name: DMA_Initialize
dkato 0:702bf7b2b7d8 119 * Description : Initialize DMA driver.
dkato 0:702bf7b2b7d8 120 * Arguments : *p_dma_init_param -
dkato 0:702bf7b2b7d8 121 * Pointer of init parameters.
dkato 0:702bf7b2b7d8 122 * Return Value : ESUCCESS -
dkato 0:702bf7b2b7d8 123 * Operation successful.
dkato 0:702bf7b2b7d8 124 * OS error num -
dkato 0:702bf7b2b7d8 125 * Registering handler failed.
dkato 0:702bf7b2b7d8 126 ******************************************************************************/
dkato 0:702bf7b2b7d8 127
dkato 5:1390bfcb667c 128 int_t DMA_Initialize(const dma_drv_init_t * const p_dma_init_param)
dkato 0:702bf7b2b7d8 129 {
dkato 0:702bf7b2b7d8 130 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 131 int_t ch_count;
dkato 0:702bf7b2b7d8 132 uint32_t error_code;
dkato 0:702bf7b2b7d8 133 bool_t init_check_flag;
dkato 0:702bf7b2b7d8 134
dkato 0:702bf7b2b7d8 135 /* ->MISRA 11.3, 11.4, IPA R3.6.2 This cast is needed for register access. */
dkato 0:702bf7b2b7d8 136 /* address table of register set for each channel */
dkato 0:702bf7b2b7d8 137 static volatile struct st_dmac_n *gb_dma_ch_register_addr_table[DMA_CH_NUM] =
dkato 0:702bf7b2b7d8 138 { &DMAC0,
dkato 0:702bf7b2b7d8 139 &DMAC1,
dkato 0:702bf7b2b7d8 140 &DMAC2,
dkato 0:702bf7b2b7d8 141 &DMAC3,
dkato 0:702bf7b2b7d8 142 &DMAC4,
dkato 0:702bf7b2b7d8 143 &DMAC5,
dkato 0:702bf7b2b7d8 144 &DMAC6,
dkato 0:702bf7b2b7d8 145 &DMAC7,
dkato 0:702bf7b2b7d8 146 &DMAC8,
dkato 0:702bf7b2b7d8 147 &DMAC9,
dkato 0:702bf7b2b7d8 148 &DMAC10,
dkato 0:702bf7b2b7d8 149 &DMAC11,
dkato 0:702bf7b2b7d8 150 &DMAC12,
dkato 0:702bf7b2b7d8 151 &DMAC13,
dkato 0:702bf7b2b7d8 152 &DMAC14,
dkato 0:702bf7b2b7d8 153 &DMAC15
dkato 0:702bf7b2b7d8 154 };
dkato 0:702bf7b2b7d8 155 /* <-MISRA 11.3, 11.4, IPA R3.6.2*/
dkato 0:702bf7b2b7d8 156
dkato 0:702bf7b2b7d8 157 /* ->MISRA 11.3, 11.4, IPA R3.6.2 This cast is needed for register access. */
dkato 0:702bf7b2b7d8 158 /* address table of register set for common register */
dkato 0:702bf7b2b7d8 159 static volatile struct st_dmaccommon_n *gb_dma_common_register_addr_table[DMA_CH_NUM] =
dkato 0:702bf7b2b7d8 160 { &DMAC07,
dkato 0:702bf7b2b7d8 161 &DMAC07,
dkato 0:702bf7b2b7d8 162 &DMAC07,
dkato 0:702bf7b2b7d8 163 &DMAC07,
dkato 0:702bf7b2b7d8 164 &DMAC07,
dkato 0:702bf7b2b7d8 165 &DMAC07,
dkato 0:702bf7b2b7d8 166 &DMAC07,
dkato 0:702bf7b2b7d8 167 &DMAC07,
dkato 0:702bf7b2b7d8 168 &DMAC815,
dkato 0:702bf7b2b7d8 169 &DMAC815,
dkato 0:702bf7b2b7d8 170 &DMAC815,
dkato 0:702bf7b2b7d8 171 &DMAC815,
dkato 0:702bf7b2b7d8 172 &DMAC815,
dkato 0:702bf7b2b7d8 173 &DMAC815,
dkato 0:702bf7b2b7d8 174 &DMAC815,
dkato 0:702bf7b2b7d8 175 &DMAC815
dkato 0:702bf7b2b7d8 176 };
dkato 0:702bf7b2b7d8 177 /* <-MISRA 11.3, 11.4, IPA R3.6.2*/
dkato 0:702bf7b2b7d8 178
dkato 0:702bf7b2b7d8 179 /* ->MISRA 11.3, 11.4 This cast is needed for register access. */
dkato 0:702bf7b2b7d8 180 /* address table of register set for DMARS */
dkato 0:702bf7b2b7d8 181 static volatile uint32_t *gb_dmars_register_addr_table[DMA_CH_NUM] =
dkato 0:702bf7b2b7d8 182 { &DMACDMARS0,
dkato 0:702bf7b2b7d8 183 &DMACDMARS0,
dkato 0:702bf7b2b7d8 184 &DMACDMARS1,
dkato 0:702bf7b2b7d8 185 &DMACDMARS1,
dkato 0:702bf7b2b7d8 186 &DMACDMARS2,
dkato 0:702bf7b2b7d8 187 &DMACDMARS2,
dkato 0:702bf7b2b7d8 188 &DMACDMARS3,
dkato 0:702bf7b2b7d8 189 &DMACDMARS3,
dkato 0:702bf7b2b7d8 190 &DMACDMARS4,
dkato 0:702bf7b2b7d8 191 &DMACDMARS4,
dkato 0:702bf7b2b7d8 192 &DMACDMARS5,
dkato 0:702bf7b2b7d8 193 &DMACDMARS5,
dkato 0:702bf7b2b7d8 194 &DMACDMARS6,
dkato 0:702bf7b2b7d8 195 &DMACDMARS6,
dkato 0:702bf7b2b7d8 196 &DMACDMARS7,
dkato 0:702bf7b2b7d8 197 &DMACDMARS7
dkato 0:702bf7b2b7d8 198 };
dkato 0:702bf7b2b7d8 199 /* <-MISRA 11.3, 11.4 */
dkato 0:702bf7b2b7d8 200
dkato 0:702bf7b2b7d8 201 /* Interrpt handlers table */
dkato 0:702bf7b2b7d8 202 static const IRQHandler gb_dma_int_handler_table[DMA_CH_NUM] =
dkato 0:702bf7b2b7d8 203 { &R_DMA_End0InterruptHandler, /* DMA end interrupt for ch0 - ch15 */
dkato 0:702bf7b2b7d8 204 &R_DMA_End1InterruptHandler,
dkato 0:702bf7b2b7d8 205 &R_DMA_End2InterruptHandler,
dkato 0:702bf7b2b7d8 206 &R_DMA_End3InterruptHandler,
dkato 0:702bf7b2b7d8 207 &R_DMA_End4InterruptHandler,
dkato 0:702bf7b2b7d8 208 &R_DMA_End5InterruptHandler,
dkato 0:702bf7b2b7d8 209 &R_DMA_End6InterruptHandler,
dkato 0:702bf7b2b7d8 210 &R_DMA_End7InterruptHandler,
dkato 0:702bf7b2b7d8 211 &R_DMA_End8InterruptHandler,
dkato 0:702bf7b2b7d8 212 &R_DMA_End9InterruptHandler,
dkato 0:702bf7b2b7d8 213 &R_DMA_End10InterruptHandler,
dkato 0:702bf7b2b7d8 214 &R_DMA_End11InterruptHandler,
dkato 0:702bf7b2b7d8 215 &R_DMA_End12InterruptHandler,
dkato 0:702bf7b2b7d8 216 &R_DMA_End13InterruptHandler,
dkato 0:702bf7b2b7d8 217 &R_DMA_End14InterruptHandler,
dkato 0:702bf7b2b7d8 218 &R_DMA_End15InterruptHandler
dkato 0:702bf7b2b7d8 219 };
dkato 0:702bf7b2b7d8 220
dkato 0:702bf7b2b7d8 221 /* Interrupt numbers table */
dkato 0:702bf7b2b7d8 222 static const IRQn_Type gb_dma_int_num_table[DMA_CH_NUM] =
dkato 0:702bf7b2b7d8 223 { DMAINT0_IRQn, /* DMA end interrupt for ch0 - ch15 */
dkato 0:702bf7b2b7d8 224 DMAINT1_IRQn,
dkato 0:702bf7b2b7d8 225 DMAINT2_IRQn,
dkato 0:702bf7b2b7d8 226 DMAINT3_IRQn,
dkato 0:702bf7b2b7d8 227 DMAINT4_IRQn,
dkato 0:702bf7b2b7d8 228 DMAINT5_IRQn,
dkato 0:702bf7b2b7d8 229 DMAINT6_IRQn,
dkato 0:702bf7b2b7d8 230 DMAINT7_IRQn,
dkato 0:702bf7b2b7d8 231 DMAINT8_IRQn,
dkato 0:702bf7b2b7d8 232 DMAINT9_IRQn,
dkato 0:702bf7b2b7d8 233 DMAINT10_IRQn,
dkato 0:702bf7b2b7d8 234 DMAINT11_IRQn,
dkato 0:702bf7b2b7d8 235 DMAINT12_IRQn,
dkato 0:702bf7b2b7d8 236 DMAINT13_IRQn,
dkato 0:702bf7b2b7d8 237 DMAINT14_IRQn,
dkato 0:702bf7b2b7d8 238 DMAINT15_IRQn
dkato 0:702bf7b2b7d8 239 };
dkato 0:702bf7b2b7d8 240
dkato 0:702bf7b2b7d8 241 /* element of p_dma_init_param is copied to element of gb_info_drv */
dkato 0:702bf7b2b7d8 242 gb_info_drv.p_err_aio = p_dma_init_param->p_aio;
dkato 0:702bf7b2b7d8 243
dkato 0:702bf7b2b7d8 244 /* set DMA error interrupt number */
dkato 0:702bf7b2b7d8 245 gb_info_drv.err_irq_num = DMAERR_IRQn;
dkato 0:702bf7b2b7d8 246
dkato 0:702bf7b2b7d8 247 /* init channel management information */
dkato 0:702bf7b2b7d8 248 for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
dkato 0:702bf7b2b7d8 249 {
dkato 0:702bf7b2b7d8 250 /* set channel number */
dkato 0:702bf7b2b7d8 251 gb_info_drv.info_ch[ch_count].ch = ch_count;
dkato 0:702bf7b2b7d8 252
dkato 0:702bf7b2b7d8 253 /* set DMA end interrupt number */
dkato 0:702bf7b2b7d8 254 gb_info_drv.info_ch[ch_count].end_irq_num = gb_dma_int_num_table[ch_count];
dkato 0:702bf7b2b7d8 255
dkato 0:702bf7b2b7d8 256 /* init next DMA setting flag */
dkato 0:702bf7b2b7d8 257 gb_info_drv.info_ch[ch_count].next_dma_flag = false;
dkato 0:702bf7b2b7d8 258
dkato 0:702bf7b2b7d8 259 if (1U == ((uint32_t)ch_count & CHECK_ODD_EVEN_MASK))
dkato 0:702bf7b2b7d8 260 {
dkato 0:702bf7b2b7d8 261 /* set shift number when channel is odd value */
dkato 0:702bf7b2b7d8 262 gb_info_drv.info_ch[ch_count].shift_dmars = SHIFT_DMARS_ODD_CH;
dkato 0:702bf7b2b7d8 263 /* set mask value when channel is odd value */
dkato 0:702bf7b2b7d8 264 gb_info_drv.info_ch[ch_count].mask_dmars = MASK_DMARS_ODD_CH;
dkato 0:702bf7b2b7d8 265 }
dkato 0:702bf7b2b7d8 266 else
dkato 0:702bf7b2b7d8 267 {
dkato 0:702bf7b2b7d8 268 /* set shift number when channel is even value */
dkato 0:702bf7b2b7d8 269 gb_info_drv.info_ch[ch_count].shift_dmars = SHIFT_DMARS_EVEN_CH;
dkato 0:702bf7b2b7d8 270 /* set mask value when channel is even value */
dkato 0:702bf7b2b7d8 271 gb_info_drv.info_ch[ch_count].mask_dmars = MASK_DMARS_EVEN_CH;
dkato 0:702bf7b2b7d8 272 }
dkato 0:702bf7b2b7d8 273
dkato 0:702bf7b2b7d8 274 /* init DMA setup flag */
dkato 0:702bf7b2b7d8 275 gb_info_drv.info_ch[ch_count].setup_flag = false;
dkato 0:702bf7b2b7d8 276
dkato 0:702bf7b2b7d8 277 /* ->MISRA 11.4 This cast is needed for register access. */
dkato 0:702bf7b2b7d8 278 /* set DMA register address for each channel */
dkato 0:702bf7b2b7d8 279 gb_info_drv.info_ch[ch_count].p_dma_ch_reg = gb_dma_ch_register_addr_table[ch_count];
dkato 0:702bf7b2b7d8 280 /* set common resgiter for channel 0 - 7 */
dkato 0:702bf7b2b7d8 281 gb_info_drv.info_ch[ch_count].p_dma_common_reg = gb_dma_common_register_addr_table[ch_count];
dkato 0:702bf7b2b7d8 282 /* <-MISRA 11.4 */
dkato 0:702bf7b2b7d8 283
dkato 0:702bf7b2b7d8 284 /* set DMARS register for each channel */
dkato 0:702bf7b2b7d8 285 gb_info_drv.info_ch[ch_count].p_dma_dmars_reg = gb_dmars_register_addr_table[ch_count];
dkato 0:702bf7b2b7d8 286 }
dkato 0:702bf7b2b7d8 287
dkato 0:702bf7b2b7d8 288 /* init DMA registers */
dkato 0:702bf7b2b7d8 289 for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
dkato 0:702bf7b2b7d8 290 {
dkato 0:702bf7b2b7d8 291 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0SA_n = N0SA_INIT_VALUE;
dkato 0:702bf7b2b7d8 292 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1SA_n = N1SA_INIT_VALUE;
dkato 0:702bf7b2b7d8 293 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0DA_n = N0DA_INIT_VALUE;
dkato 0:702bf7b2b7d8 294 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1DA_n = N1DA_INIT_VALUE;
dkato 0:702bf7b2b7d8 295 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0TB_n = N0TB_INIT_VALUE;
dkato 0:702bf7b2b7d8 296 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1TB_n = N1TB_INIT_VALUE;
dkato 0:702bf7b2b7d8 297 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCTRL_n = CHCTRL_INIT_VALUE;
dkato 0:702bf7b2b7d8 298 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCFG_n = CHCFG_INIT_VALUE;
dkato 0:702bf7b2b7d8 299 /* set DMA interval = 0 */
dkato 0:702bf7b2b7d8 300 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHITVL_n = CHITVL_INIT_VALUE;
dkato 0:702bf7b2b7d8 301 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHEXT_n = CHEXT_INIT_VALUE;
dkato 0:702bf7b2b7d8 302 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->NXLA_n = NXLA_INIT_VALUE;
dkato 0:702bf7b2b7d8 303 *(gb_info_drv.info_ch[ch_count].p_dma_dmars_reg) = DMARS_INIT_VALUE;
dkato 0:702bf7b2b7d8 304 }
dkato 0:702bf7b2b7d8 305 /* init common resgiter for channel 0 - 7 */
dkato 0:702bf7b2b7d8 306 /* set interrupt output : pulse,
dkato 0:702bf7b2b7d8 307 set round robin mode */
dkato 0:702bf7b2b7d8 308 gb_info_drv.info_ch[DMA_CH_0].p_dma_common_reg->DCTRL_0_7 = DCTRL_INIT_VALUE;
dkato 0:702bf7b2b7d8 309 /* init common resgiter for channel 8 - 15 */
dkato 0:702bf7b2b7d8 310 /* set interrupt output : pulse,
dkato 0:702bf7b2b7d8 311 set round robin mode */
dkato 0:702bf7b2b7d8 312 gb_info_drv.info_ch[HIGH_COMMON_REG_OFFSET].p_dma_common_reg->DCTRL_0_7 = DCTRL_INIT_VALUE;
dkato 0:702bf7b2b7d8 313
dkato 0:702bf7b2b7d8 314 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 315 {
dkato 0:702bf7b2b7d8 316 /* DMA end interrupt handler register */
dkato 0:702bf7b2b7d8 317 init_check_flag = false;
dkato 0:702bf7b2b7d8 318 ch_count = 0;
dkato 0:702bf7b2b7d8 319 while (false == init_check_flag)
dkato 0:702bf7b2b7d8 320 {
dkato 0:702bf7b2b7d8 321 error_code = InterruptHandlerRegister(gb_info_drv.info_ch[ch_count].end_irq_num,
dkato 0:702bf7b2b7d8 322 gb_dma_int_handler_table[ch_count]
dkato 0:702bf7b2b7d8 323 );
dkato 0:702bf7b2b7d8 324 /* 0 is no error on InterruptHandlerRegister() */
dkato 0:702bf7b2b7d8 325 if (0U != error_code)
dkato 0:702bf7b2b7d8 326 {
dkato 0:702bf7b2b7d8 327 retval = (int_t)error_code;
dkato 0:702bf7b2b7d8 328 init_check_flag = true;
dkato 0:702bf7b2b7d8 329 }
dkato 0:702bf7b2b7d8 330 if ((DMA_CH_NUM - 1) == ch_count)
dkato 0:702bf7b2b7d8 331 {
dkato 0:702bf7b2b7d8 332 init_check_flag = true;
dkato 0:702bf7b2b7d8 333 }
dkato 0:702bf7b2b7d8 334 ch_count++;
dkato 0:702bf7b2b7d8 335 }
dkato 0:702bf7b2b7d8 336
dkato 0:702bf7b2b7d8 337 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 338 {
dkato 0:702bf7b2b7d8 339 /* DMA error interrupt handler register */
dkato 0:702bf7b2b7d8 340 error_code = InterruptHandlerRegister(gb_info_drv.err_irq_num,
dkato 0:702bf7b2b7d8 341 &R_DMA_ErrInterruptHandler
dkato 0:702bf7b2b7d8 342 );
dkato 0:702bf7b2b7d8 343 /* 0 is no error on InterruptHandlerRegister() */
dkato 0:702bf7b2b7d8 344 if (0U != error_code)
dkato 0:702bf7b2b7d8 345 {
dkato 0:702bf7b2b7d8 346 retval = (int_t)error_code;
dkato 0:702bf7b2b7d8 347 }
dkato 0:702bf7b2b7d8 348 }
dkato 0:702bf7b2b7d8 349 }
dkato 0:702bf7b2b7d8 350
dkato 0:702bf7b2b7d8 351 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 352 {
dkato 0:702bf7b2b7d8 353 /* set DMA end interrupt level & priority */
dkato 0:702bf7b2b7d8 354 for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
dkato 0:702bf7b2b7d8 355 {
dkato 0:702bf7b2b7d8 356 /* set interrupt level (set edge trigger, 1-N model) */
dkato 0:702bf7b2b7d8 357 GIC_SetLevelModel(gb_info_drv.info_ch[ch_count].end_irq_num, 1, 1);
dkato 0:702bf7b2b7d8 358 }
dkato 0:702bf7b2b7d8 359 /* set DMA error interrupt level (set edge trgger, 1-N model) */
dkato 0:702bf7b2b7d8 360 GIC_SetLevelModel(gb_info_drv.err_irq_num, 1, 1);
dkato 0:702bf7b2b7d8 361 /* DMA error interrupt enable */
dkato 0:702bf7b2b7d8 362 GIC_EnableIRQ(gb_info_drv.err_irq_num);
dkato 0:702bf7b2b7d8 363 }
dkato 0:702bf7b2b7d8 364
dkato 0:702bf7b2b7d8 365 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 366 {
dkato 0:702bf7b2b7d8 367 /* set channel status */
dkato 0:702bf7b2b7d8 368 for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
dkato 0:702bf7b2b7d8 369 {
dkato 0:702bf7b2b7d8 370 if ((bool_t)false != p_dma_init_param->channel[ch_count])
dkato 0:702bf7b2b7d8 371 {
dkato 0:702bf7b2b7d8 372 gb_info_drv.info_ch[ch_count].ch_stat = DMA_CH_INIT;
dkato 0:702bf7b2b7d8 373 }
dkato 0:702bf7b2b7d8 374 else
dkato 0:702bf7b2b7d8 375 {
dkato 0:702bf7b2b7d8 376 gb_info_drv.info_ch[ch_count].ch_stat = DMA_CH_UNINIT;
dkato 0:702bf7b2b7d8 377 }
dkato 0:702bf7b2b7d8 378 }
dkato 0:702bf7b2b7d8 379 /* set driver status to DMA_DRV_INIT */
dkato 0:702bf7b2b7d8 380 gb_info_drv.drv_stat = DMA_DRV_INIT;
dkato 0:702bf7b2b7d8 381 }
dkato 0:702bf7b2b7d8 382
dkato 0:702bf7b2b7d8 383 return retval;
dkato 0:702bf7b2b7d8 384 }
dkato 0:702bf7b2b7d8 385
dkato 0:702bf7b2b7d8 386 /******************************************************************************
dkato 0:702bf7b2b7d8 387 End of function DMA_Initialize
dkato 0:702bf7b2b7d8 388 ******************************************************************************/
dkato 0:702bf7b2b7d8 389
dkato 0:702bf7b2b7d8 390 /******************************************************************************
dkato 0:702bf7b2b7d8 391 * Function Name: DMA_UnInitialize
dkato 0:702bf7b2b7d8 392 * Description : UnInitialize DMA driver.
dkato 0:702bf7b2b7d8 393 * Arguments : None.
dkato 0:702bf7b2b7d8 394 * Return Value : ESUCCESS -
dkato 0:702bf7b2b7d8 395 * Operation successful.
dkato 0:702bf7b2b7d8 396 * OS error num -
dkato 5:1390bfcb667c 397 * Unregistering handler failed
dkato 0:702bf7b2b7d8 398 ******************************************************************************/
dkato 0:702bf7b2b7d8 399
dkato 0:702bf7b2b7d8 400 int_t DMA_UnInitialize(void)
dkato 0:702bf7b2b7d8 401 {
dkato 0:702bf7b2b7d8 402 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 403 int_t ch_count;
dkato 0:702bf7b2b7d8 404 uint32_t error_code;
dkato 0:702bf7b2b7d8 405 bool_t uninit_check_flag;
dkato 0:702bf7b2b7d8 406
dkato 0:702bf7b2b7d8 407 /* init DMA registers */
dkato 0:702bf7b2b7d8 408 for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
dkato 0:702bf7b2b7d8 409 {
dkato 0:702bf7b2b7d8 410 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCTRL_n = 0;
dkato 0:702bf7b2b7d8 411 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCFG_n = 0;
dkato 0:702bf7b2b7d8 412 *(gb_info_drv.info_ch[ch_count].p_dma_dmars_reg) = 0;
dkato 0:702bf7b2b7d8 413 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0SA_n = 0;
dkato 0:702bf7b2b7d8 414 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1SA_n = 0;
dkato 0:702bf7b2b7d8 415 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0DA_n = 0;
dkato 0:702bf7b2b7d8 416 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1DA_n = 0;
dkato 0:702bf7b2b7d8 417 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0TB_n = 0;
dkato 0:702bf7b2b7d8 418 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1TB_n = 0;
dkato 0:702bf7b2b7d8 419 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHITVL_n = 0;
dkato 0:702bf7b2b7d8 420 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHEXT_n = 0;
dkato 0:702bf7b2b7d8 421 gb_info_drv.info_ch[ch_count].p_dma_ch_reg->NXLA_n = 0;
dkato 0:702bf7b2b7d8 422 }
dkato 0:702bf7b2b7d8 423 /* init common resgiter for channel 0 - 7 */
dkato 0:702bf7b2b7d8 424 gb_info_drv.info_ch[DMA_CH_0].p_dma_common_reg->DCTRL_0_7 = 0;
dkato 0:702bf7b2b7d8 425 /* init common resgiter for channel 8 - 15 */
dkato 0:702bf7b2b7d8 426 gb_info_drv.info_ch[HIGH_COMMON_REG_OFFSET].p_dma_common_reg->DCTRL_0_7 = 0;
dkato 0:702bf7b2b7d8 427
dkato 0:702bf7b2b7d8 428 /* uninit DMA interrupt */
dkato 0:702bf7b2b7d8 429 ch_count = 0;
dkato 0:702bf7b2b7d8 430 uninit_check_flag = false;
dkato 0:702bf7b2b7d8 431 while (false == uninit_check_flag)
dkato 0:702bf7b2b7d8 432 {
dkato 0:702bf7b2b7d8 433 /* disable DMA end interrupt */
dkato 0:702bf7b2b7d8 434 GIC_DisableIRQ(gb_info_drv.info_ch[ch_count].end_irq_num);
dkato 0:702bf7b2b7d8 435
dkato 0:702bf7b2b7d8 436 /* unregister DMA end interrupt handler */
dkato 0:702bf7b2b7d8 437 error_code = InterruptHandlerUnregister(gb_info_drv.info_ch[ch_count].end_irq_num);
dkato 0:702bf7b2b7d8 438 /* 0 is no error on InterruptHandlerUnRegister() */
dkato 0:702bf7b2b7d8 439 if (0U != error_code)
dkato 0:702bf7b2b7d8 440 {
dkato 0:702bf7b2b7d8 441 retval = (int_t)error_code;
dkato 0:702bf7b2b7d8 442 uninit_check_flag = true;
dkato 0:702bf7b2b7d8 443 }
dkato 0:702bf7b2b7d8 444 if ((DMA_CH_NUM - 1) == ch_count)
dkato 0:702bf7b2b7d8 445 {
dkato 0:702bf7b2b7d8 446 uninit_check_flag = true;
dkato 0:702bf7b2b7d8 447 }
dkato 0:702bf7b2b7d8 448 ch_count++;
dkato 0:702bf7b2b7d8 449 }
dkato 0:702bf7b2b7d8 450 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 451 {
dkato 0:702bf7b2b7d8 452 /* disable DMA error interrupt */
dkato 0:702bf7b2b7d8 453 GIC_DisableIRQ(gb_info_drv.err_irq_num);
dkato 0:702bf7b2b7d8 454
dkato 0:702bf7b2b7d8 455 /* unregister DMA interrupt error handler */
dkato 0:702bf7b2b7d8 456 error_code = InterruptHandlerUnregister(gb_info_drv.err_irq_num);
dkato 0:702bf7b2b7d8 457 /* 0 is no error on InterruptHandlerUnRegister() */
dkato 0:702bf7b2b7d8 458 if (0U != error_code)
dkato 0:702bf7b2b7d8 459 {
dkato 0:702bf7b2b7d8 460 retval = (int_t)error_code;
dkato 0:702bf7b2b7d8 461 }
dkato 0:702bf7b2b7d8 462 }
dkato 0:702bf7b2b7d8 463
dkato 0:702bf7b2b7d8 464 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 465 {
dkato 0:702bf7b2b7d8 466 /* set channel status to DMA_CH_UNINIT */
dkato 0:702bf7b2b7d8 467 for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
dkato 0:702bf7b2b7d8 468 {
dkato 0:702bf7b2b7d8 469 gb_info_drv.info_ch[ch_count].ch_stat = DMA_CH_UNINIT;
dkato 0:702bf7b2b7d8 470 }
dkato 0:702bf7b2b7d8 471 /* set driver status to DMA_DRV_UNINIT*/
dkato 0:702bf7b2b7d8 472 gb_info_drv.drv_stat = DMA_DRV_UNINIT;
dkato 0:702bf7b2b7d8 473 }
dkato 0:702bf7b2b7d8 474
dkato 0:702bf7b2b7d8 475 return retval;
dkato 0:702bf7b2b7d8 476 }
dkato 0:702bf7b2b7d8 477
dkato 0:702bf7b2b7d8 478 /******************************************************************************
dkato 0:702bf7b2b7d8 479 End of function DMA_UnInitialize
dkato 0:702bf7b2b7d8 480 ******************************************************************************/
dkato 0:702bf7b2b7d8 481
dkato 0:702bf7b2b7d8 482 /******************************************************************************
dkato 0:702bf7b2b7d8 483 * Function Name: DMA_OpenChannel
dkato 0:702bf7b2b7d8 484 * Description : DMA channel open.
dkato 0:702bf7b2b7d8 485 * Set DMA channel status to DMA_CH_OPEN.
dkato 0:702bf7b2b7d8 486 * Arguments : channel -
dkato 0:702bf7b2b7d8 487 * Open channel number.
dkato 0:702bf7b2b7d8 488 * Return Value : None.
dkato 0:702bf7b2b7d8 489 ******************************************************************************/
dkato 0:702bf7b2b7d8 490
dkato 0:702bf7b2b7d8 491 static void DMA_OpenChannel(const int_t channel)
dkato 0:702bf7b2b7d8 492 {
dkato 0:702bf7b2b7d8 493 /* set channel status to DMA_CH_OPEN */
dkato 0:702bf7b2b7d8 494 gb_info_drv.info_ch[channel].ch_stat = DMA_CH_OPEN;
dkato 0:702bf7b2b7d8 495
dkato 0:702bf7b2b7d8 496 return;
dkato 0:702bf7b2b7d8 497 }
dkato 0:702bf7b2b7d8 498
dkato 0:702bf7b2b7d8 499 /******************************************************************************
dkato 0:702bf7b2b7d8 500 End of function DMA_OpenChannel
dkato 0:702bf7b2b7d8 501 ******************************************************************************/
dkato 0:702bf7b2b7d8 502
dkato 0:702bf7b2b7d8 503 /******************************************************************************
dkato 0:702bf7b2b7d8 504 * Function Name: DMA_GetFreeChannel
dkato 0:702bf7b2b7d8 505 * Description : Find free DMA channel and Get DMA channel.
dkato 0:702bf7b2b7d8 506 * Arguments : None
dkato 0:702bf7b2b7d8 507 * Return Value : channel -
dkato 0:702bf7b2b7d8 508 * Open channel number.
dkato 0:702bf7b2b7d8 509 * error code -
dkato 5:1390bfcb667c 510 * EMFILE : When looking for a free channel, but a free
dkato 5:1390bfcb667c 511 * channel didn't exist.
dkato 0:702bf7b2b7d8 512 ******************************************************************************/
dkato 0:702bf7b2b7d8 513
dkato 0:702bf7b2b7d8 514 int_t DMA_GetFreeChannel(void)
dkato 0:702bf7b2b7d8 515 {
dkato 0:702bf7b2b7d8 516 int_t retval = EFAULT;
dkato 0:702bf7b2b7d8 517 dma_info_ch_t *dma_info_ch;
dkato 0:702bf7b2b7d8 518 int_t ch_alloc;
dkato 0:702bf7b2b7d8 519 bool_t ch_stat_check_flag;
dkato 0:702bf7b2b7d8 520
dkato 0:702bf7b2b7d8 521 /* looking for free channel */
dkato 0:702bf7b2b7d8 522 ch_stat_check_flag = false;
dkato 0:702bf7b2b7d8 523 ch_alloc = 0;
dkato 0:702bf7b2b7d8 524 while (false == ch_stat_check_flag)
dkato 0:702bf7b2b7d8 525 {
dkato 0:702bf7b2b7d8 526 dma_info_ch = DMA_GetDrvChInfo(ch_alloc);
dkato 0:702bf7b2b7d8 527
dkato 0:702bf7b2b7d8 528 if (false == ch_stat_check_flag)
dkato 0:702bf7b2b7d8 529 {
dkato 0:702bf7b2b7d8 530 if (DMA_CH_INIT == dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 531 {
dkato 0:702bf7b2b7d8 532 DMA_OpenChannel(ch_alloc);
dkato 0:702bf7b2b7d8 533 retval = ch_alloc;
dkato 0:702bf7b2b7d8 534 ch_stat_check_flag = true;
dkato 0:702bf7b2b7d8 535 }
dkato 0:702bf7b2b7d8 536 if (false == ch_stat_check_flag)
dkato 0:702bf7b2b7d8 537 {
dkato 0:702bf7b2b7d8 538 ch_alloc++;
dkato 0:702bf7b2b7d8 539 /* not detected free channel */
dkato 0:702bf7b2b7d8 540 if (DMA_CH_NUM == ch_alloc)
dkato 0:702bf7b2b7d8 541 {
dkato 0:702bf7b2b7d8 542 /* set error return value */
dkato 0:702bf7b2b7d8 543 retval = EMFILE;
dkato 0:702bf7b2b7d8 544 ch_stat_check_flag = true;
dkato 0:702bf7b2b7d8 545 }
dkato 0:702bf7b2b7d8 546 }
dkato 0:702bf7b2b7d8 547 }
dkato 0:702bf7b2b7d8 548 }
dkato 0:702bf7b2b7d8 549
dkato 0:702bf7b2b7d8 550 return retval;
dkato 0:702bf7b2b7d8 551 }
dkato 0:702bf7b2b7d8 552
dkato 0:702bf7b2b7d8 553 /******************************************************************************
dkato 0:702bf7b2b7d8 554 End of function DMA_GetFreeChannel
dkato 0:702bf7b2b7d8 555 ******************************************************************************/
dkato 0:702bf7b2b7d8 556
dkato 0:702bf7b2b7d8 557 /******************************************************************************
dkato 0:702bf7b2b7d8 558 * Function Name: DMA_GetFixedChannel
dkato 0:702bf7b2b7d8 559 * Description : Get specified DMA channel number.
dkato 0:702bf7b2b7d8 560 * Arguments : channel -
dkato 0:702bf7b2b7d8 561 * Open channel number.
dkato 0:702bf7b2b7d8 562 * Return Value : channel -
dkato 0:702bf7b2b7d8 563 * Open channel number.
dkato 0:702bf7b2b7d8 564 * error code -
dkato 0:702bf7b2b7d8 565 * EBUSY : It has been allocated already in channel.
dkato 0:702bf7b2b7d8 566 * ENOTSUP : Channel status is DMA_CH_UNINIT.
dkato 0:702bf7b2b7d8 567 * EFAULT: Channel status is besides the status definded in
dkato 0:702bf7b2b7d8 568 * dma_stat_ch_t.
dkato 0:702bf7b2b7d8 569 ******************************************************************************/
dkato 0:702bf7b2b7d8 570
dkato 0:702bf7b2b7d8 571 int_t DMA_GetFixedChannel(const int_t channel)
dkato 0:702bf7b2b7d8 572 {
dkato 0:702bf7b2b7d8 573 int_t retval = ESUCCESS;
dkato 0:702bf7b2b7d8 574 dma_info_ch_t *dma_info_ch;
dkato 0:702bf7b2b7d8 575
dkato 0:702bf7b2b7d8 576 /* allocate the specified number */
dkato 0:702bf7b2b7d8 577 dma_info_ch = DMA_GetDrvChInfo(channel);
dkato 0:702bf7b2b7d8 578
dkato 0:702bf7b2b7d8 579 if (ESUCCESS == retval)
dkato 0:702bf7b2b7d8 580 {
dkato 0:702bf7b2b7d8 581 if (DMA_CH_INIT == dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 582 {
dkato 0:702bf7b2b7d8 583 DMA_OpenChannel(channel);
dkato 0:702bf7b2b7d8 584 /* return alloc channel number */
dkato 0:702bf7b2b7d8 585 retval = channel;
dkato 0:702bf7b2b7d8 586 }
dkato 0:702bf7b2b7d8 587 else
dkato 0:702bf7b2b7d8 588 {
dkato 0:702bf7b2b7d8 589 /* set error return value */
dkato 0:702bf7b2b7d8 590 switch (dma_info_ch->ch_stat)
dkato 0:702bf7b2b7d8 591 {
dkato 0:702bf7b2b7d8 592 case DMA_CH_UNINIT:
dkato 0:702bf7b2b7d8 593 retval = ENOTSUP;
dkato 0:702bf7b2b7d8 594 break;
dkato 0:702bf7b2b7d8 595 /* These 2 cases are intentionally combined. */
dkato 0:702bf7b2b7d8 596 case DMA_CH_OPEN:
dkato 0:702bf7b2b7d8 597 case DMA_CH_TRANSFER:
dkato 0:702bf7b2b7d8 598 retval = EBUSY;
dkato 0:702bf7b2b7d8 599 break;
dkato 0:702bf7b2b7d8 600
dkato 0:702bf7b2b7d8 601 default:
dkato 0:702bf7b2b7d8 602 retval = EFAULT;
dkato 0:702bf7b2b7d8 603 break;
dkato 0:702bf7b2b7d8 604
dkato 0:702bf7b2b7d8 605 }
dkato 0:702bf7b2b7d8 606 }
dkato 0:702bf7b2b7d8 607 }
dkato 0:702bf7b2b7d8 608
dkato 0:702bf7b2b7d8 609 return retval;
dkato 0:702bf7b2b7d8 610 }
dkato 0:702bf7b2b7d8 611
dkato 0:702bf7b2b7d8 612 /******************************************************************************
dkato 0:702bf7b2b7d8 613 End of function DMA_GetFixedChannel
dkato 0:702bf7b2b7d8 614 ******************************************************************************/
dkato 0:702bf7b2b7d8 615
dkato 0:702bf7b2b7d8 616 /******************************************************************************
dkato 0:702bf7b2b7d8 617 * Function Name: DMA_CloseChannel
dkato 0:702bf7b2b7d8 618 * Description : DMA channel close.
dkato 0:702bf7b2b7d8 619 * Set DMA channel status to DMA_CH_INIT.
dkato 0:702bf7b2b7d8 620 * Arguments : channel -
dkato 0:702bf7b2b7d8 621 * Close channel number.
dkato 0:702bf7b2b7d8 622 * Return Value : None.
dkato 0:702bf7b2b7d8 623 ******************************************************************************/
dkato 0:702bf7b2b7d8 624
dkato 0:702bf7b2b7d8 625 void DMA_CloseChannel(const int_t channel)
dkato 0:702bf7b2b7d8 626 {
dkato 0:702bf7b2b7d8 627 /* clear DMARS register */
dkato 0:702bf7b2b7d8 628 *(gb_info_drv.info_ch[channel].p_dma_dmars_reg) &= gb_info_drv.info_ch[channel].mask_dmars;
dkato 5:1390bfcb667c 629
dkato 0:702bf7b2b7d8 630 /* set channel status to DMA_CH_INIT */
dkato 0:702bf7b2b7d8 631 gb_info_drv.info_ch[channel].ch_stat = DMA_CH_INIT;
dkato 0:702bf7b2b7d8 632
dkato 0:702bf7b2b7d8 633 return;
dkato 0:702bf7b2b7d8 634 }
dkato 0:702bf7b2b7d8 635
dkato 0:702bf7b2b7d8 636 /******************************************************************************
dkato 0:702bf7b2b7d8 637 End of function DMA_CloseChannel
dkato 0:702bf7b2b7d8 638 ******************************************************************************/
dkato 0:702bf7b2b7d8 639
dkato 0:702bf7b2b7d8 640 /******************************************************************************
dkato 0:702bf7b2b7d8 641 * Function Name: DMA_Setparam
dkato 0:702bf7b2b7d8 642 * Description : Set DMA transfer parameter to Register.
dkato 0:702bf7b2b7d8 643 * Arguments : channel -
dkato 0:702bf7b2b7d8 644 * Set up channel number.
dkato 0:702bf7b2b7d8 645 * *p_ch_setup -
dkato 0:702bf7b2b7d8 646 * Set up parameters.
dkato 0:702bf7b2b7d8 647 * *p_ch_cfg -
dkato 0:702bf7b2b7d8 648 * DMA channel config table parameters.
dkato 0:702bf7b2b7d8 649 * *reqd
dkato 0:702bf7b2b7d8 650 * set vaule for REQD bit on CHCFG
dkato 0:702bf7b2b7d8 651 * Return Value : None.
dkato 0:702bf7b2b7d8 652 ******************************************************************************/
dkato 0:702bf7b2b7d8 653
dkato 0:702bf7b2b7d8 654 void DMA_SetParam(const int_t channel, const dma_ch_setup_t *const p_ch_setup,
dkato 0:702bf7b2b7d8 655 const dma_ch_cfg_t * const p_ch_cfg, const uint32_t reqd)
dkato 0:702bf7b2b7d8 656 {
dkato 0:702bf7b2b7d8 657 uint32_t chcfg_sel;
dkato 0:702bf7b2b7d8 658 uint32_t value_dmars;
dkato 0:702bf7b2b7d8 659
dkato 0:702bf7b2b7d8 660 /* set DMA transfer parameter to DMA channel infomation */
dkato 0:702bf7b2b7d8 661 gb_info_drv.info_ch[channel].resource = p_ch_setup->resource;
dkato 0:702bf7b2b7d8 662 gb_info_drv.info_ch[channel].direction = p_ch_setup->direction;
dkato 0:702bf7b2b7d8 663 gb_info_drv.info_ch[channel].src_width = p_ch_setup->src_width;
dkato 0:702bf7b2b7d8 664 gb_info_drv.info_ch[channel].src_cnt = p_ch_setup->src_cnt;
dkato 0:702bf7b2b7d8 665 gb_info_drv.info_ch[channel].dst_width = p_ch_setup->dst_width;
dkato 0:702bf7b2b7d8 666 gb_info_drv.info_ch[channel].dst_cnt = p_ch_setup->dst_cnt;
dkato 0:702bf7b2b7d8 667 gb_info_drv.info_ch[channel].p_end_aio = p_ch_setup->p_aio;
dkato 0:702bf7b2b7d8 668
dkato 0:702bf7b2b7d8 669 /* set DMARS value and protect non change bit */
dkato 0:702bf7b2b7d8 670 value_dmars = *(gb_info_drv.info_ch[channel].p_dma_dmars_reg);
dkato 0:702bf7b2b7d8 671 value_dmars = ((value_dmars & gb_info_drv.info_ch[channel].mask_dmars) |
dkato 0:702bf7b2b7d8 672 (uint32_t)(p_ch_cfg->dmars << gb_info_drv.info_ch[channel].shift_dmars));
dkato 0:702bf7b2b7d8 673 /* set DMARS register value */
dkato 0:702bf7b2b7d8 674 *(gb_info_drv.info_ch[channel].p_dma_dmars_reg) = value_dmars;
dkato 0:702bf7b2b7d8 675
dkato 0:702bf7b2b7d8 676 /* set CHCFG regsiter */
dkato 0:702bf7b2b7d8 677 if (channel < HIGH_COMMON_REG_OFFSET)
dkato 0:702bf7b2b7d8 678 {
dkato 0:702bf7b2b7d8 679 chcfg_sel = (uint32_t)channel;
dkato 0:702bf7b2b7d8 680 }
dkato 0:702bf7b2b7d8 681 else
dkato 0:702bf7b2b7d8 682 {
dkato 0:702bf7b2b7d8 683 chcfg_sel = (uint32_t)(channel - HIGH_COMMON_REG_OFFSET);
dkato 0:702bf7b2b7d8 684 }
dkato 0:702bf7b2b7d8 685 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n
dkato 0:702bf7b2b7d8 686 = ((uint32_t)CHCFG_FIXED_VALUE |
dkato 0:702bf7b2b7d8 687 /* ->MISRA 21.1 ,IPA R2.4.1 The value of every parameter won't be minus.
dkato 0:702bf7b2b7d8 688 and the value after a shift will be less than 0x80000000 certainly.
dkato 0:702bf7b2b7d8 689 */
dkato 0:702bf7b2b7d8 690 (((uint32_t)p_ch_setup->dst_cnt << CHCFG_SHIFT_DAD) & CHCFG_MASK_DAD) |
dkato 0:702bf7b2b7d8 691 (((uint32_t)p_ch_setup->src_cnt << CHCFG_SHIFT_SAD) & CHCFG_MASK_SAD) |
dkato 0:702bf7b2b7d8 692 (((uint32_t)p_ch_setup->dst_width << CHCFG_SHIFT_DDS) & CHCFG_MASK_DDS) |
dkato 0:702bf7b2b7d8 693 (((uint32_t)p_ch_setup->src_width << CHCFG_SHIFT_SDS) & CHCFG_MASK_SDS) |
dkato 0:702bf7b2b7d8 694 /* <-MISRA 21.1, IPA R2.4.1 */
dkato 0:702bf7b2b7d8 695 p_ch_cfg->tm |
dkato 0:702bf7b2b7d8 696 p_ch_cfg->lvl |
dkato 0:702bf7b2b7d8 697 reqd |
dkato 0:702bf7b2b7d8 698 chcfg_sel);
dkato 0:702bf7b2b7d8 699
dkato 0:702bf7b2b7d8 700 /* set setup flag */
dkato 0:702bf7b2b7d8 701 gb_info_drv.info_ch[channel].setup_flag = true;
dkato 0:702bf7b2b7d8 702
dkato 0:702bf7b2b7d8 703 return;
dkato 0:702bf7b2b7d8 704 }
dkato 0:702bf7b2b7d8 705
dkato 0:702bf7b2b7d8 706 /******************************************************************************
dkato 0:702bf7b2b7d8 707 End of function DMA_SetParam
dkato 0:702bf7b2b7d8 708 ******************************************************************************/
dkato 0:702bf7b2b7d8 709
dkato 0:702bf7b2b7d8 710 /******************************************************************************
dkato 0:702bf7b2b7d8 711 * Function Name: DMA_BusParam
dkato 0:702bf7b2b7d8 712 * Description : Set bus parameter for DMA.
dkato 0:702bf7b2b7d8 713 * Arguments : channel -
dkato 0:702bf7b2b7d8 714 * Set address channel number.
dkato 0:702bf7b2b7d8 715 * *p_dma_data -
dkato 0:702bf7b2b7d8 716 * DMA transfer address parameter set.
dkato 0:702bf7b2b7d8 717 * Return Value : None.
dkato 0:702bf7b2b7d8 718 ******************************************************************************/
dkato 0:702bf7b2b7d8 719
dkato 0:702bf7b2b7d8 720 void DMA_BusParam(const int_t channel, const dma_trans_data_t * const p_dma_data)
dkato 0:702bf7b2b7d8 721 {
dkato 0:702bf7b2b7d8 722 uint32_t src_bus_addr = (uint32_t)p_dma_data->src_addr;
dkato 0:702bf7b2b7d8 723 uint32_t dst_bus_addr = (uint32_t)p_dma_data->dst_addr;
dkato 0:702bf7b2b7d8 724 uint32_t chext_value = (CHEXT_SET_DPR_NON_SECURE | CHEXT_SET_SPR_NON_SECURE);
dkato 0:702bf7b2b7d8 725
dkato 0:702bf7b2b7d8 726 /* set bus parameter for SRC */
dkato 0:702bf7b2b7d8 727 if ((DMA_EXTERNAL_BUS_END >= src_bus_addr) ||
dkato 0:702bf7b2b7d8 728 ((DMA_EXTERNAL_BUS_MIRROR_START <= src_bus_addr) &&
dkato 0:702bf7b2b7d8 729 (DMA_EXTERNAL_BUS_MIRROR_END >= src_bus_addr)))
dkato 0:702bf7b2b7d8 730
dkato 0:702bf7b2b7d8 731 {
dkato 0:702bf7b2b7d8 732 chext_value |= CHEXT_SET_SCA_NORMAL;
dkato 0:702bf7b2b7d8 733 }
dkato 0:702bf7b2b7d8 734 else
dkato 0:702bf7b2b7d8 735 {
dkato 0:702bf7b2b7d8 736 chext_value |= CHEXT_SET_SCA_STRONG;
dkato 0:702bf7b2b7d8 737 }
dkato 0:702bf7b2b7d8 738
dkato 0:702bf7b2b7d8 739 /* set bus parameter for DST */
dkato 0:702bf7b2b7d8 740 if ((DMA_EXTERNAL_BUS_END >= dst_bus_addr) ||
dkato 0:702bf7b2b7d8 741 ((DMA_EXTERNAL_BUS_MIRROR_START <= dst_bus_addr) &&
dkato 0:702bf7b2b7d8 742 (DMA_EXTERNAL_BUS_MIRROR_END >= dst_bus_addr)))
dkato 0:702bf7b2b7d8 743
dkato 0:702bf7b2b7d8 744 {
dkato 0:702bf7b2b7d8 745 chext_value |= CHEXT_SET_DCA_NORMAL;
dkato 0:702bf7b2b7d8 746 }
dkato 0:702bf7b2b7d8 747 else
dkato 0:702bf7b2b7d8 748 {
dkato 0:702bf7b2b7d8 749 chext_value |= CHEXT_SET_DCA_STRONG;
dkato 0:702bf7b2b7d8 750 }
dkato 0:702bf7b2b7d8 751
dkato 0:702bf7b2b7d8 752 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHEXT_n = chext_value;
dkato 0:702bf7b2b7d8 753
dkato 0:702bf7b2b7d8 754 return;
dkato 0:702bf7b2b7d8 755 }
dkato 0:702bf7b2b7d8 756
dkato 0:702bf7b2b7d8 757 /******************************************************************************
dkato 0:702bf7b2b7d8 758 End of function DMA_BusParam
dkato 0:702bf7b2b7d8 759 ******************************************************************************/
dkato 0:702bf7b2b7d8 760
dkato 0:702bf7b2b7d8 761 /******************************************************************************
dkato 0:702bf7b2b7d8 762 * Function Name: DMA_SetData
dkato 0:702bf7b2b7d8 763 * Description : Set DMA transfer address to Register.
dkato 0:702bf7b2b7d8 764 * Arguments : channel -
dkato 0:702bf7b2b7d8 765 * Set address channel number.
dkato 0:702bf7b2b7d8 766 * *p_dma_data -
dkato 0:702bf7b2b7d8 767 * DMA transfer address parameter set.
dkato 0:702bf7b2b7d8 768 * next_register_set -
dkato 0:702bf7b2b7d8 769 * Number of next register set.
dkato 0:702bf7b2b7d8 770 * Return Value : None.
dkato 0:702bf7b2b7d8 771 ******************************************************************************/
dkato 0:702bf7b2b7d8 772
dkato 0:702bf7b2b7d8 773 void DMA_SetData(const int_t channel, const dma_trans_data_t * const p_dma_data,
dkato 0:702bf7b2b7d8 774 const uint32_t next_register_set)
dkato 0:702bf7b2b7d8 775 {
dkato 0:702bf7b2b7d8 776 if (0U == next_register_set)
dkato 0:702bf7b2b7d8 777 {
dkato 0:702bf7b2b7d8 778 /* set DMA transfer address parameters to next register set0 */
dkato 0:702bf7b2b7d8 779 gb_info_drv.info_ch[channel].src_addr0 = p_dma_data->src_addr;
dkato 0:702bf7b2b7d8 780 gb_info_drv.info_ch[channel].dst_addr0 = p_dma_data->dst_addr;
dkato 0:702bf7b2b7d8 781 gb_info_drv.info_ch[channel].count0 = p_dma_data->count;
dkato 0:702bf7b2b7d8 782
dkato 0:702bf7b2b7d8 783 /* ->MISRA 11.3 This cast is needed for setting address to register. */
dkato 0:702bf7b2b7d8 784 /* set DAM transfer addres to register */
dkato 0:702bf7b2b7d8 785 gb_info_drv.info_ch[channel].p_dma_ch_reg->N0SA_n = (uint32_t)p_dma_data->src_addr;
dkato 0:702bf7b2b7d8 786 gb_info_drv.info_ch[channel].p_dma_ch_reg->N0DA_n = (uint32_t)p_dma_data->dst_addr;
dkato 0:702bf7b2b7d8 787 /* <-MISRA 11.3 */
dkato 0:702bf7b2b7d8 788 gb_info_drv.info_ch[channel].p_dma_ch_reg->N0TB_n = p_dma_data->count;
dkato 0:702bf7b2b7d8 789 }
dkato 0:702bf7b2b7d8 790 else
dkato 0:702bf7b2b7d8 791 {
dkato 0:702bf7b2b7d8 792 /* set DMA transfer address parameters to next regiter set1 */
dkato 0:702bf7b2b7d8 793 gb_info_drv.info_ch[channel].src_addr1 = p_dma_data->src_addr;
dkato 0:702bf7b2b7d8 794 gb_info_drv.info_ch[channel].dst_addr1 = p_dma_data->dst_addr;
dkato 0:702bf7b2b7d8 795 gb_info_drv.info_ch[channel].count1 = p_dma_data->count;
dkato 0:702bf7b2b7d8 796
dkato 0:702bf7b2b7d8 797 /* ->MISRA 11.3 This cast is needed for setting address to register. */
dkato 0:702bf7b2b7d8 798 /* set DAM transfer addres to register */
dkato 0:702bf7b2b7d8 799 gb_info_drv.info_ch[channel].p_dma_ch_reg->N1SA_n = (uint32_t)p_dma_data->src_addr;
dkato 0:702bf7b2b7d8 800 gb_info_drv.info_ch[channel].p_dma_ch_reg->N1DA_n = (uint32_t)p_dma_data->dst_addr;
dkato 0:702bf7b2b7d8 801 /* <-MISRA 11.3 */
dkato 0:702bf7b2b7d8 802 gb_info_drv.info_ch[channel].p_dma_ch_reg->N1TB_n = p_dma_data->count;
dkato 0:702bf7b2b7d8 803 }
dkato 0:702bf7b2b7d8 804
dkato 0:702bf7b2b7d8 805 return;
dkato 0:702bf7b2b7d8 806 }
dkato 0:702bf7b2b7d8 807
dkato 0:702bf7b2b7d8 808 /******************************************************************************
dkato 0:702bf7b2b7d8 809 End of function DMA_SetData
dkato 0:702bf7b2b7d8 810 ******************************************************************************/
dkato 0:702bf7b2b7d8 811
dkato 0:702bf7b2b7d8 812 /******************************************************************************
dkato 0:702bf7b2b7d8 813 * Function Name: DMA_SetNextData
dkato 0:702bf7b2b7d8 814 * Description : Set continuous DMA transfer setting.
dkato 0:702bf7b2b7d8 815 * Arguments : channel -
dkato 0:702bf7b2b7d8 816 * Set continuous DMA transfer channel number.
dkato 0:702bf7b2b7d8 817 * *p_dma_data -
dkato 0:702bf7b2b7d8 818 * DMA transfer address parameter set.
dkato 0:702bf7b2b7d8 819 * Return Value : None.
dkato 0:702bf7b2b7d8 820 ******************************************************************************/
dkato 0:702bf7b2b7d8 821
dkato 0:702bf7b2b7d8 822 void DMA_SetNextData(const int_t channel, const dma_trans_data_t * const p_dma_data)
dkato 0:702bf7b2b7d8 823 {
dkato 0:702bf7b2b7d8 824 uint32_t next_register_set;
dkato 0:702bf7b2b7d8 825
dkato 0:702bf7b2b7d8 826 /* check number of next register set for next DMA transfer */
dkato 0:702bf7b2b7d8 827 /* The reverse number in current number is set in next regsiter set of next DMA. */
dkato 0:702bf7b2b7d8 828 if (0U == (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_SR))
dkato 0:702bf7b2b7d8 829 {
dkato 0:702bf7b2b7d8 830 next_register_set = 1U;
dkato 0:702bf7b2b7d8 831 }
dkato 0:702bf7b2b7d8 832 else
dkato 0:702bf7b2b7d8 833 {
dkato 0:702bf7b2b7d8 834 next_register_set = 0U;
dkato 0:702bf7b2b7d8 835 }
dkato 0:702bf7b2b7d8 836
dkato 0:702bf7b2b7d8 837 /* set DMA transfer address for next DMA */
dkato 0:702bf7b2b7d8 838 DMA_SetData(channel, p_dma_data, next_register_set);
dkato 0:702bf7b2b7d8 839
dkato 0:702bf7b2b7d8 840 /* start setting for next DMA */
dkato 0:702bf7b2b7d8 841 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n |= (uint32_t)(CHCFG_SET_REN | CHCFG_SET_RSW);
dkato 0:702bf7b2b7d8 842
dkato 0:702bf7b2b7d8 843 /* set flag wich indicates that next DMA transfer set already */
dkato 0:702bf7b2b7d8 844 gb_info_drv.info_ch[channel].next_dma_flag = true;
dkato 0:702bf7b2b7d8 845
dkato 0:702bf7b2b7d8 846 /* auto restart continous DMA */
dkato 0:702bf7b2b7d8 847 if ((0U == (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_EN)) &&
dkato 0:702bf7b2b7d8 848 (false == gb_info_drv.info_ch[channel].setup_flag))
dkato 0:702bf7b2b7d8 849 {
dkato 0:702bf7b2b7d8 850 /* auto restart DMA */
dkato 0:702bf7b2b7d8 851 DMA_SetData(channel, p_dma_data, 0);
dkato 0:702bf7b2b7d8 852 DMA_Start(channel, true);
dkato 0:702bf7b2b7d8 853 }
dkato 0:702bf7b2b7d8 854
dkato 0:702bf7b2b7d8 855 return;
dkato 0:702bf7b2b7d8 856 }
dkato 0:702bf7b2b7d8 857
dkato 0:702bf7b2b7d8 858 /******************************************************************************
dkato 0:702bf7b2b7d8 859 End of function DMA_Nextdata
dkato 0:702bf7b2b7d8 860 ******************************************************************************/
dkato 0:702bf7b2b7d8 861
dkato 0:702bf7b2b7d8 862 /******************************************************************************
dkato 0:702bf7b2b7d8 863 * Function Name: DMA_Start
dkato 0:702bf7b2b7d8 864 * Description : Start DMA transfer.
dkato 0:702bf7b2b7d8 865 * Arguments : channel -
dkato 0:702bf7b2b7d8 866 * DMA transfer start channel number.
dkato 0:702bf7b2b7d8 867 * :restart_flag -
dkato 0:702bf7b2b7d8 868 * Flag of DMA continous transfer auto restart.
dkato 0:702bf7b2b7d8 869 * Return Value : None.
dkato 0:702bf7b2b7d8 870 ******************************************************************************/
dkato 0:702bf7b2b7d8 871
dkato 0:702bf7b2b7d8 872 void DMA_Start(const int_t channel, const bool_t restart_flag)
dkato 0:702bf7b2b7d8 873 {
dkato 0:702bf7b2b7d8 874 if (false != restart_flag)
dkato 0:702bf7b2b7d8 875 {
dkato 0:702bf7b2b7d8 876 /* clear continous DMA setting */
dkato 0:702bf7b2b7d8 877 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &=
dkato 0:702bf7b2b7d8 878 ~(uint32_t)(CHCFG_SET_RSW | CHCFG_SET_RSEL | CHCFG_SET_REN);
dkato 0:702bf7b2b7d8 879 gb_info_drv.info_ch[channel].next_dma_flag = false;
dkato 0:702bf7b2b7d8 880 }
dkato 0:702bf7b2b7d8 881
dkato 0:702bf7b2b7d8 882 /* clear setup flag */
dkato 0:702bf7b2b7d8 883 gb_info_drv.info_ch[channel].setup_flag = false;
dkato 0:702bf7b2b7d8 884
dkato 0:702bf7b2b7d8 885 /* reset DMA */
dkato 0:702bf7b2b7d8 886 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = CHCTRL_SET_SWRST;
dkato 0:702bf7b2b7d8 887
dkato 0:702bf7b2b7d8 888 /* clear mask of DMA transfer end */
dkato 0:702bf7b2b7d8 889 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &= ~((uint32_t)CHCFG_SET_DEM);
dkato 0:702bf7b2b7d8 890
dkato 0:702bf7b2b7d8 891 GIC_EnableIRQ(gb_info_drv.info_ch[channel].end_irq_num);
dkato 0:702bf7b2b7d8 892
dkato 0:702bf7b2b7d8 893 /* start DMA transfer */
dkato 0:702bf7b2b7d8 894 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = CHCTRL_SET_SETEN;
dkato 0:702bf7b2b7d8 895
dkato 0:702bf7b2b7d8 896 /* set channel status to DMA_CH_TRANSFER */
dkato 0:702bf7b2b7d8 897 gb_info_drv.info_ch[channel].ch_stat = DMA_CH_TRANSFER;
dkato 0:702bf7b2b7d8 898
dkato 0:702bf7b2b7d8 899 return;
dkato 0:702bf7b2b7d8 900 }
dkato 0:702bf7b2b7d8 901
dkato 0:702bf7b2b7d8 902 /******************************************************************************
dkato 0:702bf7b2b7d8 903 End of function DMA_Start
dkato 0:702bf7b2b7d8 904 ******************************************************************************/
dkato 0:702bf7b2b7d8 905
dkato 0:702bf7b2b7d8 906 /******************************************************************************
dkato 0:702bf7b2b7d8 907 * Function Name: DMA_Stop
dkato 0:702bf7b2b7d8 908 * Description : Stop DMA transfer.
dkato 0:702bf7b2b7d8 909 * Arguments : channel -
dkato 0:702bf7b2b7d8 910 * DMA transfer start channel number.
dkato 0:702bf7b2b7d8 911 * *p_remain -
dkato 0:702bf7b2b7d8 912 * Remain data size of DMA transfer.
dkato 0:702bf7b2b7d8 913 * Return Value : None.
dkato 0:702bf7b2b7d8 914 ******************************************************************************/
dkato 0:702bf7b2b7d8 915
dkato 0:702bf7b2b7d8 916 void DMA_Stop(const int_t channel, uint32_t * const p_remain)
dkato 0:702bf7b2b7d8 917 {
dkato 0:702bf7b2b7d8 918 uint32_t stop_wait_cnt;
dkato 0:702bf7b2b7d8 919
dkato 0:702bf7b2b7d8 920 /* disable DMA end interrupt */
dkato 0:702bf7b2b7d8 921 GIC_DisableIRQ(gb_info_drv.info_ch[channel].end_irq_num);
dkato 0:702bf7b2b7d8 922
dkato 0:702bf7b2b7d8 923 /* stop DMA transfer */
dkato 0:702bf7b2b7d8 924 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = CHCTRL_SET_CLREN;
dkato 0:702bf7b2b7d8 925
dkato 0:702bf7b2b7d8 926 /* wait DMA stop */
dkato 0:702bf7b2b7d8 927 stop_wait_cnt = 0;
dkato 0:702bf7b2b7d8 928 while ((0 != (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_TACT)) &&
dkato 0:702bf7b2b7d8 929 (DMA_STOP_WAIT_MAX_CNT > stop_wait_cnt))
dkato 0:702bf7b2b7d8 930 {
dkato 0:702bf7b2b7d8 931 stop_wait_cnt++;
dkato 0:702bf7b2b7d8 932 }
dkato 0:702bf7b2b7d8 933
dkato 0:702bf7b2b7d8 934 if (DMA_STOP_WAIT_MAX_CNT <= stop_wait_cnt)
dkato 0:702bf7b2b7d8 935 {
dkato 0:702bf7b2b7d8 936 /* NON_NOTICE_ASSERT: wait count is abnormal value (usually, a count is set to 0 or 1) */
dkato 0:702bf7b2b7d8 937 }
dkato 0:702bf7b2b7d8 938
dkato 0:702bf7b2b7d8 939 /* get remain data size */
dkato 0:702bf7b2b7d8 940 *p_remain = gb_info_drv.info_ch[channel].p_dma_ch_reg->CRTB_n;
dkato 0:702bf7b2b7d8 941
dkato 0:702bf7b2b7d8 942 /* set mask of DMA transfer end */
dkato 0:702bf7b2b7d8 943 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n |= (uint32_t)CHCFG_SET_DEM;
dkato 0:702bf7b2b7d8 944
dkato 0:702bf7b2b7d8 945 /* clear setting of continuous DMA */
dkato 0:702bf7b2b7d8 946 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &= ~(uint32_t)(CHCFG_SET_RSW | CHCFG_SET_RSEL);
dkato 0:702bf7b2b7d8 947
dkato 0:702bf7b2b7d8 948 /* clear TC, END bit */
dkato 0:702bf7b2b7d8 949 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = (CHCTRL_SET_CLRTC | CHCTRL_SET_CLREND);
dkato 0:702bf7b2b7d8 950
dkato 0:702bf7b2b7d8 951 /* clear flag wich indicates that next DMA transfer set already */
dkato 0:702bf7b2b7d8 952 gb_info_drv.info_ch[channel].next_dma_flag = false;
dkato 0:702bf7b2b7d8 953
dkato 0:702bf7b2b7d8 954 /* interrupt clear, if interrupt occured already */
dkato 0:702bf7b2b7d8 955 GIC_ClearPendingIRQ(gb_info_drv.info_ch[channel].end_irq_num);
dkato 0:702bf7b2b7d8 956
dkato 0:702bf7b2b7d8 957 /* set channel status to DMA_CH_OPEN */
dkato 0:702bf7b2b7d8 958 gb_info_drv.info_ch[channel].ch_stat = DMA_CH_OPEN;
dkato 0:702bf7b2b7d8 959
dkato 0:702bf7b2b7d8 960 return;
dkato 0:702bf7b2b7d8 961 }
dkato 0:702bf7b2b7d8 962
dkato 0:702bf7b2b7d8 963 /******************************************************************************
dkato 0:702bf7b2b7d8 964 End of function DMA_Stop
dkato 0:702bf7b2b7d8 965 ******************************************************************************/
dkato 0:702bf7b2b7d8 966
dkato 0:702bf7b2b7d8 967 /******************************************************************************
dkato 0:702bf7b2b7d8 968 * Function Name: DMA_SetErrCode
dkato 0:702bf7b2b7d8 969 * Description : Set error code to error code pointer.
dkato 0:702bf7b2b7d8 970 * If error code pointer is NULL, nothing is done.
dkato 0:702bf7b2b7d8 971 * Arguments : error_code -
dkato 0:702bf7b2b7d8 972 * Error code.
dkato 0:702bf7b2b7d8 973 * *p_errno -
dkato 0:702bf7b2b7d8 974 * Pointer of set error code.
dkato 0:702bf7b2b7d8 975 * Return Value : None.
dkato 0:702bf7b2b7d8 976 ******************************************************************************/
dkato 0:702bf7b2b7d8 977
dkato 0:702bf7b2b7d8 978 void DMA_SetErrCode(const int_t error_code, int32_t * const p_errno)
dkato 0:702bf7b2b7d8 979 {
dkato 0:702bf7b2b7d8 980 if (NULL != p_errno)
dkato 0:702bf7b2b7d8 981 {
dkato 0:702bf7b2b7d8 982 *p_errno = error_code;
dkato 0:702bf7b2b7d8 983 }
dkato 0:702bf7b2b7d8 984
dkato 0:702bf7b2b7d8 985 return;
dkato 0:702bf7b2b7d8 986 }
dkato 0:702bf7b2b7d8 987
dkato 0:702bf7b2b7d8 988 /******************************************************************************
dkato 0:702bf7b2b7d8 989 End of function DMA_SetErrCode
dkato 0:702bf7b2b7d8 990 ******************************************************************************/
dkato 0:702bf7b2b7d8 991
dkato 0:702bf7b2b7d8 992 /******************************************************************************
dkato 0:702bf7b2b7d8 993 * Function Name: R_DMA_ErrInterruptHandler
dkato 0:702bf7b2b7d8 994 * Description : DMA error interrupt handler.
dkato 0:702bf7b2b7d8 995 * Notify error information to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 996 * Arguments : None.
dkato 0:702bf7b2b7d8 997 * Return Value : None.
dkato 0:702bf7b2b7d8 998 * Note: store error code (EIO) to AIOCB member.
dkato 0:702bf7b2b7d8 999 ******************************************************************************/
dkato 0:702bf7b2b7d8 1000
dkato 0:702bf7b2b7d8 1001 static void R_DMA_ErrInterruptHandler(void)
dkato 0:702bf7b2b7d8 1002 {
dkato 0:702bf7b2b7d8 1003 uint32_t dstat_er_0_7;
dkato 0:702bf7b2b7d8 1004 uint32_t dstat_er_8_15;
dkato 0:702bf7b2b7d8 1005
dkato 0:702bf7b2b7d8 1006 if (NULL != gb_info_drv.p_err_aio)
dkato 0:702bf7b2b7d8 1007 {
dkato 0:702bf7b2b7d8 1008 /* get error channel number */
dkato 0:702bf7b2b7d8 1009 dstat_er_0_7 = gb_info_drv.info_ch[DMA_CH_0].p_dma_common_reg->DSTAT_ER_0_7;
dkato 0:702bf7b2b7d8 1010 dstat_er_8_15 = gb_info_drv.info_ch[HIGH_COMMON_REG_OFFSET].p_dma_common_reg->DSTAT_ER_0_7;
dkato 0:702bf7b2b7d8 1011
dkato 0:702bf7b2b7d8 1012 /* set error infrmation */
dkato 0:702bf7b2b7d8 1013 gb_info_drv.p_err_aio->aio_sigevent.sigev_value.sival_int = (int_t)(dstat_er_0_7 | (dstat_er_8_15 << HIGH_COMMON_REG_OFFSET));
dkato 0:702bf7b2b7d8 1014
dkato 0:702bf7b2b7d8 1015 /* set error code (EIO) */
dkato 0:702bf7b2b7d8 1016 gb_info_drv.p_err_aio->aio_return = EIO;
dkato 0:702bf7b2b7d8 1017
dkato 0:702bf7b2b7d8 1018 /* call back to the module function which called DMA driver */
dkato 0:702bf7b2b7d8 1019 ahf_complete(NULL, gb_info_drv.p_err_aio);
dkato 0:702bf7b2b7d8 1020 }
dkato 0:702bf7b2b7d8 1021 else
dkato 0:702bf7b2b7d8 1022 {
dkato 0:702bf7b2b7d8 1023 ;
dkato 0:702bf7b2b7d8 1024 /* NON_NOTICE_ASSERT:<callback pointer is NULL> */
dkato 0:702bf7b2b7d8 1025 }
dkato 0:702bf7b2b7d8 1026
dkato 0:702bf7b2b7d8 1027 }
dkato 0:702bf7b2b7d8 1028
dkato 0:702bf7b2b7d8 1029 /******************************************************************************
dkato 0:702bf7b2b7d8 1030 End of function R_DMA_ErrInteruuptHandler
dkato 0:702bf7b2b7d8 1031 ******************************************************************************/
dkato 0:702bf7b2b7d8 1032
dkato 0:702bf7b2b7d8 1033 /******************************************************************************
dkato 0:702bf7b2b7d8 1034 * Function Name: R_DMA_End0InterruptHandler
dkato 0:702bf7b2b7d8 1035 * Description : DMA end interrupt handler for channel 0.
dkato 0:702bf7b2b7d8 1036 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1037 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1038 * Arguments : None.
dkato 0:702bf7b2b7d8 1039 * Return Value : None.
dkato 0:702bf7b2b7d8 1040 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1041 * ESUCCESS -
dkato 0:702bf7b2b7d8 1042 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1043 * EIO -
dkato 0:702bf7b2b7d8 1044 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1045 ******************************************************************************/
dkato 0:702bf7b2b7d8 1046
dkato 0:702bf7b2b7d8 1047 static void R_DMA_End0InterruptHandler(void)
dkato 0:702bf7b2b7d8 1048 {
dkato 0:702bf7b2b7d8 1049
dkato 0:702bf7b2b7d8 1050 R_DMA_EndHandlerProcess(DMA_CH_0);
dkato 0:702bf7b2b7d8 1051
dkato 0:702bf7b2b7d8 1052 }
dkato 0:702bf7b2b7d8 1053
dkato 0:702bf7b2b7d8 1054 /******************************************************************************
dkato 0:702bf7b2b7d8 1055 End of function R_DMA_End0InterruptHandler
dkato 0:702bf7b2b7d8 1056 ******************************************************************************/
dkato 0:702bf7b2b7d8 1057
dkato 0:702bf7b2b7d8 1058 /******************************************************************************
dkato 0:702bf7b2b7d8 1059 * Function Name: R_DMA_End1InterruptHandler
dkato 0:702bf7b2b7d8 1060 * Description : DMA end interrupt handler for channel 1.
dkato 0:702bf7b2b7d8 1061 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1062 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1063 * Arguments : None.
dkato 0:702bf7b2b7d8 1064 * Return Value : None.
dkato 0:702bf7b2b7d8 1065 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1066 * ESUCCESS -
dkato 0:702bf7b2b7d8 1067 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1068 * EIO -
dkato 0:702bf7b2b7d8 1069 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1070 ******************************************************************************/
dkato 0:702bf7b2b7d8 1071
dkato 0:702bf7b2b7d8 1072 static void R_DMA_End1InterruptHandler(void)
dkato 0:702bf7b2b7d8 1073 {
dkato 0:702bf7b2b7d8 1074
dkato 0:702bf7b2b7d8 1075 R_DMA_EndHandlerProcess(DMA_CH_1);
dkato 0:702bf7b2b7d8 1076
dkato 0:702bf7b2b7d8 1077 }
dkato 0:702bf7b2b7d8 1078
dkato 0:702bf7b2b7d8 1079 /******************************************************************************
dkato 0:702bf7b2b7d8 1080 End of function R_DMA_End1InterruptHandler
dkato 0:702bf7b2b7d8 1081 ******************************************************************************/
dkato 0:702bf7b2b7d8 1082
dkato 0:702bf7b2b7d8 1083 /******************************************************************************
dkato 0:702bf7b2b7d8 1084 * Function Name: R_DMA_End2InterruptHandler
dkato 0:702bf7b2b7d8 1085 * Description : DMA end interrupt handler for channel 2.
dkato 0:702bf7b2b7d8 1086 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1087 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1088 * Arguments : None.
dkato 0:702bf7b2b7d8 1089 * Return Value : None.
dkato 0:702bf7b2b7d8 1090 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1091 * ESUCCESS -
dkato 0:702bf7b2b7d8 1092 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1093 * EIO -
dkato 0:702bf7b2b7d8 1094 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1095 ******************************************************************************/
dkato 0:702bf7b2b7d8 1096
dkato 0:702bf7b2b7d8 1097 static void R_DMA_End2InterruptHandler(void)
dkato 0:702bf7b2b7d8 1098 {
dkato 0:702bf7b2b7d8 1099
dkato 0:702bf7b2b7d8 1100 R_DMA_EndHandlerProcess(DMA_CH_2);
dkato 0:702bf7b2b7d8 1101
dkato 0:702bf7b2b7d8 1102 }
dkato 0:702bf7b2b7d8 1103
dkato 0:702bf7b2b7d8 1104 /******************************************************************************
dkato 0:702bf7b2b7d8 1105 End of function R_DMA_End2InterruptHandler
dkato 0:702bf7b2b7d8 1106 ******************************************************************************/
dkato 0:702bf7b2b7d8 1107
dkato 0:702bf7b2b7d8 1108 /******************************************************************************
dkato 0:702bf7b2b7d8 1109 * Function Name: R_DMA_End3InterruptHandler
dkato 0:702bf7b2b7d8 1110 * Description : DMA end interrupt handler for channel 3.
dkato 0:702bf7b2b7d8 1111 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1112 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1113 * Arguments : None.
dkato 0:702bf7b2b7d8 1114 * Return Value : None.
dkato 0:702bf7b2b7d8 1115 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1116 * ESUCCESS -
dkato 0:702bf7b2b7d8 1117 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1118 * EIO -
dkato 0:702bf7b2b7d8 1119 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1120 ******************************************************************************/
dkato 0:702bf7b2b7d8 1121
dkato 0:702bf7b2b7d8 1122 static void R_DMA_End3InterruptHandler(void)
dkato 0:702bf7b2b7d8 1123 {
dkato 0:702bf7b2b7d8 1124
dkato 0:702bf7b2b7d8 1125 R_DMA_EndHandlerProcess(DMA_CH_3);
dkato 0:702bf7b2b7d8 1126
dkato 0:702bf7b2b7d8 1127 }
dkato 0:702bf7b2b7d8 1128
dkato 0:702bf7b2b7d8 1129 /******************************************************************************
dkato 0:702bf7b2b7d8 1130 End of function R_DMA_End3InterruptHandler
dkato 0:702bf7b2b7d8 1131 ******************************************************************************/
dkato 0:702bf7b2b7d8 1132
dkato 0:702bf7b2b7d8 1133 /******************************************************************************
dkato 0:702bf7b2b7d8 1134 * Function Name: R_DMA_End4InterruptHandler
dkato 0:702bf7b2b7d8 1135 * Description : DMA end interrupt handler for channel 4.
dkato 0:702bf7b2b7d8 1136 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1137 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1138 * Arguments : None.
dkato 0:702bf7b2b7d8 1139 * Return Value : None.
dkato 0:702bf7b2b7d8 1140 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1141 * ESUCCESS -
dkato 0:702bf7b2b7d8 1142 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1143 * EIO -
dkato 0:702bf7b2b7d8 1144 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1145 ******************************************************************************/
dkato 0:702bf7b2b7d8 1146
dkato 0:702bf7b2b7d8 1147 static void R_DMA_End4InterruptHandler(void)
dkato 0:702bf7b2b7d8 1148 {
dkato 0:702bf7b2b7d8 1149
dkato 0:702bf7b2b7d8 1150 R_DMA_EndHandlerProcess(DMA_CH_4);
dkato 0:702bf7b2b7d8 1151
dkato 0:702bf7b2b7d8 1152 }
dkato 0:702bf7b2b7d8 1153
dkato 0:702bf7b2b7d8 1154 /******************************************************************************
dkato 0:702bf7b2b7d8 1155 End of function R_DMA_End4InterruptHandler
dkato 0:702bf7b2b7d8 1156 ******************************************************************************/
dkato 0:702bf7b2b7d8 1157
dkato 0:702bf7b2b7d8 1158 /******************************************************************************
dkato 0:702bf7b2b7d8 1159 * Function Name: R_DMA_End5InterruptHandler
dkato 0:702bf7b2b7d8 1160 * Description : DMA end interrupt handler for channel 5.
dkato 0:702bf7b2b7d8 1161 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1162 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1163 * Arguments : None.
dkato 0:702bf7b2b7d8 1164 * Return Value : None.
dkato 0:702bf7b2b7d8 1165 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1166 * ESUCCESS -
dkato 0:702bf7b2b7d8 1167 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1168 * EIO -
dkato 0:702bf7b2b7d8 1169 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1170 ******************************************************************************/
dkato 0:702bf7b2b7d8 1171
dkato 0:702bf7b2b7d8 1172 static void R_DMA_End5InterruptHandler(void)
dkato 0:702bf7b2b7d8 1173 {
dkato 0:702bf7b2b7d8 1174
dkato 0:702bf7b2b7d8 1175 R_DMA_EndHandlerProcess(DMA_CH_5);
dkato 0:702bf7b2b7d8 1176
dkato 0:702bf7b2b7d8 1177 }
dkato 0:702bf7b2b7d8 1178
dkato 0:702bf7b2b7d8 1179 /******************************************************************************
dkato 0:702bf7b2b7d8 1180 End of function R_DMA_End5InterruptHandler
dkato 0:702bf7b2b7d8 1181 ******************************************************************************/
dkato 0:702bf7b2b7d8 1182
dkato 0:702bf7b2b7d8 1183 /******************************************************************************
dkato 0:702bf7b2b7d8 1184 * Function Name: R_DMA_End6InterruptHandler
dkato 0:702bf7b2b7d8 1185 * Description : DMA end interrupt handler for channel 6.
dkato 0:702bf7b2b7d8 1186 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1187 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1188 * Arguments : None.
dkato 0:702bf7b2b7d8 1189 * Return Value : None.
dkato 0:702bf7b2b7d8 1190 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1191 * ESUCCESS -
dkato 0:702bf7b2b7d8 1192 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1193 * EIO -
dkato 0:702bf7b2b7d8 1194 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1195 ******************************************************************************/
dkato 0:702bf7b2b7d8 1196
dkato 0:702bf7b2b7d8 1197 static void R_DMA_End6InterruptHandler(void)
dkato 0:702bf7b2b7d8 1198 {
dkato 0:702bf7b2b7d8 1199
dkato 0:702bf7b2b7d8 1200 R_DMA_EndHandlerProcess(DMA_CH_6);
dkato 0:702bf7b2b7d8 1201
dkato 0:702bf7b2b7d8 1202 }
dkato 0:702bf7b2b7d8 1203
dkato 0:702bf7b2b7d8 1204 /******************************************************************************
dkato 0:702bf7b2b7d8 1205 End of function R_DMA_End6InterruptHandler
dkato 0:702bf7b2b7d8 1206 ******************************************************************************/
dkato 0:702bf7b2b7d8 1207
dkato 0:702bf7b2b7d8 1208 /******************************************************************************
dkato 0:702bf7b2b7d8 1209 * Function Name: R_DMA_End7InterruptHandler
dkato 0:702bf7b2b7d8 1210 * Description : DMA end interrupt handler for channel 7.
dkato 0:702bf7b2b7d8 1211 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1212 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1213 * Arguments : None.
dkato 0:702bf7b2b7d8 1214 * Return Value : None.
dkato 0:702bf7b2b7d8 1215 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1216 * ESUCCESS -
dkato 0:702bf7b2b7d8 1217 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1218 * EIO -
dkato 0:702bf7b2b7d8 1219 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1220 ******************************************************************************/
dkato 0:702bf7b2b7d8 1221
dkato 0:702bf7b2b7d8 1222 static void R_DMA_End7InterruptHandler(void)
dkato 0:702bf7b2b7d8 1223 {
dkato 0:702bf7b2b7d8 1224
dkato 0:702bf7b2b7d8 1225 R_DMA_EndHandlerProcess(DMA_CH_7);
dkato 0:702bf7b2b7d8 1226
dkato 0:702bf7b2b7d8 1227 }
dkato 0:702bf7b2b7d8 1228
dkato 0:702bf7b2b7d8 1229 /******************************************************************************
dkato 0:702bf7b2b7d8 1230 End of function R_DMA_End7InterruptHandler
dkato 0:702bf7b2b7d8 1231 ******************************************************************************/
dkato 0:702bf7b2b7d8 1232
dkato 0:702bf7b2b7d8 1233 /******************************************************************************
dkato 0:702bf7b2b7d8 1234 * Function Name: R_DMA_End8InterruptHandler
dkato 0:702bf7b2b7d8 1235 * Description : DMA end interrupt handler for channel 8.
dkato 0:702bf7b2b7d8 1236 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1237 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1238 * Arguments : None.
dkato 0:702bf7b2b7d8 1239 * Return Value : None.
dkato 0:702bf7b2b7d8 1240 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1241 * ESUCCESS -
dkato 0:702bf7b2b7d8 1242 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1243 * EIO -
dkato 0:702bf7b2b7d8 1244 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1245 ******************************************************************************/
dkato 0:702bf7b2b7d8 1246
dkato 0:702bf7b2b7d8 1247 static void R_DMA_End8InterruptHandler(void)
dkato 0:702bf7b2b7d8 1248 {
dkato 0:702bf7b2b7d8 1249
dkato 0:702bf7b2b7d8 1250 R_DMA_EndHandlerProcess(DMA_CH_8);
dkato 0:702bf7b2b7d8 1251
dkato 0:702bf7b2b7d8 1252 }
dkato 0:702bf7b2b7d8 1253
dkato 0:702bf7b2b7d8 1254 /******************************************************************************
dkato 0:702bf7b2b7d8 1255 End of function R_DMA_End8InterruptHandler
dkato 0:702bf7b2b7d8 1256 ******************************************************************************/
dkato 0:702bf7b2b7d8 1257
dkato 0:702bf7b2b7d8 1258 /******************************************************************************
dkato 0:702bf7b2b7d8 1259 * Function Name: R_DMA_End9InterruptHandler
dkato 0:702bf7b2b7d8 1260 * Description : DMA end interrupt handler for channel 9.
dkato 0:702bf7b2b7d8 1261 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1262 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1263 * Arguments : None.
dkato 0:702bf7b2b7d8 1264 * Return Value : None.
dkato 0:702bf7b2b7d8 1265 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1266 * ESUCCESS -
dkato 0:702bf7b2b7d8 1267 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1268 * EIO -
dkato 0:702bf7b2b7d8 1269 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1270 ******************************************************************************/
dkato 0:702bf7b2b7d8 1271
dkato 0:702bf7b2b7d8 1272 static void R_DMA_End9InterruptHandler(void)
dkato 0:702bf7b2b7d8 1273 {
dkato 0:702bf7b2b7d8 1274
dkato 0:702bf7b2b7d8 1275 R_DMA_EndHandlerProcess(DMA_CH_9);
dkato 0:702bf7b2b7d8 1276
dkato 0:702bf7b2b7d8 1277 }
dkato 0:702bf7b2b7d8 1278
dkato 0:702bf7b2b7d8 1279 /******************************************************************************
dkato 0:702bf7b2b7d8 1280 End of function R_DMA_End9InterruptHandler
dkato 0:702bf7b2b7d8 1281 ******************************************************************************/
dkato 0:702bf7b2b7d8 1282
dkato 0:702bf7b2b7d8 1283 /******************************************************************************
dkato 0:702bf7b2b7d8 1284 * Function Name: R_DMA_End10InterruptHandler
dkato 0:702bf7b2b7d8 1285 * Description : DMA end interrupt handler for channel 10.
dkato 0:702bf7b2b7d8 1286 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1287 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1288 * Arguments : None.
dkato 0:702bf7b2b7d8 1289 * Return Value : None.
dkato 0:702bf7b2b7d8 1290 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1291 * ESUCCESS -
dkato 0:702bf7b2b7d8 1292 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1293 * EIO -
dkato 0:702bf7b2b7d8 1294 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1295 ******************************************************************************/
dkato 0:702bf7b2b7d8 1296
dkato 0:702bf7b2b7d8 1297 static void R_DMA_End10InterruptHandler(void)
dkato 0:702bf7b2b7d8 1298 {
dkato 0:702bf7b2b7d8 1299
dkato 0:702bf7b2b7d8 1300 R_DMA_EndHandlerProcess(DMA_CH_10);
dkato 0:702bf7b2b7d8 1301
dkato 0:702bf7b2b7d8 1302 }
dkato 0:702bf7b2b7d8 1303
dkato 0:702bf7b2b7d8 1304 /******************************************************************************
dkato 0:702bf7b2b7d8 1305 End of function R_DMA_End10InterruptHandler
dkato 0:702bf7b2b7d8 1306 ******************************************************************************/
dkato 0:702bf7b2b7d8 1307
dkato 0:702bf7b2b7d8 1308 /******************************************************************************
dkato 0:702bf7b2b7d8 1309 * Function Name: R_DMA_End11InterruptHandler
dkato 0:702bf7b2b7d8 1310 * Description : DMA end interrupt handler for channel 11.
dkato 0:702bf7b2b7d8 1311 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1312 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1313 * Arguments : None.
dkato 0:702bf7b2b7d8 1314 * Return Value : None.
dkato 0:702bf7b2b7d8 1315 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1316 * ESUCCESS -
dkato 0:702bf7b2b7d8 1317 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1318 * EIO -
dkato 0:702bf7b2b7d8 1319 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1320 ******************************************************************************/
dkato 0:702bf7b2b7d8 1321
dkato 0:702bf7b2b7d8 1322 static void R_DMA_End11InterruptHandler(void)
dkato 0:702bf7b2b7d8 1323 {
dkato 0:702bf7b2b7d8 1324
dkato 0:702bf7b2b7d8 1325 R_DMA_EndHandlerProcess(DMA_CH_11);
dkato 0:702bf7b2b7d8 1326
dkato 0:702bf7b2b7d8 1327 }
dkato 0:702bf7b2b7d8 1328
dkato 0:702bf7b2b7d8 1329 /******************************************************************************
dkato 0:702bf7b2b7d8 1330 End of function R_DMA_End11InterruptHandler
dkato 0:702bf7b2b7d8 1331 ******************************************************************************/
dkato 0:702bf7b2b7d8 1332
dkato 0:702bf7b2b7d8 1333 /******************************************************************************
dkato 0:702bf7b2b7d8 1334 * Function Name: R_DMA_End12InterruptHandler
dkato 0:702bf7b2b7d8 1335 * Description : DMA end interrupt handler for channel 12.
dkato 0:702bf7b2b7d8 1336 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1337 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1338 * Arguments : None.
dkato 0:702bf7b2b7d8 1339 * Return Value : None.
dkato 0:702bf7b2b7d8 1340 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1341 * ESUCCESS -
dkato 0:702bf7b2b7d8 1342 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1343 * EIO -
dkato 0:702bf7b2b7d8 1344 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1345 ******************************************************************************/
dkato 0:702bf7b2b7d8 1346
dkato 0:702bf7b2b7d8 1347 static void R_DMA_End12InterruptHandler(void)
dkato 0:702bf7b2b7d8 1348 {
dkato 0:702bf7b2b7d8 1349
dkato 0:702bf7b2b7d8 1350 R_DMA_EndHandlerProcess(DMA_CH_12);
dkato 0:702bf7b2b7d8 1351
dkato 0:702bf7b2b7d8 1352 }
dkato 0:702bf7b2b7d8 1353
dkato 0:702bf7b2b7d8 1354 /******************************************************************************
dkato 0:702bf7b2b7d8 1355 End of function R_DMA_End12InterruptHandler
dkato 0:702bf7b2b7d8 1356 ******************************************************************************/
dkato 0:702bf7b2b7d8 1357
dkato 0:702bf7b2b7d8 1358 /******************************************************************************
dkato 0:702bf7b2b7d8 1359 * Function Name: R_DMA_End13InterruptHandler
dkato 0:702bf7b2b7d8 1360 * Description : DMA end interrupt handler for channel 13.
dkato 0:702bf7b2b7d8 1361 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1362 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1363 * Arguments : None.
dkato 0:702bf7b2b7d8 1364 * Return Value : None.
dkato 0:702bf7b2b7d8 1365 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1366 * ESUCCESS -
dkato 0:702bf7b2b7d8 1367 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1368 * EIO -
dkato 0:702bf7b2b7d8 1369 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1370 ******************************************************************************/
dkato 0:702bf7b2b7d8 1371
dkato 0:702bf7b2b7d8 1372 static void R_DMA_End13InterruptHandler(void)
dkato 0:702bf7b2b7d8 1373 {
dkato 0:702bf7b2b7d8 1374
dkato 0:702bf7b2b7d8 1375 R_DMA_EndHandlerProcess(DMA_CH_13);
dkato 0:702bf7b2b7d8 1376
dkato 0:702bf7b2b7d8 1377 }
dkato 0:702bf7b2b7d8 1378
dkato 0:702bf7b2b7d8 1379 /******************************************************************************
dkato 0:702bf7b2b7d8 1380 End of function R_DMA_End13InterruptHandler
dkato 0:702bf7b2b7d8 1381 ******************************************************************************/
dkato 0:702bf7b2b7d8 1382
dkato 0:702bf7b2b7d8 1383 /******************************************************************************
dkato 0:702bf7b2b7d8 1384 * Function Name: R_DMA_End14InterruptHandler
dkato 0:702bf7b2b7d8 1385 * Description : DMA end interrupt handler for channel 14.
dkato 0:702bf7b2b7d8 1386 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1387 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1388 * Arguments : None.
dkato 0:702bf7b2b7d8 1389 * Return Value : None.
dkato 0:702bf7b2b7d8 1390 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1391 * ESUCCESS -
dkato 0:702bf7b2b7d8 1392 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1393 * EIO -
dkato 0:702bf7b2b7d8 1394 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1395 ******************************************************************************/
dkato 0:702bf7b2b7d8 1396
dkato 0:702bf7b2b7d8 1397 static void R_DMA_End14InterruptHandler(void)
dkato 0:702bf7b2b7d8 1398 {
dkato 0:702bf7b2b7d8 1399
dkato 0:702bf7b2b7d8 1400 R_DMA_EndHandlerProcess(DMA_CH_14);
dkato 0:702bf7b2b7d8 1401
dkato 0:702bf7b2b7d8 1402 }
dkato 0:702bf7b2b7d8 1403
dkato 0:702bf7b2b7d8 1404 /******************************************************************************
dkato 0:702bf7b2b7d8 1405 End of function R_DMA_End14InterruptHandler
dkato 0:702bf7b2b7d8 1406 ******************************************************************************/
dkato 0:702bf7b2b7d8 1407
dkato 0:702bf7b2b7d8 1408 /******************************************************************************
dkato 0:702bf7b2b7d8 1409 * Function Name: R_DMA_End15InterruptHandler
dkato 0:702bf7b2b7d8 1410 * Description : DMA end interrupt handler for channel 15.
dkato 0:702bf7b2b7d8 1411 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1412 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1413 * Arguments : None.
dkato 0:702bf7b2b7d8 1414 * Return Value : None.
dkato 0:702bf7b2b7d8 1415 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1416 * ESUCCESS -
dkato 0:702bf7b2b7d8 1417 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1418 * EIO -
dkato 0:702bf7b2b7d8 1419 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1420 ******************************************************************************/
dkato 0:702bf7b2b7d8 1421
dkato 0:702bf7b2b7d8 1422 static void R_DMA_End15InterruptHandler(void)
dkato 0:702bf7b2b7d8 1423 {
dkato 0:702bf7b2b7d8 1424
dkato 0:702bf7b2b7d8 1425 R_DMA_EndHandlerProcess(DMA_CH_15);
dkato 0:702bf7b2b7d8 1426
dkato 0:702bf7b2b7d8 1427 }
dkato 0:702bf7b2b7d8 1428
dkato 0:702bf7b2b7d8 1429 /******************************************************************************
dkato 0:702bf7b2b7d8 1430 End of function R_DMA_End15InterruptHandler
dkato 0:702bf7b2b7d8 1431 ******************************************************************************/
dkato 0:702bf7b2b7d8 1432
dkato 0:702bf7b2b7d8 1433 /******************************************************************************
dkato 0:702bf7b2b7d8 1434 * Function Name: R_DMA_EndHandlerProcess
dkato 0:702bf7b2b7d8 1435 * Description : DMA end interrupt handler process carry out.
dkato 0:702bf7b2b7d8 1436 * It's processed to DMA complete and notify DMA transfer finished
dkato 0:702bf7b2b7d8 1437 * to the module function which called DMA driver.
dkato 0:702bf7b2b7d8 1438 * Arguments : channel -
dkato 0:702bf7b2b7d8 1439 * Open channel number.
dkato 0:702bf7b2b7d8 1440 * Return Value : None.
dkato 0:702bf7b2b7d8 1441 * Note: store error code (EIO) to AIOCB.
dkato 0:702bf7b2b7d8 1442 * ESUCCESS -
dkato 0:702bf7b2b7d8 1443 * DMA transfer completed.
dkato 0:702bf7b2b7d8 1444 * EIO -
dkato 0:702bf7b2b7d8 1445 * DMA transfer don't stopped.
dkato 0:702bf7b2b7d8 1446 ******************************************************************************/
dkato 0:702bf7b2b7d8 1447
dkato 0:702bf7b2b7d8 1448 __inline static void R_DMA_EndHandlerProcess(const int_t channel)
dkato 0:702bf7b2b7d8 1449 {
dkato 0:702bf7b2b7d8 1450 bool_t store_next_dma_flag;
dkato 5:1390bfcb667c 1451 int_t was_masked;
dkato 0:702bf7b2b7d8 1452
dkato 0:702bf7b2b7d8 1453 if (NULL != gb_info_drv.info_ch[channel].p_end_aio)
dkato 0:702bf7b2b7d8 1454 {
dkato 5:1390bfcb667c 1455 /* disable all irq */
dkato 5:1390bfcb667c 1456 #if defined (__ICCARM__)
dkato 5:1390bfcb667c 1457 was_masked = __disable_irq_iar();
dkato 5:1390bfcb667c 1458 #else
dkato 5:1390bfcb667c 1459 was_masked = __disable_irq();
dkato 5:1390bfcb667c 1460 #endif
dkato 5:1390bfcb667c 1461
dkato 0:702bf7b2b7d8 1462 /* store next_dma_flag */
dkato 0:702bf7b2b7d8 1463 store_next_dma_flag = gb_info_drv.info_ch[channel].next_dma_flag;
dkato 0:702bf7b2b7d8 1464
dkato 0:702bf7b2b7d8 1465 /* clear flag wich indicates that next DMA transfer set already */
dkato 0:702bf7b2b7d8 1466 gb_info_drv.info_ch[channel].next_dma_flag = false;
dkato 0:702bf7b2b7d8 1467
dkato 0:702bf7b2b7d8 1468 if (false == store_next_dma_flag)
dkato 0:702bf7b2b7d8 1469 {
dkato 0:702bf7b2b7d8 1470 /* DMA transfer complete */
dkato 0:702bf7b2b7d8 1471 /* mask DMA end interrupt */
dkato 0:702bf7b2b7d8 1472 GIC_DisableIRQ(gb_info_drv.info_ch[channel].end_irq_num);
dkato 0:702bf7b2b7d8 1473
dkato 0:702bf7b2b7d8 1474 /* set channel status to DMA_CH_OPEN */
dkato 0:702bf7b2b7d8 1475 gb_info_drv.info_ch[channel].ch_stat = DMA_CH_OPEN;
dkato 0:702bf7b2b7d8 1476
dkato 0:702bf7b2b7d8 1477 /* set mask of DMA transfer end */
dkato 0:702bf7b2b7d8 1478 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n |= (uint32_t)CHCFG_SET_DEM;
dkato 0:702bf7b2b7d8 1479
dkato 0:702bf7b2b7d8 1480 /* clear setting of continuous DMA */
dkato 0:702bf7b2b7d8 1481 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &= ~(uint32_t)(CHCFG_SET_RSW | CHCFG_SET_RSEL);
dkato 0:702bf7b2b7d8 1482
dkato 0:702bf7b2b7d8 1483 /* check EN bit is clear */
dkato 0:702bf7b2b7d8 1484 if (0U == (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_EN))
dkato 0:702bf7b2b7d8 1485 {
dkato 0:702bf7b2b7d8 1486 /* set error code (ESUCCESS) */
dkato 0:702bf7b2b7d8 1487 gb_info_drv.info_ch[channel].p_end_aio->aio_return = ESUCCESS;
dkato 0:702bf7b2b7d8 1488 }
dkato 0:702bf7b2b7d8 1489 else
dkato 0:702bf7b2b7d8 1490 {
dkato 0:702bf7b2b7d8 1491 /* set error code (EIO) */
dkato 0:702bf7b2b7d8 1492 gb_info_drv.info_ch[channel].p_end_aio->aio_return = EIO;
dkato 0:702bf7b2b7d8 1493 }
dkato 0:702bf7b2b7d8 1494 }
dkato 0:702bf7b2b7d8 1495 else
dkato 0:702bf7b2b7d8 1496 {
dkato 0:702bf7b2b7d8 1497 /* set next DMA already */
dkato 0:702bf7b2b7d8 1498 /* set error code (ESUCCESS) */
dkato 0:702bf7b2b7d8 1499 gb_info_drv.info_ch[channel].p_end_aio->aio_return = ESUCCESS;
dkato 0:702bf7b2b7d8 1500 }
dkato 0:702bf7b2b7d8 1501
dkato 0:702bf7b2b7d8 1502 /* clear TC, END bit */
dkato 0:702bf7b2b7d8 1503 gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = (CHCTRL_SET_CLRTC | CHCTRL_SET_CLREND);
dkato 0:702bf7b2b7d8 1504
dkato 5:1390bfcb667c 1505 if (0 == was_masked)
dkato 5:1390bfcb667c 1506 {
dkato 5:1390bfcb667c 1507 __enable_irq();
dkato 5:1390bfcb667c 1508 }
dkato 5:1390bfcb667c 1509
dkato 0:702bf7b2b7d8 1510 /* call back to the module function which called DMA driver */
dkato 0:702bf7b2b7d8 1511 ahf_complete(NULL, gb_info_drv.info_ch[channel].p_end_aio);
dkato 0:702bf7b2b7d8 1512 }
dkato 0:702bf7b2b7d8 1513 else
dkato 0:702bf7b2b7d8 1514 {
dkato 0:702bf7b2b7d8 1515 ;
dkato 0:702bf7b2b7d8 1516 /* NON_NOTICE_ASSERT:<callback pointer is NULL> */
dkato 0:702bf7b2b7d8 1517 }
dkato 5:1390bfcb667c 1518
dkato 5:1390bfcb667c 1519 return;
dkato 0:702bf7b2b7d8 1520 }
dkato 0:702bf7b2b7d8 1521
dkato 0:702bf7b2b7d8 1522 /******************************************************************************
dkato 0:702bf7b2b7d8 1523 End of function R_DMA_EndHandlerProcess
dkato 0:702bf7b2b7d8 1524 ******************************************************************************/
dkato 0:702bf7b2b7d8 1525