mbed library sources. Supersedes mbed-src.
Fork of mbed by
targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)
- Committer:
- <>
- Date:
- Fri Sep 02 15:07:44 2016 +0100
- Revision:
- 144:ef7eb2e8f9f7
- Parent:
- 0:9b334a45a8ff
This updates the lib to the mbed lib v125
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. |
<> | 144:ef7eb2e8f9f7 | 3 | * |
<> | 144:ef7eb2e8f9f7 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
<> | 144:ef7eb2e8f9f7 | 5 | * copy of this software and associated documentation files (the "Software"), |
<> | 144:ef7eb2e8f9f7 | 6 | * to deal in the Software without restriction, including without limitation |
<> | 144:ef7eb2e8f9f7 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
<> | 144:ef7eb2e8f9f7 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
<> | 144:ef7eb2e8f9f7 | 9 | * Software is furnished to do so, subject to the following conditions: |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * The above copyright notice and this permission notice shall be included |
<> | 144:ef7eb2e8f9f7 | 12 | * in all copies or substantial portions of the Software. |
<> | 144:ef7eb2e8f9f7 | 13 | * |
<> | 144:ef7eb2e8f9f7 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
<> | 144:ef7eb2e8f9f7 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
<> | 144:ef7eb2e8f9f7 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
<> | 144:ef7eb2e8f9f7 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
<> | 144:ef7eb2e8f9f7 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
<> | 144:ef7eb2e8f9f7 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
<> | 144:ef7eb2e8f9f7 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
<> | 144:ef7eb2e8f9f7 | 21 | * |
<> | 144:ef7eb2e8f9f7 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
<> | 144:ef7eb2e8f9f7 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
<> | 144:ef7eb2e8f9f7 | 24 | * Products, Inc. Branding Policy. |
<> | 144:ef7eb2e8f9f7 | 25 | * |
<> | 144:ef7eb2e8f9f7 | 26 | * The mere transfer of this software does not imply any licenses |
<> | 144:ef7eb2e8f9f7 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
<> | 144:ef7eb2e8f9f7 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
<> | 144:ef7eb2e8f9f7 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
<> | 144:ef7eb2e8f9f7 | 30 | * ownership rights. |
<> | 144:ef7eb2e8f9f7 | 31 | ******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 32 | */ |
<> | 144:ef7eb2e8f9f7 | 33 | |
<> | 144:ef7eb2e8f9f7 | 34 | #include "max32600.h" |
<> | 144:ef7eb2e8f9f7 | 35 | #include "clkman_regs.h" |
<> | 144:ef7eb2e8f9f7 | 36 | #include "pwrman_regs.h" |
<> | 144:ef7eb2e8f9f7 | 37 | #include "ioman_regs.h" |
<> | 144:ef7eb2e8f9f7 | 38 | #include "trim_regs.h" |
<> | 144:ef7eb2e8f9f7 | 39 | #include "flc_regs.h" |
<> | 144:ef7eb2e8f9f7 | 40 | #include "pwrseq_regs.h" |
<> | 144:ef7eb2e8f9f7 | 41 | #include "dac_regs.h" |
<> | 144:ef7eb2e8f9f7 | 42 | #include "icc_regs.h" |
<> | 144:ef7eb2e8f9f7 | 43 | #include "adc_regs.h" |
<> | 144:ef7eb2e8f9f7 | 44 | |
<> | 144:ef7eb2e8f9f7 | 45 | /* Application developer should override where necessary with different external HFX source */ |
<> | 144:ef7eb2e8f9f7 | 46 | #ifndef __SYSTEM_HFX |
<> | 144:ef7eb2e8f9f7 | 47 | #define __SYSTEM_HFX 8000000 |
<> | 144:ef7eb2e8f9f7 | 48 | #endif |
<> | 144:ef7eb2e8f9f7 | 49 | |
<> | 144:ef7eb2e8f9f7 | 50 | uint32_t SystemCoreClock = 24000000; |
<> | 144:ef7eb2e8f9f7 | 51 | |
<> | 144:ef7eb2e8f9f7 | 52 | void SystemCoreClockUpdate(void) |
<> | 144:ef7eb2e8f9f7 | 53 | { |
<> | 144:ef7eb2e8f9f7 | 54 | switch ((MXC_CLKMAN->clk_ctrl & MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) >> MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS) { |
<> | 144:ef7eb2e8f9f7 | 55 | case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8: |
<> | 144:ef7eb2e8f9f7 | 56 | SystemCoreClock = 3000000; |
<> | 144:ef7eb2e8f9f7 | 57 | break; |
<> | 144:ef7eb2e8f9f7 | 58 | case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO: |
<> | 144:ef7eb2e8f9f7 | 59 | case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2: |
<> | 144:ef7eb2e8f9f7 | 60 | SystemCoreClock = 24000000; |
<> | 144:ef7eb2e8f9f7 | 61 | break; |
<> | 144:ef7eb2e8f9f7 | 62 | case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX: |
<> | 144:ef7eb2e8f9f7 | 63 | SystemCoreClock = __SYSTEM_HFX; |
<> | 144:ef7eb2e8f9f7 | 64 | break; |
<> | 144:ef7eb2e8f9f7 | 65 | } |
<> | 144:ef7eb2e8f9f7 | 66 | |
<> | 144:ef7eb2e8f9f7 | 67 | uint32_t shift = MXC_CLKMAN->clk_ctrl_0_system; |
<> | 144:ef7eb2e8f9f7 | 68 | if (shift) { |
<> | 144:ef7eb2e8f9f7 | 69 | SystemCoreClock = SystemCoreClock >> (shift - 1); |
<> | 144:ef7eb2e8f9f7 | 70 | } |
<> | 144:ef7eb2e8f9f7 | 71 | } |
<> | 144:ef7eb2e8f9f7 | 72 | |
<> | 144:ef7eb2e8f9f7 | 73 | /* power seq registers */ |
<> | 144:ef7eb2e8f9f7 | 74 | static void set_pwr_regs(void) |
<> | 144:ef7eb2e8f9f7 | 75 | { |
<> | 144:ef7eb2e8f9f7 | 76 | uint32_t dac2trim = MXC_DAC2->reg & 0xff00ffff; |
<> | 144:ef7eb2e8f9f7 | 77 | uint32_t dac3trim = MXC_DAC3->reg & 0xff00ffff; |
<> | 144:ef7eb2e8f9f7 | 78 | dac2trim = dac2trim + MXC_TRIM->trim_reg_36; |
<> | 144:ef7eb2e8f9f7 | 79 | dac3trim = dac3trim + MXC_TRIM->trim_reg_37; |
<> | 144:ef7eb2e8f9f7 | 80 | if ((MXC_TRIM->trim_reg_13 != 0) && (MXC_TRIM->trim_reg_13 != 0xFFFFFFFF)) { |
<> | 144:ef7eb2e8f9f7 | 81 | MXC_PWRSEQ->reg5 = MXC_TRIM->trim_reg_13; |
<> | 144:ef7eb2e8f9f7 | 82 | } |
<> | 144:ef7eb2e8f9f7 | 83 | if ((MXC_TRIM->trim_reg_14 != 0) && (MXC_TRIM->trim_reg_14 != 0xFFFFFFFF)) { |
<> | 144:ef7eb2e8f9f7 | 84 | MXC_PWRSEQ->reg6 = MXC_TRIM->trim_reg_14; |
<> | 144:ef7eb2e8f9f7 | 85 | } |
<> | 144:ef7eb2e8f9f7 | 86 | MXC_DAC0->trm = MXC_TRIM->trim_reg_34; |
<> | 144:ef7eb2e8f9f7 | 87 | MXC_DAC1->trm = MXC_TRIM->trim_reg_35; |
<> | 144:ef7eb2e8f9f7 | 88 | MXC_DAC2->reg = dac2trim; |
<> | 144:ef7eb2e8f9f7 | 89 | MXC_DAC3->reg = dac3trim; |
<> | 144:ef7eb2e8f9f7 | 90 | } |
<> | 144:ef7eb2e8f9f7 | 91 | |
<> | 144:ef7eb2e8f9f7 | 92 | void ICC_Enable(void) |
<> | 144:ef7eb2e8f9f7 | 93 | { |
<> | 144:ef7eb2e8f9f7 | 94 | /* clock gater must be 'on' not 'dynamic' for cache control */ |
<> | 144:ef7eb2e8f9f7 | 95 | uint32_t temp = MXC_CLKMAN->clk_gate_ctrl0; |
<> | 144:ef7eb2e8f9f7 | 96 | temp &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER; |
<> | 144:ef7eb2e8f9f7 | 97 | temp |= (MXC_E_CLKMAN_CLK_GATE_ON << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS); |
<> | 144:ef7eb2e8f9f7 | 98 | MXC_CLKMAN->clk_gate_ctrl0 = temp; |
<> | 144:ef7eb2e8f9f7 | 99 | |
<> | 144:ef7eb2e8f9f7 | 100 | |
<> | 144:ef7eb2e8f9f7 | 101 | /* invalidate, wait, enable */ |
<> | 144:ef7eb2e8f9f7 | 102 | MXC_ICC->invdt_all = 0xFFFF; |
<> | 144:ef7eb2e8f9f7 | 103 | while(!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY)); |
<> | 144:ef7eb2e8f9f7 | 104 | MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE; |
<> | 144:ef7eb2e8f9f7 | 105 | |
<> | 144:ef7eb2e8f9f7 | 106 | /* must invalidate a second time for proper use */ |
<> | 144:ef7eb2e8f9f7 | 107 | MXC_ICC->invdt_all = 1; |
<> | 144:ef7eb2e8f9f7 | 108 | |
<> | 144:ef7eb2e8f9f7 | 109 | /* clock gater 'dynamic' safe again */ |
<> | 144:ef7eb2e8f9f7 | 110 | temp = MXC_CLKMAN->clk_gate_ctrl0; |
<> | 144:ef7eb2e8f9f7 | 111 | temp &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER; |
<> | 144:ef7eb2e8f9f7 | 112 | temp |= (MXC_E_CLKMAN_CLK_GATE_DYNAMIC << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS); |
<> | 144:ef7eb2e8f9f7 | 113 | MXC_CLKMAN->clk_gate_ctrl0 = temp; |
<> | 144:ef7eb2e8f9f7 | 114 | } |
<> | 144:ef7eb2e8f9f7 | 115 | |
<> | 144:ef7eb2e8f9f7 | 116 | void Trim_RO(void) |
<> | 144:ef7eb2e8f9f7 | 117 | { |
<> | 144:ef7eb2e8f9f7 | 118 | uint32_t reg0; |
<> | 144:ef7eb2e8f9f7 | 119 | uint32_t trim; |
<> | 144:ef7eb2e8f9f7 | 120 | |
<> | 144:ef7eb2e8f9f7 | 121 | // Save the RTCEN_RUN state and set it |
<> | 144:ef7eb2e8f9f7 | 122 | reg0 = MXC_PWRSEQ->reg0; |
<> | 144:ef7eb2e8f9f7 | 123 | MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN; |
<> | 144:ef7eb2e8f9f7 | 124 | |
<> | 144:ef7eb2e8f9f7 | 125 | /* needed if parts are untrimmed */ |
<> | 144:ef7eb2e8f9f7 | 126 | if ((MXC_TRIM->trim_reg_13 == 0) || (MXC_TRIM->trim_reg_13 == 0xFFFFFFFF)) { |
<> | 144:ef7eb2e8f9f7 | 127 | MXC_PWRSEQ->reg5 = (MXC_PWRSEQ->reg5 & ~MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF) | (16 << MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS); |
<> | 144:ef7eb2e8f9f7 | 128 | } |
<> | 144:ef7eb2e8f9f7 | 129 | trim = (MXC_PWRSEQ->reg5 & MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF) >> (MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS - 2); |
<> | 144:ef7eb2e8f9f7 | 130 | MXC_ADCCFG->ro_cal1 = (MXC_ADCCFG->ro_cal1 & ~MXC_F_ADC_RO_CAL1_TRM_INIT) | |
<> | 144:ef7eb2e8f9f7 | 131 | ((trim << MXC_F_ADC_RO_CAL1_TRM_INIT_POS) & MXC_F_ADC_RO_CAL1_TRM_INIT); |
<> | 144:ef7eb2e8f9f7 | 132 | MXC_ADCCFG->ro_cal0 = (MXC_ADCCFG->ro_cal0 & ~MXC_F_ADC_RO_CAL0_TRM_MU) | (0x04 << MXC_F_ADC_RO_CAL0_TRM_MU_POS); |
<> | 144:ef7eb2e8f9f7 | 133 | MXC_SETBIT(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS); |
<> | 144:ef7eb2e8f9f7 | 134 | MXC_SETBIT(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS); |
<> | 144:ef7eb2e8f9f7 | 135 | MXC_SETBIT(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS); |
<> | 144:ef7eb2e8f9f7 | 136 | |
<> | 144:ef7eb2e8f9f7 | 137 | SysTick->LOAD = 1635; /* about 50ms, based on a 32KHz systick clock */ |
<> | 144:ef7eb2e8f9f7 | 138 | SysTick->VAL = 0; |
<> | 144:ef7eb2e8f9f7 | 139 | SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; /* Enable SysTick Timer */ |
<> | 144:ef7eb2e8f9f7 | 140 | while(SysTick->VAL == 0); |
<> | 144:ef7eb2e8f9f7 | 141 | while(!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)); |
<> | 144:ef7eb2e8f9f7 | 142 | SysTick->CTRL = 0; |
<> | 144:ef7eb2e8f9f7 | 143 | |
<> | 144:ef7eb2e8f9f7 | 144 | trim = (MXC_ADCCFG->ro_cal0 & MXC_F_ADC_RO_CAL0_RO_TRM) >> (MXC_F_ADC_RO_CAL0_RO_TRM_POS + 2); |
<> | 144:ef7eb2e8f9f7 | 145 | MXC_CLRBIT(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS); |
<> | 144:ef7eb2e8f9f7 | 146 | MXC_PWRSEQ->reg5 = (MXC_PWRSEQ->reg5 & ~MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF) | |
<> | 144:ef7eb2e8f9f7 | 147 | ((trim << MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS) & MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF); |
<> | 144:ef7eb2e8f9f7 | 148 | |
<> | 144:ef7eb2e8f9f7 | 149 | // Restore the RTCEN_RUN state |
<> | 144:ef7eb2e8f9f7 | 150 | if (!(reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN)) { |
<> | 144:ef7eb2e8f9f7 | 151 | MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN; |
<> | 144:ef7eb2e8f9f7 | 152 | } |
<> | 144:ef7eb2e8f9f7 | 153 | } |
<> | 144:ef7eb2e8f9f7 | 154 | |
<> | 144:ef7eb2e8f9f7 | 155 | // This function to be implemented by the hal |
<> | 144:ef7eb2e8f9f7 | 156 | extern void low_level_init(void); |
<> | 144:ef7eb2e8f9f7 | 157 | |
<> | 144:ef7eb2e8f9f7 | 158 | void SystemInit(void) |
<> | 144:ef7eb2e8f9f7 | 159 | { |
<> | 144:ef7eb2e8f9f7 | 160 | set_pwr_regs(); |
<> | 144:ef7eb2e8f9f7 | 161 | |
<> | 144:ef7eb2e8f9f7 | 162 | // Enable instruction cache |
<> | 144:ef7eb2e8f9f7 | 163 | ICC_Enable(); |
<> | 144:ef7eb2e8f9f7 | 164 | |
<> | 144:ef7eb2e8f9f7 | 165 | low_level_init(); |
<> | 144:ef7eb2e8f9f7 | 166 | |
<> | 144:ef7eb2e8f9f7 | 167 | // Clear IO Active |
<> | 144:ef7eb2e8f9f7 | 168 | MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE | |
<> | 144:ef7eb2e8f9f7 | 169 | MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE); |
<> | 144:ef7eb2e8f9f7 | 170 | |
<> | 144:ef7eb2e8f9f7 | 171 | // Set WUD Clear |
<> | 144:ef7eb2e8f9f7 | 172 | MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE | |
<> | 144:ef7eb2e8f9f7 | 173 | MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE | |
<> | 144:ef7eb2e8f9f7 | 174 | MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR); |
<> | 144:ef7eb2e8f9f7 | 175 | |
<> | 144:ef7eb2e8f9f7 | 176 | // Set IO Active |
<> | 144:ef7eb2e8f9f7 | 177 | MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE | |
<> | 144:ef7eb2e8f9f7 | 178 | MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE | |
<> | 144:ef7eb2e8f9f7 | 179 | MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE | |
<> | 144:ef7eb2e8f9f7 | 180 | MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED); |
<> | 144:ef7eb2e8f9f7 | 181 | |
<> | 144:ef7eb2e8f9f7 | 182 | // Clear the first boot flag. Use low_level_init() if special handling is required. |
<> | 144:ef7eb2e8f9f7 | 183 | MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT; |
<> | 144:ef7eb2e8f9f7 | 184 | |
<> | 144:ef7eb2e8f9f7 | 185 | // Enable the regulator |
<> | 144:ef7eb2e8f9f7 | 186 | MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN; |
<> | 144:ef7eb2e8f9f7 | 187 | |
<> | 144:ef7eb2e8f9f7 | 188 | // Mask all wakeups |
<> | 144:ef7eb2e8f9f7 | 189 | MXC_PWRSEQ->msk_flags = 0xFFFFFFFF; |
<> | 144:ef7eb2e8f9f7 | 190 | |
<> | 144:ef7eb2e8f9f7 | 191 | // Set systick to the RTC input 32.768kHz clock, not system clock; this is needed to keep JTAG alive during sleep |
<> | 144:ef7eb2e8f9f7 | 192 | MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE; |
<> | 144:ef7eb2e8f9f7 | 193 | |
<> | 144:ef7eb2e8f9f7 | 194 | SystemCoreClockUpdate(); |
<> | 144:ef7eb2e8f9f7 | 195 | |
<> | 144:ef7eb2e8f9f7 | 196 | Trim_RO(); |
<> | 144:ef7eb2e8f9f7 | 197 | } |