mbed library sources. Supersedes mbed-src.
Fork of mbed by
targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.c@0:9b334a45a8ff, 2015-10-01 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Oct 01 15:25:22 2015 +0300
- Revision:
- 0:9b334a45a8ff
- Child:
- 144:ef7eb2e8f9f7
Initial commit on mbed-dev
Replaces mbed-src (now inactive)
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 0:9b334a45a8ff | 1 | /******************************************************************************* |
bogdanm | 0:9b334a45a8ff | 2 | * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. |
bogdanm | 0:9b334a45a8ff | 3 | * |
bogdanm | 0:9b334a45a8ff | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
bogdanm | 0:9b334a45a8ff | 5 | * copy of this software and associated documentation files (the "Software"), |
bogdanm | 0:9b334a45a8ff | 6 | * to deal in the Software without restriction, including without limitation |
bogdanm | 0:9b334a45a8ff | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
bogdanm | 0:9b334a45a8ff | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
bogdanm | 0:9b334a45a8ff | 9 | * Software is furnished to do so, subject to the following conditions: |
bogdanm | 0:9b334a45a8ff | 10 | * |
bogdanm | 0:9b334a45a8ff | 11 | * The above copyright notice and this permission notice shall be included |
bogdanm | 0:9b334a45a8ff | 12 | * in all copies or substantial portions of the Software. |
bogdanm | 0:9b334a45a8ff | 13 | * |
bogdanm | 0:9b334a45a8ff | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
bogdanm | 0:9b334a45a8ff | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
bogdanm | 0:9b334a45a8ff | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
bogdanm | 0:9b334a45a8ff | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
bogdanm | 0:9b334a45a8ff | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
bogdanm | 0:9b334a45a8ff | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
bogdanm | 0:9b334a45a8ff | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
bogdanm | 0:9b334a45a8ff | 21 | * |
bogdanm | 0:9b334a45a8ff | 22 | * Except as contained in this notice, the name of Maxim Integrated |
bogdanm | 0:9b334a45a8ff | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
bogdanm | 0:9b334a45a8ff | 24 | * Products, Inc. Branding Policy. |
bogdanm | 0:9b334a45a8ff | 25 | * |
bogdanm | 0:9b334a45a8ff | 26 | * The mere transfer of this software does not imply any licenses |
bogdanm | 0:9b334a45a8ff | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
bogdanm | 0:9b334a45a8ff | 28 | * trademarks, maskwork rights, or any other form of intellectual |
bogdanm | 0:9b334a45a8ff | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
bogdanm | 0:9b334a45a8ff | 30 | * ownership rights. |
bogdanm | 0:9b334a45a8ff | 31 | ******************************************************************************* |
bogdanm | 0:9b334a45a8ff | 32 | */ |
bogdanm | 0:9b334a45a8ff | 33 | |
bogdanm | 0:9b334a45a8ff | 34 | #include "max32600.h" |
bogdanm | 0:9b334a45a8ff | 35 | #include "clkman_regs.h" |
bogdanm | 0:9b334a45a8ff | 36 | #include "pwrman_regs.h" |
bogdanm | 0:9b334a45a8ff | 37 | #include "ioman_regs.h" |
bogdanm | 0:9b334a45a8ff | 38 | #include "trim_regs.h" |
bogdanm | 0:9b334a45a8ff | 39 | #include "flc_regs.h" |
bogdanm | 0:9b334a45a8ff | 40 | #include "pwrseq_regs.h" |
bogdanm | 0:9b334a45a8ff | 41 | #include "dac_regs.h" |
bogdanm | 0:9b334a45a8ff | 42 | #include "icc_regs.h" |
bogdanm | 0:9b334a45a8ff | 43 | #include "adc_regs.h" |
bogdanm | 0:9b334a45a8ff | 44 | |
bogdanm | 0:9b334a45a8ff | 45 | /* Application developer should override where necessary with different external HFX source */ |
bogdanm | 0:9b334a45a8ff | 46 | #ifndef __SYSTEM_HFX |
bogdanm | 0:9b334a45a8ff | 47 | #define __SYSTEM_HFX 8000000 |
bogdanm | 0:9b334a45a8ff | 48 | #endif |
bogdanm | 0:9b334a45a8ff | 49 | |
bogdanm | 0:9b334a45a8ff | 50 | uint32_t SystemCoreClock = 24000000; |
bogdanm | 0:9b334a45a8ff | 51 | |
bogdanm | 0:9b334a45a8ff | 52 | void SystemCoreClockUpdate(void) |
bogdanm | 0:9b334a45a8ff | 53 | { |
bogdanm | 0:9b334a45a8ff | 54 | switch ((MXC_CLKMAN->clk_ctrl & MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) >> MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS) { |
bogdanm | 0:9b334a45a8ff | 55 | case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8: |
bogdanm | 0:9b334a45a8ff | 56 | SystemCoreClock = 3000000; |
bogdanm | 0:9b334a45a8ff | 57 | break; |
bogdanm | 0:9b334a45a8ff | 58 | case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO: |
bogdanm | 0:9b334a45a8ff | 59 | case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2: |
bogdanm | 0:9b334a45a8ff | 60 | SystemCoreClock = 24000000; |
bogdanm | 0:9b334a45a8ff | 61 | break; |
bogdanm | 0:9b334a45a8ff | 62 | case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX: |
bogdanm | 0:9b334a45a8ff | 63 | SystemCoreClock = __SYSTEM_HFX; |
bogdanm | 0:9b334a45a8ff | 64 | break; |
bogdanm | 0:9b334a45a8ff | 65 | } |
bogdanm | 0:9b334a45a8ff | 66 | |
bogdanm | 0:9b334a45a8ff | 67 | uint32_t shift = MXC_CLKMAN->clk_ctrl_0_system; |
bogdanm | 0:9b334a45a8ff | 68 | if (shift) { |
bogdanm | 0:9b334a45a8ff | 69 | SystemCoreClock = SystemCoreClock >> (shift - 1); |
bogdanm | 0:9b334a45a8ff | 70 | } |
bogdanm | 0:9b334a45a8ff | 71 | } |
bogdanm | 0:9b334a45a8ff | 72 | |
bogdanm | 0:9b334a45a8ff | 73 | /* power seq registers */ |
bogdanm | 0:9b334a45a8ff | 74 | static void set_pwr_regs(void) |
bogdanm | 0:9b334a45a8ff | 75 | { |
bogdanm | 0:9b334a45a8ff | 76 | uint32_t dac2trim = MXC_DAC2->reg & 0xff00ffff; |
bogdanm | 0:9b334a45a8ff | 77 | uint32_t dac3trim = MXC_DAC3->reg & 0xff00ffff; |
bogdanm | 0:9b334a45a8ff | 78 | dac2trim = dac2trim + MXC_TRIM->trim_reg_36; |
bogdanm | 0:9b334a45a8ff | 79 | dac3trim = dac3trim + MXC_TRIM->trim_reg_37; |
bogdanm | 0:9b334a45a8ff | 80 | if ((MXC_TRIM->trim_reg_13 != 0) && (MXC_TRIM->trim_reg_13 != 0xFFFFFFFF)) { |
bogdanm | 0:9b334a45a8ff | 81 | MXC_PWRSEQ->reg5 = MXC_TRIM->trim_reg_13; |
bogdanm | 0:9b334a45a8ff | 82 | } |
bogdanm | 0:9b334a45a8ff | 83 | if ((MXC_TRIM->trim_reg_14 != 0) && (MXC_TRIM->trim_reg_14 != 0xFFFFFFFF)) { |
bogdanm | 0:9b334a45a8ff | 84 | MXC_PWRSEQ->reg6 = MXC_TRIM->trim_reg_14; |
bogdanm | 0:9b334a45a8ff | 85 | } |
bogdanm | 0:9b334a45a8ff | 86 | MXC_DAC0->trm = MXC_TRIM->trim_reg_34; |
bogdanm | 0:9b334a45a8ff | 87 | MXC_DAC1->trm = MXC_TRIM->trim_reg_35; |
bogdanm | 0:9b334a45a8ff | 88 | MXC_DAC2->reg = dac2trim; |
bogdanm | 0:9b334a45a8ff | 89 | MXC_DAC3->reg = dac3trim; |
bogdanm | 0:9b334a45a8ff | 90 | } |
bogdanm | 0:9b334a45a8ff | 91 | |
bogdanm | 0:9b334a45a8ff | 92 | void ICC_Enable(void) |
bogdanm | 0:9b334a45a8ff | 93 | { |
bogdanm | 0:9b334a45a8ff | 94 | /* clock gater must be 'on' not 'dynamic' for cache control */ |
bogdanm | 0:9b334a45a8ff | 95 | uint32_t temp = MXC_CLKMAN->clk_gate_ctrl0; |
bogdanm | 0:9b334a45a8ff | 96 | temp &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER; |
bogdanm | 0:9b334a45a8ff | 97 | temp |= (MXC_E_CLKMAN_CLK_GATE_ON << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS); |
bogdanm | 0:9b334a45a8ff | 98 | MXC_CLKMAN->clk_gate_ctrl0 = temp; |
bogdanm | 0:9b334a45a8ff | 99 | |
bogdanm | 0:9b334a45a8ff | 100 | |
bogdanm | 0:9b334a45a8ff | 101 | /* invalidate, wait, enable */ |
bogdanm | 0:9b334a45a8ff | 102 | MXC_ICC->invdt_all = 0xFFFF; |
bogdanm | 0:9b334a45a8ff | 103 | while(!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY)); |
bogdanm | 0:9b334a45a8ff | 104 | MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE; |
bogdanm | 0:9b334a45a8ff | 105 | |
bogdanm | 0:9b334a45a8ff | 106 | /* must invalidate a second time for proper use */ |
bogdanm | 0:9b334a45a8ff | 107 | MXC_ICC->invdt_all = 1; |
bogdanm | 0:9b334a45a8ff | 108 | |
bogdanm | 0:9b334a45a8ff | 109 | /* clock gater 'dynamic' safe again */ |
bogdanm | 0:9b334a45a8ff | 110 | temp = MXC_CLKMAN->clk_gate_ctrl0; |
bogdanm | 0:9b334a45a8ff | 111 | temp &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER; |
bogdanm | 0:9b334a45a8ff | 112 | temp |= (MXC_E_CLKMAN_CLK_GATE_DYNAMIC << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS); |
bogdanm | 0:9b334a45a8ff | 113 | MXC_CLKMAN->clk_gate_ctrl0 = temp; |
bogdanm | 0:9b334a45a8ff | 114 | } |
bogdanm | 0:9b334a45a8ff | 115 | |
bogdanm | 0:9b334a45a8ff | 116 | void Trim_RO(void) |
bogdanm | 0:9b334a45a8ff | 117 | { |
bogdanm | 0:9b334a45a8ff | 118 | uint32_t reg0; |
bogdanm | 0:9b334a45a8ff | 119 | uint32_t trim; |
bogdanm | 0:9b334a45a8ff | 120 | |
bogdanm | 0:9b334a45a8ff | 121 | // Save the RTCEN_RUN state and set it |
bogdanm | 0:9b334a45a8ff | 122 | reg0 = MXC_PWRSEQ->reg0; |
bogdanm | 0:9b334a45a8ff | 123 | MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN; |
bogdanm | 0:9b334a45a8ff | 124 | |
bogdanm | 0:9b334a45a8ff | 125 | /* needed if parts are untrimmed */ |
bogdanm | 0:9b334a45a8ff | 126 | if ((MXC_TRIM->trim_reg_13 == 0) || (MXC_TRIM->trim_reg_13 == 0xFFFFFFFF)) { |
bogdanm | 0:9b334a45a8ff | 127 | MXC_PWRSEQ->reg5 = (MXC_PWRSEQ->reg5 & ~MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF) | (16 << MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS); |
bogdanm | 0:9b334a45a8ff | 128 | } |
bogdanm | 0:9b334a45a8ff | 129 | trim = (MXC_PWRSEQ->reg5 & MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF) >> (MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS - 2); |
bogdanm | 0:9b334a45a8ff | 130 | MXC_ADCCFG->ro_cal1 = (MXC_ADCCFG->ro_cal1 & ~MXC_F_ADC_RO_CAL1_TRM_INIT) | |
bogdanm | 0:9b334a45a8ff | 131 | ((trim << MXC_F_ADC_RO_CAL1_TRM_INIT_POS) & MXC_F_ADC_RO_CAL1_TRM_INIT); |
bogdanm | 0:9b334a45a8ff | 132 | MXC_ADCCFG->ro_cal0 = (MXC_ADCCFG->ro_cal0 & ~MXC_F_ADC_RO_CAL0_TRM_MU) | (0x04 << MXC_F_ADC_RO_CAL0_TRM_MU_POS); |
bogdanm | 0:9b334a45a8ff | 133 | BITBAND_SetBit(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS); |
bogdanm | 0:9b334a45a8ff | 134 | BITBAND_SetBit(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS); |
bogdanm | 0:9b334a45a8ff | 135 | BITBAND_SetBit(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS); |
bogdanm | 0:9b334a45a8ff | 136 | |
bogdanm | 0:9b334a45a8ff | 137 | SysTick->LOAD = 1635; /* about 50ms, based on a 32KHz systick clock */ |
bogdanm | 0:9b334a45a8ff | 138 | SysTick->VAL = 0; |
bogdanm | 0:9b334a45a8ff | 139 | SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; /* Enable SysTick Timer */ |
bogdanm | 0:9b334a45a8ff | 140 | while(SysTick->VAL == 0); |
bogdanm | 0:9b334a45a8ff | 141 | while(!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)); |
bogdanm | 0:9b334a45a8ff | 142 | SysTick->CTRL = 0; |
bogdanm | 0:9b334a45a8ff | 143 | |
bogdanm | 0:9b334a45a8ff | 144 | trim = (MXC_ADCCFG->ro_cal0 & MXC_F_ADC_RO_CAL0_RO_TRM) >> (MXC_F_ADC_RO_CAL0_RO_TRM_POS + 2); |
bogdanm | 0:9b334a45a8ff | 145 | BITBAND_ClrBit(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS); |
bogdanm | 0:9b334a45a8ff | 146 | MXC_PWRSEQ->reg5 = (MXC_PWRSEQ->reg5 & ~MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF) | |
bogdanm | 0:9b334a45a8ff | 147 | ((trim << MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS) & MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF); |
bogdanm | 0:9b334a45a8ff | 148 | |
bogdanm | 0:9b334a45a8ff | 149 | // Restore the RTCEN_RUN state |
bogdanm | 0:9b334a45a8ff | 150 | if (!(reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN)) { |
bogdanm | 0:9b334a45a8ff | 151 | MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN; |
bogdanm | 0:9b334a45a8ff | 152 | } |
bogdanm | 0:9b334a45a8ff | 153 | } |
bogdanm | 0:9b334a45a8ff | 154 | |
bogdanm | 0:9b334a45a8ff | 155 | // This function to be implemented by the hal |
bogdanm | 0:9b334a45a8ff | 156 | extern void low_level_init(void); |
bogdanm | 0:9b334a45a8ff | 157 | |
bogdanm | 0:9b334a45a8ff | 158 | void SystemInit(void) |
bogdanm | 0:9b334a45a8ff | 159 | { |
bogdanm | 0:9b334a45a8ff | 160 | set_pwr_regs(); |
bogdanm | 0:9b334a45a8ff | 161 | |
bogdanm | 0:9b334a45a8ff | 162 | // Enable instruction cache |
bogdanm | 0:9b334a45a8ff | 163 | ICC_Enable(); |
bogdanm | 0:9b334a45a8ff | 164 | |
bogdanm | 0:9b334a45a8ff | 165 | low_level_init(); |
bogdanm | 0:9b334a45a8ff | 166 | |
bogdanm | 0:9b334a45a8ff | 167 | // Clear IO Active |
bogdanm | 0:9b334a45a8ff | 168 | MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE | |
bogdanm | 0:9b334a45a8ff | 169 | MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE); |
bogdanm | 0:9b334a45a8ff | 170 | |
bogdanm | 0:9b334a45a8ff | 171 | // Set WUD Clear |
bogdanm | 0:9b334a45a8ff | 172 | MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE | |
bogdanm | 0:9b334a45a8ff | 173 | MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE | |
bogdanm | 0:9b334a45a8ff | 174 | MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR); |
bogdanm | 0:9b334a45a8ff | 175 | |
bogdanm | 0:9b334a45a8ff | 176 | // Set IO Active |
bogdanm | 0:9b334a45a8ff | 177 | MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE | |
bogdanm | 0:9b334a45a8ff | 178 | MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE | |
bogdanm | 0:9b334a45a8ff | 179 | MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE | |
bogdanm | 0:9b334a45a8ff | 180 | MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED); |
bogdanm | 0:9b334a45a8ff | 181 | |
bogdanm | 0:9b334a45a8ff | 182 | // Clear the first boot flag. Use low_level_init() if special handling is required. |
bogdanm | 0:9b334a45a8ff | 183 | MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT; |
bogdanm | 0:9b334a45a8ff | 184 | |
bogdanm | 0:9b334a45a8ff | 185 | // Enable the regulator |
bogdanm | 0:9b334a45a8ff | 186 | MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN; |
bogdanm | 0:9b334a45a8ff | 187 | |
bogdanm | 0:9b334a45a8ff | 188 | // Mask all wakeups |
bogdanm | 0:9b334a45a8ff | 189 | MXC_PWRSEQ->msk_flags = 0xFFFFFFFF; |
bogdanm | 0:9b334a45a8ff | 190 | |
bogdanm | 0:9b334a45a8ff | 191 | // Set systick to the RTC input 32.768kHz clock, not system clock; this is needed to keep JTAG alive during sleep |
bogdanm | 0:9b334a45a8ff | 192 | MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE; |
bogdanm | 0:9b334a45a8ff | 193 | |
bogdanm | 0:9b334a45a8ff | 194 | SystemCoreClockUpdate(); |
bogdanm | 0:9b334a45a8ff | 195 | |
bogdanm | 0:9b334a45a8ff | 196 | Trim_RO(); |
bogdanm | 0:9b334a45a8ff | 197 | } |