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atmel-rf-driver/source/AT86RFReg.h@4:daf182af022b, 2017-04-19 (annotated)

Committer:
JMF
Date:
Wed Apr 19 20:58:54 2017 +0000
Revision:
4:daf182af022b
Parent:
0:2563b0415d1f 
json file changes;

Who changed what in which revision?

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JMF 0:2563b0415d1f 1 /*
JMF 0:2563b0415d1f 2 * Copyright (c) 2014-2015 ARM Limited. All rights reserved.
JMF 0:2563b0415d1f 3 * SPDX-License-Identifier: Apache-2.0
JMF 0:2563b0415d1f 4 * Licensed under the Apache License, Version 2.0 (the License); you may
JMF 0:2563b0415d1f 5 * not use this file except in compliance with the License.
JMF 0:2563b0415d1f 6 * You may obtain a copy of the License at
JMF 0:2563b0415d1f 7 *
JMF 0:2563b0415d1f 8 * http://www.apache.org/licenses/LICENSE-2.0
JMF 0:2563b0415d1f 9 *
JMF 0:2563b0415d1f 10 * Unless required by applicable law or agreed to in writing, software
JMF 0:2563b0415d1f 11 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
JMF 0:2563b0415d1f 12 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
JMF 0:2563b0415d1f 13 * See the License for the specific language governing permissions and
JMF 0:2563b0415d1f 14 * limitations under the License.
JMF 0:2563b0415d1f 15 */
JMF 0:2563b0415d1f 16
JMF 0:2563b0415d1f 17 #ifndef AT86RFREG_H_
JMF 0:2563b0415d1f 18 #define AT86RFREG_H_
JMF 0:2563b0415d1f 19 #ifdef __cplusplus
JMF 0:2563b0415d1f 20 extern "C" {
JMF 0:2563b0415d1f 21 #endif
JMF 0:2563b0415d1f 22
JMF 0:2563b0415d1f 23 /*AT86RF212 PHY Modes*/
JMF 0:2563b0415d1f 24 #define BPSK_20 0x00
JMF 0:2563b0415d1f 25 #define BPSK_40 0x04
JMF 0:2563b0415d1f 26 #define BPSK_40_ALT 0x14
JMF 0:2563b0415d1f 27 #define OQPSK_SIN_RC_100 0x08
JMF 0:2563b0415d1f 28 #define OQPSK_SIN_RC_200 0x09
JMF 0:2563b0415d1f 29 #define OQPSK_RC_100 0x18
JMF 0:2563b0415d1f 30 #define OQPSK_RC_200 0x19
JMF 0:2563b0415d1f 31 #define OQPSK_SIN_250 0x0c
JMF 0:2563b0415d1f 32 #define OQPSK_SIN_500 0x0d
JMF 0:2563b0415d1f 33 #define OQPSK_SIN_500_ALT 0x0f
JMF 0:2563b0415d1f 34 #define OQPSK_RC_250 0x1c
JMF 0:2563b0415d1f 35 #define OQPSK_RC_500 0x1d
JMF 0:2563b0415d1f 36 #define OQPSK_RC_500_ALT 0x1f
JMF 0:2563b0415d1f 37 #define OQPSK_SIN_RC_400_SCR_ON 0x2A
JMF 0:2563b0415d1f 38 #define OQPSK_SIN_RC_400_SCR_OFF 0x0A
JMF 0:2563b0415d1f 39 #define OQPSK_RC_400_SCR_ON 0x3A
JMF 0:2563b0415d1f 40 #define OQPSK_RC_400_SCR_OFF 0x1A
JMF 0:2563b0415d1f 41 #define OQPSK_SIN_1000_SCR_ON 0x2E
JMF 0:2563b0415d1f 42 #define OQPSK_SIN_1000_SCR_OFF 0x0E
JMF 0:2563b0415d1f 43 #define OQPSK_RC_1000_SCR_ON 0x3E
JMF 0:2563b0415d1f 44 #define OQPSK_RC_1000_SCR_OFF 0x1E
JMF 0:2563b0415d1f 45
JMF 0:2563b0415d1f 46 /*Supported transceivers*/
JMF 0:2563b0415d1f 47 #define PART_AT86RF231 0x03
JMF 0:2563b0415d1f 48 #define PART_AT86RF212 0x07
JMF 0:2563b0415d1f 49 #define PART_AT86RF233 0x0B
JMF 0:2563b0415d1f 50 #define VERSION_AT86RF212 0x01
JMF 0:2563b0415d1f 51 #define VERSION_AT86RF212B 0x03
JMF 0:2563b0415d1f 52
JMF 0:2563b0415d1f 53 /*RF Configuration Registers*/
JMF 0:2563b0415d1f 54 #define TRX_STATUS 0x01
JMF 0:2563b0415d1f 55 #define TRX_STATE 0x02
JMF 0:2563b0415d1f 56 #define TRX_CTRL_0 0x03
JMF 0:2563b0415d1f 57 #define TRX_CTRL_1 0x04
JMF 0:2563b0415d1f 58 #define PHY_TX_PWR 0x05
JMF 0:2563b0415d1f 59 #define PHY_RSSI 0x06
JMF 0:2563b0415d1f 60 #define PHY_ED_LEVEL 0x07
JMF 0:2563b0415d1f 61 #define PHY_CC_CCA 0x08
JMF 0:2563b0415d1f 62 #define RX_CTRL 0x0A
JMF 0:2563b0415d1f 63 #define SFD_VALUE 0x0B
JMF 0:2563b0415d1f 64 #define TRX_CTRL_2 0x0C
JMF 0:2563b0415d1f 65 #define ANT_DIV 0x0D
JMF 0:2563b0415d1f 66 #define IRQ_MASK 0x0E
JMF 0:2563b0415d1f 67 #define IRQ_STATUS 0x0F
JMF 0:2563b0415d1f 68 #define VREG_CTRL 0x10
JMF 0:2563b0415d1f 69 #define BATMON 0x11
JMF 0:2563b0415d1f 70 #define XOSC_CTRL 0x12
JMF 0:2563b0415d1f 71 #define CC_CTRL_0 0x13
JMF 0:2563b0415d1f 72 #define CC_CTRL_1 0x14
JMF 0:2563b0415d1f 73 #define RX_SYN 0x15
JMF 0:2563b0415d1f 74 #define TRX_RPC 0x16
JMF 0:2563b0415d1f 75 #define RF_CTRL_0 0x16
JMF 0:2563b0415d1f 76 #define XAH_CTRL_1 0x17
JMF 0:2563b0415d1f 77 #define FTN_CTRL 0x18
JMF 0:2563b0415d1f 78 #define PLL_CF 0x1A
JMF 0:2563b0415d1f 79 #define PLL_DCU 0x1B
JMF 0:2563b0415d1f 80 #define PART_NUM 0x1C
JMF 0:2563b0415d1f 81 #define VERSION_NUM 0x1D
JMF 0:2563b0415d1f 82 #define MAN_ID_0 0x1E
JMF 0:2563b0415d1f 83 #define MAN_ID_1 0x1F
JMF 0:2563b0415d1f 84 #define SHORT_ADDR_0 0x20
JMF 0:2563b0415d1f 85 #define SHORT_ADDR_1 0x21
JMF 0:2563b0415d1f 86 #define PAN_ID_0 0x22
JMF 0:2563b0415d1f 87 #define PAN_ID_1 0x23
JMF 0:2563b0415d1f 88 #define IEEE_ADDR_0 0x24
JMF 0:2563b0415d1f 89 #define IEEE_ADDR_1 0x25
JMF 0:2563b0415d1f 90 #define IEEE_ADDR_2 0x26
JMF 0:2563b0415d1f 91 #define IEEE_ADDR_3 0x27
JMF 0:2563b0415d1f 92 #define IEEE_ADDR_4 0x28
JMF 0:2563b0415d1f 93 #define IEEE_ADDR_5 0x29
JMF 0:2563b0415d1f 94 #define IEEE_ADDR_6 0x2A
JMF 0:2563b0415d1f 95 #define IEEE_ADDR_7 0x2B
JMF 0:2563b0415d1f 96 #define XAH_CTRL_0 0x2C
JMF 0:2563b0415d1f 97 #define CSMA_SEED_0 0x2D
JMF 0:2563b0415d1f 98 #define CSMA_SEED_1 0x2E
JMF 0:2563b0415d1f 99 #define CSMA_BE 0x2F
JMF 0:2563b0415d1f 100
JMF 0:2563b0415d1f 101 /* CSMA_SEED_1*/
JMF 0:2563b0415d1f 102 #define AACK_FVN_MODE1 7
JMF 0:2563b0415d1f 103 #define AACK_FVN_MODE0 6
JMF 0:2563b0415d1f 104 #define AACK_SET_PD 5
JMF 0:2563b0415d1f 105 #define AACK_DIS_ACK 4
JMF 0:2563b0415d1f 106 #define AACK_I_AM_COORD 3
JMF 0:2563b0415d1f 107 #define CSMA_SEED_12 2
JMF 0:2563b0415d1f 108 #define CSMA_SEED_11 1
JMF 0:2563b0415d1f 109 #define CSMA_SEED_10 0
JMF 0:2563b0415d1f 110
JMF 0:2563b0415d1f 111 /*TRX_STATUS bits*/
JMF 0:2563b0415d1f 112 #define CCA_STATUS 0x40
JMF 0:2563b0415d1f 113 #define CCA_DONE 0x80
JMF 0:2563b0415d1f 114
JMF 0:2563b0415d1f 115 /*PHY_CC_CCA bits*/
JMF 0:2563b0415d1f 116 #define CCA_REQUEST 0x80
JMF 0:2563b0415d1f 117 #define CCA_MODE_1 0x20
JMF 0:2563b0415d1f 118 #define CCA_MODE_3 0x60
JMF 0:2563b0415d1f 119
JMF 0:2563b0415d1f 120 /*IRQ_MASK bits*/
JMF 0:2563b0415d1f 121 #define RX_START 0x04
JMF 0:2563b0415d1f 122 #define TRX_END 0x08
JMF 0:2563b0415d1f 123 #define CCA_ED_DONE 0x10
JMF 0:2563b0415d1f 124 #define AMI 0x20
JMF 0:2563b0415d1f 125 #define TRX_UR 0x40
JMF 0:2563b0415d1f 126
JMF 0:2563b0415d1f 127 /*ANT_DIV bits*/
JMF 0:2563b0415d1f 128 #define ANT_DIV_EN 0x08
JMF 0:2563b0415d1f 129 #define ANT_EXT_SW_EN 0x04
JMF 0:2563b0415d1f 130 #define ANT_CTRL_DEFAULT 0x03
JMF 0:2563b0415d1f 131
JMF 0:2563b0415d1f 132 /*TRX_CTRL_1 bits*/
JMF 0:2563b0415d1f 133 #define PA_EXT_EN 0x80
JMF 0:2563b0415d1f 134
JMF 0:2563b0415d1f 135 /*FTN_CTRL bits*/
JMF 0:2563b0415d1f 136 #define FTN_START 0x80
JMF 0:2563b0415d1f 137
JMF 0:2563b0415d1f 138 /*PHY_RSSI bits*/
JMF 0:2563b0415d1f 139 #define CRC_VALID 0x80
JMF 0:2563b0415d1f 140
JMF 0:2563b0415d1f 141 /*RX_SYN bits*/
JMF 0:2563b0415d1f 142 #define RX_PDT_DIS 0x80
JMF 0:2563b0415d1f 143
JMF 0:2563b0415d1f 144 /*TRX_RPC bits */
JMF 0:2563b0415d1f 145 #define RX_RPC_CTRL 0xC0
JMF 0:2563b0415d1f 146 #define RX_RPC_EN 0x20
JMF 0:2563b0415d1f 147 #define PDT_RPC_EN 0x10
JMF 0:2563b0415d1f 148 #define PLL_RPC_EN 0x08
JMF 0:2563b0415d1f 149 #define XAH_TX_RPC_EN 0x04
JMF 0:2563b0415d1f 150 #define IPAN_RPC_EN 0x02
JMF 0:2563b0415d1f 151 #define TRX_RPC_RSVD_1 0x01
JMF 0:2563b0415d1f 152
JMF 0:2563b0415d1f 153 /*XAH_CTRL_1 bits*/
JMF 0:2563b0415d1f 154 #define AACK_PROM_MODE 0x02
JMF 0:2563b0415d1f 155
JMF 0:2563b0415d1f 156
JMF 0:2563b0415d1f 157 #ifdef __cplusplus
JMF 0:2563b0415d1f 158 }
JMF 0:2563b0415d1f 159 #endif
JMF 0:2563b0415d1f 160
JMF 0:2563b0415d1f 161 #endif /* AT86RFREG_H_ */