NXP
/
mcr20_wireless_uart
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Dependencies: fsl_phy_mcr20a fsl_smac mbed-rtos mbed
Fork of
mcr20_wireless_uart
by 
Freescale
By default, the application uses broadcast addresses for OTA communication. This way, the application can be directly downloaded and run without any user intervention. The following use case assumes no changes have been done to the project.
- Two (or more) MCR20A platforms (plugged into the FRDM-K64F Freescale Freedom Development platform) have to be connected to the PC using the mini/micro-USB cables.
- The code must be downloaded on the platforms via CMSIS-DAP (or other means).
- After that, two or more TERM applications must be opened, and the serial ports must be configured with the same baud rate as the one in the project (default baud rate is 115200). Other necessary serial configurations are 8 bit, no parity, and 1 stop bit.
- To start the setup, each platform must be reset, and one of the (user) push buttons found on the MCR20A platform must be pressed. The user can press any of the non-reset buttons on the FRDM-K64F Freescale Freedom Development platform as well. *This initiates the state machine of the application so user can start.
Documentation
SMAC Demo Applications User Guide
IEEE802_14_5_PHY/PhyTime.c@18:b02fc0e53df8, 2015-04-03 (annotated)
- Committer:
- cotigac
- Date:
- Fri Apr 03 05:23:33 2015 +0000
- Revision:
- 18:b02fc0e53df8
Started creating wireless uart demo based on mbed-rtos
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| cotigac | 18:b02fc0e53df8 | 1 | /*! |
| cotigac | 18:b02fc0e53df8 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
| cotigac | 18:b02fc0e53df8 | 3 | * All rights reserved. |
| cotigac | 18:b02fc0e53df8 | 4 | * |
| cotigac | 18:b02fc0e53df8 | 5 | * \file PhyTime.c |
| cotigac | 18:b02fc0e53df8 | 6 | * |
| cotigac | 18:b02fc0e53df8 | 7 | * Redistribution and use in source and binary forms, with or without modification, |
| cotigac | 18:b02fc0e53df8 | 8 | * are permitted provided that the following conditions are met: |
| cotigac | 18:b02fc0e53df8 | 9 | * |
| cotigac | 18:b02fc0e53df8 | 10 | * o Redistributions of source code must retain the above copyright notice, this list |
| cotigac | 18:b02fc0e53df8 | 11 | * of conditions and the following disclaimer. |
| cotigac | 18:b02fc0e53df8 | 12 | * |
| cotigac | 18:b02fc0e53df8 | 13 | * o Redistributions in binary form must reproduce the above copyright notice, this |
| cotigac | 18:b02fc0e53df8 | 14 | * list of conditions and the following disclaimer in the documentation and/or |
| cotigac | 18:b02fc0e53df8 | 15 | * other materials provided with the distribution. |
| cotigac | 18:b02fc0e53df8 | 16 | * |
| cotigac | 18:b02fc0e53df8 | 17 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
| cotigac | 18:b02fc0e53df8 | 18 | * contributors may be used to endorse or promote products derived from this |
| cotigac | 18:b02fc0e53df8 | 19 | * software without specific prior written permission. |
| cotigac | 18:b02fc0e53df8 | 20 | * |
| cotigac | 18:b02fc0e53df8 | 21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| cotigac | 18:b02fc0e53df8 | 22 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| cotigac | 18:b02fc0e53df8 | 23 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| cotigac | 18:b02fc0e53df8 | 24 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| cotigac | 18:b02fc0e53df8 | 25 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| cotigac | 18:b02fc0e53df8 | 26 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| cotigac | 18:b02fc0e53df8 | 27 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| cotigac | 18:b02fc0e53df8 | 28 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| cotigac | 18:b02fc0e53df8 | 29 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| cotigac | 18:b02fc0e53df8 | 30 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| cotigac | 18:b02fc0e53df8 | 31 | */ |
| cotigac | 18:b02fc0e53df8 | 32 | |
| cotigac | 18:b02fc0e53df8 | 33 | |
| cotigac | 18:b02fc0e53df8 | 34 | /************************************************************************************ |
| cotigac | 18:b02fc0e53df8 | 35 | ************************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 36 | * Include |
| cotigac | 18:b02fc0e53df8 | 37 | ************************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 38 | ************************************************************************************/ |
| cotigac | 18:b02fc0e53df8 | 39 | #include "EmbeddedTypes.h" |
| cotigac | 18:b02fc0e53df8 | 40 | //#include "fsl_os_abstraction.h" |
| cotigac | 18:b02fc0e53df8 | 41 | #include "MCR20Drv.h" |
| cotigac | 18:b02fc0e53df8 | 42 | #include "MCR20Reg.h" |
| cotigac | 18:b02fc0e53df8 | 43 | #include "Phy.h" |
| cotigac | 18:b02fc0e53df8 | 44 | |
| cotigac | 18:b02fc0e53df8 | 45 | //#include "FunctionLib.h" |
| cotigac | 18:b02fc0e53df8 | 46 | //#include "arm_hal_interrupt.h" |
| cotigac | 18:b02fc0e53df8 | 47 | |
| cotigac | 18:b02fc0e53df8 | 48 | /************************************************************************************ |
| cotigac | 18:b02fc0e53df8 | 49 | ************************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 50 | * Private macros |
| cotigac | 18:b02fc0e53df8 | 51 | ************************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 52 | ************************************************************************************/ |
| cotigac | 18:b02fc0e53df8 | 53 | #define gPhyTimeMinSetupTime_c (10) /* symbols */ |
| cotigac | 18:b02fc0e53df8 | 54 | |
| cotigac | 18:b02fc0e53df8 | 55 | /************************************************************************************ |
| cotigac | 18:b02fc0e53df8 | 56 | ************************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 57 | * Public memory declarations |
| cotigac | 18:b02fc0e53df8 | 58 | ************************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 59 | ************************************************************************************/ |
| cotigac | 18:b02fc0e53df8 | 60 | void (*gpfPhyTimeNotify)(void) = NULL; |
| cotigac | 18:b02fc0e53df8 | 61 | |
| cotigac | 18:b02fc0e53df8 | 62 | /************************************************************************************ |
| cotigac | 18:b02fc0e53df8 | 63 | ************************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 64 | * Private memory declarations |
| cotigac | 18:b02fc0e53df8 | 65 | ************************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 66 | ************************************************************************************/ |
| cotigac | 18:b02fc0e53df8 | 67 | static phyTimeEvent_t mPhyTimers[gMaxPhyTimers_c]; |
| cotigac | 18:b02fc0e53df8 | 68 | static phyTimeEvent_t *pNextEvent; |
| cotigac | 18:b02fc0e53df8 | 69 | volatile uint32_t mPhySeqTimeout; |
| cotigac | 18:b02fc0e53df8 | 70 | volatile uint64_t gPhyTimerOverflow; |
| cotigac | 18:b02fc0e53df8 | 71 | |
| cotigac | 18:b02fc0e53df8 | 72 | /************************************************************************************ |
| cotigac | 18:b02fc0e53df8 | 73 | ************************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 74 | * Private prototypes |
| cotigac | 18:b02fc0e53df8 | 75 | ************************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 76 | ************************************************************************************/ |
| cotigac | 18:b02fc0e53df8 | 77 | static void PhyTime_OverflowCB( uint32_t param ); |
| cotigac | 18:b02fc0e53df8 | 78 | static phyTimeEvent_t* PhyTime_GetNextEvent( void ); |
| cotigac | 18:b02fc0e53df8 | 79 | |
| cotigac | 18:b02fc0e53df8 | 80 | /************************************************************************************ |
| cotigac | 18:b02fc0e53df8 | 81 | ************************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 82 | * Public functions |
| cotigac | 18:b02fc0e53df8 | 83 | ************************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 84 | ************************************************************************************/ |
| cotigac | 18:b02fc0e53df8 | 85 | |
| cotigac | 18:b02fc0e53df8 | 86 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 87 | * \brief Sets the start time of a sequence |
| cotigac | 18:b02fc0e53df8 | 88 | * |
| cotigac | 18:b02fc0e53df8 | 89 | * \param[in] startTime the start time for a sequence |
| cotigac | 18:b02fc0e53df8 | 90 | * |
| cotigac | 18:b02fc0e53df8 | 91 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 92 | void PhyTimeSetEventTrigger |
| cotigac | 18:b02fc0e53df8 | 93 | ( |
| cotigac | 18:b02fc0e53df8 | 94 | uint32_t startTime |
| cotigac | 18:b02fc0e53df8 | 95 | ) |
| cotigac | 18:b02fc0e53df8 | 96 | { |
| cotigac | 18:b02fc0e53df8 | 97 | uint8_t phyReg, phyCtrl3Reg; |
| cotigac | 18:b02fc0e53df8 | 98 | |
| cotigac | 18:b02fc0e53df8 | 99 | __disable_irq(); |
| cotigac | 18:b02fc0e53df8 | 100 | |
| cotigac | 18:b02fc0e53df8 | 101 | phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL1); |
| cotigac | 18:b02fc0e53df8 | 102 | phyReg |= cPHY_CTRL1_TMRTRIGEN; // enable autosequence start by TC2 match |
| cotigac | 18:b02fc0e53df8 | 103 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL1, phyReg); |
| cotigac | 18:b02fc0e53df8 | 104 | |
| cotigac | 18:b02fc0e53df8 | 105 | phyCtrl3Reg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL3); |
| cotigac | 18:b02fc0e53df8 | 106 | phyCtrl3Reg &= ~(cPHY_CTRL3_TMR2CMP_EN);// disable TMR2 compare |
| cotigac | 18:b02fc0e53df8 | 107 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyCtrl3Reg); |
| cotigac | 18:b02fc0e53df8 | 108 | |
| cotigac | 18:b02fc0e53df8 | 109 | MCR20Drv_DirectAccessSPIMultiByteWrite( (uint8_t) T2PRIMECMP_LSB, (uint8_t *) &startTime, 2); |
| cotigac | 18:b02fc0e53df8 | 110 | |
| cotigac | 18:b02fc0e53df8 | 111 | phyReg = MCR20Drv_DirectAccessSPIRead(IRQSTS3); |
| cotigac | 18:b02fc0e53df8 | 112 | phyReg &= 0xF0; // do not change other IRQs status |
| cotigac | 18:b02fc0e53df8 | 113 | phyReg &= ~(cIRQSTS3_TMR2MSK); // unmask TMR2 interrupt |
| cotigac | 18:b02fc0e53df8 | 114 | phyReg |= (cIRQSTS3_TMR2IRQ); // aknowledge TMR2 IRQ |
| cotigac | 18:b02fc0e53df8 | 115 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) IRQSTS3, phyReg); |
| cotigac | 18:b02fc0e53df8 | 116 | |
| cotigac | 18:b02fc0e53df8 | 117 | // TC2PRIME_EN must be enabled in PHY_CTRL4 register |
| cotigac | 18:b02fc0e53df8 | 118 | phyCtrl3Reg |= cPHY_CTRL3_TMR2CMP_EN; // enable TMR2 compare |
| cotigac | 18:b02fc0e53df8 | 119 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyCtrl3Reg); |
| cotigac | 18:b02fc0e53df8 | 120 | |
| cotigac | 18:b02fc0e53df8 | 121 | __enable_irq(); |
| cotigac | 18:b02fc0e53df8 | 122 | } |
| cotigac | 18:b02fc0e53df8 | 123 | |
| cotigac | 18:b02fc0e53df8 | 124 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 125 | * \brief Disable the time trigger for a sequence. |
| cotigac | 18:b02fc0e53df8 | 126 | * |
| cotigac | 18:b02fc0e53df8 | 127 | * \remarks The sequence will start asap |
| cotigac | 18:b02fc0e53df8 | 128 | * |
| cotigac | 18:b02fc0e53df8 | 129 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 130 | void PhyTimeDisableEventTrigger |
| cotigac | 18:b02fc0e53df8 | 131 | ( |
| cotigac | 18:b02fc0e53df8 | 132 | void |
| cotigac | 18:b02fc0e53df8 | 133 | ) |
| cotigac | 18:b02fc0e53df8 | 134 | { |
| cotigac | 18:b02fc0e53df8 | 135 | uint8_t phyReg; |
| cotigac | 18:b02fc0e53df8 | 136 | |
| cotigac | 18:b02fc0e53df8 | 137 | __disable_irq(); |
| cotigac | 18:b02fc0e53df8 | 138 | |
| cotigac | 18:b02fc0e53df8 | 139 | phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL1); |
| cotigac | 18:b02fc0e53df8 | 140 | phyReg &= ~(cPHY_CTRL1_TMRTRIGEN); // disable autosequence start by TC2 match |
| cotigac | 18:b02fc0e53df8 | 141 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL1, phyReg); |
| cotigac | 18:b02fc0e53df8 | 142 | |
| cotigac | 18:b02fc0e53df8 | 143 | phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL3); |
| cotigac | 18:b02fc0e53df8 | 144 | phyReg &= ~(cPHY_CTRL3_TMR2CMP_EN);// disable TMR2 compare |
| cotigac | 18:b02fc0e53df8 | 145 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyReg); |
| cotigac | 18:b02fc0e53df8 | 146 | |
| cotigac | 18:b02fc0e53df8 | 147 | phyReg = MCR20Drv_DirectAccessSPIRead(IRQSTS3); |
| cotigac | 18:b02fc0e53df8 | 148 | phyReg &= 0xF0; // do not change other IRQs status |
| cotigac | 18:b02fc0e53df8 | 149 | phyReg |= (cIRQSTS3_TMR2MSK); // mask TMR2 interrupt |
| cotigac | 18:b02fc0e53df8 | 150 | phyReg |= (cIRQSTS3_TMR2IRQ); // aknowledge TMR2 IRQ |
| cotigac | 18:b02fc0e53df8 | 151 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) IRQSTS3, phyReg); |
| cotigac | 18:b02fc0e53df8 | 152 | |
| cotigac | 18:b02fc0e53df8 | 153 | __enable_irq(); |
| cotigac | 18:b02fc0e53df8 | 154 | } |
| cotigac | 18:b02fc0e53df8 | 155 | |
| cotigac | 18:b02fc0e53df8 | 156 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 157 | * \brief Sets the timeout value for a sequence |
| cotigac | 18:b02fc0e53df8 | 158 | * |
| cotigac | 18:b02fc0e53df8 | 159 | * \param[in] pEndTime the absolute time when a sequence should terminate |
| cotigac | 18:b02fc0e53df8 | 160 | * |
| cotigac | 18:b02fc0e53df8 | 161 | * \remarks If the sequence does not finish until the timeout, it will be aborted |
| cotigac | 18:b02fc0e53df8 | 162 | * |
| cotigac | 18:b02fc0e53df8 | 163 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 164 | void PhyTimeSetEventTimeout |
| cotigac | 18:b02fc0e53df8 | 165 | ( |
| cotigac | 18:b02fc0e53df8 | 166 | uint32_t *pEndTime |
| cotigac | 18:b02fc0e53df8 | 167 | ) |
| cotigac | 18:b02fc0e53df8 | 168 | { |
| cotigac | 18:b02fc0e53df8 | 169 | uint8_t phyReg, phyCtrl3Reg; |
| cotigac | 18:b02fc0e53df8 | 170 | |
| cotigac | 18:b02fc0e53df8 | 171 | #ifdef PHY_PARAMETERS_VALIDATION |
| cotigac | 18:b02fc0e53df8 | 172 | if(NULL == pEndTime) |
| cotigac | 18:b02fc0e53df8 | 173 | { |
| cotigac | 18:b02fc0e53df8 | 174 | return; |
| cotigac | 18:b02fc0e53df8 | 175 | } |
| cotigac | 18:b02fc0e53df8 | 176 | #endif // PHY_PARAMETERS_VALIDATION |
| cotigac | 18:b02fc0e53df8 | 177 | |
| cotigac | 18:b02fc0e53df8 | 178 | __disable_irq(); |
| cotigac | 18:b02fc0e53df8 | 179 | |
| cotigac | 18:b02fc0e53df8 | 180 | phyCtrl3Reg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL3); |
| cotigac | 18:b02fc0e53df8 | 181 | phyCtrl3Reg &= ~(cPHY_CTRL3_TMR3CMP_EN);// disable TMR3 compare |
| cotigac | 18:b02fc0e53df8 | 182 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyCtrl3Reg); |
| cotigac | 18:b02fc0e53df8 | 183 | |
| cotigac | 18:b02fc0e53df8 | 184 | phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL4); |
| cotigac | 18:b02fc0e53df8 | 185 | phyReg |= cPHY_CTRL4_TC3TMOUT; // enable autosequence stop by TC3 match |
| cotigac | 18:b02fc0e53df8 | 186 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL4, phyReg); |
| cotigac | 18:b02fc0e53df8 | 187 | |
| cotigac | 18:b02fc0e53df8 | 188 | mPhySeqTimeout = *pEndTime & 0x00FFFFFF; |
| cotigac | 18:b02fc0e53df8 | 189 | MCR20Drv_DirectAccessSPIMultiByteWrite( (uint8_t) T3CMP_LSB, (uint8_t *) pEndTime, 3); |
| cotigac | 18:b02fc0e53df8 | 190 | |
| cotigac | 18:b02fc0e53df8 | 191 | phyReg = MCR20Drv_DirectAccessSPIRead(IRQSTS3); |
| cotigac | 18:b02fc0e53df8 | 192 | phyReg &= 0xF0; // do not change IRQ status |
| cotigac | 18:b02fc0e53df8 | 193 | // phyReg &= ~(cIRQSTS3_TMR3MSK); // unmask TMR3 interrupt |
| cotigac | 18:b02fc0e53df8 | 194 | phyReg |= (cIRQSTS3_TMR3IRQ); // aknowledge TMR3 IRQ |
| cotigac | 18:b02fc0e53df8 | 195 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) IRQSTS3, phyReg); |
| cotigac | 18:b02fc0e53df8 | 196 | |
| cotigac | 18:b02fc0e53df8 | 197 | phyCtrl3Reg |= cPHY_CTRL3_TMR3CMP_EN; // enable TMR3 compare |
| cotigac | 18:b02fc0e53df8 | 198 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyCtrl3Reg); |
| cotigac | 18:b02fc0e53df8 | 199 | |
| cotigac | 18:b02fc0e53df8 | 200 | __enable_irq(); |
| cotigac | 18:b02fc0e53df8 | 201 | } |
| cotigac | 18:b02fc0e53df8 | 202 | |
| cotigac | 18:b02fc0e53df8 | 203 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 204 | * \brief Return the timeout value for the current sequence |
| cotigac | 18:b02fc0e53df8 | 205 | * |
| cotigac | 18:b02fc0e53df8 | 206 | * \return uint32_t the timeout value |
| cotigac | 18:b02fc0e53df8 | 207 | * |
| cotigac | 18:b02fc0e53df8 | 208 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 209 | uint32_t PhyTimeGetEventTimeout( void ) |
| cotigac | 18:b02fc0e53df8 | 210 | { |
| cotigac | 18:b02fc0e53df8 | 211 | return mPhySeqTimeout; |
| cotigac | 18:b02fc0e53df8 | 212 | } |
| cotigac | 18:b02fc0e53df8 | 213 | |
| cotigac | 18:b02fc0e53df8 | 214 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 215 | * \brief Disables the sequence timeout |
| cotigac | 18:b02fc0e53df8 | 216 | * |
| cotigac | 18:b02fc0e53df8 | 217 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 218 | void PhyTimeDisableEventTimeout |
| cotigac | 18:b02fc0e53df8 | 219 | ( |
| cotigac | 18:b02fc0e53df8 | 220 | void |
| cotigac | 18:b02fc0e53df8 | 221 | ) |
| cotigac | 18:b02fc0e53df8 | 222 | { |
| cotigac | 18:b02fc0e53df8 | 223 | uint8_t phyReg; |
| cotigac | 18:b02fc0e53df8 | 224 | |
| cotigac | 18:b02fc0e53df8 | 225 | __disable_irq(); |
| cotigac | 18:b02fc0e53df8 | 226 | |
| cotigac | 18:b02fc0e53df8 | 227 | phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL4); |
| cotigac | 18:b02fc0e53df8 | 228 | phyReg &= ~(cPHY_CTRL4_TC3TMOUT); // disable autosequence stop by TC3 match |
| cotigac | 18:b02fc0e53df8 | 229 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL4, phyReg); |
| cotigac | 18:b02fc0e53df8 | 230 | |
| cotigac | 18:b02fc0e53df8 | 231 | phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL3); |
| cotigac | 18:b02fc0e53df8 | 232 | phyReg &= ~(cPHY_CTRL3_TMR3CMP_EN);// disable TMR3 compare |
| cotigac | 18:b02fc0e53df8 | 233 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyReg); |
| cotigac | 18:b02fc0e53df8 | 234 | |
| cotigac | 18:b02fc0e53df8 | 235 | phyReg = MCR20Drv_DirectAccessSPIRead(IRQSTS3); |
| cotigac | 18:b02fc0e53df8 | 236 | phyReg &= 0xF0; // do not change IRQ status |
| cotigac | 18:b02fc0e53df8 | 237 | phyReg |= cIRQSTS3_TMR3IRQ; // aknowledge TMR3 IRQ |
| cotigac | 18:b02fc0e53df8 | 238 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) IRQSTS3, phyReg); |
| cotigac | 18:b02fc0e53df8 | 239 | |
| cotigac | 18:b02fc0e53df8 | 240 | __enable_irq(); |
| cotigac | 18:b02fc0e53df8 | 241 | } |
| cotigac | 18:b02fc0e53df8 | 242 | |
| cotigac | 18:b02fc0e53df8 | 243 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 244 | * \brief Reads the absolute clock from the radio |
| cotigac | 18:b02fc0e53df8 | 245 | * |
| cotigac | 18:b02fc0e53df8 | 246 | * \param[out] pRetClk pointer to a location where the current clock will be stored |
| cotigac | 18:b02fc0e53df8 | 247 | * |
| cotigac | 18:b02fc0e53df8 | 248 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 249 | void PhyTimeReadClock |
| cotigac | 18:b02fc0e53df8 | 250 | ( |
| cotigac | 18:b02fc0e53df8 | 251 | uint32_t *pRetClk |
| cotigac | 18:b02fc0e53df8 | 252 | ) |
| cotigac | 18:b02fc0e53df8 | 253 | { |
| cotigac | 18:b02fc0e53df8 | 254 | #ifdef PHY_PARAMETERS_VALIDATION |
| cotigac | 18:b02fc0e53df8 | 255 | if(NULL == pRetClk) |
| cotigac | 18:b02fc0e53df8 | 256 | { |
| cotigac | 18:b02fc0e53df8 | 257 | return; |
| cotigac | 18:b02fc0e53df8 | 258 | } |
| cotigac | 18:b02fc0e53df8 | 259 | #endif // PHY_PARAMETERS_VALIDATION |
| cotigac | 18:b02fc0e53df8 | 260 | |
| cotigac | 18:b02fc0e53df8 | 261 | __disable_irq(); |
| cotigac | 18:b02fc0e53df8 | 262 | |
| cotigac | 18:b02fc0e53df8 | 263 | MCR20Drv_DirectAccessSPIMultiByteRead( (uint8_t) EVENT_TMR_LSB, (uint8_t *) pRetClk, 3); |
| cotigac | 18:b02fc0e53df8 | 264 | *(((uint8_t *)pRetClk) + 3) = 0; |
| cotigac | 18:b02fc0e53df8 | 265 | |
| cotigac | 18:b02fc0e53df8 | 266 | __enable_irq(); |
| cotigac | 18:b02fc0e53df8 | 267 | |
| cotigac | 18:b02fc0e53df8 | 268 | } |
| cotigac | 18:b02fc0e53df8 | 269 | |
| cotigac | 18:b02fc0e53df8 | 270 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 271 | * \brief Initialize the Event Timer |
| cotigac | 18:b02fc0e53df8 | 272 | * |
| cotigac | 18:b02fc0e53df8 | 273 | * \param[in] pAbsTime pointer to the location where the new time is stored |
| cotigac | 18:b02fc0e53df8 | 274 | * |
| cotigac | 18:b02fc0e53df8 | 275 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 276 | void PhyTimeInitEventTimer |
| cotigac | 18:b02fc0e53df8 | 277 | ( |
| cotigac | 18:b02fc0e53df8 | 278 | uint32_t *pAbsTime |
| cotigac | 18:b02fc0e53df8 | 279 | ) |
| cotigac | 18:b02fc0e53df8 | 280 | { |
| cotigac | 18:b02fc0e53df8 | 281 | uint8_t phyCtrl4Reg; |
| cotigac | 18:b02fc0e53df8 | 282 | |
| cotigac | 18:b02fc0e53df8 | 283 | #ifdef PHY_PARAMETERS_VALIDATION |
| cotigac | 18:b02fc0e53df8 | 284 | if(NULL == pAbsTime) |
| cotigac | 18:b02fc0e53df8 | 285 | { |
| cotigac | 18:b02fc0e53df8 | 286 | return; |
| cotigac | 18:b02fc0e53df8 | 287 | } |
| cotigac | 18:b02fc0e53df8 | 288 | #endif // PHY_PARAMETERS_VALIDATION |
| cotigac | 18:b02fc0e53df8 | 289 | |
| cotigac | 18:b02fc0e53df8 | 290 | __disable_irq(); |
| cotigac | 18:b02fc0e53df8 | 291 | |
| cotigac | 18:b02fc0e53df8 | 292 | phyCtrl4Reg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL4); |
| cotigac | 18:b02fc0e53df8 | 293 | phyCtrl4Reg |= cPHY_CTRL4_TMRLOAD; // self clearing bit |
| cotigac | 18:b02fc0e53df8 | 294 | |
| cotigac | 18:b02fc0e53df8 | 295 | MCR20Drv_DirectAccessSPIMultiByteWrite( (uint8_t) T1CMP_LSB, (uint8_t *) pAbsTime, 3); |
| cotigac | 18:b02fc0e53df8 | 296 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL4, phyCtrl4Reg); |
| cotigac | 18:b02fc0e53df8 | 297 | |
| cotigac | 18:b02fc0e53df8 | 298 | __enable_irq(); |
| cotigac | 18:b02fc0e53df8 | 299 | } |
| cotigac | 18:b02fc0e53df8 | 300 | |
| cotigac | 18:b02fc0e53df8 | 301 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 302 | * \brief Set TMR1 timeout value |
| cotigac | 18:b02fc0e53df8 | 303 | * |
| cotigac | 18:b02fc0e53df8 | 304 | * \param[in] pWaitTimeout the timeout value |
| cotigac | 18:b02fc0e53df8 | 305 | * |
| cotigac | 18:b02fc0e53df8 | 306 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 307 | void PhyTimeSetWaitTimeout |
| cotigac | 18:b02fc0e53df8 | 308 | ( |
| cotigac | 18:b02fc0e53df8 | 309 | uint32_t *pWaitTimeout |
| cotigac | 18:b02fc0e53df8 | 310 | ) |
| cotigac | 18:b02fc0e53df8 | 311 | { |
| cotigac | 18:b02fc0e53df8 | 312 | uint8_t phyCtrl3Reg, irqSts3Reg; |
| cotigac | 18:b02fc0e53df8 | 313 | |
| cotigac | 18:b02fc0e53df8 | 314 | __disable_irq(); |
| cotigac | 18:b02fc0e53df8 | 315 | |
| cotigac | 18:b02fc0e53df8 | 316 | phyCtrl3Reg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL3); |
| cotigac | 18:b02fc0e53df8 | 317 | phyCtrl3Reg &= ~(cPHY_CTRL3_TMR1CMP_EN);// disable TMR1 compare |
| cotigac | 18:b02fc0e53df8 | 318 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyCtrl3Reg); |
| cotigac | 18:b02fc0e53df8 | 319 | |
| cotigac | 18:b02fc0e53df8 | 320 | MCR20Drv_DirectAccessSPIMultiByteWrite( (uint8_t) T1CMP_LSB, (uint8_t *) pWaitTimeout, 3); |
| cotigac | 18:b02fc0e53df8 | 321 | |
| cotigac | 18:b02fc0e53df8 | 322 | irqSts3Reg = MCR20Drv_DirectAccessSPIRead(IRQSTS3); |
| cotigac | 18:b02fc0e53df8 | 323 | irqSts3Reg &= ~(cIRQSTS3_TMR1MSK); // unmask TMR1 interrupt |
| cotigac | 18:b02fc0e53df8 | 324 | irqSts3Reg &= 0xF0; // do not change other IRQs status |
| cotigac | 18:b02fc0e53df8 | 325 | irqSts3Reg |= (cIRQSTS3_TMR1IRQ); // aknowledge TMR1 IRQ |
| cotigac | 18:b02fc0e53df8 | 326 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) IRQSTS3, irqSts3Reg); |
| cotigac | 18:b02fc0e53df8 | 327 | |
| cotigac | 18:b02fc0e53df8 | 328 | phyCtrl3Reg |= cPHY_CTRL3_TMR1CMP_EN; // enable TMR1 compare |
| cotigac | 18:b02fc0e53df8 | 329 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyCtrl3Reg); |
| cotigac | 18:b02fc0e53df8 | 330 | |
| cotigac | 18:b02fc0e53df8 | 331 | __enable_irq(); |
| cotigac | 18:b02fc0e53df8 | 332 | |
| cotigac | 18:b02fc0e53df8 | 333 | } |
| cotigac | 18:b02fc0e53df8 | 334 | |
| cotigac | 18:b02fc0e53df8 | 335 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 336 | * \brief Disable the TMR1 timeout |
| cotigac | 18:b02fc0e53df8 | 337 | * |
| cotigac | 18:b02fc0e53df8 | 338 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 339 | void PhyTimeDisableWaitTimeout |
| cotigac | 18:b02fc0e53df8 | 340 | ( |
| cotigac | 18:b02fc0e53df8 | 341 | void |
| cotigac | 18:b02fc0e53df8 | 342 | ) |
| cotigac | 18:b02fc0e53df8 | 343 | { |
| cotigac | 18:b02fc0e53df8 | 344 | uint8_t phyReg; |
| cotigac | 18:b02fc0e53df8 | 345 | |
| cotigac | 18:b02fc0e53df8 | 346 | __disable_irq(); |
| cotigac | 18:b02fc0e53df8 | 347 | |
| cotigac | 18:b02fc0e53df8 | 348 | phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL3); |
| cotigac | 18:b02fc0e53df8 | 349 | phyReg &= ~(cPHY_CTRL3_TMR1CMP_EN);// disable TMR1 compare |
| cotigac | 18:b02fc0e53df8 | 350 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyReg); |
| cotigac | 18:b02fc0e53df8 | 351 | |
| cotigac | 18:b02fc0e53df8 | 352 | phyReg = MCR20Drv_DirectAccessSPIRead(IRQSTS3); |
| cotigac | 18:b02fc0e53df8 | 353 | phyReg &= 0xF0; // do not change IRQ status |
| cotigac | 18:b02fc0e53df8 | 354 | phyReg |= cIRQSTS3_TMR1IRQ; // aknowledge TMR1 IRQ |
| cotigac | 18:b02fc0e53df8 | 355 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) IRQSTS3, phyReg); |
| cotigac | 18:b02fc0e53df8 | 356 | |
| cotigac | 18:b02fc0e53df8 | 357 | __enable_irq(); |
| cotigac | 18:b02fc0e53df8 | 358 | } |
| cotigac | 18:b02fc0e53df8 | 359 | |
| cotigac | 18:b02fc0e53df8 | 360 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 361 | * \brief Set TMR4 timeout value |
| cotigac | 18:b02fc0e53df8 | 362 | * |
| cotigac | 18:b02fc0e53df8 | 363 | * \param[in] pWakeUpTime absolute time |
| cotigac | 18:b02fc0e53df8 | 364 | * |
| cotigac | 18:b02fc0e53df8 | 365 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 366 | void PhyTimeSetWakeUpTime |
| cotigac | 18:b02fc0e53df8 | 367 | ( |
| cotigac | 18:b02fc0e53df8 | 368 | uint32_t *pWakeUpTime |
| cotigac | 18:b02fc0e53df8 | 369 | ) |
| cotigac | 18:b02fc0e53df8 | 370 | { |
| cotigac | 18:b02fc0e53df8 | 371 | uint8_t phyCtrl3Reg, irqSts3Reg; |
| cotigac | 18:b02fc0e53df8 | 372 | |
| cotigac | 18:b02fc0e53df8 | 373 | __disable_irq(); |
| cotigac | 18:b02fc0e53df8 | 374 | |
| cotigac | 18:b02fc0e53df8 | 375 | phyCtrl3Reg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL3); |
| cotigac | 18:b02fc0e53df8 | 376 | // phyCtrl3Reg &= ~(cPHY_CTRL3_TMR4CMP_EN);// disable TMR4 compare |
| cotigac | 18:b02fc0e53df8 | 377 | // MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyCtrl3Reg); |
| cotigac | 18:b02fc0e53df8 | 378 | |
| cotigac | 18:b02fc0e53df8 | 379 | MCR20Drv_DirectAccessSPIMultiByteWrite( (uint8_t) T4CMP_LSB, (uint8_t *) pWakeUpTime, 3); |
| cotigac | 18:b02fc0e53df8 | 380 | |
| cotigac | 18:b02fc0e53df8 | 381 | irqSts3Reg = MCR20Drv_DirectAccessSPIRead(IRQSTS3); |
| cotigac | 18:b02fc0e53df8 | 382 | irqSts3Reg &= ~(cIRQSTS3_TMR4MSK); // unmask TMR4 interrupt |
| cotigac | 18:b02fc0e53df8 | 383 | irqSts3Reg &= 0xF0; // do not change other IRQs status |
| cotigac | 18:b02fc0e53df8 | 384 | irqSts3Reg |= (cIRQSTS3_TMR4IRQ); // aknowledge TMR4 IRQ |
| cotigac | 18:b02fc0e53df8 | 385 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) IRQSTS3, irqSts3Reg); |
| cotigac | 18:b02fc0e53df8 | 386 | |
| cotigac | 18:b02fc0e53df8 | 387 | phyCtrl3Reg |= cPHY_CTRL3_TMR4CMP_EN; // enable TMR4 compare |
| cotigac | 18:b02fc0e53df8 | 388 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyCtrl3Reg); |
| cotigac | 18:b02fc0e53df8 | 389 | |
| cotigac | 18:b02fc0e53df8 | 390 | __enable_irq(); |
| cotigac | 18:b02fc0e53df8 | 391 | } |
| cotigac | 18:b02fc0e53df8 | 392 | |
| cotigac | 18:b02fc0e53df8 | 393 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 394 | * \brief Check if TMR4 IRQ occured, and aknowledge it |
| cotigac | 18:b02fc0e53df8 | 395 | * |
| cotigac | 18:b02fc0e53df8 | 396 | * \return TRUE if TMR4 IRQ occured |
| cotigac | 18:b02fc0e53df8 | 397 | * |
| cotigac | 18:b02fc0e53df8 | 398 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 399 | bool_t PhyTimeIsWakeUpTimeExpired |
| cotigac | 18:b02fc0e53df8 | 400 | ( |
| cotigac | 18:b02fc0e53df8 | 401 | void |
| cotigac | 18:b02fc0e53df8 | 402 | ) |
| cotigac | 18:b02fc0e53df8 | 403 | { |
| cotigac | 18:b02fc0e53df8 | 404 | bool_t wakeUpIrq = FALSE; |
| cotigac | 18:b02fc0e53df8 | 405 | uint8_t phyReg; |
| cotigac | 18:b02fc0e53df8 | 406 | |
| cotigac | 18:b02fc0e53df8 | 407 | __disable_irq(); |
| cotigac | 18:b02fc0e53df8 | 408 | |
| cotigac | 18:b02fc0e53df8 | 409 | phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL3); |
| cotigac | 18:b02fc0e53df8 | 410 | phyReg &= ~(cPHY_CTRL3_TMR4CMP_EN);// disable TMR4 compare |
| cotigac | 18:b02fc0e53df8 | 411 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyReg); |
| cotigac | 18:b02fc0e53df8 | 412 | |
| cotigac | 18:b02fc0e53df8 | 413 | phyReg = MCR20Drv_DirectAccessSPIRead(IRQSTS3); |
| cotigac | 18:b02fc0e53df8 | 414 | |
| cotigac | 18:b02fc0e53df8 | 415 | if( (phyReg & cIRQSTS3_TMR4IRQ) == cIRQSTS3_TMR4IRQ ) |
| cotigac | 18:b02fc0e53df8 | 416 | { |
| cotigac | 18:b02fc0e53df8 | 417 | wakeUpIrq = TRUE; |
| cotigac | 18:b02fc0e53df8 | 418 | } |
| cotigac | 18:b02fc0e53df8 | 419 | |
| cotigac | 18:b02fc0e53df8 | 420 | phyReg &= ~(cIRQSTS3_TMR4MSK); // unmask TMR4 interrupt |
| cotigac | 18:b02fc0e53df8 | 421 | phyReg &= 0xF0; // do not change other IRQs status |
| cotigac | 18:b02fc0e53df8 | 422 | phyReg |= (cIRQSTS3_TMR4IRQ); // aknowledge TMR2 IRQ |
| cotigac | 18:b02fc0e53df8 | 423 | |
| cotigac | 18:b02fc0e53df8 | 424 | MCR20Drv_DirectAccessSPIWrite( (uint8_t) IRQSTS3, phyReg); |
| cotigac | 18:b02fc0e53df8 | 425 | |
| cotigac | 18:b02fc0e53df8 | 426 | __enable_irq(); |
| cotigac | 18:b02fc0e53df8 | 427 | |
| cotigac | 18:b02fc0e53df8 | 428 | return wakeUpIrq; |
| cotigac | 18:b02fc0e53df8 | 429 | } |
| cotigac | 18:b02fc0e53df8 | 430 | |
| cotigac | 18:b02fc0e53df8 | 431 | |
| cotigac | 18:b02fc0e53df8 | 432 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 433 | * \brief PHY Timer Interrupt Service Routine |
| cotigac | 18:b02fc0e53df8 | 434 | * |
| cotigac | 18:b02fc0e53df8 | 435 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 436 | void PhyTime_ISR(void) |
| cotigac | 18:b02fc0e53df8 | 437 | { |
| cotigac | 18:b02fc0e53df8 | 438 | if( pNextEvent->callback == PhyTime_OverflowCB ) |
| cotigac | 18:b02fc0e53df8 | 439 | { |
| cotigac | 18:b02fc0e53df8 | 440 | gPhyTimerOverflow++; |
| cotigac | 18:b02fc0e53df8 | 441 | } |
| cotigac | 18:b02fc0e53df8 | 442 | |
| cotigac | 18:b02fc0e53df8 | 443 | if( gpfPhyTimeNotify ) |
| cotigac | 18:b02fc0e53df8 | 444 | { |
| cotigac | 18:b02fc0e53df8 | 445 | gpfPhyTimeNotify(); |
| cotigac | 18:b02fc0e53df8 | 446 | } |
| cotigac | 18:b02fc0e53df8 | 447 | else |
| cotigac | 18:b02fc0e53df8 | 448 | { |
| cotigac | 18:b02fc0e53df8 | 449 | PhyTime_RunCallback(); |
| cotigac | 18:b02fc0e53df8 | 450 | PhyTime_Maintenance(); |
| cotigac | 18:b02fc0e53df8 | 451 | } |
| cotigac | 18:b02fc0e53df8 | 452 | } |
| cotigac | 18:b02fc0e53df8 | 453 | |
| cotigac | 18:b02fc0e53df8 | 454 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 455 | * \brief Initialize the PHY Timer module |
| cotigac | 18:b02fc0e53df8 | 456 | * |
| cotigac | 18:b02fc0e53df8 | 457 | * \return phyTimeStatus_t |
| cotigac | 18:b02fc0e53df8 | 458 | * |
| cotigac | 18:b02fc0e53df8 | 459 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 460 | phyTimeStatus_t PhyTime_TimerInit( void (*cb)(void) ) |
| cotigac | 18:b02fc0e53df8 | 461 | { |
| cotigac | 18:b02fc0e53df8 | 462 | if( gpfPhyTimeNotify ) |
| cotigac | 18:b02fc0e53df8 | 463 | return gPhyTimeError_c; |
| cotigac | 18:b02fc0e53df8 | 464 | |
| cotigac | 18:b02fc0e53df8 | 465 | gpfPhyTimeNotify = cb; |
| cotigac | 18:b02fc0e53df8 | 466 | gPhyTimerOverflow = 0; |
| cotigac | 18:b02fc0e53df8 | 467 | FLib_MemSet( mPhyTimers, 0, sizeof(mPhyTimers) ); |
| cotigac | 18:b02fc0e53df8 | 468 | |
| cotigac | 18:b02fc0e53df8 | 469 | /* Schedule Overflow Calback */ |
| cotigac | 18:b02fc0e53df8 | 470 | pNextEvent = &mPhyTimers[0]; |
| cotigac | 18:b02fc0e53df8 | 471 | pNextEvent->callback = PhyTime_OverflowCB; |
| cotigac | 18:b02fc0e53df8 | 472 | pNextEvent->timestamp = (gPhyTimerOverflow+1) << gPhyTimeShift_c; |
| cotigac | 18:b02fc0e53df8 | 473 | PhyTimeSetWaitTimeout( (uint32_t*)&pNextEvent->timestamp ); |
| cotigac | 18:b02fc0e53df8 | 474 | |
| cotigac | 18:b02fc0e53df8 | 475 | return gPhyTimeOk_c; |
| cotigac | 18:b02fc0e53df8 | 476 | } |
| cotigac | 18:b02fc0e53df8 | 477 | |
| cotigac | 18:b02fc0e53df8 | 478 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 479 | * \brief Returns a 64bit timestamp value to be used by the MAC Layer |
| cotigac | 18:b02fc0e53df8 | 480 | * |
| cotigac | 18:b02fc0e53df8 | 481 | * \return phyTimeTimestamp_t PHY timestamp |
| cotigac | 18:b02fc0e53df8 | 482 | * |
| cotigac | 18:b02fc0e53df8 | 483 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 484 | phyTimeTimestamp_t PhyTime_GetTimestamp(void) |
| cotigac | 18:b02fc0e53df8 | 485 | { |
| cotigac | 18:b02fc0e53df8 | 486 | phyTimeTimestamp_t time = 0; |
| cotigac | 18:b02fc0e53df8 | 487 | |
| cotigac | 18:b02fc0e53df8 | 488 | __disable_irq(); |
| cotigac | 18:b02fc0e53df8 | 489 | PhyTimeReadClock( (uint32_t*)&time ); |
| cotigac | 18:b02fc0e53df8 | 490 | time |= (gPhyTimerOverflow << gPhyTimeShift_c); |
| cotigac | 18:b02fc0e53df8 | 491 | __enable_irq(); |
| cotigac | 18:b02fc0e53df8 | 492 | |
| cotigac | 18:b02fc0e53df8 | 493 | return time; |
| cotigac | 18:b02fc0e53df8 | 494 | } |
| cotigac | 18:b02fc0e53df8 | 495 | |
| cotigac | 18:b02fc0e53df8 | 496 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 497 | * \brief Schedules an event |
| cotigac | 18:b02fc0e53df8 | 498 | * |
| cotigac | 18:b02fc0e53df8 | 499 | * \param[in] pEvent event to be scheduled |
| cotigac | 18:b02fc0e53df8 | 500 | * |
| cotigac | 18:b02fc0e53df8 | 501 | * \return phyTimeTimerId_t the id of the alocated timer |
| cotigac | 18:b02fc0e53df8 | 502 | * |
| cotigac | 18:b02fc0e53df8 | 503 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 504 | phyTimeTimerId_t PhyTime_ScheduleEvent( phyTimeEvent_t *pEvent ) |
| cotigac | 18:b02fc0e53df8 | 505 | { |
| cotigac | 18:b02fc0e53df8 | 506 | phyTimeTimerId_t tmr; |
| cotigac | 18:b02fc0e53df8 | 507 | |
| cotigac | 18:b02fc0e53df8 | 508 | /* Parameter validation */ |
| cotigac | 18:b02fc0e53df8 | 509 | if( NULL == pEvent->callback ) |
| cotigac | 18:b02fc0e53df8 | 510 | { |
| cotigac | 18:b02fc0e53df8 | 511 | return gInvalidTimerId_c; |
| cotigac | 18:b02fc0e53df8 | 512 | } |
| cotigac | 18:b02fc0e53df8 | 513 | |
| cotigac | 18:b02fc0e53df8 | 514 | /* Search for a free slot (slot 0 is reserved for the Overflow calback) */ |
| cotigac | 18:b02fc0e53df8 | 515 | __disable_irq(); |
| cotigac | 18:b02fc0e53df8 | 516 | for( tmr=1; tmr<gMaxPhyTimers_c; tmr++ ) |
| cotigac | 18:b02fc0e53df8 | 517 | { |
| cotigac | 18:b02fc0e53df8 | 518 | if( mPhyTimers[tmr].callback == NULL ) |
| cotigac | 18:b02fc0e53df8 | 519 | { |
| cotigac | 18:b02fc0e53df8 | 520 | mPhyTimers[tmr] = *pEvent; |
| cotigac | 18:b02fc0e53df8 | 521 | break; |
| cotigac | 18:b02fc0e53df8 | 522 | } |
| cotigac | 18:b02fc0e53df8 | 523 | } |
| cotigac | 18:b02fc0e53df8 | 524 | __enable_irq(); |
| cotigac | 18:b02fc0e53df8 | 525 | |
| cotigac | 18:b02fc0e53df8 | 526 | if( tmr >= gMaxPhyTimers_c ) |
| cotigac | 18:b02fc0e53df8 | 527 | return gInvalidTimerId_c; |
| cotigac | 18:b02fc0e53df8 | 528 | |
| cotigac | 18:b02fc0e53df8 | 529 | /* Program the next event */ |
| cotigac | 18:b02fc0e53df8 | 530 | if((NULL == pNextEvent) || |
| cotigac | 18:b02fc0e53df8 | 531 | (NULL != pNextEvent && mPhyTimers[tmr].timestamp < pNextEvent->timestamp)) |
| cotigac | 18:b02fc0e53df8 | 532 | { |
| cotigac | 18:b02fc0e53df8 | 533 | PhyTime_Maintenance(); |
| cotigac | 18:b02fc0e53df8 | 534 | } |
| cotigac | 18:b02fc0e53df8 | 535 | |
| cotigac | 18:b02fc0e53df8 | 536 | return tmr; |
| cotigac | 18:b02fc0e53df8 | 537 | } |
| cotigac | 18:b02fc0e53df8 | 538 | |
| cotigac | 18:b02fc0e53df8 | 539 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 540 | * \brief Cancel an event |
| cotigac | 18:b02fc0e53df8 | 541 | * |
| cotigac | 18:b02fc0e53df8 | 542 | * \param[in] timerId the Id of the timer |
| cotigac | 18:b02fc0e53df8 | 543 | * |
| cotigac | 18:b02fc0e53df8 | 544 | * \return phyTimeStatus_t |
| cotigac | 18:b02fc0e53df8 | 545 | * |
| cotigac | 18:b02fc0e53df8 | 546 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 547 | phyTimeStatus_t PhyTime_CancelEvent( phyTimeTimerId_t timerId ) |
| cotigac | 18:b02fc0e53df8 | 548 | { |
| cotigac | 18:b02fc0e53df8 | 549 | if( (timerId == 0) || (timerId >= gMaxPhyTimers_c) || (NULL == mPhyTimers[timerId].callback) ) |
| cotigac | 18:b02fc0e53df8 | 550 | { |
| cotigac | 18:b02fc0e53df8 | 551 | return gPhyTimeNotFound_c; |
| cotigac | 18:b02fc0e53df8 | 552 | } |
| cotigac | 18:b02fc0e53df8 | 553 | |
| cotigac | 18:b02fc0e53df8 | 554 | __disable_irq(); |
| cotigac | 18:b02fc0e53df8 | 555 | if( pNextEvent == &mPhyTimers[timerId] ) |
| cotigac | 18:b02fc0e53df8 | 556 | pNextEvent = NULL; |
| cotigac | 18:b02fc0e53df8 | 557 | |
| cotigac | 18:b02fc0e53df8 | 558 | mPhyTimers[timerId].callback = NULL; |
| cotigac | 18:b02fc0e53df8 | 559 | __enable_irq(); |
| cotigac | 18:b02fc0e53df8 | 560 | |
| cotigac | 18:b02fc0e53df8 | 561 | return gPhyTimeOk_c; |
| cotigac | 18:b02fc0e53df8 | 562 | } |
| cotigac | 18:b02fc0e53df8 | 563 | |
| cotigac | 18:b02fc0e53df8 | 564 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 565 | * \brief Cancel all event with the specified paameter |
| cotigac | 18:b02fc0e53df8 | 566 | * |
| cotigac | 18:b02fc0e53df8 | 567 | * \param[in] param event parameter |
| cotigac | 18:b02fc0e53df8 | 568 | * |
| cotigac | 18:b02fc0e53df8 | 569 | * \return phyTimeStatus_t |
| cotigac | 18:b02fc0e53df8 | 570 | * |
| cotigac | 18:b02fc0e53df8 | 571 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 572 | phyTimeStatus_t PhyTime_CancelEventsWithParam ( uint32_t param ) |
| cotigac | 18:b02fc0e53df8 | 573 | { |
| cotigac | 18:b02fc0e53df8 | 574 | uint32_t i; |
| cotigac | 18:b02fc0e53df8 | 575 | phyTimeStatus_t status = gPhyTimeNotFound_c; |
| cotigac | 18:b02fc0e53df8 | 576 | |
| cotigac | 18:b02fc0e53df8 | 577 | __disable_irq(); |
| cotigac | 18:b02fc0e53df8 | 578 | for( i=1; i<gMaxPhyTimers_c; i++ ) |
| cotigac | 18:b02fc0e53df8 | 579 | { |
| cotigac | 18:b02fc0e53df8 | 580 | if( mPhyTimers[i].callback && (param == mPhyTimers[i].parameter) ) |
| cotigac | 18:b02fc0e53df8 | 581 | { |
| cotigac | 18:b02fc0e53df8 | 582 | status = gPhyTimeOk_c; |
| cotigac | 18:b02fc0e53df8 | 583 | mPhyTimers[i].callback = NULL; |
| cotigac | 18:b02fc0e53df8 | 584 | if( pNextEvent == &mPhyTimers[i] ) |
| cotigac | 18:b02fc0e53df8 | 585 | pNextEvent = NULL; |
| cotigac | 18:b02fc0e53df8 | 586 | } |
| cotigac | 18:b02fc0e53df8 | 587 | } |
| cotigac | 18:b02fc0e53df8 | 588 | __enable_irq(); |
| cotigac | 18:b02fc0e53df8 | 589 | |
| cotigac | 18:b02fc0e53df8 | 590 | return status; |
| cotigac | 18:b02fc0e53df8 | 591 | } |
| cotigac | 18:b02fc0e53df8 | 592 | |
| cotigac | 18:b02fc0e53df8 | 593 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 594 | * \brief Run the callback for the recently expired event |
| cotigac | 18:b02fc0e53df8 | 595 | * |
| cotigac | 18:b02fc0e53df8 | 596 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 597 | void PhyTime_RunCallback( void ) |
| cotigac | 18:b02fc0e53df8 | 598 | { |
| cotigac | 18:b02fc0e53df8 | 599 | uint32_t param; |
| cotigac | 18:b02fc0e53df8 | 600 | phyTimeCallback_t cb; |
| cotigac | 18:b02fc0e53df8 | 601 | |
| cotigac | 18:b02fc0e53df8 | 602 | if( pNextEvent ) |
| cotigac | 18:b02fc0e53df8 | 603 | { |
| cotigac | 18:b02fc0e53df8 | 604 | __disable_irq(); |
| cotigac | 18:b02fc0e53df8 | 605 | |
| cotigac | 18:b02fc0e53df8 | 606 | param = pNextEvent->parameter; |
| cotigac | 18:b02fc0e53df8 | 607 | cb = pNextEvent->callback; |
| cotigac | 18:b02fc0e53df8 | 608 | pNextEvent->callback = NULL; |
| cotigac | 18:b02fc0e53df8 | 609 | pNextEvent = NULL; |
| cotigac | 18:b02fc0e53df8 | 610 | |
| cotigac | 18:b02fc0e53df8 | 611 | __enable_irq(); |
| cotigac | 18:b02fc0e53df8 | 612 | |
| cotigac | 18:b02fc0e53df8 | 613 | cb(param); |
| cotigac | 18:b02fc0e53df8 | 614 | } |
| cotigac | 18:b02fc0e53df8 | 615 | } |
| cotigac | 18:b02fc0e53df8 | 616 | |
| cotigac | 18:b02fc0e53df8 | 617 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 618 | * \brief Expire events too close to be scheduled. |
| cotigac | 18:b02fc0e53df8 | 619 | * Program the next event |
| cotigac | 18:b02fc0e53df8 | 620 | * |
| cotigac | 18:b02fc0e53df8 | 621 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 622 | void PhyTime_Maintenance( void ) |
| cotigac | 18:b02fc0e53df8 | 623 | { |
| cotigac | 18:b02fc0e53df8 | 624 | phyTimeTimestamp_t currentTime; |
| cotigac | 18:b02fc0e53df8 | 625 | phyTimeEvent_t *pEv; |
| cotigac | 18:b02fc0e53df8 | 626 | |
| cotigac | 18:b02fc0e53df8 | 627 | PhyTimeDisableWaitTimeout(); |
| cotigac | 18:b02fc0e53df8 | 628 | |
| cotigac | 18:b02fc0e53df8 | 629 | while(1) |
| cotigac | 18:b02fc0e53df8 | 630 | { |
| cotigac | 18:b02fc0e53df8 | 631 | __disable_irq(); |
| cotigac | 18:b02fc0e53df8 | 632 | |
| cotigac | 18:b02fc0e53df8 | 633 | pEv = PhyTime_GetNextEvent(); |
| cotigac | 18:b02fc0e53df8 | 634 | currentTime = PhyTime_GetTimestamp(); |
| cotigac | 18:b02fc0e53df8 | 635 | |
| cotigac | 18:b02fc0e53df8 | 636 | /* Program next event if exists */ |
| cotigac | 18:b02fc0e53df8 | 637 | if( pEv ) |
| cotigac | 18:b02fc0e53df8 | 638 | { |
| cotigac | 18:b02fc0e53df8 | 639 | pNextEvent = pEv; |
| cotigac | 18:b02fc0e53df8 | 640 | |
| cotigac | 18:b02fc0e53df8 | 641 | if( pEv->timestamp > (currentTime + gPhyTimeMinSetupTime_c) ) |
| cotigac | 18:b02fc0e53df8 | 642 | { |
| cotigac | 18:b02fc0e53df8 | 643 | PhyTimeSetWaitTimeout( (uint32_t*)&pEv->timestamp ); |
| cotigac | 18:b02fc0e53df8 | 644 | pEv = NULL; |
| cotigac | 18:b02fc0e53df8 | 645 | } |
| cotigac | 18:b02fc0e53df8 | 646 | } |
| cotigac | 18:b02fc0e53df8 | 647 | |
| cotigac | 18:b02fc0e53df8 | 648 | __enable_irq(); |
| cotigac | 18:b02fc0e53df8 | 649 | |
| cotigac | 18:b02fc0e53df8 | 650 | if( !pEv ) |
| cotigac | 18:b02fc0e53df8 | 651 | break; |
| cotigac | 18:b02fc0e53df8 | 652 | |
| cotigac | 18:b02fc0e53df8 | 653 | PhyTime_RunCallback(); |
| cotigac | 18:b02fc0e53df8 | 654 | } |
| cotigac | 18:b02fc0e53df8 | 655 | |
| cotigac | 18:b02fc0e53df8 | 656 | } |
| cotigac | 18:b02fc0e53df8 | 657 | |
| cotigac | 18:b02fc0e53df8 | 658 | |
| cotigac | 18:b02fc0e53df8 | 659 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 660 | * \brief Timer Overflow callback |
| cotigac | 18:b02fc0e53df8 | 661 | * |
| cotigac | 18:b02fc0e53df8 | 662 | * \param[in] param |
| cotigac | 18:b02fc0e53df8 | 663 | * |
| cotigac | 18:b02fc0e53df8 | 664 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 665 | static void PhyTime_OverflowCB( uint32_t param ) |
| cotigac | 18:b02fc0e53df8 | 666 | { |
| cotigac | 18:b02fc0e53df8 | 667 | (void)param; |
| cotigac | 18:b02fc0e53df8 | 668 | |
| cotigac | 18:b02fc0e53df8 | 669 | /* Reprogram the next overflow callback */ |
| cotigac | 18:b02fc0e53df8 | 670 | mPhyTimers[0].callback = PhyTime_OverflowCB; |
| cotigac | 18:b02fc0e53df8 | 671 | mPhyTimers[0].timestamp = (gPhyTimerOverflow+1) << 24; |
| cotigac | 18:b02fc0e53df8 | 672 | } |
| cotigac | 18:b02fc0e53df8 | 673 | |
| cotigac | 18:b02fc0e53df8 | 674 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 675 | * \brief Search for the next event to be scheduled |
| cotigac | 18:b02fc0e53df8 | 676 | * |
| cotigac | 18:b02fc0e53df8 | 677 | * \return phyTimeEvent_t pointer to the next event to be scheduled |
| cotigac | 18:b02fc0e53df8 | 678 | * |
| cotigac | 18:b02fc0e53df8 | 679 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 680 | static phyTimeEvent_t* PhyTime_GetNextEvent( void ) |
| cotigac | 18:b02fc0e53df8 | 681 | { |
| cotigac | 18:b02fc0e53df8 | 682 | phyTimeEvent_t *pEv = NULL; |
| cotigac | 18:b02fc0e53df8 | 683 | uint32_t i; |
| cotigac | 18:b02fc0e53df8 | 684 | |
| cotigac | 18:b02fc0e53df8 | 685 | /* Search for the next event to be serviced */ |
| cotigac | 18:b02fc0e53df8 | 686 | for( i=0; i<gMaxPhyTimers_c; i++ ) |
| cotigac | 18:b02fc0e53df8 | 687 | { |
| cotigac | 18:b02fc0e53df8 | 688 | if( NULL != mPhyTimers[i].callback ) |
| cotigac | 18:b02fc0e53df8 | 689 | { |
| cotigac | 18:b02fc0e53df8 | 690 | if( NULL == pEv ) |
| cotigac | 18:b02fc0e53df8 | 691 | { |
| cotigac | 18:b02fc0e53df8 | 692 | pEv = &mPhyTimers[i]; |
| cotigac | 18:b02fc0e53df8 | 693 | } |
| cotigac | 18:b02fc0e53df8 | 694 | /* Check which event expires first */ |
| cotigac | 18:b02fc0e53df8 | 695 | else if( mPhyTimers[i].timestamp < pEv->timestamp ) |
| cotigac | 18:b02fc0e53df8 | 696 | { |
| cotigac | 18:b02fc0e53df8 | 697 | pEv = &mPhyTimers[i]; |
| cotigac | 18:b02fc0e53df8 | 698 | } |
| cotigac | 18:b02fc0e53df8 | 699 | } |
| cotigac | 18:b02fc0e53df8 | 700 | } |
| cotigac | 18:b02fc0e53df8 | 701 | |
| cotigac | 18:b02fc0e53df8 | 702 | return pEv; |
| cotigac | 18:b02fc0e53df8 | 703 | } |
| cotigac | 18:b02fc0e53df8 | 704 |