NXP / Mbed 2 deprecated mcr20_wireless_uart

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Dependencies:   fsl_phy_mcr20a fsl_smac mbed-rtos mbed

Fork of mcr20_wireless_uart by Freescale

By default, the application uses broadcast addresses for OTA communication. This way, the application can be directly downloaded and run without any user intervention. The following use case assumes no changes have been done to the project.

  • Two (or more) MCR20A platforms (plugged into the FRDM-K64F Freescale Freedom Development platform) have to be connected to the PC using the mini/micro-USB cables.
  • The code must be downloaded on the platforms via CMSIS-DAP (or other means).
  • After that, two or more TERM applications must be opened, and the serial ports must be configured with the same baud rate as the one in the project (default baud rate is 115200). Other necessary serial configurations are 8 bit, no parity, and 1 stop bit.
  • To start the setup, each platform must be reset, and one of the (user) push buttons found on the MCR20A platform must be pressed. The user can press any of the non-reset buttons on the FRDM-K64F Freescale Freedom Development platform as well. *This initiates the state machine of the application so user can start.

Documentation

SMAC Demo Applications User Guide

RF_Drivers_Freescale/MCR20Drv/MCR20Drv.h@15:990a8b5664e1, 2015-03-15 (annotated)

Committer:
FSL\B36402
Date:
Sun Mar 15 00:56:28 2015 -0500
Revision:
15:990a8b5664e1
Parent:
13:4fa8e504061f 
Integrated PHY version from the official K64F+MCR20A package

Who changed what in which revision?

UserRevisionLine numberNew contents of line
FSL\B36402 5:69f1634cd40b 1 /*!
FSL\B36402 5:69f1634cd40b 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
FSL\B36402 5:69f1634cd40b 3 * All rights reserved.
FSL\B36402 5:69f1634cd40b 4 *
FSL\B36402 5:69f1634cd40b 5 * \file MCR20Drv.h
FSL\B36402 5:69f1634cd40b 6 *
FSL\B36402 5:69f1634cd40b 7 * Redistribution and use in source and binary forms, with or without modification,
FSL\B36402 5:69f1634cd40b 8 * are permitted provided that the following conditions are met:
FSL\B36402 5:69f1634cd40b 9 *
FSL\B36402 5:69f1634cd40b 10 * o Redistributions of source code must retain the above copyright notice, this list
FSL\B36402 5:69f1634cd40b 11 * of conditions and the following disclaimer.
FSL\B36402 5:69f1634cd40b 12 *
FSL\B36402 5:69f1634cd40b 13 * o Redistributions in binary form must reproduce the above copyright notice, this
FSL\B36402 5:69f1634cd40b 14 * list of conditions and the following disclaimer in the documentation and/or
FSL\B36402 5:69f1634cd40b 15 * other materials provided with the distribution.
FSL\B36402 5:69f1634cd40b 16 *
FSL\B36402 5:69f1634cd40b 17 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
FSL\B36402 5:69f1634cd40b 18 * contributors may be used to endorse or promote products derived from this
FSL\B36402 5:69f1634cd40b 19 * software without specific prior written permission.
FSL\B36402 5:69f1634cd40b 20 *
FSL\B36402 5:69f1634cd40b 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
FSL\B36402 5:69f1634cd40b 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
FSL\B36402 5:69f1634cd40b 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
FSL\B36402 5:69f1634cd40b 24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
FSL\B36402 5:69f1634cd40b 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
FSL\B36402 5:69f1634cd40b 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
FSL\B36402 5:69f1634cd40b 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
FSL\B36402 5:69f1634cd40b 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
FSL\B36402 5:69f1634cd40b 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
FSL\B36402 5:69f1634cd40b 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
FSL\B36402 5:69f1634cd40b 31 */
FSL\B36402 5:69f1634cd40b 32
FSL\B36402 5:69f1634cd40b 33 #ifndef __MCR20_DRV_H__
FSL\B36402 5:69f1634cd40b 34 #define __MCR20_DRV_H__
FSL\B36402 5:69f1634cd40b 35
FSL\B36402 5:69f1634cd40b 36
FSL\B36402 5:69f1634cd40b 37 /*****************************************************************************
FSL\B36402 5:69f1634cd40b 38 * INCLUDED HEADERS *
FSL\B36402 5:69f1634cd40b 39 *---------------------------------------------------------------------------*
FSL\B36402 5:69f1634cd40b 40 * Add to this section all the headers that this module needs to include. *
FSL\B36402 5:69f1634cd40b 41 * Note that it is not a good practice to include header files into header *
FSL\B36402 5:69f1634cd40b 42 * files, so use this section only if there is no other better solution. *
FSL\B36402 5:69f1634cd40b 43 *---------------------------------------------------------------------------*
FSL\B36402 5:69f1634cd40b 44 *****************************************************************************/
FSL\B36402 5:69f1634cd40b 45
FSL\B36402 15:990a8b5664e1 46 #include "EmbeddedTypes.h"
FSL\B36402 5:69f1634cd40b 47
FSL\B36402 5:69f1634cd40b 48 /*****************************************************************************
FSL\B36402 5:69f1634cd40b 49 * PRIVATE MACROS *
FSL\B36402 5:69f1634cd40b 50 *---------------------------------------------------------------------------*
FSL\B36402 5:69f1634cd40b 51 * Add to this section all the access macros, registers mappings, bit access *
FSL\B36402 5:69f1634cd40b 52 * macros, masks, flags etc ...
FSL\B36402 5:69f1634cd40b 53 *---------------------------------------------------------------------------*
FSL\B36402 5:69f1634cd40b 54 *****************************************************************************/
FSL\B36402 5:69f1634cd40b 55 #ifndef gMCR20_ClkOutFreq_d
FSL\B36402 5:69f1634cd40b 56 #define gMCR20_ClkOutFreq_d gCLK_OUT_FREQ_4_MHz
FSL\B36402 5:69f1634cd40b 57 #endif
FSL\B36402 5:69f1634cd40b 58
FSL\B36402 5:69f1634cd40b 59 /*****************************************************************************
FSL\B36402 5:69f1634cd40b 60 * PUBLIC FUNCTIONS *
FSL\B36402 5:69f1634cd40b 61 *---------------------------------------------------------------------------*
FSL\B36402 5:69f1634cd40b 62 * Add to this section all the global functions prototype preceded (as a *
FSL\B36402 5:69f1634cd40b 63 * good practice) by the keyword 'extern' *
FSL\B36402 5:69f1634cd40b 64 *---------------------------------------------------------------------------*
FSL\B36402 5:69f1634cd40b 65 *****************************************************************************/
FSL\B36402 5:69f1634cd40b 66
FSL\B36402 5:69f1634cd40b 67 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 68 * Name: MCR20Drv_Init
FSL\B36402 5:69f1634cd40b 69 * Description: -
FSL\B36402 5:69f1634cd40b 70 * Parameters: -
FSL\B36402 5:69f1634cd40b 71 * Return: -
FSL\B36402 5:69f1634cd40b 72 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 73 extern void MCR20Drv_Init
FSL\B36402 5:69f1634cd40b 74 (
FSL\B36402 5:69f1634cd40b 75 void
FSL\B36402 5:69f1634cd40b 76 );
FSL\B36402 5:69f1634cd40b 77
FSL\B36402 5:69f1634cd40b 78 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 79 * Name: MCR20Drv_SPI_DMA_Init
FSL\B36402 5:69f1634cd40b 80 * Description: -
FSL\B36402 5:69f1634cd40b 81 * Parameters: -
FSL\B36402 5:69f1634cd40b 82 * Return: -
FSL\B36402 5:69f1634cd40b 83 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 84 void MCR20Drv_SPI_DMA_Init
FSL\B36402 5:69f1634cd40b 85 (
FSL\B36402 5:69f1634cd40b 86 void
FSL\B36402 5:69f1634cd40b 87 );
FSL\B36402 5:69f1634cd40b 88
FSL\B36402 5:69f1634cd40b 89 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 90 * Name: MCR20Drv_Start_PB_DMA_SPI_Write
FSL\B36402 5:69f1634cd40b 91 * Description: -
FSL\B36402 5:69f1634cd40b 92 * Parameters: -
FSL\B36402 5:69f1634cd40b 93 * Return: -
FSL\B36402 5:69f1634cd40b 94 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 95 void MCR20Drv_Start_PB_DMA_SPI_Write
FSL\B36402 5:69f1634cd40b 96 (
FSL\B36402 5:69f1634cd40b 97 uint8_t * srcAddress,
FSL\B36402 5:69f1634cd40b 98 uint8_t numOfBytes
FSL\B36402 5:69f1634cd40b 99 );
FSL\B36402 5:69f1634cd40b 100
FSL\B36402 5:69f1634cd40b 101 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 102 * Name: MCR20Drv_Start_PB_DMA_SPI_Read
FSL\B36402 5:69f1634cd40b 103 * Description: -
FSL\B36402 5:69f1634cd40b 104 * Parameters: -
FSL\B36402 5:69f1634cd40b 105 * Return: -
FSL\B36402 5:69f1634cd40b 106 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 107 void MCR20Drv_Start_PB_DMA_SPI_Read
FSL\B36402 5:69f1634cd40b 108 (
FSL\B36402 5:69f1634cd40b 109 uint8_t * dstAddress,
FSL\B36402 5:69f1634cd40b 110 uint8_t numOfBytes
FSL\B36402 5:69f1634cd40b 111 );
FSL\B36402 5:69f1634cd40b 112
FSL\B36402 5:69f1634cd40b 113 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 114 * Name: MCR20Drv_DirectAccessSPIWrite
FSL\B36402 5:69f1634cd40b 115 * Description: -
FSL\B36402 5:69f1634cd40b 116 * Parameters: -
FSL\B36402 5:69f1634cd40b 117 * Return: -
FSL\B36402 5:69f1634cd40b 118 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 119 void MCR20Drv_DirectAccessSPIWrite
FSL\B36402 5:69f1634cd40b 120 (
FSL\B36402 5:69f1634cd40b 121 uint8_t address,
FSL\B36402 5:69f1634cd40b 122 uint8_t value
FSL\B36402 5:69f1634cd40b 123 );
FSL\B36402 5:69f1634cd40b 124
FSL\B36402 5:69f1634cd40b 125 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 126 * Name: MCR20Drv_DirectAccessSPIMultiByteWrite
FSL\B36402 5:69f1634cd40b 127 * Description: -
FSL\B36402 5:69f1634cd40b 128 * Parameters: -
FSL\B36402 5:69f1634cd40b 129 * Return: -
FSL\B36402 5:69f1634cd40b 130 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 131 void MCR20Drv_DirectAccessSPIMultiByteWrite
FSL\B36402 5:69f1634cd40b 132 (
FSL\B36402 5:69f1634cd40b 133 uint8_t startAddress,
FSL\B36402 5:69f1634cd40b 134 uint8_t * byteArray,
FSL\B36402 5:69f1634cd40b 135 uint8_t numOfBytes
FSL\B36402 5:69f1634cd40b 136 );
FSL\B36402 5:69f1634cd40b 137
FSL\B36402 5:69f1634cd40b 138 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 139 * Name: MCR20Drv_PB_SPIBurstWrite
FSL\B36402 5:69f1634cd40b 140 * Description: -
FSL\B36402 5:69f1634cd40b 141 * Parameters: -
FSL\B36402 5:69f1634cd40b 142 * Return: -
FSL\B36402 5:69f1634cd40b 143 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 144 void MCR20Drv_PB_SPIBurstWrite
FSL\B36402 5:69f1634cd40b 145 (
FSL\B36402 5:69f1634cd40b 146 uint8_t * byteArray,
FSL\B36402 5:69f1634cd40b 147 uint8_t numOfBytes
FSL\B36402 5:69f1634cd40b 148 );
FSL\B36402 5:69f1634cd40b 149
FSL\B36402 5:69f1634cd40b 150 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 151 * Name: MCR20Drv_DirectAccessSPIRead
FSL\B36402 5:69f1634cd40b 152 * Description: -
FSL\B36402 5:69f1634cd40b 153 * Parameters: -
FSL\B36402 5:69f1634cd40b 154 * Return: -
FSL\B36402 5:69f1634cd40b 155 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 156 uint8_t MCR20Drv_DirectAccessSPIRead
FSL\B36402 5:69f1634cd40b 157 (
FSL\B36402 5:69f1634cd40b 158 uint8_t address
FSL\B36402 5:69f1634cd40b 159 );
FSL\B36402 5:69f1634cd40b 160
FSL\B36402 5:69f1634cd40b 161 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 162 * Name: MCR20Drv_DirectAccessSPIMultyByteRead
FSL\B36402 5:69f1634cd40b 163 * Description: -
FSL\B36402 5:69f1634cd40b 164 * Parameters: -
FSL\B36402 5:69f1634cd40b 165 * Return: -
FSL\B36402 5:69f1634cd40b 166 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 167
FSL\B36402 5:69f1634cd40b 168 uint8_t MCR20Drv_DirectAccessSPIMultiByteRead
FSL\B36402 5:69f1634cd40b 169 (
FSL\B36402 5:69f1634cd40b 170 uint8_t startAddress,
FSL\B36402 5:69f1634cd40b 171 uint8_t * byteArray,
FSL\B36402 5:69f1634cd40b 172 uint8_t numOfBytes
FSL\B36402 5:69f1634cd40b 173 );
FSL\B36402 5:69f1634cd40b 174
FSL\B36402 5:69f1634cd40b 175 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 176 * Name: MCR20Drv_PB_SPIByteWrite
FSL\B36402 5:69f1634cd40b 177 * Description: -
FSL\B36402 5:69f1634cd40b 178 * Parameters: -
FSL\B36402 5:69f1634cd40b 179 * Return: -
FSL\B36402 5:69f1634cd40b 180 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 181 void MCR20Drv_PB_SPIByteWrite
FSL\B36402 5:69f1634cd40b 182 (
FSL\B36402 5:69f1634cd40b 183 uint8_t address,
FSL\B36402 5:69f1634cd40b 184 uint8_t value
FSL\B36402 5:69f1634cd40b 185 );
FSL\B36402 5:69f1634cd40b 186
FSL\B36402 5:69f1634cd40b 187 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 188 * Name: MCR20Drv_PB_SPIBurstRead
FSL\B36402 5:69f1634cd40b 189 * Description: -
FSL\B36402 5:69f1634cd40b 190 * Parameters: -
FSL\B36402 5:69f1634cd40b 191 * Return: -
FSL\B36402 5:69f1634cd40b 192 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 193 uint8_t MCR20Drv_PB_SPIBurstRead
FSL\B36402 5:69f1634cd40b 194 (
FSL\B36402 5:69f1634cd40b 195 uint8_t * byteArray,
FSL\B36402 5:69f1634cd40b 196 uint8_t numOfBytes
FSL\B36402 5:69f1634cd40b 197 );
FSL\B36402 5:69f1634cd40b 198
FSL\B36402 5:69f1634cd40b 199 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 200 * Name: MCR20Drv_IndirectAccessSPIWrite
FSL\B36402 5:69f1634cd40b 201 * Description: -
FSL\B36402 5:69f1634cd40b 202 * Parameters: -
FSL\B36402 5:69f1634cd40b 203 * Return: -
FSL\B36402 5:69f1634cd40b 204 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 205 void MCR20Drv_IndirectAccessSPIWrite
FSL\B36402 5:69f1634cd40b 206 (
FSL\B36402 5:69f1634cd40b 207 uint8_t address,
FSL\B36402 5:69f1634cd40b 208 uint8_t value
FSL\B36402 5:69f1634cd40b 209 );
FSL\B36402 5:69f1634cd40b 210
FSL\B36402 5:69f1634cd40b 211 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 212 * Name: MCR20Drv_IndirectAccessSPIMultiByteWrite
FSL\B36402 5:69f1634cd40b 213 * Description: -
FSL\B36402 5:69f1634cd40b 214 * Parameters: -
FSL\B36402 5:69f1634cd40b 215 * Return: -
FSL\B36402 5:69f1634cd40b 216 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 217 void MCR20Drv_IndirectAccessSPIMultiByteWrite
FSL\B36402 5:69f1634cd40b 218 (
FSL\B36402 5:69f1634cd40b 219 uint8_t startAddress,
FSL\B36402 5:69f1634cd40b 220 uint8_t * byteArray,
FSL\B36402 5:69f1634cd40b 221 uint8_t numOfBytes
FSL\B36402 5:69f1634cd40b 222 );
FSL\B36402 5:69f1634cd40b 223
FSL\B36402 5:69f1634cd40b 224 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 225 * Name: MCR20Drv_IndirectAccessSPIRead
FSL\B36402 5:69f1634cd40b 226 * Description: -
FSL\B36402 5:69f1634cd40b 227 * Parameters: -
FSL\B36402 5:69f1634cd40b 228 * Return: -
FSL\B36402 5:69f1634cd40b 229 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 230 uint8_t MCR20Drv_IndirectAccessSPIRead
FSL\B36402 5:69f1634cd40b 231 (
FSL\B36402 5:69f1634cd40b 232 uint8_t address
FSL\B36402 5:69f1634cd40b 233 );
FSL\B36402 5:69f1634cd40b 234 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 235 * Name: MCR20Drv_IndirectAccessSPIMultiByteRead
FSL\B36402 5:69f1634cd40b 236 * Description: -
FSL\B36402 5:69f1634cd40b 237 * Parameters: -
FSL\B36402 5:69f1634cd40b 238 * Return: -
FSL\B36402 5:69f1634cd40b 239 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 240 void MCR20Drv_IndirectAccessSPIMultiByteRead
FSL\B36402 5:69f1634cd40b 241 (
FSL\B36402 5:69f1634cd40b 242 uint8_t startAddress,
FSL\B36402 5:69f1634cd40b 243 uint8_t * byteArray,
FSL\B36402 5:69f1634cd40b 244 uint8_t numOfBytes
FSL\B36402 5:69f1634cd40b 245 );
FSL\B36402 5:69f1634cd40b 246
FSL\B36402 5:69f1634cd40b 247 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 248 * Name: MCR20Drv_IRQ_PortConfig
FSL\B36402 5:69f1634cd40b 249 * Description: -
FSL\B36402 5:69f1634cd40b 250 * Parameters: -
FSL\B36402 5:69f1634cd40b 251 * Return: -
FSL\B36402 5:69f1634cd40b 252 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 253 void MCR20Drv_IRQ_PortConfig
FSL\B36402 5:69f1634cd40b 254 (
FSL\B36402 5:69f1634cd40b 255 void
FSL\B36402 5:69f1634cd40b 256 );
FSL\B36402 5:69f1634cd40b 257
FSL\B36402 5:69f1634cd40b 258 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 259 * Name: MCR20Drv_IsIrqPending
FSL\B36402 5:69f1634cd40b 260 * Description: -
FSL\B36402 5:69f1634cd40b 261 * Parameters: -
FSL\B36402 5:69f1634cd40b 262 * Return: -
FSL\B36402 5:69f1634cd40b 263 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 264 uint32_t MCR20Drv_IsIrqPending
FSL\B36402 5:69f1634cd40b 265 (
FSL\B36402 5:69f1634cd40b 266 void
FSL\B36402 5:69f1634cd40b 267 );
FSL\B36402 5:69f1634cd40b 268
FSL\B36402 5:69f1634cd40b 269 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 270 * Name: MCR20Drv_IRQ_Disable
FSL\B36402 5:69f1634cd40b 271 * Description: -
FSL\B36402 5:69f1634cd40b 272 * Parameters: -
FSL\B36402 5:69f1634cd40b 273 * Return: -
FSL\B36402 5:69f1634cd40b 274 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 275 void MCR20Drv_IRQ_Disable
FSL\B36402 5:69f1634cd40b 276 (
FSL\B36402 5:69f1634cd40b 277 void
FSL\B36402 5:69f1634cd40b 278 );
FSL\B36402 5:69f1634cd40b 279
FSL\B36402 5:69f1634cd40b 280 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 281 * Name: MCR20Drv_IRQ_Enable
FSL\B36402 5:69f1634cd40b 282 * Description: -
FSL\B36402 5:69f1634cd40b 283 * Parameters: -
FSL\B36402 5:69f1634cd40b 284 * Return: -
FSL\B36402 5:69f1634cd40b 285 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 286 void MCR20Drv_IRQ_Enable
FSL\B36402 5:69f1634cd40b 287 (
FSL\B36402 5:69f1634cd40b 288 void
FSL\B36402 5:69f1634cd40b 289 );
FSL\B36402 5:69f1634cd40b 290
FSL\B36402 5:69f1634cd40b 291 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 292 * Name: MCR20Drv_IRQ_IsEnabled
FSL\B36402 5:69f1634cd40b 293 * Description: -
FSL\B36402 5:69f1634cd40b 294 * Parameters: -
FSL\B36402 5:69f1634cd40b 295 * Return: -
FSL\B36402 5:69f1634cd40b 296 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 297 uint32_t MCR20Drv_IRQ_IsEnabled
FSL\B36402 5:69f1634cd40b 298 (
FSL\B36402 5:69f1634cd40b 299 void
FSL\B36402 5:69f1634cd40b 300 );
FSL\B36402 5:69f1634cd40b 301
FSL\B36402 5:69f1634cd40b 302 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 303 * Name: MCR20Drv_IRQ_Clear
FSL\B36402 5:69f1634cd40b 304 * Description: -
FSL\B36402 5:69f1634cd40b 305 * Parameters: -
FSL\B36402 5:69f1634cd40b 306 * Return: -
FSL\B36402 5:69f1634cd40b 307 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 308 void MCR20Drv_IRQ_Clear
FSL\B36402 5:69f1634cd40b 309 (
FSL\B36402 5:69f1634cd40b 310 void
FSL\B36402 5:69f1634cd40b 311 );
FSL\B36402 5:69f1634cd40b 312
FSL\B36402 5:69f1634cd40b 313 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 314 * Name: MCR20Drv_RST_PortConfig
FSL\B36402 5:69f1634cd40b 315 * Description: -
FSL\B36402 5:69f1634cd40b 316 * Parameters: -
FSL\B36402 5:69f1634cd40b 317 * Return: -
FSL\B36402 5:69f1634cd40b 318 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 319 void MCR20Drv_RST_B_PortConfig
FSL\B36402 5:69f1634cd40b 320 (
FSL\B36402 5:69f1634cd40b 321 void
FSL\B36402 5:69f1634cd40b 322 );
FSL\B36402 5:69f1634cd40b 323
FSL\B36402 5:69f1634cd40b 324 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 325 * Name: MCR20Drv_RST_Assert
FSL\B36402 5:69f1634cd40b 326 * Description: -
FSL\B36402 5:69f1634cd40b 327 * Parameters: -
FSL\B36402 5:69f1634cd40b 328 * Return: -
FSL\B36402 5:69f1634cd40b 329 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 330 void MCR20Drv_RST_B_Assert
FSL\B36402 5:69f1634cd40b 331 (
FSL\B36402 5:69f1634cd40b 332 void
FSL\B36402 5:69f1634cd40b 333 );
FSL\B36402 5:69f1634cd40b 334
FSL\B36402 5:69f1634cd40b 335 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 336 * Name: MCR20Drv_RST_Deassert
FSL\B36402 5:69f1634cd40b 337 * Description: -
FSL\B36402 5:69f1634cd40b 338 * Parameters: -
FSL\B36402 5:69f1634cd40b 339 * Return: -
FSL\B36402 5:69f1634cd40b 340 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 341 void MCR20Drv_RST_B_Deassert
FSL\B36402 5:69f1634cd40b 342 (
FSL\B36402 5:69f1634cd40b 343 void
FSL\B36402 5:69f1634cd40b 344 );
FSL\B36402 5:69f1634cd40b 345
FSL\B36402 5:69f1634cd40b 346 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 347 * Name: MCR20Drv_SoftRST_Assert
FSL\B36402 5:69f1634cd40b 348 * Description: -
FSL\B36402 5:69f1634cd40b 349 * Parameters: -
FSL\B36402 5:69f1634cd40b 350 * Return: -
FSL\B36402 5:69f1634cd40b 351 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 352 void MCR20Drv_SoftRST_Assert
FSL\B36402 5:69f1634cd40b 353 (
FSL\B36402 5:69f1634cd40b 354 void
FSL\B36402 5:69f1634cd40b 355 );
FSL\B36402 5:69f1634cd40b 356
FSL\B36402 5:69f1634cd40b 357 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 358 * Name: MCR20Drv_SoftRST_Deassert
FSL\B36402 5:69f1634cd40b 359 * Description: -
FSL\B36402 5:69f1634cd40b 360 * Parameters: -
FSL\B36402 5:69f1634cd40b 361 * Return: -
FSL\B36402 5:69f1634cd40b 362 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 363 void MCR20Drv_SoftRST_Deassert
FSL\B36402 5:69f1634cd40b 364 (
FSL\B36402 5:69f1634cd40b 365 void
FSL\B36402 5:69f1634cd40b 366 );
FSL\B36402 5:69f1634cd40b 367
FSL\B36402 5:69f1634cd40b 368
FSL\B36402 5:69f1634cd40b 369 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 370 * Name: MCR20Drv_RESET
FSL\B36402 5:69f1634cd40b 371 * Description: -
FSL\B36402 5:69f1634cd40b 372 * Parameters: -
FSL\B36402 5:69f1634cd40b 373 * Return: -
FSL\B36402 5:69f1634cd40b 374 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 375 void MCR20Drv_RESET
FSL\B36402 5:69f1634cd40b 376 (
FSL\B36402 5:69f1634cd40b 377 void
FSL\B36402 5:69f1634cd40b 378 );
FSL\B36402 5:69f1634cd40b 379
FSL\B36402 5:69f1634cd40b 380 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 381 * Name: MCR20Drv_Soft_RESET
FSL\B36402 5:69f1634cd40b 382 * Description: -
FSL\B36402 5:69f1634cd40b 383 * Parameters: -
FSL\B36402 5:69f1634cd40b 384 * Return: -
FSL\B36402 5:69f1634cd40b 385 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 386 void MCR20Drv_Soft_RESET
FSL\B36402 5:69f1634cd40b 387 (
FSL\B36402 5:69f1634cd40b 388 void
FSL\B36402 5:69f1634cd40b 389 );
FSL\B36402 5:69f1634cd40b 390
FSL\B36402 5:69f1634cd40b 391 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 392 * Name: MCR20Drv_Set_CLK_OUT_Freq
FSL\B36402 5:69f1634cd40b 393 * Description: -
FSL\B36402 5:69f1634cd40b 394 * Parameters: -
FSL\B36402 5:69f1634cd40b 395 * Return: -
FSL\B36402 5:69f1634cd40b 396 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 397 void MCR20Drv_Set_CLK_OUT_Freq
FSL\B36402 5:69f1634cd40b 398 (
FSL\B36402 5:69f1634cd40b 399 uint8_t freqDiv
FSL\B36402 5:69f1634cd40b 400 );
FSL\B36402 5:69f1634cd40b 401
FSL\B36402 5:69f1634cd40b 402 #define ProtectFromMCR20Interrupt() MCR20Drv_IRQ_Disable()
FSL\B36402 5:69f1634cd40b 403 #define UnprotectFromMCR20Interrupt() MCR20Drv_IRQ_Enable()
FSL\B36402 5:69f1634cd40b 404
FSL\B36402 5:69f1634cd40b 405 #endif /* __MCR20_DRV_H__ */