NXP
The MCR20A Wireless UART application functions as an wireless UART bridge between two (one-to-one) or several (one to many) boards. The application can be used with both a TERM, or with software that is capable of opening a serial port and writing to or reading from it. The characters sent or received are not necessarily ASCII printable characters.
Dependencies: fsl_phy_mcr20a fsl_smac mbed-rtos mbed
Fork of
mcr20_wireless_uart
by 
Freescale
By default, the application uses broadcast addresses for OTA communication. This way, the application can be directly downloaded and run without any user intervention. The following use case assumes no changes have been done to the project.
- Two (or more) MCR20A platforms (plugged into the FRDM-K64F Freescale Freedom Development platform) have to be connected to the PC using the mini/micro-USB cables.
- The code must be downloaded on the platforms via CMSIS-DAP (or other means).
- After that, two or more TERM applications must be opened, and the serial ports must be configured with the same baud rate as the one in the project (default baud rate is 115200). Other necessary serial configurations are 8 bit, no parity, and 1 stop bit.
- To start the setup, each platform must be reset, and one of the (user) push buttons found on the MCR20A platform must be pressed. The user can press any of the non-reset buttons on the FRDM-K64F Freescale Freedom Development platform as well. *This initiates the state machine of the application so user can start.
Documentation
SMAC Demo Applications User Guide
IEEE802_14_5_PHY/PhyISR.c@18:b02fc0e53df8, 2015-04-03 (annotated)
- Committer:
- cotigac
- Date:
- Fri Apr 03 05:23:33 2015 +0000
- Revision:
- 18:b02fc0e53df8
Started creating wireless uart demo based on mbed-rtos
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| cotigac | 18:b02fc0e53df8 | 1 | /*! |
| cotigac | 18:b02fc0e53df8 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
| cotigac | 18:b02fc0e53df8 | 3 | * All rights reserved. |
| cotigac | 18:b02fc0e53df8 | 4 | * |
| cotigac | 18:b02fc0e53df8 | 5 | * \file PhyISR.c |
| cotigac | 18:b02fc0e53df8 | 6 | * PHY ISR Functions |
| cotigac | 18:b02fc0e53df8 | 7 | * |
| cotigac | 18:b02fc0e53df8 | 8 | * Redistribution and use in source and binary forms, with or without modification, |
| cotigac | 18:b02fc0e53df8 | 9 | * are permitted provided that the following conditions are met: |
| cotigac | 18:b02fc0e53df8 | 10 | * |
| cotigac | 18:b02fc0e53df8 | 11 | * o Redistributions of source code must retain the above copyright notice, this list |
| cotigac | 18:b02fc0e53df8 | 12 | * of conditions and the following disclaimer. |
| cotigac | 18:b02fc0e53df8 | 13 | * |
| cotigac | 18:b02fc0e53df8 | 14 | * o Redistributions in binary form must reproduce the above copyright notice, this |
| cotigac | 18:b02fc0e53df8 | 15 | * list of conditions and the following disclaimer in the documentation and/or |
| cotigac | 18:b02fc0e53df8 | 16 | * other materials provided with the distribution. |
| cotigac | 18:b02fc0e53df8 | 17 | * |
| cotigac | 18:b02fc0e53df8 | 18 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
| cotigac | 18:b02fc0e53df8 | 19 | * contributors may be used to endorse or promote products derived from this |
| cotigac | 18:b02fc0e53df8 | 20 | * software without specific prior written permission. |
| cotigac | 18:b02fc0e53df8 | 21 | * |
| cotigac | 18:b02fc0e53df8 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| cotigac | 18:b02fc0e53df8 | 23 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| cotigac | 18:b02fc0e53df8 | 24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| cotigac | 18:b02fc0e53df8 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| cotigac | 18:b02fc0e53df8 | 26 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| cotigac | 18:b02fc0e53df8 | 27 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| cotigac | 18:b02fc0e53df8 | 28 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| cotigac | 18:b02fc0e53df8 | 29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| cotigac | 18:b02fc0e53df8 | 30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| cotigac | 18:b02fc0e53df8 | 31 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| cotigac | 18:b02fc0e53df8 | 32 | */ |
| cotigac | 18:b02fc0e53df8 | 33 | |
| cotigac | 18:b02fc0e53df8 | 34 | /************************************************************************************ |
| cotigac | 18:b02fc0e53df8 | 35 | ************************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 36 | * Include |
| cotigac | 18:b02fc0e53df8 | 37 | ************************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 38 | ************************************************************************************/ |
| cotigac | 18:b02fc0e53df8 | 39 | #include "EmbeddedTypes.h" |
| cotigac | 18:b02fc0e53df8 | 40 | //#include "board.h" |
| cotigac | 18:b02fc0e53df8 | 41 | #include "MCR20Drv.h" |
| cotigac | 18:b02fc0e53df8 | 42 | #include "MCR20Reg.h" |
| cotigac | 18:b02fc0e53df8 | 43 | #include "Phy.h" |
| cotigac | 18:b02fc0e53df8 | 44 | #include "PhyInterface.h" |
| cotigac | 18:b02fc0e53df8 | 45 | //#include "Gpio_IrqAdapter.h" |
| cotigac | 18:b02fc0e53df8 | 46 | |
| cotigac | 18:b02fc0e53df8 | 47 | //#include "fsl_os_abstraction.h" |
| cotigac | 18:b02fc0e53df8 | 48 | |
| cotigac | 18:b02fc0e53df8 | 49 | #include "XcvrSpi.h" |
| cotigac | 18:b02fc0e53df8 | 50 | |
| cotigac | 18:b02fc0e53df8 | 51 | /************************************************************************************ |
| cotigac | 18:b02fc0e53df8 | 52 | ************************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 53 | * Private macros |
| cotigac | 18:b02fc0e53df8 | 54 | ************************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 55 | ************************************************************************************/ |
| cotigac | 18:b02fc0e53df8 | 56 | #if defined(MCU_MKL46Z4) |
| cotigac | 18:b02fc0e53df8 | 57 | #define MCR20_Irq_Priority (0xC0) |
| cotigac | 18:b02fc0e53df8 | 58 | #else |
| cotigac | 18:b02fc0e53df8 | 59 | #define MCR20_Irq_Priority (0x80) |
| cotigac | 18:b02fc0e53df8 | 60 | #endif |
| cotigac | 18:b02fc0e53df8 | 61 | |
| cotigac | 18:b02fc0e53df8 | 62 | #define PHY_IRQSTS1_INDEX_c 0x00 |
| cotigac | 18:b02fc0e53df8 | 63 | #define PHY_IRQSTS2_INDEX_c 0x01 |
| cotigac | 18:b02fc0e53df8 | 64 | #define PHY_IRQSTS3_INDEX_c 0x02 |
| cotigac | 18:b02fc0e53df8 | 65 | #define PHY_CTRL1_INDEX_c 0x03 |
| cotigac | 18:b02fc0e53df8 | 66 | #define PHY_CTRL2_INDEX_c 0x04 |
| cotigac | 18:b02fc0e53df8 | 67 | #define PHY_CTRL3_INDEX_c 0x05 |
| cotigac | 18:b02fc0e53df8 | 68 | #define PHY_RX_FRM_LEN_INDEX_c 0x06 |
| cotigac | 18:b02fc0e53df8 | 69 | #define PHY_CTRL4_INDEX_c 0x07 |
| cotigac | 18:b02fc0e53df8 | 70 | |
| cotigac | 18:b02fc0e53df8 | 71 | /************************************************************************************ |
| cotigac | 18:b02fc0e53df8 | 72 | ************************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 73 | * Private memory declarations |
| cotigac | 18:b02fc0e53df8 | 74 | ************************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 75 | ************************************************************************************/ |
| cotigac | 18:b02fc0e53df8 | 76 | extern Phy_PhyLocalStruct_t phyLocal[]; |
| cotigac | 18:b02fc0e53df8 | 77 | static volatile phyRxParams_t * mpRxParams = NULL; |
| cotigac | 18:b02fc0e53df8 | 78 | static uint32_t mPhyTaskInstance; |
| cotigac | 18:b02fc0e53df8 | 79 | uint8_t mStatusAndControlRegs[8]; |
| cotigac | 18:b02fc0e53df8 | 80 | uint8_t mPhyLastRxLQI = 0; |
| cotigac | 18:b02fc0e53df8 | 81 | uint8_t mPhyLastRxRSSI = 0; |
| cotigac | 18:b02fc0e53df8 | 82 | |
| cotigac | 18:b02fc0e53df8 | 83 | void (*gpfPhyPreprocessData)(uint8_t *pData) = NULL; |
| cotigac | 18:b02fc0e53df8 | 84 | |
| cotigac | 18:b02fc0e53df8 | 85 | #if gUsePBTransferThereshold_d |
| cotigac | 18:b02fc0e53df8 | 86 | static uint8_t mPhyWatermarkLevel; |
| cotigac | 18:b02fc0e53df8 | 87 | #define mPhyGetPBTransferThreshold(len) ((len) - 2) |
| cotigac | 18:b02fc0e53df8 | 88 | //#define mPhyGetPBTransferThreshold(len) ((len)*93/100) |
| cotigac | 18:b02fc0e53df8 | 89 | //#define mPhyGetPBTransferThreshold(len) (((len) < 20) ? ((len) - 2) : ((len) * 93 / 100)) |
| cotigac | 18:b02fc0e53df8 | 90 | #endif |
| cotigac | 18:b02fc0e53df8 | 91 | |
| cotigac | 18:b02fc0e53df8 | 92 | /************************************************************************************ |
| cotigac | 18:b02fc0e53df8 | 93 | ************************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 94 | * Public functions |
| cotigac | 18:b02fc0e53df8 | 95 | ************************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 96 | ************************************************************************************/ |
| cotigac | 18:b02fc0e53df8 | 97 | |
| cotigac | 18:b02fc0e53df8 | 98 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 99 | * \brief Sets the current PHY instance waiting for an IRQ |
| cotigac | 18:b02fc0e53df8 | 100 | * |
| cotigac | 18:b02fc0e53df8 | 101 | * \param[in] instanceId instance of the PHY |
| cotigac | 18:b02fc0e53df8 | 102 | * |
| cotigac | 18:b02fc0e53df8 | 103 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 104 | void PhyIsrPassTaskParams |
| cotigac | 18:b02fc0e53df8 | 105 | ( |
| cotigac | 18:b02fc0e53df8 | 106 | instanceId_t instanceId |
| cotigac | 18:b02fc0e53df8 | 107 | ) |
| cotigac | 18:b02fc0e53df8 | 108 | { |
| cotigac | 18:b02fc0e53df8 | 109 | mPhyTaskInstance = instanceId; |
| cotigac | 18:b02fc0e53df8 | 110 | } |
| cotigac | 18:b02fc0e53df8 | 111 | |
| cotigac | 18:b02fc0e53df8 | 112 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 113 | * \brief Sets the location of the Rx parameters |
| cotigac | 18:b02fc0e53df8 | 114 | * |
| cotigac | 18:b02fc0e53df8 | 115 | * \param[in] pRxParam pointer to Rx parameters |
| cotigac | 18:b02fc0e53df8 | 116 | * |
| cotigac | 18:b02fc0e53df8 | 117 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 118 | void PhyIsrPassRxParams |
| cotigac | 18:b02fc0e53df8 | 119 | ( |
| cotigac | 18:b02fc0e53df8 | 120 | volatile phyRxParams_t * pRxParam |
| cotigac | 18:b02fc0e53df8 | 121 | ) |
| cotigac | 18:b02fc0e53df8 | 122 | { |
| cotigac | 18:b02fc0e53df8 | 123 | mpRxParams = pRxParam; |
| cotigac | 18:b02fc0e53df8 | 124 | } |
| cotigac | 18:b02fc0e53df8 | 125 | |
| cotigac | 18:b02fc0e53df8 | 126 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 127 | * \brief Clear and mask PHY IRQ, set sequence to Idle |
| cotigac | 18:b02fc0e53df8 | 128 | * |
| cotigac | 18:b02fc0e53df8 | 129 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 130 | void PhyIsrSeqCleanup |
| cotigac | 18:b02fc0e53df8 | 131 | ( |
| cotigac | 18:b02fc0e53df8 | 132 | void |
| cotigac | 18:b02fc0e53df8 | 133 | ) |
| cotigac | 18:b02fc0e53df8 | 134 | { |
| cotigac | 18:b02fc0e53df8 | 135 | mStatusAndControlRegs[PHY_IRQSTS3_INDEX_c] &= 0xF0; |
| cotigac | 18:b02fc0e53df8 | 136 | mStatusAndControlRegs[PHY_IRQSTS3_INDEX_c] &= (uint8_t) ~( cIRQSTS3_TMR3MSK ); // unmask TMR3 interrupt |
| cotigac | 18:b02fc0e53df8 | 137 | mStatusAndControlRegs[PHY_CTRL1_INDEX_c] &= (uint8_t) ~( cPHY_CTRL1_XCVSEQ ); |
| cotigac | 18:b02fc0e53df8 | 138 | mStatusAndControlRegs[PHY_CTRL2_INDEX_c] |= (uint8_t) ( cPHY_CTRL2_CCAMSK | \ |
| cotigac | 18:b02fc0e53df8 | 139 | cPHY_CTRL2_RXMSK | \ |
| cotigac | 18:b02fc0e53df8 | 140 | cPHY_CTRL2_TXMSK | \ |
| cotigac | 18:b02fc0e53df8 | 141 | cPHY_CTRL2_SEQMSK ); |
| cotigac | 18:b02fc0e53df8 | 142 | |
| cotigac | 18:b02fc0e53df8 | 143 | // clear transceiver interrupts, mask SEQ, RX, TX and CCA interrupts and set the PHY sequencer back to IDLE |
| cotigac | 18:b02fc0e53df8 | 144 | MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, mStatusAndControlRegs, 5); |
| cotigac | 18:b02fc0e53df8 | 145 | } |
| cotigac | 18:b02fc0e53df8 | 146 | |
| cotigac | 18:b02fc0e53df8 | 147 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 148 | * \brief Clear and mask PHY IRQ, disable timeout, set sequence to Idle |
| cotigac | 18:b02fc0e53df8 | 149 | * |
| cotigac | 18:b02fc0e53df8 | 150 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 151 | void PhyIsrTimeoutCleanup |
| cotigac | 18:b02fc0e53df8 | 152 | ( |
| cotigac | 18:b02fc0e53df8 | 153 | void |
| cotigac | 18:b02fc0e53df8 | 154 | ) |
| cotigac | 18:b02fc0e53df8 | 155 | { |
| cotigac | 18:b02fc0e53df8 | 156 | mStatusAndControlRegs[PHY_IRQSTS3_INDEX_c] &= 0xF0; |
| cotigac | 18:b02fc0e53df8 | 157 | mStatusAndControlRegs[PHY_IRQSTS3_INDEX_c] |= (uint8_t) ( cIRQSTS3_TMR3MSK | \ |
| cotigac | 18:b02fc0e53df8 | 158 | cIRQSTS3_TMR3IRQ); // mask and clear TMR3 interrupt |
| cotigac | 18:b02fc0e53df8 | 159 | mStatusAndControlRegs[PHY_CTRL1_INDEX_c] &= (uint8_t) ~( cPHY_CTRL1_XCVSEQ ); |
| cotigac | 18:b02fc0e53df8 | 160 | mStatusAndControlRegs[PHY_CTRL2_INDEX_c] |= (uint8_t) ( cPHY_CTRL2_CCAMSK | \ |
| cotigac | 18:b02fc0e53df8 | 161 | cPHY_CTRL2_RXMSK | \ |
| cotigac | 18:b02fc0e53df8 | 162 | cPHY_CTRL2_TXMSK | \ |
| cotigac | 18:b02fc0e53df8 | 163 | cPHY_CTRL2_SEQMSK ); |
| cotigac | 18:b02fc0e53df8 | 164 | |
| cotigac | 18:b02fc0e53df8 | 165 | // disable TMR3 comparator and timeout |
| cotigac | 18:b02fc0e53df8 | 166 | mStatusAndControlRegs[PHY_CTRL3_INDEX_c] &= (uint8_t) ~( cPHY_CTRL3_TMR3CMP_EN ); |
| cotigac | 18:b02fc0e53df8 | 167 | mStatusAndControlRegs[PHY_CTRL4_INDEX_c] &= (uint8_t) ~( cPHY_CTRL4_TC3TMOUT ); |
| cotigac | 18:b02fc0e53df8 | 168 | |
| cotigac | 18:b02fc0e53df8 | 169 | // clear transceiver interrupts, mask mask SEQ, RX, TX, TMR3 and CCA interrupts interrupts and set the PHY sequencer back to IDLE |
| cotigac | 18:b02fc0e53df8 | 170 | MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, mStatusAndControlRegs, 8); |
| cotigac | 18:b02fc0e53df8 | 171 | } |
| cotigac | 18:b02fc0e53df8 | 172 | |
| cotigac | 18:b02fc0e53df8 | 173 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 174 | * \brief Scales energy level to 0-255 |
| cotigac | 18:b02fc0e53df8 | 175 | * |
| cotigac | 18:b02fc0e53df8 | 176 | * \param[in] energyLevel the energ level reported by HW |
| cotigac | 18:b02fc0e53df8 | 177 | * |
| cotigac | 18:b02fc0e53df8 | 178 | * \return uint8_t the energy level scaled in 0x00-0xFF |
| cotigac | 18:b02fc0e53df8 | 179 | * |
| cotigac | 18:b02fc0e53df8 | 180 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 181 | uint8_t Phy_GetEnergyLevel |
| cotigac | 18:b02fc0e53df8 | 182 | ( |
| cotigac | 18:b02fc0e53df8 | 183 | uint8_t energyLevel /* db */ |
| cotigac | 18:b02fc0e53df8 | 184 | ) |
| cotigac | 18:b02fc0e53df8 | 185 | { |
| cotigac | 18:b02fc0e53df8 | 186 | if(energyLevel >= 90) |
| cotigac | 18:b02fc0e53df8 | 187 | { |
| cotigac | 18:b02fc0e53df8 | 188 | /* ED value is below minimum. Return 0x00. */ |
| cotigac | 18:b02fc0e53df8 | 189 | energyLevel = 0x00; |
| cotigac | 18:b02fc0e53df8 | 190 | } |
| cotigac | 18:b02fc0e53df8 | 191 | else if(energyLevel <= 26) |
| cotigac | 18:b02fc0e53df8 | 192 | { |
| cotigac | 18:b02fc0e53df8 | 193 | /* ED value is above maximum. Return 0xFF. */ |
| cotigac | 18:b02fc0e53df8 | 194 | energyLevel = 0xFF; |
| cotigac | 18:b02fc0e53df8 | 195 | } |
| cotigac | 18:b02fc0e53df8 | 196 | else |
| cotigac | 18:b02fc0e53df8 | 197 | { |
| cotigac | 18:b02fc0e53df8 | 198 | /* Energy level (-90 dBm to -26 dBm ) --> varies form 0 to 64 */ |
| cotigac | 18:b02fc0e53df8 | 199 | energyLevel = (90 - energyLevel); |
| cotigac | 18:b02fc0e53df8 | 200 | /* Rescale the energy level values to the 0x00-0xff range (0 to 64 translates in 0 to 255) */ |
| cotigac | 18:b02fc0e53df8 | 201 | /* energyLevel * 3.9844 ~= 4 */ |
| cotigac | 18:b02fc0e53df8 | 202 | /* Multiply with 4=2^2 by shifting left. |
| cotigac | 18:b02fc0e53df8 | 203 | The multiplication will not overflow beacause energyLevel has values between 0 and 63 */ |
| cotigac | 18:b02fc0e53df8 | 204 | energyLevel <<= 2; |
| cotigac | 18:b02fc0e53df8 | 205 | } |
| cotigac | 18:b02fc0e53df8 | 206 | |
| cotigac | 18:b02fc0e53df8 | 207 | return energyLevel; |
| cotigac | 18:b02fc0e53df8 | 208 | } |
| cotigac | 18:b02fc0e53df8 | 209 | |
| cotigac | 18:b02fc0e53df8 | 210 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 211 | * \brief Scales LQI to 0-255 |
| cotigac | 18:b02fc0e53df8 | 212 | * |
| cotigac | 18:b02fc0e53df8 | 213 | * \param[in] hwLqi the LQI reported by HW |
| cotigac | 18:b02fc0e53df8 | 214 | * |
| cotigac | 18:b02fc0e53df8 | 215 | * \return uint8_t the LQI scaled in 0x00-0xFF |
| cotigac | 18:b02fc0e53df8 | 216 | * |
| cotigac | 18:b02fc0e53df8 | 217 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 218 | static uint8_t Phy_LqiConvert |
| cotigac | 18:b02fc0e53df8 | 219 | ( |
| cotigac | 18:b02fc0e53df8 | 220 | uint8_t hwLqi |
| cotigac | 18:b02fc0e53df8 | 221 | ) |
| cotigac | 18:b02fc0e53df8 | 222 | { |
| cotigac | 18:b02fc0e53df8 | 223 | uint32_t tmpLQI; |
| cotigac | 18:b02fc0e53df8 | 224 | |
| cotigac | 18:b02fc0e53df8 | 225 | /* LQI Saturation Level */ |
| cotigac | 18:b02fc0e53df8 | 226 | if (hwLqi >= 230) |
| cotigac | 18:b02fc0e53df8 | 227 | { |
| cotigac | 18:b02fc0e53df8 | 228 | return 0xFF; |
| cotigac | 18:b02fc0e53df8 | 229 | } |
| cotigac | 18:b02fc0e53df8 | 230 | else if (hwLqi <= 9) |
| cotigac | 18:b02fc0e53df8 | 231 | { |
| cotigac | 18:b02fc0e53df8 | 232 | return 0; |
| cotigac | 18:b02fc0e53df8 | 233 | } |
| cotigac | 18:b02fc0e53df8 | 234 | else |
| cotigac | 18:b02fc0e53df8 | 235 | { |
| cotigac | 18:b02fc0e53df8 | 236 | /* Rescale the LQI values from min to saturation to the 0x00 - 0xFF range */ |
| cotigac | 18:b02fc0e53df8 | 237 | /* The LQI value mst be multiplied by ~1.1087 */ |
| cotigac | 18:b02fc0e53df8 | 238 | /* tmpLQI = hwLqi * 7123 ~= hwLqi * 65536 * 0.1087 = hwLqi * 2^16 * 0.1087*/ |
| cotigac | 18:b02fc0e53df8 | 239 | tmpLQI = ((uint32_t)hwLqi * (uint32_t)7123 ); |
| cotigac | 18:b02fc0e53df8 | 240 | /* tmpLQI = (tmpLQI / 2^16) + hwLqi */ |
| cotigac | 18:b02fc0e53df8 | 241 | tmpLQI = (uint32_t)(tmpLQI >> 16) + (uint32_t)hwLqi; |
| cotigac | 18:b02fc0e53df8 | 242 | |
| cotigac | 18:b02fc0e53df8 | 243 | return (uint8_t)tmpLQI; |
| cotigac | 18:b02fc0e53df8 | 244 | } |
| cotigac | 18:b02fc0e53df8 | 245 | } |
| cotigac | 18:b02fc0e53df8 | 246 | |
| cotigac | 18:b02fc0e53df8 | 247 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 248 | * \brief This function returns the LQI for the las received packet |
| cotigac | 18:b02fc0e53df8 | 249 | * |
| cotigac | 18:b02fc0e53df8 | 250 | * \return uint8_t LQI value |
| cotigac | 18:b02fc0e53df8 | 251 | * |
| cotigac | 18:b02fc0e53df8 | 252 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 253 | uint8_t PhyGetLastRxLqiValue(void) |
| cotigac | 18:b02fc0e53df8 | 254 | { |
| cotigac | 18:b02fc0e53df8 | 255 | return mPhyLastRxLQI; |
| cotigac | 18:b02fc0e53df8 | 256 | } |
| cotigac | 18:b02fc0e53df8 | 257 | |
| cotigac | 18:b02fc0e53df8 | 258 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 259 | * \brief This function returns the RSSI for the las received packet |
| cotigac | 18:b02fc0e53df8 | 260 | * |
| cotigac | 18:b02fc0e53df8 | 261 | * \return uint8_t RSSI value |
| cotigac | 18:b02fc0e53df8 | 262 | * |
| cotigac | 18:b02fc0e53df8 | 263 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 264 | uint8_t PhyGetLastRxRssiValue(void) |
| cotigac | 18:b02fc0e53df8 | 265 | { |
| cotigac | 18:b02fc0e53df8 | 266 | return mPhyLastRxRSSI; |
| cotigac | 18:b02fc0e53df8 | 267 | } |
| cotigac | 18:b02fc0e53df8 | 268 | |
| cotigac | 18:b02fc0e53df8 | 269 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 270 | * \brief PHY ISR |
| cotigac | 18:b02fc0e53df8 | 271 | * |
| cotigac | 18:b02fc0e53df8 | 272 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 273 | void PHY_InterruptHandler(void) |
| cotigac | 18:b02fc0e53df8 | 274 | { |
| cotigac | 18:b02fc0e53df8 | 275 | uint8_t xcvseqCopy; |
| cotigac | 18:b02fc0e53df8 | 276 | |
| cotigac | 18:b02fc0e53df8 | 277 | /* The ISR may be called even if another PORTx pin has changed */ |
| cotigac | 18:b02fc0e53df8 | 278 | //if( !PORT_HAL_IsPinIntPending(g_portBaseAddr[GPIO_EXTRACT_PORT(kGpioXcvrIrqPin)], GPIO_EXTRACT_PIN(kGpioXcvrIrqPin)) ) |
| cotigac | 18:b02fc0e53df8 | 279 | if( !RF_isIRQ_Pending() ) |
| cotigac | 18:b02fc0e53df8 | 280 | { |
| cotigac | 18:b02fc0e53df8 | 281 | return; |
| cotigac | 18:b02fc0e53df8 | 282 | } |
| cotigac | 18:b02fc0e53df8 | 283 | |
| cotigac | 18:b02fc0e53df8 | 284 | /* Disable and clear transceiver(IRQ_B) interrupt */ |
| cotigac | 18:b02fc0e53df8 | 285 | MCR20Drv_IRQ_Disable(); |
| cotigac | 18:b02fc0e53df8 | 286 | MCR20Drv_IRQ_Clear(); |
| cotigac | 18:b02fc0e53df8 | 287 | |
| cotigac | 18:b02fc0e53df8 | 288 | /* Read transceiver interrupt status and control registers */ |
| cotigac | 18:b02fc0e53df8 | 289 | mStatusAndControlRegs[PHY_IRQSTS1_INDEX_c] = |
| cotigac | 18:b02fc0e53df8 | 290 | MCR20Drv_DirectAccessSPIMultiByteRead(IRQSTS2, &mStatusAndControlRegs[1], 7); |
| cotigac | 18:b02fc0e53df8 | 291 | xcvseqCopy = mStatusAndControlRegs[PHY_CTRL1_INDEX_c] & cPHY_CTRL1_XCVSEQ; |
| cotigac | 18:b02fc0e53df8 | 292 | /* clear transceiver interrupts */ |
| cotigac | 18:b02fc0e53df8 | 293 | MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, mStatusAndControlRegs, 3); |
| cotigac | 18:b02fc0e53df8 | 294 | |
| cotigac | 18:b02fc0e53df8 | 295 | if( (mStatusAndControlRegs[PHY_IRQSTS2_INDEX_c] & cIRQSTS2_WAKE_IRQ) && |
| cotigac | 18:b02fc0e53df8 | 296 | !(mStatusAndControlRegs[PHY_CTRL3_INDEX_c] & cPHY_CTRL3_WAKE_MSK) ) |
| cotigac | 18:b02fc0e53df8 | 297 | { |
| cotigac | 18:b02fc0e53df8 | 298 | #ifdef MAC_PHY_DEBUG |
| cotigac | 18:b02fc0e53df8 | 299 | Radio_Phy_UnexpectedTransceiverReset(mPhyTaskInstance); |
| cotigac | 18:b02fc0e53df8 | 300 | #endif |
| cotigac | 18:b02fc0e53df8 | 301 | MCR20Drv_IRQ_Enable(); |
| cotigac | 18:b02fc0e53df8 | 302 | return; |
| cotigac | 18:b02fc0e53df8 | 303 | } |
| cotigac | 18:b02fc0e53df8 | 304 | |
| cotigac | 18:b02fc0e53df8 | 305 | /* Flter Fail IRQ */ |
| cotigac | 18:b02fc0e53df8 | 306 | if( (mStatusAndControlRegs[PHY_IRQSTS1_INDEX_c] & cIRQSTS1_FILTERFAIL_IRQ) && |
| cotigac | 18:b02fc0e53df8 | 307 | !(mStatusAndControlRegs[PHY_CTRL2_INDEX_c] & cPHY_CTRL2_FILTERFAIL_MSK) ) |
| cotigac | 18:b02fc0e53df8 | 308 | { |
| cotigac | 18:b02fc0e53df8 | 309 | #if gUsePBTransferThereshold_d |
| cotigac | 18:b02fc0e53df8 | 310 | /* Reset the RX_WTR_MARK level since packet was dropped. */ |
| cotigac | 18:b02fc0e53df8 | 311 | mPhyWatermarkLevel = 0; |
| cotigac | 18:b02fc0e53df8 | 312 | MCR20Drv_IndirectAccessSPIWrite(RX_WTR_MARK, mPhyWatermarkLevel); |
| cotigac | 18:b02fc0e53df8 | 313 | #endif |
| cotigac | 18:b02fc0e53df8 | 314 | Radio_Phy_PlmeFilterFailRx(mPhyTaskInstance); |
| cotigac | 18:b02fc0e53df8 | 315 | } |
| cotigac | 18:b02fc0e53df8 | 316 | /* Rx Watermark IRQ */ |
| cotigac | 18:b02fc0e53df8 | 317 | else if( (mStatusAndControlRegs[PHY_IRQSTS1_INDEX_c] & cIRQSTS1_RXWTRMRKIRQ) && |
| cotigac | 18:b02fc0e53df8 | 318 | !(mStatusAndControlRegs[PHY_CTRL2_INDEX_c] & cPHY_CTRL2_RX_WMRK_MSK) ) |
| cotigac | 18:b02fc0e53df8 | 319 | { |
| cotigac | 18:b02fc0e53df8 | 320 | #if gUsePBTransferThereshold_d |
| cotigac | 18:b02fc0e53df8 | 321 | if( 0 == mPhyWatermarkLevel ) |
| cotigac | 18:b02fc0e53df8 | 322 | { |
| cotigac | 18:b02fc0e53df8 | 323 | /* Check if this is a standalone RX because we could end up here during a TR sequence also. */ |
| cotigac | 18:b02fc0e53df8 | 324 | if( xcvseqCopy == gRX_c ) |
| cotigac | 18:b02fc0e53df8 | 325 | { |
| cotigac | 18:b02fc0e53df8 | 326 | /* Set the thereshold packet length at which to start the PB Burst Read.*/ |
| cotigac | 18:b02fc0e53df8 | 327 | mPhyWatermarkLevel = mPhyGetPBTransferThreshold( mStatusAndControlRegs[PHY_RX_FRM_LEN_INDEX_c] ); |
| cotigac | 18:b02fc0e53df8 | 328 | MCR20Drv_IndirectAccessSPIWrite(RX_WTR_MARK, mPhyWatermarkLevel); |
| cotigac | 18:b02fc0e53df8 | 329 | } |
| cotigac | 18:b02fc0e53df8 | 330 | #endif |
| cotigac | 18:b02fc0e53df8 | 331 | Radio_Phy_PlmeRxSfdDetect(mPhyTaskInstance, mStatusAndControlRegs[PHY_RX_FRM_LEN_INDEX_c]); |
| cotigac | 18:b02fc0e53df8 | 332 | #if gUsePBTransferThereshold_d |
| cotigac | 18:b02fc0e53df8 | 333 | } |
| cotigac | 18:b02fc0e53df8 | 334 | else |
| cotigac | 18:b02fc0e53df8 | 335 | { |
| cotigac | 18:b02fc0e53df8 | 336 | /* Reset RX_WTR_MARK here, because if the FCS fails, no other IRQ will arrive |
| cotigac | 18:b02fc0e53df8 | 337 | * and the RX will restart automatically. */ |
| cotigac | 18:b02fc0e53df8 | 338 | mPhyWatermarkLevel = 0; |
| cotigac | 18:b02fc0e53df8 | 339 | MCR20Drv_IndirectAccessSPIWrite(RX_WTR_MARK, mPhyWatermarkLevel); |
| cotigac | 18:b02fc0e53df8 | 340 | |
| cotigac | 18:b02fc0e53df8 | 341 | if( mpRxParams ) |
| cotigac | 18:b02fc0e53df8 | 342 | { |
| cotigac | 18:b02fc0e53df8 | 343 | // Read data from PB |
| cotigac | 18:b02fc0e53df8 | 344 | MCR20Drv_PB_SPIBurstRead(mpRxParams->pRxData->msgData.dataInd.pPsdu, (uint8_t)(mStatusAndControlRegs[PHY_RX_FRM_LEN_INDEX_c] - 2)); |
| cotigac | 18:b02fc0e53df8 | 345 | if( gpfPhyPreprocessData ) |
| cotigac | 18:b02fc0e53df8 | 346 | gpfPhyPreprocessData(mpRxParams->pRxData->msgData.dataInd.pPsdu); |
| cotigac | 18:b02fc0e53df8 | 347 | } |
| cotigac | 18:b02fc0e53df8 | 348 | } |
| cotigac | 18:b02fc0e53df8 | 349 | #endif |
| cotigac | 18:b02fc0e53df8 | 350 | } |
| cotigac | 18:b02fc0e53df8 | 351 | |
| cotigac | 18:b02fc0e53df8 | 352 | /* Timer 1 Compare Match */ |
| cotigac | 18:b02fc0e53df8 | 353 | if( (mStatusAndControlRegs[PHY_IRQSTS3_INDEX_c] & cIRQSTS3_TMR1IRQ) && |
| cotigac | 18:b02fc0e53df8 | 354 | !(mStatusAndControlRegs[PHY_IRQSTS3_INDEX_c] & cIRQSTS3_TMR1MSK)) |
| cotigac | 18:b02fc0e53df8 | 355 | { |
| cotigac | 18:b02fc0e53df8 | 356 | // disable TMR1 comparator |
| cotigac | 18:b02fc0e53df8 | 357 | mStatusAndControlRegs[PHY_CTRL3_INDEX_c] &= (uint8_t) ~( cPHY_CTRL3_TMR1CMP_EN); |
| cotigac | 18:b02fc0e53df8 | 358 | MCR20Drv_DirectAccessSPIWrite(PHY_CTRL3, mStatusAndControlRegs[PHY_CTRL3_INDEX_c]); |
| cotigac | 18:b02fc0e53df8 | 359 | |
| cotigac | 18:b02fc0e53df8 | 360 | Radio_Phy_TimeWaitTimeoutIndication(mPhyTaskInstance); |
| cotigac | 18:b02fc0e53df8 | 361 | } |
| cotigac | 18:b02fc0e53df8 | 362 | |
| cotigac | 18:b02fc0e53df8 | 363 | /* Sequencer interrupt, the autosequence has completed */ |
| cotigac | 18:b02fc0e53df8 | 364 | if( (mStatusAndControlRegs[PHY_IRQSTS1_INDEX_c] & cIRQSTS1_SEQIRQ) && |
| cotigac | 18:b02fc0e53df8 | 365 | !(mStatusAndControlRegs[PHY_CTRL2_INDEX_c] & cPHY_CTRL2_SEQMSK) ) |
| cotigac | 18:b02fc0e53df8 | 366 | { |
| cotigac | 18:b02fc0e53df8 | 367 | // PLL unlock, the autosequence has been aborted due to PLL unlock |
| cotigac | 18:b02fc0e53df8 | 368 | if( mStatusAndControlRegs[PHY_IRQSTS1_INDEX_c] & cIRQSTS1_PLL_UNLOCK_IRQ ) |
| cotigac | 18:b02fc0e53df8 | 369 | { |
| cotigac | 18:b02fc0e53df8 | 370 | PhyIsrSeqCleanup(); |
| cotigac | 18:b02fc0e53df8 | 371 | Radio_Phy_PlmeSyncLossIndication(mPhyTaskInstance); |
| cotigac | 18:b02fc0e53df8 | 372 | MCR20Drv_IRQ_Enable(); |
| cotigac | 18:b02fc0e53df8 | 373 | return; |
| cotigac | 18:b02fc0e53df8 | 374 | } |
| cotigac | 18:b02fc0e53df8 | 375 | |
| cotigac | 18:b02fc0e53df8 | 376 | // TMR3 timeout, the autosequence has been aborted due to TMR3 timeout |
| cotigac | 18:b02fc0e53df8 | 377 | if( (mStatusAndControlRegs[PHY_IRQSTS3_INDEX_c] & cIRQSTS3_TMR3IRQ) && |
| cotigac | 18:b02fc0e53df8 | 378 | !(mStatusAndControlRegs[PHY_IRQSTS1_INDEX_c] & cIRQSTS1_RXIRQ) && |
| cotigac | 18:b02fc0e53df8 | 379 | (gTX_c != xcvseqCopy) ) |
| cotigac | 18:b02fc0e53df8 | 380 | { |
| cotigac | 18:b02fc0e53df8 | 381 | PhyIsrTimeoutCleanup(); |
| cotigac | 18:b02fc0e53df8 | 382 | |
| cotigac | 18:b02fc0e53df8 | 383 | Radio_Phy_TimeRxTimeoutIndication(mPhyTaskInstance); |
| cotigac | 18:b02fc0e53df8 | 384 | MCR20Drv_IRQ_Enable(); |
| cotigac | 18:b02fc0e53df8 | 385 | return; |
| cotigac | 18:b02fc0e53df8 | 386 | } |
| cotigac | 18:b02fc0e53df8 | 387 | |
| cotigac | 18:b02fc0e53df8 | 388 | PhyIsrSeqCleanup(); |
| cotigac | 18:b02fc0e53df8 | 389 | |
| cotigac | 18:b02fc0e53df8 | 390 | switch(xcvseqCopy) |
| cotigac | 18:b02fc0e53df8 | 391 | { |
| cotigac | 18:b02fc0e53df8 | 392 | case gTX_c: |
| cotigac | 18:b02fc0e53df8 | 393 | if( (mStatusAndControlRegs[PHY_IRQSTS2_INDEX_c] & cIRQSTS2_CCA) && |
| cotigac | 18:b02fc0e53df8 | 394 | (mStatusAndControlRegs[PHY_CTRL1_INDEX_c] & cPHY_CTRL1_CCABFRTX) ) |
| cotigac | 18:b02fc0e53df8 | 395 | { |
| cotigac | 18:b02fc0e53df8 | 396 | Radio_Phy_PlmeCcaConfirm(gPhyChannelBusy_c, mPhyTaskInstance); |
| cotigac | 18:b02fc0e53df8 | 397 | } |
| cotigac | 18:b02fc0e53df8 | 398 | else |
| cotigac | 18:b02fc0e53df8 | 399 | { |
| cotigac | 18:b02fc0e53df8 | 400 | Radio_Phy_PdDataConfirm(mPhyTaskInstance, FALSE); |
| cotigac | 18:b02fc0e53df8 | 401 | } |
| cotigac | 18:b02fc0e53df8 | 402 | break; |
| cotigac | 18:b02fc0e53df8 | 403 | |
| cotigac | 18:b02fc0e53df8 | 404 | case gTR_c: |
| cotigac | 18:b02fc0e53df8 | 405 | if( (mStatusAndControlRegs[PHY_IRQSTS2_INDEX_c] & cIRQSTS2_CCA) && |
| cotigac | 18:b02fc0e53df8 | 406 | (mStatusAndControlRegs[PHY_CTRL1_INDEX_c] & cPHY_CTRL1_CCABFRTX) ) |
| cotigac | 18:b02fc0e53df8 | 407 | { |
| cotigac | 18:b02fc0e53df8 | 408 | Radio_Phy_PlmeCcaConfirm(gPhyChannelBusy_c, mPhyTaskInstance); |
| cotigac | 18:b02fc0e53df8 | 409 | } |
| cotigac | 18:b02fc0e53df8 | 410 | else |
| cotigac | 18:b02fc0e53df8 | 411 | { |
| cotigac | 18:b02fc0e53df8 | 412 | if(NULL != mpRxParams) |
| cotigac | 18:b02fc0e53df8 | 413 | { |
| cotigac | 18:b02fc0e53df8 | 414 | // reports value of 0x00 for -105 dBm of received input power and 0xFF for 0 dBm of received input power |
| cotigac | 18:b02fc0e53df8 | 415 | mPhyLastRxRSSI = MCR20Drv_DirectAccessSPIRead((uint8_t) LQI_VALUE); |
| cotigac | 18:b02fc0e53df8 | 416 | mpRxParams->linkQuality = Phy_LqiConvert(mPhyLastRxRSSI); |
| cotigac | 18:b02fc0e53df8 | 417 | mPhyLastRxLQI = mpRxParams->linkQuality; |
| cotigac | 18:b02fc0e53df8 | 418 | MCR20Drv_DirectAccessSPIMultiByteRead( (uint8_t) TIMESTAMP_LSB, (uint8_t *)&mpRxParams->timeStamp, 3); |
| cotigac | 18:b02fc0e53df8 | 419 | mpRxParams->psduLength = (uint8_t)(mStatusAndControlRegs[PHY_RX_FRM_LEN_INDEX_c]); //Including FCS (2 bytes) |
| cotigac | 18:b02fc0e53df8 | 420 | } |
| cotigac | 18:b02fc0e53df8 | 421 | if( (mStatusAndControlRegs[PHY_IRQSTS1_INDEX_c] & cIRQSTS1_RX_FRM_PEND) == cIRQSTS1_RX_FRM_PEND ) |
| cotigac | 18:b02fc0e53df8 | 422 | { |
| cotigac | 18:b02fc0e53df8 | 423 | Radio_Phy_PdDataConfirm(mPhyTaskInstance, TRUE); |
| cotigac | 18:b02fc0e53df8 | 424 | } |
| cotigac | 18:b02fc0e53df8 | 425 | else |
| cotigac | 18:b02fc0e53df8 | 426 | { |
| cotigac | 18:b02fc0e53df8 | 427 | Radio_Phy_PdDataConfirm(mPhyTaskInstance, FALSE); |
| cotigac | 18:b02fc0e53df8 | 428 | } |
| cotigac | 18:b02fc0e53df8 | 429 | } |
| cotigac | 18:b02fc0e53df8 | 430 | break; |
| cotigac | 18:b02fc0e53df8 | 431 | |
| cotigac | 18:b02fc0e53df8 | 432 | case gRX_c: |
| cotigac | 18:b02fc0e53df8 | 433 | if( NULL != mpRxParams ) |
| cotigac | 18:b02fc0e53df8 | 434 | { |
| cotigac | 18:b02fc0e53df8 | 435 | // reports value of 0x00 for -105 dBm of received input power and 0xFF for 0 dBm of received input power |
| cotigac | 18:b02fc0e53df8 | 436 | mPhyLastRxRSSI = MCR20Drv_DirectAccessSPIRead((uint8_t) LQI_VALUE); |
| cotigac | 18:b02fc0e53df8 | 437 | mpRxParams->linkQuality = Phy_LqiConvert(mPhyLastRxRSSI); |
| cotigac | 18:b02fc0e53df8 | 438 | mPhyLastRxLQI = mpRxParams->linkQuality; |
| cotigac | 18:b02fc0e53df8 | 439 | MCR20Drv_DirectAccessSPIMultiByteRead( (uint8_t) TIMESTAMP_LSB, (uint8_t *)&mpRxParams->timeStamp, 3); |
| cotigac | 18:b02fc0e53df8 | 440 | mpRxParams->psduLength = (uint8_t)(mStatusAndControlRegs[PHY_RX_FRM_LEN_INDEX_c]); //Including FCS (2 bytes) |
| cotigac | 18:b02fc0e53df8 | 441 | } |
| cotigac | 18:b02fc0e53df8 | 442 | Radio_Phy_PdDataIndication(mPhyTaskInstance); |
| cotigac | 18:b02fc0e53df8 | 443 | break; |
| cotigac | 18:b02fc0e53df8 | 444 | |
| cotigac | 18:b02fc0e53df8 | 445 | case gCCA_c: |
| cotigac | 18:b02fc0e53df8 | 446 | if( (mStatusAndControlRegs[PHY_CTRL4_INDEX_c] & (cPHY_CTRL4_CCATYPE << cPHY_CTRL4_CCATYPE_Shift_c)) == (gCcaED_c << cPHY_CTRL4_CCATYPE_Shift_c) ) |
| cotigac | 18:b02fc0e53df8 | 447 | { |
| cotigac | 18:b02fc0e53df8 | 448 | // Ed |
| cotigac | 18:b02fc0e53df8 | 449 | Radio_Phy_PlmeEdConfirm(MCR20Drv_DirectAccessSPIRead((uint8_t) CCA1_ED_FNL), mPhyTaskInstance); |
| cotigac | 18:b02fc0e53df8 | 450 | } |
| cotigac | 18:b02fc0e53df8 | 451 | else |
| cotigac | 18:b02fc0e53df8 | 452 | { |
| cotigac | 18:b02fc0e53df8 | 453 | // CCA |
| cotigac | 18:b02fc0e53df8 | 454 | if( mStatusAndControlRegs[PHY_IRQSTS2_INDEX_c] & cIRQSTS2_CCA ) |
| cotigac | 18:b02fc0e53df8 | 455 | { |
| cotigac | 18:b02fc0e53df8 | 456 | #if (gUseStandaloneCCABeforeTx_d == 1) |
| cotigac | 18:b02fc0e53df8 | 457 | phyLocal[mPhyTaskInstance].txParams.numOfCca = 0; |
| cotigac | 18:b02fc0e53df8 | 458 | #endif |
| cotigac | 18:b02fc0e53df8 | 459 | Radio_Phy_PlmeCcaConfirm(gPhyChannelBusy_c, mPhyTaskInstance); |
| cotigac | 18:b02fc0e53df8 | 460 | } |
| cotigac | 18:b02fc0e53df8 | 461 | else |
| cotigac | 18:b02fc0e53df8 | 462 | { |
| cotigac | 18:b02fc0e53df8 | 463 | #if (gUseStandaloneCCABeforeTx_d == 1) |
| cotigac | 18:b02fc0e53df8 | 464 | if( phyLocal[mPhyTaskInstance].txParams.numOfCca > 0 ) |
| cotigac | 18:b02fc0e53df8 | 465 | { |
| cotigac | 18:b02fc0e53df8 | 466 | mStatusAndControlRegs[PHY_CTRL1] &= (uint8_t) ~(cPHY_CTRL1_XCVSEQ); |
| cotigac | 18:b02fc0e53df8 | 467 | |
| cotigac | 18:b02fc0e53df8 | 468 | if( --phyLocal[mPhyTaskInstance].txParams.numOfCca == 0 ) |
| cotigac | 18:b02fc0e53df8 | 469 | { |
| cotigac | 18:b02fc0e53df8 | 470 | // perform TxRxAck sequence if required by phyTxMode |
| cotigac | 18:b02fc0e53df8 | 471 | if( gPhyRxAckRqd_c == phyLocal[mPhyTaskInstance].txParams.ackRequired ) |
| cotigac | 18:b02fc0e53df8 | 472 | { |
| cotigac | 18:b02fc0e53df8 | 473 | mStatusAndControlRegs[PHY_CTRL1] |= (uint8_t) (cPHY_CTRL1_RXACKRQD); |
| cotigac | 18:b02fc0e53df8 | 474 | mStatusAndControlRegs[PHY_CTRL1] |= gTR_c; |
| cotigac | 18:b02fc0e53df8 | 475 | } |
| cotigac | 18:b02fc0e53df8 | 476 | else |
| cotigac | 18:b02fc0e53df8 | 477 | { |
| cotigac | 18:b02fc0e53df8 | 478 | mStatusAndControlRegs[PHY_CTRL1] &= (uint8_t) ~(cPHY_CTRL1_RXACKRQD); |
| cotigac | 18:b02fc0e53df8 | 479 | mStatusAndControlRegs[PHY_CTRL1] |= gTX_c; |
| cotigac | 18:b02fc0e53df8 | 480 | } |
| cotigac | 18:b02fc0e53df8 | 481 | } |
| cotigac | 18:b02fc0e53df8 | 482 | else |
| cotigac | 18:b02fc0e53df8 | 483 | { |
| cotigac | 18:b02fc0e53df8 | 484 | mStatusAndControlRegs[PHY_CTRL1] |= gCCA_c; |
| cotigac | 18:b02fc0e53df8 | 485 | } |
| cotigac | 18:b02fc0e53df8 | 486 | |
| cotigac | 18:b02fc0e53df8 | 487 | mStatusAndControlRegs[PHY_CTRL2] &= (uint8_t) ~(cPHY_CTRL2_SEQMSK); // unmask SEQ interrupt |
| cotigac | 18:b02fc0e53df8 | 488 | // start the sequence immediately |
| cotigac | 18:b02fc0e53df8 | 489 | MCR20Drv_DirectAccessSPIMultiByteWrite(PHY_CTRL1, |
| cotigac | 18:b02fc0e53df8 | 490 | &mStatusAndControlRegs[PHY_CTRL1], |
| cotigac | 18:b02fc0e53df8 | 491 | 2); |
| cotigac | 18:b02fc0e53df8 | 492 | } |
| cotigac | 18:b02fc0e53df8 | 493 | else |
| cotigac | 18:b02fc0e53df8 | 494 | #endif |
| cotigac | 18:b02fc0e53df8 | 495 | { |
| cotigac | 18:b02fc0e53df8 | 496 | Radio_Phy_PlmeCcaConfirm(gPhyChannelIdle_c, mPhyTaskInstance); |
| cotigac | 18:b02fc0e53df8 | 497 | } |
| cotigac | 18:b02fc0e53df8 | 498 | } |
| cotigac | 18:b02fc0e53df8 | 499 | } |
| cotigac | 18:b02fc0e53df8 | 500 | break; |
| cotigac | 18:b02fc0e53df8 | 501 | |
| cotigac | 18:b02fc0e53df8 | 502 | case gCCCA_c: |
| cotigac | 18:b02fc0e53df8 | 503 | Radio_Phy_PlmeCcaConfirm(gPhyChannelIdle_c, mPhyTaskInstance); |
| cotigac | 18:b02fc0e53df8 | 504 | break; |
| cotigac | 18:b02fc0e53df8 | 505 | |
| cotigac | 18:b02fc0e53df8 | 506 | default: |
| cotigac | 18:b02fc0e53df8 | 507 | Radio_Phy_PlmeSyncLossIndication(mPhyTaskInstance); |
| cotigac | 18:b02fc0e53df8 | 508 | break; |
| cotigac | 18:b02fc0e53df8 | 509 | } |
| cotigac | 18:b02fc0e53df8 | 510 | } |
| cotigac | 18:b02fc0e53df8 | 511 | // timers interrupt |
| cotigac | 18:b02fc0e53df8 | 512 | else |
| cotigac | 18:b02fc0e53df8 | 513 | { |
| cotigac | 18:b02fc0e53df8 | 514 | if( mStatusAndControlRegs[PHY_IRQSTS3_INDEX_c] & cIRQSTS3_TMR2IRQ ) |
| cotigac | 18:b02fc0e53df8 | 515 | { |
| cotigac | 18:b02fc0e53df8 | 516 | // disable TMR2 comparator and time triggered action |
| cotigac | 18:b02fc0e53df8 | 517 | mStatusAndControlRegs[PHY_CTRL3_INDEX_c] &= (uint8_t) ~( cPHY_CTRL3_TMR2CMP_EN); |
| cotigac | 18:b02fc0e53df8 | 518 | mStatusAndControlRegs[PHY_CTRL1_INDEX_c] &= (uint8_t) ~( cPHY_CTRL1_TMRTRIGEN); |
| cotigac | 18:b02fc0e53df8 | 519 | |
| cotigac | 18:b02fc0e53df8 | 520 | MCR20Drv_DirectAccessSPIWrite(PHY_CTRL3, mStatusAndControlRegs[PHY_CTRL3_INDEX_c]); |
| cotigac | 18:b02fc0e53df8 | 521 | MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, mStatusAndControlRegs[PHY_CTRL1_INDEX_c]); |
| cotigac | 18:b02fc0e53df8 | 522 | |
| cotigac | 18:b02fc0e53df8 | 523 | Radio_Phy_TimeStartEventIndication(mPhyTaskInstance); |
| cotigac | 18:b02fc0e53df8 | 524 | } |
| cotigac | 18:b02fc0e53df8 | 525 | |
| cotigac | 18:b02fc0e53df8 | 526 | if( mStatusAndControlRegs[PHY_IRQSTS3_INDEX_c] & cIRQSTS3_TMR3IRQ ) |
| cotigac | 18:b02fc0e53df8 | 527 | { |
| cotigac | 18:b02fc0e53df8 | 528 | /* disable TMR3 comparator and timeout */ |
| cotigac | 18:b02fc0e53df8 | 529 | mStatusAndControlRegs[PHY_CTRL3_INDEX_c] &= (uint8_t) ~( cPHY_CTRL3_TMR3CMP_EN); |
| cotigac | 18:b02fc0e53df8 | 530 | mStatusAndControlRegs[PHY_CTRL4_INDEX_c] &= (uint8_t) ~( cPHY_CTRL4_TC3TMOUT); |
| cotigac | 18:b02fc0e53df8 | 531 | |
| cotigac | 18:b02fc0e53df8 | 532 | MCR20Drv_DirectAccessSPIWrite(PHY_CTRL3, mStatusAndControlRegs[PHY_CTRL3_INDEX_c]); |
| cotigac | 18:b02fc0e53df8 | 533 | MCR20Drv_DirectAccessSPIWrite(PHY_CTRL4, mStatusAndControlRegs[PHY_CTRL4_INDEX_c]); |
| cotigac | 18:b02fc0e53df8 | 534 | |
| cotigac | 18:b02fc0e53df8 | 535 | /* Ensure that we're not issuing TimeoutIndication while the Automated sequence is still in progress */ |
| cotigac | 18:b02fc0e53df8 | 536 | /* TMR3 can expire during R-T turnaround for example, case in which the sequence is not interrupted */ |
| cotigac | 18:b02fc0e53df8 | 537 | if( gIdle_c == xcvseqCopy ) |
| cotigac | 18:b02fc0e53df8 | 538 | { |
| cotigac | 18:b02fc0e53df8 | 539 | Radio_Phy_TimeRxTimeoutIndication(mPhyTaskInstance); |
| cotigac | 18:b02fc0e53df8 | 540 | } |
| cotigac | 18:b02fc0e53df8 | 541 | } |
| cotigac | 18:b02fc0e53df8 | 542 | |
| cotigac | 18:b02fc0e53df8 | 543 | /* Timer 4 Compare Match */ |
| cotigac | 18:b02fc0e53df8 | 544 | if( mStatusAndControlRegs[PHY_IRQSTS3_INDEX_c] & cIRQSTS3_TMR4IRQ ) |
| cotigac | 18:b02fc0e53df8 | 545 | { |
| cotigac | 18:b02fc0e53df8 | 546 | /* disable TMR4 comparator */ |
| cotigac | 18:b02fc0e53df8 | 547 | mStatusAndControlRegs[PHY_CTRL3_INDEX_c] &= (uint8_t) ~( cPHY_CTRL3_TMR4CMP_EN); |
| cotigac | 18:b02fc0e53df8 | 548 | MCR20Drv_DirectAccessSPIWrite(PHY_CTRL3, mStatusAndControlRegs[PHY_CTRL3_INDEX_c]); |
| cotigac | 18:b02fc0e53df8 | 549 | } |
| cotigac | 18:b02fc0e53df8 | 550 | } |
| cotigac | 18:b02fc0e53df8 | 551 | |
| cotigac | 18:b02fc0e53df8 | 552 | MCR20Drv_IRQ_Enable(); |
| cotigac | 18:b02fc0e53df8 | 553 | } |
| cotigac | 18:b02fc0e53df8 | 554 | |
| cotigac | 18:b02fc0e53df8 | 555 | /*! ********************************************************************************* |
| cotigac | 18:b02fc0e53df8 | 556 | * \brief This function installs the PHY ISR |
| cotigac | 18:b02fc0e53df8 | 557 | * |
| cotigac | 18:b02fc0e53df8 | 558 | ********************************************************************************** */ |
| cotigac | 18:b02fc0e53df8 | 559 | void PHY_InstallIsr( void ) |
| cotigac | 18:b02fc0e53df8 | 560 | { |
| cotigac | 18:b02fc0e53df8 | 561 | /*Initialise RF interrupt pin*/ |
| cotigac | 18:b02fc0e53df8 | 562 | RF_IRQ_Init(); |
| cotigac | 18:b02fc0e53df8 | 563 | |
| cotigac | 18:b02fc0e53df8 | 564 | //GpioInstallIsr(PHY_InterruptHandler, gGpioIsrPrioHigh_c, MCR20_Irq_Priority, kGpioXcvrIrqPin); |
| cotigac | 18:b02fc0e53df8 | 565 | } |