The MCR20A Wireless UART application functions as an wireless UART bridge between two (one-to-one) or several (one to many) boards. The application can be used with both a TERM, or with software that is capable of opening a serial port and writing to or reading from it. The characters sent or received are not necessarily ASCII printable characters.

Dependencies:   fsl_phy_mcr20a fsl_smac mbed-rtos mbed

Fork of mcr20_wireless_uart by Freescale

By default, the application uses broadcast addresses for OTA communication. This way, the application can be directly downloaded and run without any user intervention. The following use case assumes no changes have been done to the project.

  • Two (or more) MCR20A platforms (plugged into the FRDM-K64F Freescale Freedom Development platform) have to be connected to the PC using the mini/micro-USB cables.
  • The code must be downloaded on the platforms via CMSIS-DAP (or other means).
  • After that, two or more TERM applications must be opened, and the serial ports must be configured with the same baud rate as the one in the project (default baud rate is 115200). Other necessary serial configurations are 8 bit, no parity, and 1 stop bit.
  • To start the setup, each platform must be reset, and one of the (user) push buttons found on the MCR20A platform must be pressed. The user can press any of the non-reset buttons on the FRDM-K64F Freescale Freedom Development platform as well. *This initiates the state machine of the application so user can start.

Documentation

SMAC Demo Applications User Guide

Committer:
FSL\B36402
Date:
Sun Mar 15 00:56:28 2015 -0500
Revision:
15:990a8b5664e1
Child:
17:52cfd7db8da3
Integrated PHY version from the official K64F+MCR20A package

Who changed what in which revision?

UserRevisionLine numberNew contents of line
FSL\B36402 15:990a8b5664e1 1 /*
FSL\B36402 15:990a8b5664e1 2 * driverRFinterface.h
FSL\B36402 15:990a8b5664e1 3 *
FSL\B36402 15:990a8b5664e1 4 * Created on: 12 March 2015
FSL\B36402 15:990a8b5664e1 5 * Author: mBed Team
FSL\B36402 15:990a8b5664e1 6 */
FSL\B36402 15:990a8b5664e1 7
FSL\B36402 15:990a8b5664e1 8 #ifndef DRIVERRFINTERFACE_H_
FSL\B36402 15:990a8b5664e1 9 #define DRIVERRFINTERFACE_H_
FSL\B36402 15:990a8b5664e1 10
FSL\B36402 15:990a8b5664e1 11 #include "arm_hal_phy.h"
FSL\B36402 15:990a8b5664e1 12 #include "EmbeddedTypes.h"
FSL\B36402 15:990a8b5664e1 13
FSL\B36402 15:990a8b5664e1 14 #ifdef __cplusplus
FSL\B36402 15:990a8b5664e1 15 extern "C" {
FSL\B36402 15:990a8b5664e1 16 #endif
FSL\B36402 15:990a8b5664e1 17
FSL\B36402 15:990a8b5664e1 18 #define RF_BUFFER_SIZE 128
FSL\B36402 15:990a8b5664e1 19 #define RF_DEFAULT_CHANNEL 11
FSL\B36402 15:990a8b5664e1 20
FSL\B36402 15:990a8b5664e1 21 typedef union uuint16_tag
FSL\B36402 15:990a8b5664e1 22 {
FSL\B36402 15:990a8b5664e1 23 uint16_t u16;
FSL\B36402 15:990a8b5664e1 24 uint8_t u8[2];
FSL\B36402 15:990a8b5664e1 25 } uuint16_t;
FSL\B36402 15:990a8b5664e1 26
FSL\B36402 15:990a8b5664e1 27 typedef union uuint32_tag
FSL\B36402 15:990a8b5664e1 28 {
FSL\B36402 15:990a8b5664e1 29 uint32_t u32;
FSL\B36402 15:990a8b5664e1 30 uint16_t u16[2];
FSL\B36402 15:990a8b5664e1 31 uint8_t u8[4];
FSL\B36402 15:990a8b5664e1 32 } uuint32_t;
FSL\B36402 15:990a8b5664e1 33
FSL\B36402 15:990a8b5664e1 34 typedef union uuint64_tag
FSL\B36402 15:990a8b5664e1 35 {
FSL\B36402 15:990a8b5664e1 36 uint64_t u64;
FSL\B36402 15:990a8b5664e1 37 uint32_t u32[2];
FSL\B36402 15:990a8b5664e1 38 uint16_t u16[4];
FSL\B36402 15:990a8b5664e1 39 uint8_t u8[8];
FSL\B36402 15:990a8b5664e1 40 } uuint64_t;
FSL\B36402 15:990a8b5664e1 41
FSL\B36402 15:990a8b5664e1 42 extern void rf_set_mac_address(const uint8_t *ptr);
FSL\B36402 15:990a8b5664e1 43 extern void rf_channel_set(uint8_t ch);
FSL\B36402 15:990a8b5664e1 44 extern uint64_t atouint64(uint8_t* pArray);
FSL\B36402 15:990a8b5664e1 45 extern uint16_t atouint16(uint8_t* pArray);
FSL\B36402 15:990a8b5664e1 46 extern int8_t rf_tx(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle);
FSL\B36402 15:990a8b5664e1 47 static int8_t rf_extension(phy_extension_type_e extension_type,uint8_t *data_ptr);
FSL\B36402 15:990a8b5664e1 48 static int8_t rf_address_write(phy_address_type_e address_type,uint8_t *address_ptr);
FSL\B36402 15:990a8b5664e1 49 static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel);
FSL\B36402 15:990a8b5664e1 50
FSL\B36402 15:990a8b5664e1 51 #ifdef __cplusplus
FSL\B36402 15:990a8b5664e1 52 }
FSL\B36402 15:990a8b5664e1 53 #endif
FSL\B36402 15:990a8b5664e1 54
FSL\B36402 15:990a8b5664e1 55 #endif /* DRIVERRFINTERFACE_H_ */