NXP / Mbed 2 deprecated mcr20_wireless_uart

The MCR20A Wireless UART application functions as an wireless UART bridge between two (one-to-one) or several (one to many) boards. The application can be used with both a TERM, or with software that is capable of opening a serial port and writing to or reading from it. The characters sent or received are not necessarily ASCII printable characters.

Dependencies:   fsl_phy_mcr20a fsl_smac mbed-rtos mbed

Fork of mcr20_wireless_uart by Freescale

By default, the application uses broadcast addresses for OTA communication. This way, the application can be directly downloaded and run without any user intervention. The following use case assumes no changes have been done to the project.

  • Two (or more) MCR20A platforms (plugged into the FRDM-K64F Freescale Freedom Development platform) have to be connected to the PC using the mini/micro-USB cables.
  • The code must be downloaded on the platforms via CMSIS-DAP (or other means).
  • After that, two or more TERM applications must be opened, and the serial ports must be configured with the same baud rate as the one in the project (default baud rate is 115200). Other necessary serial configurations are 8 bit, no parity, and 1 stop bit.
  • To start the setup, each platform must be reset, and one of the (user) push buttons found on the MCR20A platform must be pressed. The user can press any of the non-reset buttons on the FRDM-K64F Freescale Freedom Development platform as well. *This initiates the state machine of the application so user can start.

Documentation

SMAC Demo Applications User Guide

RF_Drivers_Freescale/PhyPacketProcessor.c@15:990a8b5664e1, 2015-03-15 (annotated)

Committer:
FSL\B36402
Date:
Sun Mar 15 00:56:28 2015 -0500
Revision:
15:990a8b5664e1
Integrated PHY version from the official K64F+MCR20A package

Who changed what in which revision?

UserRevisionLine numberNew contents of line
FSL\B36402 15:990a8b5664e1 1 /*!
FSL\B36402 15:990a8b5664e1 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
FSL\B36402 15:990a8b5664e1 3 * All rights reserved.
FSL\B36402 15:990a8b5664e1 4 *
FSL\B36402 15:990a8b5664e1 5 * \file PhyPacketProcessor.c
FSL\B36402 15:990a8b5664e1 6 *
FSL\B36402 15:990a8b5664e1 7 * Redistribution and use in source and binary forms, with or without modification,
FSL\B36402 15:990a8b5664e1 8 * are permitted provided that the following conditions are met:
FSL\B36402 15:990a8b5664e1 9 *
FSL\B36402 15:990a8b5664e1 10 * o Redistributions of source code must retain the above copyright notice, this list
FSL\B36402 15:990a8b5664e1 11 * of conditions and the following disclaimer.
FSL\B36402 15:990a8b5664e1 12 *
FSL\B36402 15:990a8b5664e1 13 * o Redistributions in binary form must reproduce the above copyright notice, this
FSL\B36402 15:990a8b5664e1 14 * list of conditions and the following disclaimer in the documentation and/or
FSL\B36402 15:990a8b5664e1 15 * other materials provided with the distribution.
FSL\B36402 15:990a8b5664e1 16 *
FSL\B36402 15:990a8b5664e1 17 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
FSL\B36402 15:990a8b5664e1 18 * contributors may be used to endorse or promote products derived from this
FSL\B36402 15:990a8b5664e1 19 * software without specific prior written permission.
FSL\B36402 15:990a8b5664e1 20 *
FSL\B36402 15:990a8b5664e1 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
FSL\B36402 15:990a8b5664e1 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
FSL\B36402 15:990a8b5664e1 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
FSL\B36402 15:990a8b5664e1 24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
FSL\B36402 15:990a8b5664e1 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
FSL\B36402 15:990a8b5664e1 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
FSL\B36402 15:990a8b5664e1 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
FSL\B36402 15:990a8b5664e1 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
FSL\B36402 15:990a8b5664e1 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
FSL\B36402 15:990a8b5664e1 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
FSL\B36402 15:990a8b5664e1 31 */
FSL\B36402 15:990a8b5664e1 32
FSL\B36402 15:990a8b5664e1 33
FSL\B36402 15:990a8b5664e1 34 /************************************************************************************
FSL\B36402 15:990a8b5664e1 35 *************************************************************************************
FSL\B36402 15:990a8b5664e1 36 * Include
FSL\B36402 15:990a8b5664e1 37 *************************************************************************************
FSL\B36402 15:990a8b5664e1 38 ************************************************************************************/
FSL\B36402 15:990a8b5664e1 39 #include "EmbeddedTypes.h"
FSL\B36402 15:990a8b5664e1 40 //#include "board.h"
FSL\B36402 15:990a8b5664e1 41 #include "MCR20Drv.h"
FSL\B36402 15:990a8b5664e1 42 #include "MCR20Reg.h"
FSL\B36402 15:990a8b5664e1 43 #include "MCR20Overwrites.h"
FSL\B36402 15:990a8b5664e1 44
FSL\B36402 15:990a8b5664e1 45 #include "Phy.h"
FSL\B36402 15:990a8b5664e1 46 #include "MpmInterface.h"
FSL\B36402 15:990a8b5664e1 47
FSL\B36402 15:990a8b5664e1 48 //#include "fsl_os_abstraction.h"
FSL\B36402 15:990a8b5664e1 49 //#include "fsl_gpio_driver.h"
FSL\B36402 15:990a8b5664e1 50
FSL\B36402 15:990a8b5664e1 51 //extern const IRQn_Type g_portIrqId[HW_PORT_INSTANCE_COUNT];
FSL\B36402 15:990a8b5664e1 52
FSL\B36402 15:990a8b5664e1 53 /************************************************************************************
FSL\B36402 15:990a8b5664e1 54 *************************************************************************************
FSL\B36402 15:990a8b5664e1 55 * Public macros
FSL\B36402 15:990a8b5664e1 56 *************************************************************************************
FSL\B36402 15:990a8b5664e1 57 ************************************************************************************/
FSL\B36402 15:990a8b5664e1 58
FSL\B36402 15:990a8b5664e1 59 // Address mode indentifiers. Used for both network and MAC interfaces
FSL\B36402 15:990a8b5664e1 60 #define gPhyAddrModeNoAddr_c (0)
FSL\B36402 15:990a8b5664e1 61 #define gPhyAddrModeInvalid_c (1)
FSL\B36402 15:990a8b5664e1 62 #define gPhyAddrMode16BitAddr_c (2)
FSL\B36402 15:990a8b5664e1 63 #define gPhyAddrMode64BitAddr_c (3)
FSL\B36402 15:990a8b5664e1 64
FSL\B36402 15:990a8b5664e1 65 #define PHY_MIN_RNG_DELAY 4
FSL\B36402 15:990a8b5664e1 66
FSL\B36402 15:990a8b5664e1 67 /************************************************************************************
FSL\B36402 15:990a8b5664e1 68 *************************************************************************************
FSL\B36402 15:990a8b5664e1 69 * Private variables
FSL\B36402 15:990a8b5664e1 70 *************************************************************************************
FSL\B36402 15:990a8b5664e1 71 ************************************************************************************/
FSL\B36402 15:990a8b5664e1 72
FSL\B36402 15:990a8b5664e1 73 const uint8_t gPhyIdlePwrState = gPhyDefaultIdlePwrMode_c;
FSL\B36402 15:990a8b5664e1 74 const uint8_t gPhyActivePwrState = gPhyDefaultActivePwrMode_c;
FSL\B36402 15:990a8b5664e1 75
FSL\B36402 15:990a8b5664e1 76 const uint8_t gPhyIndirectQueueSize_c = 12;
FSL\B36402 15:990a8b5664e1 77 static uint8_t mPhyCurrentSamLvl = 12;
FSL\B36402 15:990a8b5664e1 78 static uint8_t mPhyPwrState = gPhyPwrIdle_c;
FSL\B36402 15:990a8b5664e1 79
FSL\B36402 15:990a8b5664e1 80 /************************************************************************************
FSL\B36402 15:990a8b5664e1 81 *************************************************************************************
FSL\B36402 15:990a8b5664e1 82 * Public Functions
FSL\B36402 15:990a8b5664e1 83 *************************************************************************************
FSL\B36402 15:990a8b5664e1 84 ************************************************************************************/
FSL\B36402 15:990a8b5664e1 85
FSL\B36402 15:990a8b5664e1 86
FSL\B36402 15:990a8b5664e1 87 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 88 * Name: PhyGetRandomNo
FSL\B36402 15:990a8b5664e1 89 * Description: - This function should be called only when the Radio is idle.
FSL\B36402 15:990a8b5664e1 90 * The function may take a long time to run!
FSL\B36402 15:990a8b5664e1 91 * It is recomended to use this function only to initializa a seed at startup!
FSL\B36402 15:990a8b5664e1 92 * Parameters: -
FSL\B36402 15:990a8b5664e1 93 * Return: -
FSL\B36402 15:990a8b5664e1 94 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 95
FSL\B36402 15:990a8b5664e1 96 void PhyGetRandomNo(uint32_t *pRandomNo)
FSL\B36402 15:990a8b5664e1 97 {
FSL\B36402 15:990a8b5664e1 98 uint8_t i = 4, prevRN=0;
FSL\B36402 15:990a8b5664e1 99 uint8_t* ptr = (uint8_t *)pRandomNo;
FSL\B36402 15:990a8b5664e1 100 uint32_t startTime, endTime;
FSL\B36402 15:990a8b5664e1 101 uint8_t phyReg;
FSL\B36402 15:990a8b5664e1 102
FSL\B36402 15:990a8b5664e1 103 MCR20Drv_IRQ_Disable();
FSL\B36402 15:990a8b5664e1 104
FSL\B36402 15:990a8b5664e1 105 if( PhyPpGetState() )
FSL\B36402 15:990a8b5664e1 106 {
FSL\B36402 15:990a8b5664e1 107 *pRandomNo = 0;
FSL\B36402 15:990a8b5664e1 108 MCR20Drv_IRQ_Enable();
FSL\B36402 15:990a8b5664e1 109 return;
FSL\B36402 15:990a8b5664e1 110 }
FSL\B36402 15:990a8b5664e1 111
FSL\B36402 15:990a8b5664e1 112 while (i--)
FSL\B36402 15:990a8b5664e1 113 {
FSL\B36402 15:990a8b5664e1 114 PhyTimeReadClock(&startTime);
FSL\B36402 15:990a8b5664e1 115
FSL\B36402 15:990a8b5664e1 116 // Program a new sequence
FSL\B36402 15:990a8b5664e1 117 phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL1);
FSL\B36402 15:990a8b5664e1 118 MCR20Drv_DirectAccessSPIWrite( PHY_CTRL1, phyReg | gRX_c);
FSL\B36402 15:990a8b5664e1 119
FSL\B36402 15:990a8b5664e1 120 // wait a variable number of symbols */
FSL\B36402 15:990a8b5664e1 121 do
FSL\B36402 15:990a8b5664e1 122 PhyTimeReadClock(&endTime);
FSL\B36402 15:990a8b5664e1 123 while( ((endTime - startTime) & 0x00FFFFFF) < (PHY_MIN_RNG_DELAY + (prevRN>>5)));
FSL\B36402 15:990a8b5664e1 124
FSL\B36402 15:990a8b5664e1 125 // Abort the sequence
FSL\B36402 15:990a8b5664e1 126 PhyAbort();
FSL\B36402 15:990a8b5664e1 127
FSL\B36402 15:990a8b5664e1 128 // Read new 8 bit random number
FSL\B36402 15:990a8b5664e1 129 prevRN = MCR20Drv_IndirectAccessSPIRead((uint8_t)_RNG);
FSL\B36402 15:990a8b5664e1 130 *ptr++ = prevRN;
FSL\B36402 15:990a8b5664e1 131 }
FSL\B36402 15:990a8b5664e1 132
FSL\B36402 15:990a8b5664e1 133 MCR20Drv_IRQ_Enable();
FSL\B36402 15:990a8b5664e1 134 }
FSL\B36402 15:990a8b5664e1 135
FSL\B36402 15:990a8b5664e1 136
FSL\B36402 15:990a8b5664e1 137 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 138 * Name: PhyPpSetDualPanAuto
FSL\B36402 15:990a8b5664e1 139 * Description: -
FSL\B36402 15:990a8b5664e1 140 * Parameters: -
FSL\B36402 15:990a8b5664e1 141 * Return: -
FSL\B36402 15:990a8b5664e1 142 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 143 void PhyPpSetDualPanAuto
FSL\B36402 15:990a8b5664e1 144 (
FSL\B36402 15:990a8b5664e1 145 bool_t mode
FSL\B36402 15:990a8b5664e1 146 )
FSL\B36402 15:990a8b5664e1 147 {
FSL\B36402 15:990a8b5664e1 148 uint8_t phyReg, phyReg2;
FSL\B36402 15:990a8b5664e1 149
FSL\B36402 15:990a8b5664e1 150 phyReg = MCR20Drv_IndirectAccessSPIRead( (uint8_t) DUAL_PAN_CTRL);
FSL\B36402 15:990a8b5664e1 151
FSL\B36402 15:990a8b5664e1 152 if( mode )
FSL\B36402 15:990a8b5664e1 153 {
FSL\B36402 15:990a8b5664e1 154 phyReg2 = phyReg | (cDUAL_PAN_CTRL_DUAL_PAN_AUTO);
FSL\B36402 15:990a8b5664e1 155 }
FSL\B36402 15:990a8b5664e1 156 else
FSL\B36402 15:990a8b5664e1 157 {
FSL\B36402 15:990a8b5664e1 158 phyReg2 = phyReg & (~cDUAL_PAN_CTRL_DUAL_PAN_AUTO);
FSL\B36402 15:990a8b5664e1 159 }
FSL\B36402 15:990a8b5664e1 160
FSL\B36402 15:990a8b5664e1 161 /* Write the new value only if it has changed */
FSL\B36402 15:990a8b5664e1 162 if (phyReg2 != phyReg)
FSL\B36402 15:990a8b5664e1 163 MCR20Drv_IndirectAccessSPIWrite( (uint8_t) DUAL_PAN_CTRL, phyReg2);
FSL\B36402 15:990a8b5664e1 164 }
FSL\B36402 15:990a8b5664e1 165
FSL\B36402 15:990a8b5664e1 166 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 167 * Name: PhyPpGetDualPanAuto
FSL\B36402 15:990a8b5664e1 168 * Description: -
FSL\B36402 15:990a8b5664e1 169 * Parameters: -
FSL\B36402 15:990a8b5664e1 170 * Return: -
FSL\B36402 15:990a8b5664e1 171 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 172 bool_t PhyPpGetDualPanAuto
FSL\B36402 15:990a8b5664e1 173 (
FSL\B36402 15:990a8b5664e1 174 void
FSL\B36402 15:990a8b5664e1 175 )
FSL\B36402 15:990a8b5664e1 176 {
FSL\B36402 15:990a8b5664e1 177 uint8_t phyReg = MCR20Drv_IndirectAccessSPIRead(DUAL_PAN_CTRL);
FSL\B36402 15:990a8b5664e1 178 return (phyReg & cDUAL_PAN_CTRL_DUAL_PAN_AUTO) == cDUAL_PAN_CTRL_DUAL_PAN_AUTO;
FSL\B36402 15:990a8b5664e1 179 }
FSL\B36402 15:990a8b5664e1 180
FSL\B36402 15:990a8b5664e1 181 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 182 * Name: PhyPpSetDualPanDwell
FSL\B36402 15:990a8b5664e1 183 * Description: -
FSL\B36402 15:990a8b5664e1 184 * Parameters: -
FSL\B36402 15:990a8b5664e1 185 * Return: -
FSL\B36402 15:990a8b5664e1 186 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 187 void PhyPpSetDualPanDwell // TODO: check seq state and return phyStatus_t
FSL\B36402 15:990a8b5664e1 188 (
FSL\B36402 15:990a8b5664e1 189 uint8_t dwell
FSL\B36402 15:990a8b5664e1 190 )
FSL\B36402 15:990a8b5664e1 191 {
FSL\B36402 15:990a8b5664e1 192 MCR20Drv_IndirectAccessSPIWrite( (uint8_t) DUAL_PAN_DWELL, dwell);
FSL\B36402 15:990a8b5664e1 193 }
FSL\B36402 15:990a8b5664e1 194
FSL\B36402 15:990a8b5664e1 195 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 196 * Name: PhyPpGetDualPanDwell
FSL\B36402 15:990a8b5664e1 197 * Description: -
FSL\B36402 15:990a8b5664e1 198 * Parameters: -
FSL\B36402 15:990a8b5664e1 199 * Return: -
FSL\B36402 15:990a8b5664e1 200 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 201 uint8_t PhyPpGetDualPanDwell
FSL\B36402 15:990a8b5664e1 202 (
FSL\B36402 15:990a8b5664e1 203 void
FSL\B36402 15:990a8b5664e1 204 )
FSL\B36402 15:990a8b5664e1 205 {
FSL\B36402 15:990a8b5664e1 206 return MCR20Drv_IndirectAccessSPIRead( (uint8_t) DUAL_PAN_DWELL);
FSL\B36402 15:990a8b5664e1 207 }
FSL\B36402 15:990a8b5664e1 208
FSL\B36402 15:990a8b5664e1 209 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 210 * Name: PhyPpGetDualPanRemain
FSL\B36402 15:990a8b5664e1 211 * Description: -
FSL\B36402 15:990a8b5664e1 212 * Parameters: -
FSL\B36402 15:990a8b5664e1 213 * Return: - the remaining Dwell time
FSL\B36402 15:990a8b5664e1 214 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 215 uint8_t PhyPpGetDualPanRemain()
FSL\B36402 15:990a8b5664e1 216 {
FSL\B36402 15:990a8b5664e1 217 return (MCR20Drv_IndirectAccessSPIRead(DUAL_PAN_STS) & cDUAL_PAN_STS_DUAL_PAN_REMAIN);
FSL\B36402 15:990a8b5664e1 218 }
FSL\B36402 15:990a8b5664e1 219
FSL\B36402 15:990a8b5664e1 220 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 221 * Name: PhyPpSetDualPanSamLvl
FSL\B36402 15:990a8b5664e1 222 * Description: -
FSL\B36402 15:990a8b5664e1 223 * Parameters: -
FSL\B36402 15:990a8b5664e1 224 * Return: -
FSL\B36402 15:990a8b5664e1 225 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 226 void PhyPpSetDualPanSamLvl // TODO: check seq state and return phyStatus_t
FSL\B36402 15:990a8b5664e1 227 (
FSL\B36402 15:990a8b5664e1 228 uint8_t level
FSL\B36402 15:990a8b5664e1 229 )
FSL\B36402 15:990a8b5664e1 230 {
FSL\B36402 15:990a8b5664e1 231 uint8_t phyReg;
FSL\B36402 15:990a8b5664e1 232 #ifdef PHY_PARAMETERS_VALIDATION
FSL\B36402 15:990a8b5664e1 233 if( level > gPhyIndirectQueueSize_c )
FSL\B36402 15:990a8b5664e1 234 return;
FSL\B36402 15:990a8b5664e1 235 #endif
FSL\B36402 15:990a8b5664e1 236 phyReg = MCR20Drv_IndirectAccessSPIRead( (uint8_t) DUAL_PAN_CTRL);
FSL\B36402 15:990a8b5664e1 237
FSL\B36402 15:990a8b5664e1 238 phyReg &= ~cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK; // clear current lvl
FSL\B36402 15:990a8b5664e1 239 phyReg |= level << cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_Shift_c; // set new lvl
FSL\B36402 15:990a8b5664e1 240
FSL\B36402 15:990a8b5664e1 241 MCR20Drv_IndirectAccessSPIWrite( (uint8_t) DUAL_PAN_CTRL, phyReg);
FSL\B36402 15:990a8b5664e1 242 mPhyCurrentSamLvl = level;
FSL\B36402 15:990a8b5664e1 243 }
FSL\B36402 15:990a8b5664e1 244
FSL\B36402 15:990a8b5664e1 245 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 246 * Name: PhyPpGetDualPanSamLvl
FSL\B36402 15:990a8b5664e1 247 * Description: -
FSL\B36402 15:990a8b5664e1 248 * Parameters: -
FSL\B36402 15:990a8b5664e1 249 * Return:
FSL\B36402 15:990a8b5664e1 250 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 251 uint8_t PhyPpGetDualPanSamLvl()
FSL\B36402 15:990a8b5664e1 252 {
FSL\B36402 15:990a8b5664e1 253 return mPhyCurrentSamLvl;
FSL\B36402 15:990a8b5664e1 254 }
FSL\B36402 15:990a8b5664e1 255
FSL\B36402 15:990a8b5664e1 256 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 257 * Name: PhyPpSetDualPanActiveNwk
FSL\B36402 15:990a8b5664e1 258 * Description: - Select Active PAN
FSL\B36402 15:990a8b5664e1 259 * Parameters: -
FSL\B36402 15:990a8b5664e1 260 * Return: -
FSL\B36402 15:990a8b5664e1 261 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 262 void PhyPpSetDualPanActiveNwk // TODO: check seq state and return phyStatus_t
FSL\B36402 15:990a8b5664e1 263 (
FSL\B36402 15:990a8b5664e1 264 uint8_t nwk
FSL\B36402 15:990a8b5664e1 265 )
FSL\B36402 15:990a8b5664e1 266 {
FSL\B36402 15:990a8b5664e1 267 uint8_t phyReg, phyReg2;
FSL\B36402 15:990a8b5664e1 268
FSL\B36402 15:990a8b5664e1 269 phyReg = MCR20Drv_IndirectAccessSPIRead( (uint8_t) DUAL_PAN_CTRL);
FSL\B36402 15:990a8b5664e1 270
FSL\B36402 15:990a8b5664e1 271 if( 0 == nwk )
FSL\B36402 15:990a8b5664e1 272 {
FSL\B36402 15:990a8b5664e1 273 phyReg2 = phyReg & (~cDUAL_PAN_CTRL_ACTIVE_NETWORK);
FSL\B36402 15:990a8b5664e1 274 }
FSL\B36402 15:990a8b5664e1 275 else
FSL\B36402 15:990a8b5664e1 276 {
FSL\B36402 15:990a8b5664e1 277 phyReg2 = phyReg | cDUAL_PAN_CTRL_ACTIVE_NETWORK;
FSL\B36402 15:990a8b5664e1 278 }
FSL\B36402 15:990a8b5664e1 279
FSL\B36402 15:990a8b5664e1 280 /* Write the new value only if it has changed */
FSL\B36402 15:990a8b5664e1 281 if( phyReg2 != phyReg )
FSL\B36402 15:990a8b5664e1 282 {
FSL\B36402 15:990a8b5664e1 283 MCR20Drv_IndirectAccessSPIWrite( (uint8_t) DUAL_PAN_CTRL, phyReg2);
FSL\B36402 15:990a8b5664e1 284 }
FSL\B36402 15:990a8b5664e1 285 }
FSL\B36402 15:990a8b5664e1 286
FSL\B36402 15:990a8b5664e1 287 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 288 * Name: PhyPpGetDualPanActiveNwk
FSL\B36402 15:990a8b5664e1 289 * Description: -
FSL\B36402 15:990a8b5664e1 290 * Parameters: -
FSL\B36402 15:990a8b5664e1 291 * Return: - the Active PAN
FSL\B36402 15:990a8b5664e1 292 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 293 uint8_t PhyPpGetDualPanActiveNwk(void)
FSL\B36402 15:990a8b5664e1 294 {
FSL\B36402 15:990a8b5664e1 295 uint8_t phyReg;
FSL\B36402 15:990a8b5664e1 296
FSL\B36402 15:990a8b5664e1 297 phyReg = MCR20Drv_IndirectAccessSPIRead( (uint8_t)DUAL_PAN_CTRL );
FSL\B36402 15:990a8b5664e1 298
FSL\B36402 15:990a8b5664e1 299 return (phyReg & cDUAL_PAN_CTRL_CURRENT_NETWORK) > 0;
FSL\B36402 15:990a8b5664e1 300 }
FSL\B36402 15:990a8b5664e1 301
FSL\B36402 15:990a8b5664e1 302 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 303 * Name: PhyPpGetDualPanNwkOfRxPacket
FSL\B36402 15:990a8b5664e1 304 * Description: -
FSL\B36402 15:990a8b5664e1 305 * Parameters: -
FSL\B36402 15:990a8b5664e1 306 * Return: - the Active PAN
FSL\B36402 15:990a8b5664e1 307 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 308 uint8_t PhyPpGetPanOfRxPacket(void)
FSL\B36402 15:990a8b5664e1 309 {
FSL\B36402 15:990a8b5664e1 310 uint8_t phyReg;
FSL\B36402 15:990a8b5664e1 311 uint8_t PanBitMask = 0;
FSL\B36402 15:990a8b5664e1 312
FSL\B36402 15:990a8b5664e1 313 phyReg = MCR20Drv_IndirectAccessSPIRead( (uint8_t) DUAL_PAN_STS);
FSL\B36402 15:990a8b5664e1 314
FSL\B36402 15:990a8b5664e1 315 if( phyReg & cDUAL_PAN_STS_RECD_ON_PAN0 )
FSL\B36402 15:990a8b5664e1 316 PanBitMask |= (1<<0);
FSL\B36402 15:990a8b5664e1 317
FSL\B36402 15:990a8b5664e1 318 if( phyReg & cDUAL_PAN_STS_RECD_ON_PAN1 )
FSL\B36402 15:990a8b5664e1 319 PanBitMask |= (1<<1);
FSL\B36402 15:990a8b5664e1 320
FSL\B36402 15:990a8b5664e1 321 return PanBitMask;
FSL\B36402 15:990a8b5664e1 322 }
FSL\B36402 15:990a8b5664e1 323
FSL\B36402 15:990a8b5664e1 324 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 325 * Name: PhyPpSetPromiscuous
FSL\B36402 15:990a8b5664e1 326 * Description: -
FSL\B36402 15:990a8b5664e1 327 * Parameters: -
FSL\B36402 15:990a8b5664e1 328 * Return: -
FSL\B36402 15:990a8b5664e1 329 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 330 void PhyPpSetPromiscuous
FSL\B36402 15:990a8b5664e1 331 (
FSL\B36402 15:990a8b5664e1 332 bool_t mode
FSL\B36402 15:990a8b5664e1 333 )
FSL\B36402 15:990a8b5664e1 334 {
FSL\B36402 15:990a8b5664e1 335 uint8_t rxFrameFltReg, phyCtrl4Reg;
FSL\B36402 15:990a8b5664e1 336
FSL\B36402 15:990a8b5664e1 337 rxFrameFltReg = MCR20Drv_IndirectAccessSPIRead( (uint8_t) RX_FRAME_FILTER);
FSL\B36402 15:990a8b5664e1 338 phyCtrl4Reg = MCR20Drv_DirectAccessSPIRead( (uint8_t) PHY_CTRL4);
FSL\B36402 15:990a8b5664e1 339
FSL\B36402 15:990a8b5664e1 340 if( mode )
FSL\B36402 15:990a8b5664e1 341 {
FSL\B36402 15:990a8b5664e1 342 /* FRM_VER[1:0] = b00. 00: Any FrameVersion accepted (0,1,2 & 3) */
FSL\B36402 15:990a8b5664e1 343 /* All frame types accepted*/
FSL\B36402 15:990a8b5664e1 344 phyCtrl4Reg |= cPHY_CTRL4_PROMISCUOUS;
FSL\B36402 15:990a8b5664e1 345 rxFrameFltReg &= ~(cRX_FRAME_FLT_FRM_VER);
FSL\B36402 15:990a8b5664e1 346 rxFrameFltReg |= (cRX_FRAME_FLT_ACK_FT | cRX_FRAME_FLT_NS_FT);
FSL\B36402 15:990a8b5664e1 347 }
FSL\B36402 15:990a8b5664e1 348 else
FSL\B36402 15:990a8b5664e1 349 {
FSL\B36402 15:990a8b5664e1 350 phyCtrl4Reg &= ~cPHY_CTRL4_PROMISCUOUS;
FSL\B36402 15:990a8b5664e1 351 /* FRM_VER[1:0] = b11. Accept FrameVersion 0 and 1 packets, reject all others */
FSL\B36402 15:990a8b5664e1 352 /* Beacon, Data and MAC command frame types accepted */
FSL\B36402 15:990a8b5664e1 353 rxFrameFltReg &= ~(cRX_FRAME_FLT_FRM_VER);
FSL\B36402 15:990a8b5664e1 354 rxFrameFltReg |= (0x03 << cRX_FRAME_FLT_FRM_VER_Shift_c);
FSL\B36402 15:990a8b5664e1 355 rxFrameFltReg &= ~(cRX_FRAME_FLT_ACK_FT | cRX_FRAME_FLT_NS_FT);
FSL\B36402 15:990a8b5664e1 356 }
FSL\B36402 15:990a8b5664e1 357
FSL\B36402 15:990a8b5664e1 358 MCR20Drv_IndirectAccessSPIWrite( (uint8_t) RX_FRAME_FILTER, rxFrameFltReg);
FSL\B36402 15:990a8b5664e1 359 MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL4, phyCtrl4Reg);
FSL\B36402 15:990a8b5664e1 360 }
FSL\B36402 15:990a8b5664e1 361
FSL\B36402 15:990a8b5664e1 362 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 363 * Name: PhySetActivePromiscuous()
FSL\B36402 15:990a8b5664e1 364 * Description: -
FSL\B36402 15:990a8b5664e1 365 * Parameters: -
FSL\B36402 15:990a8b5664e1 366 * Return: -
FSL\B36402 15:990a8b5664e1 367 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 368 void PhySetActivePromiscuous(bool_t state)
FSL\B36402 15:990a8b5664e1 369 {
FSL\B36402 15:990a8b5664e1 370 uint8_t phyCtrl4Reg;
FSL\B36402 15:990a8b5664e1 371 uint8_t phyFrameFilterReg;
FSL\B36402 15:990a8b5664e1 372 // bool_t currentState;
FSL\B36402 15:990a8b5664e1 373
FSL\B36402 15:990a8b5664e1 374 phyCtrl4Reg = MCR20Drv_DirectAccessSPIRead( (uint8_t) PHY_CTRL4);
FSL\B36402 15:990a8b5664e1 375 phyFrameFilterReg = MCR20Drv_IndirectAccessSPIRead(RX_FRAME_FILTER);
FSL\B36402 15:990a8b5664e1 376
FSL\B36402 15:990a8b5664e1 377 // currentState = (phyFrameFilterReg & cRX_FRAME_FLT_ACTIVE_PROMISCUOUS) ? TRUE : FALSE;
FSL\B36402 15:990a8b5664e1 378 //
FSL\B36402 15:990a8b5664e1 379 // if( state == currentState )
FSL\B36402 15:990a8b5664e1 380 // return;
FSL\B36402 15:990a8b5664e1 381
FSL\B36402 15:990a8b5664e1 382 /* if Prom is set */
FSL\B36402 15:990a8b5664e1 383 if( state )
FSL\B36402 15:990a8b5664e1 384 {
FSL\B36402 15:990a8b5664e1 385 if( phyCtrl4Reg & cPHY_CTRL4_PROMISCUOUS )
FSL\B36402 15:990a8b5664e1 386 {
FSL\B36402 15:990a8b5664e1 387 /* Disable Promiscuous mode */
FSL\B36402 15:990a8b5664e1 388 phyCtrl4Reg &= ~(cPHY_CTRL4_PROMISCUOUS);
FSL\B36402 15:990a8b5664e1 389
FSL\B36402 15:990a8b5664e1 390 /* Enable Active Promiscuous mode */
FSL\B36402 15:990a8b5664e1 391 phyFrameFilterReg |= cRX_FRAME_FLT_ACTIVE_PROMISCUOUS;
FSL\B36402 15:990a8b5664e1 392 }
FSL\B36402 15:990a8b5664e1 393 }
FSL\B36402 15:990a8b5664e1 394 else
FSL\B36402 15:990a8b5664e1 395 {
FSL\B36402 15:990a8b5664e1 396 if( phyFrameFilterReg & cRX_FRAME_FLT_ACTIVE_PROMISCUOUS )
FSL\B36402 15:990a8b5664e1 397 {
FSL\B36402 15:990a8b5664e1 398 /* Disable Active Promiscuous mode */
FSL\B36402 15:990a8b5664e1 399 phyFrameFilterReg &= ~(cRX_FRAME_FLT_ACTIVE_PROMISCUOUS);
FSL\B36402 15:990a8b5664e1 400
FSL\B36402 15:990a8b5664e1 401 /* Enable Promiscuous mode */
FSL\B36402 15:990a8b5664e1 402 phyCtrl4Reg |= cPHY_CTRL4_PROMISCUOUS;
FSL\B36402 15:990a8b5664e1 403 }
FSL\B36402 15:990a8b5664e1 404 }
FSL\B36402 15:990a8b5664e1 405
FSL\B36402 15:990a8b5664e1 406 MCR20Drv_DirectAccessSPIWrite((uint8_t) PHY_CTRL4, phyCtrl4Reg);
FSL\B36402 15:990a8b5664e1 407 MCR20Drv_IndirectAccessSPIWrite(RX_FRAME_FILTER, phyFrameFilterReg);
FSL\B36402 15:990a8b5664e1 408 }
FSL\B36402 15:990a8b5664e1 409
FSL\B36402 15:990a8b5664e1 410 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 411 * Name: PhyGetActivePromiscuous()
FSL\B36402 15:990a8b5664e1 412 * Description: - returns the state of ActivePromiscuous feature (Enabled/Disabled)
FSL\B36402 15:990a8b5664e1 413 * Parameters: -
FSL\B36402 15:990a8b5664e1 414 * Return: - TRUE/FALSE
FSL\B36402 15:990a8b5664e1 415 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 416 bool_t PhyGetActivePromiscuous( void )
FSL\B36402 15:990a8b5664e1 417 {
FSL\B36402 15:990a8b5664e1 418 uint8_t phyReg = MCR20Drv_IndirectAccessSPIRead(RX_FRAME_FILTER);
FSL\B36402 15:990a8b5664e1 419
FSL\B36402 15:990a8b5664e1 420 if( phyReg & cRX_FRAME_FLT_ACTIVE_PROMISCUOUS )
FSL\B36402 15:990a8b5664e1 421 return TRUE;
FSL\B36402 15:990a8b5664e1 422
FSL\B36402 15:990a8b5664e1 423 return FALSE;
FSL\B36402 15:990a8b5664e1 424 }
FSL\B36402 15:990a8b5664e1 425
FSL\B36402 15:990a8b5664e1 426 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 427 * Name: PhyPpSetPanId
FSL\B36402 15:990a8b5664e1 428 * Description: -
FSL\B36402 15:990a8b5664e1 429 * Parameters: -
FSL\B36402 15:990a8b5664e1 430 * Return: -
FSL\B36402 15:990a8b5664e1 431 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 432 phyStatus_t PhyPpSetPanId
FSL\B36402 15:990a8b5664e1 433 (
FSL\B36402 15:990a8b5664e1 434 uint8_t *pPanId,
FSL\B36402 15:990a8b5664e1 435 uint8_t pan
FSL\B36402 15:990a8b5664e1 436 )
FSL\B36402 15:990a8b5664e1 437 {
FSL\B36402 15:990a8b5664e1 438 #ifdef PHY_PARAMETERS_VALIDATION
FSL\B36402 15:990a8b5664e1 439 if(NULL == pPanId)
FSL\B36402 15:990a8b5664e1 440 {
FSL\B36402 15:990a8b5664e1 441 return gPhyInvalidParameter_c;
FSL\B36402 15:990a8b5664e1 442 }
FSL\B36402 15:990a8b5664e1 443 #endif // PHY_PARAMETERS_VALIDATION
FSL\B36402 15:990a8b5664e1 444
FSL\B36402 15:990a8b5664e1 445 if( 0 == pan )
FSL\B36402 15:990a8b5664e1 446 MCR20Drv_IndirectAccessSPIMultiByteWrite((uint8_t) MACPANID0_LSB, pPanId, 2);
FSL\B36402 15:990a8b5664e1 447 else
FSL\B36402 15:990a8b5664e1 448 MCR20Drv_IndirectAccessSPIMultiByteWrite((uint8_t) MACPANID1_LSB, pPanId, 2);
FSL\B36402 15:990a8b5664e1 449
FSL\B36402 15:990a8b5664e1 450 return gPhySuccess_c;
FSL\B36402 15:990a8b5664e1 451 }
FSL\B36402 15:990a8b5664e1 452
FSL\B36402 15:990a8b5664e1 453
FSL\B36402 15:990a8b5664e1 454 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 455 * Name: PhyPpSetShortAddr
FSL\B36402 15:990a8b5664e1 456 * Description: -
FSL\B36402 15:990a8b5664e1 457 * Parameters: -
FSL\B36402 15:990a8b5664e1 458 * Return: -
FSL\B36402 15:990a8b5664e1 459 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 460 phyStatus_t PhyPpSetShortAddr
FSL\B36402 15:990a8b5664e1 461 (
FSL\B36402 15:990a8b5664e1 462 uint8_t *pShortAddr,
FSL\B36402 15:990a8b5664e1 463 uint8_t pan
FSL\B36402 15:990a8b5664e1 464 )
FSL\B36402 15:990a8b5664e1 465 {
FSL\B36402 15:990a8b5664e1 466
FSL\B36402 15:990a8b5664e1 467 #ifdef PHY_PARAMETERS_VALIDATION
FSL\B36402 15:990a8b5664e1 468 if(NULL == pShortAddr)
FSL\B36402 15:990a8b5664e1 469 {
FSL\B36402 15:990a8b5664e1 470 return gPhyInvalidParameter_c;
FSL\B36402 15:990a8b5664e1 471 }
FSL\B36402 15:990a8b5664e1 472 #endif // PHY_PARAMETERS_VALIDATION
FSL\B36402 15:990a8b5664e1 473
FSL\B36402 15:990a8b5664e1 474 if( pan == 0 )
FSL\B36402 15:990a8b5664e1 475 {
FSL\B36402 15:990a8b5664e1 476 MCR20Drv_IndirectAccessSPIMultiByteWrite((uint8_t) MACSHORTADDRS0_LSB, pShortAddr, 2);
FSL\B36402 15:990a8b5664e1 477 }
FSL\B36402 15:990a8b5664e1 478 else
FSL\B36402 15:990a8b5664e1 479 {
FSL\B36402 15:990a8b5664e1 480 MCR20Drv_IndirectAccessSPIMultiByteWrite((uint8_t) MACSHORTADDRS1_LSB, pShortAddr, 2);
FSL\B36402 15:990a8b5664e1 481 }
FSL\B36402 15:990a8b5664e1 482
FSL\B36402 15:990a8b5664e1 483 return gPhySuccess_c;
FSL\B36402 15:990a8b5664e1 484 }
FSL\B36402 15:990a8b5664e1 485
FSL\B36402 15:990a8b5664e1 486 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 487 * Name: PhyPpSetLongAddr
FSL\B36402 15:990a8b5664e1 488 * Description: -
FSL\B36402 15:990a8b5664e1 489 * Parameters: -
FSL\B36402 15:990a8b5664e1 490 * Return: -
FSL\B36402 15:990a8b5664e1 491 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 492 phyStatus_t PhyPpSetLongAddr
FSL\B36402 15:990a8b5664e1 493 (
FSL\B36402 15:990a8b5664e1 494 uint8_t *pLongAddr,
FSL\B36402 15:990a8b5664e1 495 uint8_t pan
FSL\B36402 15:990a8b5664e1 496 )
FSL\B36402 15:990a8b5664e1 497 {
FSL\B36402 15:990a8b5664e1 498
FSL\B36402 15:990a8b5664e1 499 #ifdef PHY_PARAMETERS_VALIDATION
FSL\B36402 15:990a8b5664e1 500 if(NULL == pLongAddr)
FSL\B36402 15:990a8b5664e1 501 {
FSL\B36402 15:990a8b5664e1 502 return gPhyInvalidParameter_c;
FSL\B36402 15:990a8b5664e1 503 }
FSL\B36402 15:990a8b5664e1 504 #endif // PHY_PARAMETERS_VALIDATION
FSL\B36402 15:990a8b5664e1 505
FSL\B36402 15:990a8b5664e1 506 if( 0 == pan )
FSL\B36402 15:990a8b5664e1 507 MCR20Drv_IndirectAccessSPIMultiByteWrite((uint8_t) MACLONGADDRS0_0, pLongAddr, 8);
FSL\B36402 15:990a8b5664e1 508 else
FSL\B36402 15:990a8b5664e1 509 MCR20Drv_IndirectAccessSPIMultiByteWrite((uint8_t) MACLONGADDRS1_0, pLongAddr, 8);
FSL\B36402 15:990a8b5664e1 510
FSL\B36402 15:990a8b5664e1 511 return gPhySuccess_c;
FSL\B36402 15:990a8b5664e1 512 }
FSL\B36402 15:990a8b5664e1 513
FSL\B36402 15:990a8b5664e1 514
FSL\B36402 15:990a8b5664e1 515 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 516 * Name: PhyPpSetMacRole
FSL\B36402 15:990a8b5664e1 517 * Description: -
FSL\B36402 15:990a8b5664e1 518 * Parameters: -
FSL\B36402 15:990a8b5664e1 519 * Return: -
FSL\B36402 15:990a8b5664e1 520 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 521 phyStatus_t PhyPpSetMacRole
FSL\B36402 15:990a8b5664e1 522 (
FSL\B36402 15:990a8b5664e1 523 bool_t macRole,
FSL\B36402 15:990a8b5664e1 524 uint8_t pan
FSL\B36402 15:990a8b5664e1 525 )
FSL\B36402 15:990a8b5664e1 526 {
FSL\B36402 15:990a8b5664e1 527 uint8_t phyReg;
FSL\B36402 15:990a8b5664e1 528
FSL\B36402 15:990a8b5664e1 529 if( 0 == pan )
FSL\B36402 15:990a8b5664e1 530 {
FSL\B36402 15:990a8b5664e1 531 phyReg = MCR20Drv_DirectAccessSPIRead( (uint8_t) PHY_CTRL4);
FSL\B36402 15:990a8b5664e1 532
FSL\B36402 15:990a8b5664e1 533 if(gMacRole_PanCoord_c == macRole)
FSL\B36402 15:990a8b5664e1 534 {
FSL\B36402 15:990a8b5664e1 535 phyReg |= cPHY_CTRL4_PANCORDNTR0;
FSL\B36402 15:990a8b5664e1 536 }
FSL\B36402 15:990a8b5664e1 537 else
FSL\B36402 15:990a8b5664e1 538 {
FSL\B36402 15:990a8b5664e1 539 phyReg &= ~cPHY_CTRL4_PANCORDNTR0;
FSL\B36402 15:990a8b5664e1 540 }
FSL\B36402 15:990a8b5664e1 541 MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL4, phyReg);
FSL\B36402 15:990a8b5664e1 542 }
FSL\B36402 15:990a8b5664e1 543 else
FSL\B36402 15:990a8b5664e1 544 {
FSL\B36402 15:990a8b5664e1 545 phyReg = MCR20Drv_IndirectAccessSPIRead( (uint8_t) DUAL_PAN_CTRL);
FSL\B36402 15:990a8b5664e1 546
FSL\B36402 15:990a8b5664e1 547 if(gMacRole_PanCoord_c == macRole)
FSL\B36402 15:990a8b5664e1 548 {
FSL\B36402 15:990a8b5664e1 549 phyReg |= cDUAL_PAN_CTRL_PANCORDNTR1;
FSL\B36402 15:990a8b5664e1 550 }
FSL\B36402 15:990a8b5664e1 551 else
FSL\B36402 15:990a8b5664e1 552 {
FSL\B36402 15:990a8b5664e1 553 phyReg &= ~cDUAL_PAN_CTRL_PANCORDNTR1;
FSL\B36402 15:990a8b5664e1 554 }
FSL\B36402 15:990a8b5664e1 555 MCR20Drv_IndirectAccessSPIWrite( (uint8_t) DUAL_PAN_CTRL, phyReg);
FSL\B36402 15:990a8b5664e1 556 }
FSL\B36402 15:990a8b5664e1 557
FSL\B36402 15:990a8b5664e1 558 return gPhySuccess_c;
FSL\B36402 15:990a8b5664e1 559 }
FSL\B36402 15:990a8b5664e1 560
FSL\B36402 15:990a8b5664e1 561 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 562 * Name: PhyPpIsTxAckDataPending
FSL\B36402 15:990a8b5664e1 563 * Description: -
FSL\B36402 15:990a8b5664e1 564 * Parameters: -
FSL\B36402 15:990a8b5664e1 565 * Return: -
FSL\B36402 15:990a8b5664e1 566 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 567 bool_t PhyPpIsTxAckDataPending
FSL\B36402 15:990a8b5664e1 568 (
FSL\B36402 15:990a8b5664e1 569 void
FSL\B36402 15:990a8b5664e1 570 )
FSL\B36402 15:990a8b5664e1 571 {
FSL\B36402 15:990a8b5664e1 572 uint8_t srcCtrlReg;
FSL\B36402 15:990a8b5664e1 573
FSL\B36402 15:990a8b5664e1 574 srcCtrlReg = MCR20Drv_DirectAccessSPIRead(SRC_CTRL);
FSL\B36402 15:990a8b5664e1 575 if( srcCtrlReg & cSRC_CTRL_SRCADDR_EN )
FSL\B36402 15:990a8b5664e1 576 {
FSL\B36402 15:990a8b5664e1 577 uint8_t irqsts2Reg;
FSL\B36402 15:990a8b5664e1 578
FSL\B36402 15:990a8b5664e1 579 irqsts2Reg = MCR20Drv_DirectAccessSPIRead((uint8_t) IRQSTS2);
FSL\B36402 15:990a8b5664e1 580
FSL\B36402 15:990a8b5664e1 581 if(irqsts2Reg & cIRQSTS2_SRCADDR)
FSL\B36402 15:990a8b5664e1 582 return TRUE;
FSL\B36402 15:990a8b5664e1 583 else
FSL\B36402 15:990a8b5664e1 584 return FALSE;
FSL\B36402 15:990a8b5664e1 585 }
FSL\B36402 15:990a8b5664e1 586 else
FSL\B36402 15:990a8b5664e1 587 {
FSL\B36402 15:990a8b5664e1 588 return ((srcCtrlReg & cSRC_CTRL_ACK_FRM_PND) == cSRC_CTRL_ACK_FRM_PND);
FSL\B36402 15:990a8b5664e1 589 }
FSL\B36402 15:990a8b5664e1 590 }
FSL\B36402 15:990a8b5664e1 591
FSL\B36402 15:990a8b5664e1 592 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 593 * Name: PhyPpIsRxAckDataPending
FSL\B36402 15:990a8b5664e1 594 * Description: -
FSL\B36402 15:990a8b5664e1 595 * Parameters: -
FSL\B36402 15:990a8b5664e1 596 * Return: -
FSL\B36402 15:990a8b5664e1 597 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 598 bool_t PhyPpIsRxAckDataPending
FSL\B36402 15:990a8b5664e1 599 (
FSL\B36402 15:990a8b5664e1 600 void
FSL\B36402 15:990a8b5664e1 601 )
FSL\B36402 15:990a8b5664e1 602 {
FSL\B36402 15:990a8b5664e1 603 uint8_t irqsts1Reg;
FSL\B36402 15:990a8b5664e1 604 irqsts1Reg = MCR20Drv_DirectAccessSPIRead((uint8_t) IRQSTS1);
FSL\B36402 15:990a8b5664e1 605 if(irqsts1Reg & cIRQSTS1_RX_FRM_PEND)
FSL\B36402 15:990a8b5664e1 606 {
FSL\B36402 15:990a8b5664e1 607 return TRUE;
FSL\B36402 15:990a8b5664e1 608 }
FSL\B36402 15:990a8b5664e1 609 return FALSE;
FSL\B36402 15:990a8b5664e1 610 }
FSL\B36402 15:990a8b5664e1 611
FSL\B36402 15:990a8b5664e1 612 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 613 * Name: PhyPpSetFpManually
FSL\B36402 15:990a8b5664e1 614 * Description: -
FSL\B36402 15:990a8b5664e1 615 * Parameters: -
FSL\B36402 15:990a8b5664e1 616 * Return: -
FSL\B36402 15:990a8b5664e1 617 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 618 void PhyPpSetFpManually
FSL\B36402 15:990a8b5664e1 619 (
FSL\B36402 15:990a8b5664e1 620 bool_t FP
FSL\B36402 15:990a8b5664e1 621 )
FSL\B36402 15:990a8b5664e1 622 {
FSL\B36402 15:990a8b5664e1 623 uint8_t phyReg;
FSL\B36402 15:990a8b5664e1 624 /* Disable the Source Address Matching feature and set FP manually */
FSL\B36402 15:990a8b5664e1 625 phyReg = MCR20Drv_DirectAccessSPIRead(SRC_CTRL);
FSL\B36402 15:990a8b5664e1 626 phyReg &= ~(cSRC_CTRL_SRCADDR_EN);
FSL\B36402 15:990a8b5664e1 627 if(FP)
FSL\B36402 15:990a8b5664e1 628 phyReg |= cSRC_CTRL_ACK_FRM_PND;
FSL\B36402 15:990a8b5664e1 629 else
FSL\B36402 15:990a8b5664e1 630 phyReg &= ~(cSRC_CTRL_ACK_FRM_PND);
FSL\B36402 15:990a8b5664e1 631 MCR20Drv_DirectAccessSPIWrite(SRC_CTRL, phyReg);
FSL\B36402 15:990a8b5664e1 632 }
FSL\B36402 15:990a8b5664e1 633
FSL\B36402 15:990a8b5664e1 634 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 635 * Name: PhyPpIsPollIndication
FSL\B36402 15:990a8b5664e1 636 * Description: -
FSL\B36402 15:990a8b5664e1 637 * Parameters: -
FSL\B36402 15:990a8b5664e1 638 * Return: -
FSL\B36402 15:990a8b5664e1 639 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 640 bool_t PhyPpIsPollIndication
FSL\B36402 15:990a8b5664e1 641 (
FSL\B36402 15:990a8b5664e1 642 void
FSL\B36402 15:990a8b5664e1 643 )
FSL\B36402 15:990a8b5664e1 644 {
FSL\B36402 15:990a8b5664e1 645 uint8_t irqsts2Reg;
FSL\B36402 15:990a8b5664e1 646 irqsts2Reg = MCR20Drv_DirectAccessSPIRead((uint8_t) IRQSTS2);
FSL\B36402 15:990a8b5664e1 647 if(irqsts2Reg & cIRQSTS2_PI)
FSL\B36402 15:990a8b5664e1 648 {
FSL\B36402 15:990a8b5664e1 649 return TRUE;
FSL\B36402 15:990a8b5664e1 650 }
FSL\B36402 15:990a8b5664e1 651 return FALSE;
FSL\B36402 15:990a8b5664e1 652 }
FSL\B36402 15:990a8b5664e1 653
FSL\B36402 15:990a8b5664e1 654 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 655 * Name: PhyPpSetCcaThreshold
FSL\B36402 15:990a8b5664e1 656 * Description: -
FSL\B36402 15:990a8b5664e1 657 * Parameters: -
FSL\B36402 15:990a8b5664e1 658 * Return: -
FSL\B36402 15:990a8b5664e1 659 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 660 phyStatus_t PhyPpSetCcaThreshold(uint8_t ccaThreshold)
FSL\B36402 15:990a8b5664e1 661 {
FSL\B36402 15:990a8b5664e1 662 MCR20Drv_IndirectAccessSPIWrite((uint8_t) CCA1_THRESH, (uint8_t) ccaThreshold);
FSL\B36402 15:990a8b5664e1 663 return gPhySuccess_c;
FSL\B36402 15:990a8b5664e1 664 }
FSL\B36402 15:990a8b5664e1 665
FSL\B36402 15:990a8b5664e1 666 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 667 * Name: PhyPpSetSAMState
FSL\B36402 15:990a8b5664e1 668 * Description: -
FSL\B36402 15:990a8b5664e1 669 * Parameters: -
FSL\B36402 15:990a8b5664e1 670 * Return: -
FSL\B36402 15:990a8b5664e1 671 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 672 void PhyPpSetSAMState
FSL\B36402 15:990a8b5664e1 673 (
FSL\B36402 15:990a8b5664e1 674 bool_t state
FSL\B36402 15:990a8b5664e1 675 )
FSL\B36402 15:990a8b5664e1 676 {
FSL\B36402 15:990a8b5664e1 677 uint8_t phyReg, newPhyReg;
FSL\B36402 15:990a8b5664e1 678 /* Disable/Enables the Source Address Matching feature */
FSL\B36402 15:990a8b5664e1 679 phyReg = MCR20Drv_DirectAccessSPIRead(SRC_CTRL);
FSL\B36402 15:990a8b5664e1 680 if( state )
FSL\B36402 15:990a8b5664e1 681 newPhyReg = phyReg | cSRC_CTRL_SRCADDR_EN;
FSL\B36402 15:990a8b5664e1 682 else
FSL\B36402 15:990a8b5664e1 683 newPhyReg = phyReg & ~(cSRC_CTRL_SRCADDR_EN);
FSL\B36402 15:990a8b5664e1 684
FSL\B36402 15:990a8b5664e1 685 if( newPhyReg != phyReg )
FSL\B36402 15:990a8b5664e1 686 MCR20Drv_DirectAccessSPIWrite(SRC_CTRL, newPhyReg);
FSL\B36402 15:990a8b5664e1 687 }
FSL\B36402 15:990a8b5664e1 688
FSL\B36402 15:990a8b5664e1 689
FSL\B36402 15:990a8b5664e1 690 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 691 * Name: PhyPlmeSetFADStateRequest
FSL\B36402 15:990a8b5664e1 692 * Description: -
FSL\B36402 15:990a8b5664e1 693 * Parameters: -
FSL\B36402 15:990a8b5664e1 694 * Return: -
FSL\B36402 15:990a8b5664e1 695 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 696 uint8_t PhyPlmeSetFADStateRequest(bool_t state)
FSL\B36402 15:990a8b5664e1 697 {
FSL\B36402 15:990a8b5664e1 698 uint8_t phyReg;
FSL\B36402 15:990a8b5664e1 699
FSL\B36402 15:990a8b5664e1 700 phyReg = MCR20Drv_IndirectAccessSPIRead(ANT_AGC_CTRL);
FSL\B36402 15:990a8b5664e1 701 state ? (phyReg |= cANT_AGC_CTRL_FAD_EN_Mask_c) : (phyReg &= (~((uint8_t)cANT_AGC_CTRL_FAD_EN_Mask_c)));
FSL\B36402 15:990a8b5664e1 702 MCR20Drv_IndirectAccessSPIWrite(ANT_AGC_CTRL, phyReg);
FSL\B36402 15:990a8b5664e1 703
FSL\B36402 15:990a8b5664e1 704 phyReg = MCR20Drv_IndirectAccessSPIRead(ANT_PAD_CTRL);
FSL\B36402 15:990a8b5664e1 705 state ? (phyReg |= 0x02) : (phyReg &= ~cANT_PAD_CTRL_ANTX_EN);
FSL\B36402 15:990a8b5664e1 706 MCR20Drv_IndirectAccessSPIWrite(ANT_PAD_CTRL, phyReg);
FSL\B36402 15:990a8b5664e1 707
FSL\B36402 15:990a8b5664e1 708 return gPhySuccess_c;
FSL\B36402 15:990a8b5664e1 709 }
FSL\B36402 15:990a8b5664e1 710
FSL\B36402 15:990a8b5664e1 711 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 712 * Name: PhyPlmeSetFADThresholdRequest
FSL\B36402 15:990a8b5664e1 713 * Description: -
FSL\B36402 15:990a8b5664e1 714 * Parameters: -
FSL\B36402 15:990a8b5664e1 715 * Return: -
FSL\B36402 15:990a8b5664e1 716 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 717 uint8_t PhyPlmeSetFADThresholdRequest(uint8_t FADThreshold)
FSL\B36402 15:990a8b5664e1 718 {
FSL\B36402 15:990a8b5664e1 719 MCR20Drv_IndirectAccessSPIWrite(FAD_THR, FADThreshold);
FSL\B36402 15:990a8b5664e1 720 return gPhySuccess_c;
FSL\B36402 15:990a8b5664e1 721 }
FSL\B36402 15:990a8b5664e1 722
FSL\B36402 15:990a8b5664e1 723 uint8_t PhyPlmeSetANTPadStateRequest(bool_t antAB_on, bool_t rxtxSwitch_on)
FSL\B36402 15:990a8b5664e1 724 {
FSL\B36402 15:990a8b5664e1 725 uint8_t phyReg;
FSL\B36402 15:990a8b5664e1 726
FSL\B36402 15:990a8b5664e1 727 phyReg = MCR20Drv_IndirectAccessSPIRead(ANT_PAD_CTRL);
FSL\B36402 15:990a8b5664e1 728 antAB_on ? (phyReg |= 0x02) : (phyReg &= ~0x02);
FSL\B36402 15:990a8b5664e1 729 rxtxSwitch_on ? (phyReg |= 0x01) : (phyReg &= ~0x01);
FSL\B36402 15:990a8b5664e1 730 MCR20Drv_IndirectAccessSPIWrite(ANT_PAD_CTRL, phyReg);
FSL\B36402 15:990a8b5664e1 731
FSL\B36402 15:990a8b5664e1 732 return gPhySuccess_c;
FSL\B36402 15:990a8b5664e1 733 }
FSL\B36402 15:990a8b5664e1 734
FSL\B36402 15:990a8b5664e1 735 uint8_t PhyPlmeSetANTPadStrengthRequest(bool_t hiStrength)
FSL\B36402 15:990a8b5664e1 736 {
FSL\B36402 15:990a8b5664e1 737 uint8_t phyReg;
FSL\B36402 15:990a8b5664e1 738
FSL\B36402 15:990a8b5664e1 739 phyReg = MCR20Drv_IndirectAccessSPIRead(MISC_PAD_CTRL);
FSL\B36402 15:990a8b5664e1 740 hiStrength ? (phyReg |= cMISC_PAD_CTRL_ANTX_CURR) : (phyReg &= ~cMISC_PAD_CTRL_ANTX_CURR);
FSL\B36402 15:990a8b5664e1 741 MCR20Drv_IndirectAccessSPIWrite(MISC_PAD_CTRL, phyReg);
FSL\B36402 15:990a8b5664e1 742
FSL\B36402 15:990a8b5664e1 743 return gPhySuccess_c;
FSL\B36402 15:990a8b5664e1 744 }
FSL\B36402 15:990a8b5664e1 745
FSL\B36402 15:990a8b5664e1 746 uint8_t PhyPlmeSetANTPadInvertedRequest(bool_t invAntA, bool_t invAntB, bool_t invTx, bool_t invRx)
FSL\B36402 15:990a8b5664e1 747 {
FSL\B36402 15:990a8b5664e1 748 uint8_t phyReg;
FSL\B36402 15:990a8b5664e1 749
FSL\B36402 15:990a8b5664e1 750 phyReg = MCR20Drv_IndirectAccessSPIRead(MISC_PAD_CTRL);
FSL\B36402 15:990a8b5664e1 751 invAntA ? (phyReg |= 0x10) : (phyReg &= ~0x10);
FSL\B36402 15:990a8b5664e1 752 invAntB ? (phyReg |= 0x20) : (phyReg &= ~0x20);
FSL\B36402 15:990a8b5664e1 753 invTx ? (phyReg |= 0x40) : (phyReg &= ~0x40);
FSL\B36402 15:990a8b5664e1 754 invRx ? (phyReg |= 0x80) : (phyReg &= ~0x80);
FSL\B36402 15:990a8b5664e1 755 MCR20Drv_IndirectAccessSPIWrite(MISC_PAD_CTRL, phyReg);
FSL\B36402 15:990a8b5664e1 756
FSL\B36402 15:990a8b5664e1 757 return gPhySuccess_c;
FSL\B36402 15:990a8b5664e1 758 }
FSL\B36402 15:990a8b5664e1 759
FSL\B36402 15:990a8b5664e1 760 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 761 * Name: PhyPlmeSetANTXStateRequest
FSL\B36402 15:990a8b5664e1 762 * Description: -
FSL\B36402 15:990a8b5664e1 763 * Parameters: -
FSL\B36402 15:990a8b5664e1 764 * Return: -
FSL\B36402 15:990a8b5664e1 765 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 766 uint8_t PhyPlmeSetANTXStateRequest(bool_t state)
FSL\B36402 15:990a8b5664e1 767 {
FSL\B36402 15:990a8b5664e1 768 uint8_t phyReg;
FSL\B36402 15:990a8b5664e1 769
FSL\B36402 15:990a8b5664e1 770 phyReg = MCR20Drv_IndirectAccessSPIRead(ANT_AGC_CTRL);
FSL\B36402 15:990a8b5664e1 771 state ? (phyReg |= cANT_AGC_CTRL_ANTX_Mask_c) : (phyReg &= (~((uint8_t)cANT_AGC_CTRL_ANTX_Mask_c)));
FSL\B36402 15:990a8b5664e1 772 MCR20Drv_IndirectAccessSPIWrite(ANT_AGC_CTRL, phyReg);
FSL\B36402 15:990a8b5664e1 773
FSL\B36402 15:990a8b5664e1 774 return gPhySuccess_c;
FSL\B36402 15:990a8b5664e1 775 }
FSL\B36402 15:990a8b5664e1 776
FSL\B36402 15:990a8b5664e1 777 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 778 * Name: PhyPlmeGetANTXStateRequest
FSL\B36402 15:990a8b5664e1 779 * Description: -
FSL\B36402 15:990a8b5664e1 780 * Parameters: -
FSL\B36402 15:990a8b5664e1 781 * Return: -
FSL\B36402 15:990a8b5664e1 782 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 783 uint8_t PhyPlmeGetANTXStateRequest(void)
FSL\B36402 15:990a8b5664e1 784 {
FSL\B36402 15:990a8b5664e1 785 uint8_t phyReg;
FSL\B36402 15:990a8b5664e1 786
FSL\B36402 15:990a8b5664e1 787 phyReg = MCR20Drv_IndirectAccessSPIRead(ANT_AGC_CTRL);
FSL\B36402 15:990a8b5664e1 788
FSL\B36402 15:990a8b5664e1 789 return ((phyReg & cANT_AGC_CTRL_ANTX_Mask_c) == cANT_AGC_CTRL_ANTX_Mask_c);
FSL\B36402 15:990a8b5664e1 790 }
FSL\B36402 15:990a8b5664e1 791
FSL\B36402 15:990a8b5664e1 792 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 793 * Name: PhyPp_IndirectQueueInsert
FSL\B36402 15:990a8b5664e1 794 * Description: -
FSL\B36402 15:990a8b5664e1 795 * Parameters: -
FSL\B36402 15:990a8b5664e1 796 * Return: -
FSL\B36402 15:990a8b5664e1 797 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 798 phyStatus_t PhyPp_IndirectQueueInsert // TODO: to validate add to indirect queue parameters
FSL\B36402 15:990a8b5664e1 799 (
FSL\B36402 15:990a8b5664e1 800 uint8_t index,
FSL\B36402 15:990a8b5664e1 801 uint16_t checkSum,
FSL\B36402 15:990a8b5664e1 802 instanceId_t instanceId
FSL\B36402 15:990a8b5664e1 803 )
FSL\B36402 15:990a8b5664e1 804 {
FSL\B36402 15:990a8b5664e1 805 uint16_t srcAddressCheckSum = checkSum;
FSL\B36402 15:990a8b5664e1 806 uint8_t srcCtrlReg;
FSL\B36402 15:990a8b5664e1 807
FSL\B36402 15:990a8b5664e1 808 if( index >= gPhyIndirectQueueSize_c )
FSL\B36402 15:990a8b5664e1 809 return gPhyInvalidParameter_c;
FSL\B36402 15:990a8b5664e1 810
FSL\B36402 15:990a8b5664e1 811 srcCtrlReg = (uint8_t) ( (index & cSRC_CTRL_INDEX) << cSRC_CTRL_INDEX_Shift_c );
FSL\B36402 15:990a8b5664e1 812 MCR20Drv_DirectAccessSPIWrite( (uint8_t) SRC_CTRL, srcCtrlReg);
FSL\B36402 15:990a8b5664e1 813
FSL\B36402 15:990a8b5664e1 814 MCR20Drv_DirectAccessSPIMultiByteWrite( (uint8_t) SRC_ADDRS_SUM_LSB, (uint8_t *) &srcAddressCheckSum, 2);
FSL\B36402 15:990a8b5664e1 815
FSL\B36402 15:990a8b5664e1 816 srcCtrlReg |= ( cSRC_CTRL_SRCADDR_EN | cSRC_CTRL_INDEX_EN );
FSL\B36402 15:990a8b5664e1 817 MCR20Drv_DirectAccessSPIWrite( (uint8_t) SRC_CTRL, srcCtrlReg);
FSL\B36402 15:990a8b5664e1 818
FSL\B36402 15:990a8b5664e1 819 return gPhySuccess_c;
FSL\B36402 15:990a8b5664e1 820
FSL\B36402 15:990a8b5664e1 821 }
FSL\B36402 15:990a8b5664e1 822
FSL\B36402 15:990a8b5664e1 823
FSL\B36402 15:990a8b5664e1 824 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 825 * Name: PhyPp_RemoveFromIndirect
FSL\B36402 15:990a8b5664e1 826 * Description: -
FSL\B36402 15:990a8b5664e1 827 * Parameters: -
FSL\B36402 15:990a8b5664e1 828 * Return: -
FSL\B36402 15:990a8b5664e1 829 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 830 phyStatus_t PhyPp_RemoveFromIndirect
FSL\B36402 15:990a8b5664e1 831 (
FSL\B36402 15:990a8b5664e1 832 uint8_t index,
FSL\B36402 15:990a8b5664e1 833 instanceId_t instanceId
FSL\B36402 15:990a8b5664e1 834 )
FSL\B36402 15:990a8b5664e1 835 {
FSL\B36402 15:990a8b5664e1 836 uint8_t srcCtrlReg;
FSL\B36402 15:990a8b5664e1 837
FSL\B36402 15:990a8b5664e1 838 if( index >= gPhyIndirectQueueSize_c )
FSL\B36402 15:990a8b5664e1 839 return gPhyInvalidParameter_c;
FSL\B36402 15:990a8b5664e1 840
FSL\B36402 15:990a8b5664e1 841 srcCtrlReg = (uint8_t)( ( (index & cSRC_CTRL_INDEX) << cSRC_CTRL_INDEX_Shift_c )
FSL\B36402 15:990a8b5664e1 842 |( cSRC_CTRL_SRCADDR_EN )
FSL\B36402 15:990a8b5664e1 843 |( cSRC_CTRL_INDEX_DISABLE) );
FSL\B36402 15:990a8b5664e1 844
FSL\B36402 15:990a8b5664e1 845 MCR20Drv_DirectAccessSPIWrite( (uint8_t) SRC_CTRL, srcCtrlReg);
FSL\B36402 15:990a8b5664e1 846
FSL\B36402 15:990a8b5664e1 847 return gPhySuccess_c;
FSL\B36402 15:990a8b5664e1 848 }
FSL\B36402 15:990a8b5664e1 849
FSL\B36402 15:990a8b5664e1 850
FSL\B36402 15:990a8b5664e1 851 /*---------------------------------------------------------------------------
FSL\B36402 15:990a8b5664e1 852 * Name: PhyPpGetState
FSL\B36402 15:990a8b5664e1 853 * Description: -
FSL\B36402 15:990a8b5664e1 854 * Parameters: -
FSL\B36402 15:990a8b5664e1 855 * Return: -
FSL\B36402 15:990a8b5664e1 856 *---------------------------------------------------------------------------*/
FSL\B36402 15:990a8b5664e1 857 uint8_t PhyPpGetState
FSL\B36402 15:990a8b5664e1 858 (
FSL\B36402 15:990a8b5664e1 859 void
FSL\B36402 15:990a8b5664e1 860 )
FSL\B36402 15:990a8b5664e1 861 {
FSL\B36402 15:990a8b5664e1 862 return (uint8_t)( MCR20Drv_DirectAccessSPIRead( (uint8_t) PHY_CTRL1) & cPHY_CTRL1_XCVSEQ );
FSL\B36402 15:990a8b5664e1 863 }
FSL\B36402 15:990a8b5664e1 864
FSL\B36402 15:990a8b5664e1 865 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 866 * \brief Aborts the current sequence and force the radio to IDLE
FSL\B36402 15:990a8b5664e1 867 *
FSL\B36402 15:990a8b5664e1 868 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 869 void PhyAbort(void)
FSL\B36402 15:990a8b5664e1 870 {
FSL\B36402 15:990a8b5664e1 871 uint8_t phyRegs[8];
FSL\B36402 15:990a8b5664e1 872 volatile uint8_t currentTime = 0;
FSL\B36402 15:990a8b5664e1 873
FSL\B36402 15:990a8b5664e1 874 ProtectFromMCR20Interrupt();
FSL\B36402 15:990a8b5664e1 875
FSL\B36402 15:990a8b5664e1 876 phyRegs[0] = MCR20Drv_DirectAccessSPIMultiByteRead(IRQSTS2, &phyRegs[1], 7);
FSL\B36402 15:990a8b5664e1 877
FSL\B36402 15:990a8b5664e1 878 // Disable timer trigger (for scheduled XCVSEQ)
FSL\B36402 15:990a8b5664e1 879 if( phyRegs[PHY_CTRL1] & cPHY_CTRL1_TMRTRIGEN )
FSL\B36402 15:990a8b5664e1 880 {
FSL\B36402 15:990a8b5664e1 881 phyRegs[PHY_CTRL1] &= (uint8_t) ~(cPHY_CTRL1_TMRTRIGEN );
FSL\B36402 15:990a8b5664e1 882 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, phyRegs[PHY_CTRL1]);
FSL\B36402 15:990a8b5664e1 883
FSL\B36402 15:990a8b5664e1 884 // give the FSM enough time to start if it was triggered
FSL\B36402 15:990a8b5664e1 885 currentTime = (uint8_t) ( MCR20Drv_DirectAccessSPIRead(EVENT_TMR_LSB) + 2 );
FSL\B36402 15:990a8b5664e1 886 while(MCR20Drv_DirectAccessSPIRead(EVENT_TMR_LSB) != (uint8_t) (currentTime));
FSL\B36402 15:990a8b5664e1 887
FSL\B36402 15:990a8b5664e1 888 phyRegs[PHY_CTRL1] = MCR20Drv_DirectAccessSPIRead(PHY_CTRL1);
FSL\B36402 15:990a8b5664e1 889 }
FSL\B36402 15:990a8b5664e1 890
FSL\B36402 15:990a8b5664e1 891 if( (phyRegs[PHY_CTRL1] & cPHY_CTRL1_XCVSEQ) != gIdle_c )
FSL\B36402 15:990a8b5664e1 892 {
FSL\B36402 15:990a8b5664e1 893 // Abort current SEQ
FSL\B36402 15:990a8b5664e1 894 phyRegs[PHY_CTRL1] &= (uint8_t) ~(cPHY_CTRL1_XCVSEQ);
FSL\B36402 15:990a8b5664e1 895 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, phyRegs[PHY_CTRL1]);
FSL\B36402 15:990a8b5664e1 896
FSL\B36402 15:990a8b5664e1 897 // wait for Sequence Idle (if not already)
FSL\B36402 15:990a8b5664e1 898 while ((MCR20Drv_DirectAccessSPIRead(SEQ_STATE) & 0x1F) != 0);
FSL\B36402 15:990a8b5664e1 899 }
FSL\B36402 15:990a8b5664e1 900
FSL\B36402 15:990a8b5664e1 901 // mask SEQ interrupt
FSL\B36402 15:990a8b5664e1 902 phyRegs[PHY_CTRL2] |= (uint8_t) (cPHY_CTRL2_SEQMSK);
FSL\B36402 15:990a8b5664e1 903 // stop timers
FSL\B36402 15:990a8b5664e1 904 phyRegs[PHY_CTRL3] &= (uint8_t) ~(cPHY_CTRL3_TMR2CMP_EN | cPHY_CTRL3_TMR3CMP_EN);
FSL\B36402 15:990a8b5664e1 905 phyRegs[PHY_CTRL4] &= (uint8_t) ~(cPHY_CTRL4_TC3TMOUT);
FSL\B36402 15:990a8b5664e1 906
FSL\B36402 15:990a8b5664e1 907 MCR20Drv_DirectAccessSPIMultiByteWrite(PHY_CTRL2, &phyRegs[PHY_CTRL2], 4);
FSL\B36402 15:990a8b5664e1 908
FSL\B36402 15:990a8b5664e1 909 // clear all PP IRQ bits to avoid unexpected interrupts
FSL\B36402 15:990a8b5664e1 910 phyRegs[IRQSTS3] &= 0xF0; // do not change IRQ status
FSL\B36402 15:990a8b5664e1 911 phyRegs[IRQSTS3] |= (uint8_t) (cIRQSTS3_TMR3MSK |
FSL\B36402 15:990a8b5664e1 912 cIRQSTS3_TMR2IRQ |
FSL\B36402 15:990a8b5664e1 913 cIRQSTS3_TMR3IRQ); // mask TMR3 interrupt
FSL\B36402 15:990a8b5664e1 914
FSL\B36402 15:990a8b5664e1 915 MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, phyRegs, 3);
FSL\B36402 15:990a8b5664e1 916
FSL\B36402 15:990a8b5664e1 917 PhyIsrPassRxParams(NULL);
FSL\B36402 15:990a8b5664e1 918
FSL\B36402 15:990a8b5664e1 919 UnprotectFromMCR20Interrupt();
FSL\B36402 15:990a8b5664e1 920 }
FSL\B36402 15:990a8b5664e1 921
FSL\B36402 15:990a8b5664e1 922
FSL\B36402 15:990a8b5664e1 923 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 924 * \brief Initialize the 802.15.4 Radio registers
FSL\B36402 15:990a8b5664e1 925 *
FSL\B36402 15:990a8b5664e1 926 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 927
FSL\B36402 15:990a8b5664e1 928 void PhyHwInit( void )
FSL\B36402 15:990a8b5664e1 929 {
FSL\B36402 15:990a8b5664e1 930 uint8_t index;
FSL\B36402 15:990a8b5664e1 931 uint8_t phyReg;
FSL\B36402 15:990a8b5664e1 932
FSL\B36402 15:990a8b5664e1 933 /* Initialize the transceiver SPI driver */
FSL\B36402 15:990a8b5664e1 934 MCR20Drv_Init();
FSL\B36402 15:990a8b5664e1 935 /* Configure the transceiver IRQ_B port */
FSL\B36402 15:990a8b5664e1 936 MCR20Drv_IRQ_PortConfig();
FSL\B36402 15:990a8b5664e1 937 /* Initialize the SPI driver and install PHY ISR */
FSL\B36402 15:990a8b5664e1 938 PHY_InstallIsr();
FSL\B36402 15:990a8b5664e1 939
FSL\B36402 15:990a8b5664e1 940 //Disable Tristate on COCO MISO for SPI reads
FSL\B36402 15:990a8b5664e1 941 MCR20Drv_IndirectAccessSPIWrite((uint8_t) MISC_PAD_CTRL, (uint8_t) 0x02);
FSL\B36402 15:990a8b5664e1 942
FSL\B36402 15:990a8b5664e1 943 // PHY_CTRL4 unmask global TRX interrupts, enable 16 bit mode for TC2 - TC2 prime EN
FSL\B36402 15:990a8b5664e1 944 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL4, (uint8_t) (cPHY_CTRL4_TC2PRIME_EN | \
FSL\B36402 15:990a8b5664e1 945 (gCcaCCA_MODE1_c << cPHY_CTRL4_CCATYPE_Shift_c)));
FSL\B36402 15:990a8b5664e1 946
FSL\B36402 15:990a8b5664e1 947 // clear all PP IRQ bits to avoid unexpected interrupts immediately after init, disable all timer interrupts
FSL\B36402 15:990a8b5664e1 948 MCR20Drv_DirectAccessSPIWrite(IRQSTS1, (uint8_t) (cIRQSTS1_PLL_UNLOCK_IRQ | \
FSL\B36402 15:990a8b5664e1 949 cIRQSTS1_FILTERFAIL_IRQ | \
FSL\B36402 15:990a8b5664e1 950 cIRQSTS1_RXWTRMRKIRQ | \
FSL\B36402 15:990a8b5664e1 951 cIRQSTS1_CCAIRQ | \
FSL\B36402 15:990a8b5664e1 952 cIRQSTS1_RXIRQ | \
FSL\B36402 15:990a8b5664e1 953 cIRQSTS1_TXIRQ | \
FSL\B36402 15:990a8b5664e1 954 cIRQSTS1_SEQIRQ));
FSL\B36402 15:990a8b5664e1 955
FSL\B36402 15:990a8b5664e1 956 MCR20Drv_DirectAccessSPIWrite(IRQSTS2, (uint8_t) (cIRQSTS2_ASM_IRQ | \
FSL\B36402 15:990a8b5664e1 957 cIRQSTS2_PB_ERR_IRQ | \
FSL\B36402 15:990a8b5664e1 958 cIRQSTS2_WAKE_IRQ));
FSL\B36402 15:990a8b5664e1 959
FSL\B36402 15:990a8b5664e1 960 MCR20Drv_DirectAccessSPIWrite(IRQSTS3, (uint8_t) (cIRQSTS3_TMR4MSK | \
FSL\B36402 15:990a8b5664e1 961 cIRQSTS3_TMR3MSK | \
FSL\B36402 15:990a8b5664e1 962 cIRQSTS3_TMR2MSK | \
FSL\B36402 15:990a8b5664e1 963 cIRQSTS3_TMR1MSK | \
FSL\B36402 15:990a8b5664e1 964 cIRQSTS3_TMR4IRQ | \
FSL\B36402 15:990a8b5664e1 965 cIRQSTS3_TMR3IRQ | \
FSL\B36402 15:990a8b5664e1 966 cIRQSTS3_TMR2IRQ | \
FSL\B36402 15:990a8b5664e1 967 cIRQSTS3_TMR1IRQ));
FSL\B36402 15:990a8b5664e1 968
FSL\B36402 15:990a8b5664e1 969 // PHY_CTRL1 default HW settings + AUTOACK enabled
FSL\B36402 15:990a8b5664e1 970 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, (uint8_t) (cPHY_CTRL1_AUTOACK));
FSL\B36402 15:990a8b5664e1 971
FSL\B36402 15:990a8b5664e1 972 // PHY_CTRL2 : disable all interrupts
FSL\B36402 15:990a8b5664e1 973 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL2, (uint8_t) (cPHY_CTRL2_CRC_MSK | \
FSL\B36402 15:990a8b5664e1 974 cPHY_CTRL2_PLL_UNLOCK_MSK | \
FSL\B36402 15:990a8b5664e1 975 cPHY_CTRL2_FILTERFAIL_MSK | \
FSL\B36402 15:990a8b5664e1 976 cPHY_CTRL2_RX_WMRK_MSK | \
FSL\B36402 15:990a8b5664e1 977 cPHY_CTRL2_CCAMSK | \
FSL\B36402 15:990a8b5664e1 978 cPHY_CTRL2_RXMSK | \
FSL\B36402 15:990a8b5664e1 979 cPHY_CTRL2_TXMSK | \
FSL\B36402 15:990a8b5664e1 980 cPHY_CTRL2_SEQMSK));
FSL\B36402 15:990a8b5664e1 981
FSL\B36402 15:990a8b5664e1 982 // PHY_CTRL3 : disable all timers and remaining interrupts
FSL\B36402 15:990a8b5664e1 983 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL3, (uint8_t) (cPHY_CTRL3_ASM_MSK | \
FSL\B36402 15:990a8b5664e1 984 cPHY_CTRL3_PB_ERR_MSK | \
FSL\B36402 15:990a8b5664e1 985 cPHY_CTRL3_WAKE_MSK));
FSL\B36402 15:990a8b5664e1 986 // SRC_CTRL
FSL\B36402 15:990a8b5664e1 987 MCR20Drv_DirectAccessSPIWrite(SRC_CTRL, (uint8_t) (cSRC_CTRL_ACK_FRM_PND | \
FSL\B36402 15:990a8b5664e1 988 (cSRC_CTRL_INDEX << cSRC_CTRL_INDEX_Shift_c)));
FSL\B36402 15:990a8b5664e1 989 // RX_FRAME_FILTER
FSL\B36402 15:990a8b5664e1 990 // FRM_VER[1:0] = b11. Accept FrameVersion 0 and 1 packets, reject all others
FSL\B36402 15:990a8b5664e1 991 MCR20Drv_IndirectAccessSPIWrite(RX_FRAME_FILTER, (uint8_t)(cRX_FRAME_FLT_FRM_VER | \
FSL\B36402 15:990a8b5664e1 992 cRX_FRAME_FLT_BEACON_FT | \
FSL\B36402 15:990a8b5664e1 993 cRX_FRAME_FLT_DATA_FT | \
FSL\B36402 15:990a8b5664e1 994 cRX_FRAME_FLT_CMD_FT ));
FSL\B36402 15:990a8b5664e1 995 // Direct register overwrites
FSL\B36402 15:990a8b5664e1 996 for (index = 0; index < sizeof(overwrites_direct)/sizeof(overwrites_t); index++)
FSL\B36402 15:990a8b5664e1 997 MCR20Drv_DirectAccessSPIWrite(overwrites_direct[index].address, overwrites_direct[index].data);
FSL\B36402 15:990a8b5664e1 998
FSL\B36402 15:990a8b5664e1 999 // Indirect register overwrites
FSL\B36402 15:990a8b5664e1 1000 for (index = 0; index < sizeof(overwrites_indirect)/sizeof(overwrites_t); index++)
FSL\B36402 15:990a8b5664e1 1001 MCR20Drv_IndirectAccessSPIWrite(overwrites_indirect[index].address, overwrites_indirect[index].data);
FSL\B36402 15:990a8b5664e1 1002
FSL\B36402 15:990a8b5664e1 1003 // Clear HW indirect queue
FSL\B36402 15:990a8b5664e1 1004 for( index = 0; index < gPhyIndirectQueueSize_c; index++ )
FSL\B36402 15:990a8b5664e1 1005 PhyPp_RemoveFromIndirect( index, 0 );
FSL\B36402 15:990a8b5664e1 1006
FSL\B36402 15:990a8b5664e1 1007 PhyPlmeSetCurrentChannelRequest(0x0B, 0); //2405 MHz
FSL\B36402 15:990a8b5664e1 1008 #if gMpmIncluded_d
FSL\B36402 15:990a8b5664e1 1009 PhyPlmeSetCurrentChannelRequest(0x0B, 1); //2405 MHz
FSL\B36402 15:990a8b5664e1 1010
FSL\B36402 15:990a8b5664e1 1011 // Split the HW Indirect hash table in two
FSL\B36402 15:990a8b5664e1 1012 PhyPpSetDualPanSamLvl( gPhyIndirectQueueSize_c/2 );
FSL\B36402 15:990a8b5664e1 1013 #else
FSL\B36402 15:990a8b5664e1 1014 // Assign HW Indirect hash table to PAN0
FSL\B36402 15:990a8b5664e1 1015 PhyPpSetDualPanSamLvl( gPhyIndirectQueueSize_c );
FSL\B36402 15:990a8b5664e1 1016 #endif
FSL\B36402 15:990a8b5664e1 1017
FSL\B36402 15:990a8b5664e1 1018 // set the power level to 0dBm
FSL\B36402 15:990a8b5664e1 1019 PhyPlmeSetPwrLevelRequest(0x17);
FSL\B36402 15:990a8b5664e1 1020 // set CCA threshold to -75 dBm
FSL\B36402 15:990a8b5664e1 1021 PhyPpSetCcaThreshold(0x4B);
FSL\B36402 15:990a8b5664e1 1022 // Set prescaller to obtain 1 symbol (16us) timebase
FSL\B36402 15:990a8b5664e1 1023 MCR20Drv_IndirectAccessSPIWrite(TMR_PRESCALE, 0x05);
FSL\B36402 15:990a8b5664e1 1024 // write default Rx watermark level
FSL\B36402 15:990a8b5664e1 1025 MCR20Drv_IndirectAccessSPIWrite(RX_WTR_MARK, 0);
FSL\B36402 15:990a8b5664e1 1026
FSL\B36402 15:990a8b5664e1 1027 //Enable the RxWatermark IRQ and FilterFail IRQ
FSL\B36402 15:990a8b5664e1 1028 phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL2);
FSL\B36402 15:990a8b5664e1 1029 //phyReg &= (uint8_t)~(cPHY_CTRL2_FILTERFAIL_MSK);
FSL\B36402 15:990a8b5664e1 1030 phyReg &= (uint8_t)~(cPHY_CTRL2_RX_WMRK_MSK);
FSL\B36402 15:990a8b5664e1 1031 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL2, phyReg);
FSL\B36402 15:990a8b5664e1 1032
FSL\B36402 15:990a8b5664e1 1033 /* enable autodoze mode. */
FSL\B36402 15:990a8b5664e1 1034 phyReg = MCR20Drv_DirectAccessSPIRead( (uint8_t) PWR_MODES);
FSL\B36402 15:990a8b5664e1 1035 phyReg |= (uint8_t) cPWR_MODES_AUTODOZE;
FSL\B36402 15:990a8b5664e1 1036 MCR20Drv_DirectAccessSPIWrite( (uint8_t) PWR_MODES, phyReg);
FSL\B36402 15:990a8b5664e1 1037 MCR20Drv_Set_CLK_OUT_Freq(gMCR20_ClkOutFreq_d);
FSL\B36402 15:990a8b5664e1 1038
FSL\B36402 15:990a8b5664e1 1039 // Clear IRQn Pending Status
FSL\B36402 15:990a8b5664e1 1040 MCR20Drv_IRQ_Clear();
FSL\B36402 15:990a8b5664e1 1041 //NVIC_ClearPendingIRQ(g_portIrqId[GPIO_EXTRACT_PORT(kGpioXcvrIrqPin)]);
FSL\B36402 15:990a8b5664e1 1042 /* enable the transceiver IRQ_B interrupt request */
FSL\B36402 15:990a8b5664e1 1043 MCR20Drv_IRQ_Enable();
FSL\B36402 15:990a8b5664e1 1044 }
FSL\B36402 15:990a8b5664e1 1045
FSL\B36402 15:990a8b5664e1 1046 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 1047 * \brief Change the XCVR power state
FSL\B36402 15:990a8b5664e1 1048 *
FSL\B36402 15:990a8b5664e1 1049 * \param[in] state the new XCVR power state
FSL\B36402 15:990a8b5664e1 1050 *
FSL\B36402 15:990a8b5664e1 1051 * \return phyStatus_t
FSL\B36402 15:990a8b5664e1 1052 *
FSL\B36402 15:990a8b5664e1 1053 * \pre Before entering hibernate/reset states, the MCG clock source must be changed
FSL\B36402 15:990a8b5664e1 1054 * to use an input other than the one generated by the XCVR!
FSL\B36402 15:990a8b5664e1 1055 *
FSL\B36402 15:990a8b5664e1 1056 * \post When XCVR is in hibernate, indirect registers cannot be accessed in burst mode
FSL\B36402 15:990a8b5664e1 1057 * When XCVR is in reset, all registers are inaccessible!
FSL\B36402 15:990a8b5664e1 1058 *
FSL\B36402 15:990a8b5664e1 1059 * \remarks Putting the XCVR into hibernate/reset will stop the generated clock signal!
FSL\B36402 15:990a8b5664e1 1060 *
FSL\B36402 15:990a8b5664e1 1061 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 1062 phyStatus_t PhyPlmeSetPwrState( uint8_t state )
FSL\B36402 15:990a8b5664e1 1063 {
FSL\B36402 15:990a8b5664e1 1064 uint8_t phyPWR, xtalState;
FSL\B36402 15:990a8b5664e1 1065
FSL\B36402 15:990a8b5664e1 1066 /* Parameter validation */
FSL\B36402 15:990a8b5664e1 1067 if( state > gPhyPwrReset_c )
FSL\B36402 15:990a8b5664e1 1068 return gPhyInvalidParameter_c;
FSL\B36402 15:990a8b5664e1 1069
FSL\B36402 15:990a8b5664e1 1070 /* Check if the new power state = old power state */
FSL\B36402 15:990a8b5664e1 1071 if( state == mPhyPwrState )
FSL\B36402 15:990a8b5664e1 1072 return gPhyBusy_c;
FSL\B36402 15:990a8b5664e1 1073
FSL\B36402 15:990a8b5664e1 1074 /* Check if the XCVR is in reset power mode */
FSL\B36402 15:990a8b5664e1 1075 if( mPhyPwrState == gPhyPwrReset_c )
FSL\B36402 15:990a8b5664e1 1076 {
FSL\B36402 15:990a8b5664e1 1077 MCR20Drv_RST_B_Deassert();
FSL\B36402 15:990a8b5664e1 1078 /* Wait for transceiver to deassert IRQ pin */
FSL\B36402 15:990a8b5664e1 1079 while( MCR20Drv_IsIrqPending() );
FSL\B36402 15:990a8b5664e1 1080 /* Wait for transceiver wakeup from POR iterrupt */
FSL\B36402 15:990a8b5664e1 1081 while( !MCR20Drv_IsIrqPending() );
FSL\B36402 15:990a8b5664e1 1082 /* After reset, the radio is in Idle state */
FSL\B36402 15:990a8b5664e1 1083 mPhyPwrState = gPhyPwrIdle_c;
FSL\B36402 15:990a8b5664e1 1084 /* Restore default radio settings */
FSL\B36402 15:990a8b5664e1 1085 PhyHwInit();
FSL\B36402 15:990a8b5664e1 1086 }
FSL\B36402 15:990a8b5664e1 1087
FSL\B36402 15:990a8b5664e1 1088 if( state != gPhyPwrReset_c )
FSL\B36402 15:990a8b5664e1 1089 {
FSL\B36402 15:990a8b5664e1 1090 phyPWR = MCR20Drv_DirectAccessSPIRead( PWR_MODES );
FSL\B36402 15:990a8b5664e1 1091 xtalState = phyPWR & cPWR_MODES_XTALEN;
FSL\B36402 15:990a8b5664e1 1092 }
FSL\B36402 15:990a8b5664e1 1093
FSL\B36402 15:990a8b5664e1 1094 switch( state )
FSL\B36402 15:990a8b5664e1 1095 {
FSL\B36402 15:990a8b5664e1 1096 case gPhyPwrIdle_c:
FSL\B36402 15:990a8b5664e1 1097 phyPWR &= ~(cPWR_MODES_AUTODOZE);
FSL\B36402 15:990a8b5664e1 1098 phyPWR |= (cPWR_MODES_XTALEN | cPWR_MODES_PMC_MODE);
FSL\B36402 15:990a8b5664e1 1099 break;
FSL\B36402 15:990a8b5664e1 1100
FSL\B36402 15:990a8b5664e1 1101 case gPhyPwrAutodoze_c:
FSL\B36402 15:990a8b5664e1 1102 phyPWR |= (cPWR_MODES_XTALEN | cPWR_MODES_AUTODOZE | cPWR_MODES_PMC_MODE);
FSL\B36402 15:990a8b5664e1 1103 break;
FSL\B36402 15:990a8b5664e1 1104
FSL\B36402 15:990a8b5664e1 1105 case gPhyPwrDoze_c:
FSL\B36402 15:990a8b5664e1 1106 phyPWR &= ~(cPWR_MODES_AUTODOZE | cPWR_MODES_PMC_MODE);
FSL\B36402 15:990a8b5664e1 1107 phyPWR |= cPWR_MODES_XTALEN;
FSL\B36402 15:990a8b5664e1 1108 break;
FSL\B36402 15:990a8b5664e1 1109
FSL\B36402 15:990a8b5664e1 1110 case gPhyPwrHibernate_c:
FSL\B36402 15:990a8b5664e1 1111 phyPWR &= ~(cPWR_MODES_XTALEN | cPWR_MODES_AUTODOZE | cPWR_MODES_PMC_MODE);
FSL\B36402 15:990a8b5664e1 1112 break;
FSL\B36402 15:990a8b5664e1 1113
FSL\B36402 15:990a8b5664e1 1114 case gPhyPwrReset_c:
FSL\B36402 15:990a8b5664e1 1115 MCR20Drv_IRQ_Disable();
FSL\B36402 15:990a8b5664e1 1116 mPhyPwrState = gPhyPwrReset_c;
FSL\B36402 15:990a8b5664e1 1117 MCR20Drv_RST_B_Assert();
FSL\B36402 15:990a8b5664e1 1118 return gPhySuccess_c;
FSL\B36402 15:990a8b5664e1 1119 }
FSL\B36402 15:990a8b5664e1 1120
FSL\B36402 15:990a8b5664e1 1121 mPhyPwrState = state;
FSL\B36402 15:990a8b5664e1 1122 MCR20Drv_DirectAccessSPIWrite( PWR_MODES, phyPWR );
FSL\B36402 15:990a8b5664e1 1123
FSL\B36402 15:990a8b5664e1 1124 if( !xtalState && (phyPWR & cPWR_MODES_XTALEN))
FSL\B36402 15:990a8b5664e1 1125 {
FSL\B36402 15:990a8b5664e1 1126 /* wait for crystal oscillator to complet its warmup */
FSL\B36402 15:990a8b5664e1 1127 while( ( MCR20Drv_DirectAccessSPIRead(PWR_MODES) & cPWR_MODES_XTAL_READY ) != cPWR_MODES_XTAL_READY);
FSL\B36402 15:990a8b5664e1 1128 /* wait for radio wakeup from hibernate interrupt */
FSL\B36402 15:990a8b5664e1 1129 while( ( MCR20Drv_DirectAccessSPIRead(IRQSTS2) & (cIRQSTS2_WAKE_IRQ | cIRQSTS2_TMRSTATUS) ) != (cIRQSTS2_WAKE_IRQ | cIRQSTS2_TMRSTATUS) );
FSL\B36402 15:990a8b5664e1 1130
FSL\B36402 15:990a8b5664e1 1131 MCR20Drv_DirectAccessSPIWrite(IRQSTS2, cIRQSTS2_WAKE_IRQ);
FSL\B36402 15:990a8b5664e1 1132 }
FSL\B36402 15:990a8b5664e1 1133
FSL\B36402 15:990a8b5664e1 1134 return gPhySuccess_c;
FSL\B36402 15:990a8b5664e1 1135 }