NXP
The MCR20A Wireless UART application functions as an wireless UART bridge between two (one-to-one) or several (one to many) boards. The application can be used with both a TERM, or with software that is capable of opening a serial port and writing to or reading from it. The characters sent or received are not necessarily ASCII printable characters.
Dependencies: fsl_phy_mcr20a fsl_smac mbed-rtos mbed
Fork of
mcr20_wireless_uart
by 
Freescale
By default, the application uses broadcast addresses for OTA communication. This way, the application can be directly downloaded and run without any user intervention. The following use case assumes no changes have been done to the project.
- Two (or more) MCR20A platforms (plugged into the FRDM-K64F Freescale Freedom Development platform) have to be connected to the PC using the mini/micro-USB cables.
- The code must be downloaded on the platforms via CMSIS-DAP (or other means).
- After that, two or more TERM applications must be opened, and the serial ports must be configured with the same baud rate as the one in the project (default baud rate is 115200). Other necessary serial configurations are 8 bit, no parity, and 1 stop bit.
- To start the setup, each platform must be reset, and one of the (user) push buttons found on the MCR20A platform must be pressed. The user can press any of the non-reset buttons on the FRDM-K64F Freescale Freedom Development platform as well. *This initiates the state machine of the application so user can start.
Documentation
SMAC Demo Applications User Guide
RF_Drivers_Freescale/MCR20Drv/XcvrSpi.h@15:990a8b5664e1, 2015-03-15 (annotated)
- Committer:
- FSL\B36402
- Date:
- Sun Mar 15 00:56:28 2015 -0500
- Revision:
- 15:990a8b5664e1
Integrated PHY version from the official K64F+MCR20A package
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| FSL\B36402 |
15:990a8b5664e1 | 1 | /*! |
| FSL\B36402 |
15:990a8b5664e1 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
| FSL\B36402 |
15:990a8b5664e1 | 3 | * All rights reserved. |
| FSL\B36402 |
15:990a8b5664e1 | 4 | * |
| FSL\B36402 |
15:990a8b5664e1 | 5 | * \file XcvrSpi.h |
| FSL\B36402 |
15:990a8b5664e1 | 6 | * |
| FSL\B36402 |
15:990a8b5664e1 | 7 | * Redistribution and use in source and binary forms, with or without modification, |
| FSL\B36402 |
15:990a8b5664e1 | 8 | * are permitted provided that the following conditions are met: |
| FSL\B36402 |
15:990a8b5664e1 | 9 | * |
| FSL\B36402 |
15:990a8b5664e1 | 10 | * o Redistributions of source code must retain the above copyright notice, this list |
| FSL\B36402 |
15:990a8b5664e1 | 11 | * of conditions and the following disclaimer. |
| FSL\B36402 |
15:990a8b5664e1 | 12 | * |
| FSL\B36402 |
15:990a8b5664e1 | 13 | * o Redistributions in binary form must reproduce the above copyright notice, this |
| FSL\B36402 |
15:990a8b5664e1 | 14 | * list of conditions and the following disclaimer in the documentation and/or |
| FSL\B36402 |
15:990a8b5664e1 | 15 | * other materials provided with the distribution. |
| FSL\B36402 |
15:990a8b5664e1 | 16 | * |
| FSL\B36402 |
15:990a8b5664e1 | 17 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
| FSL\B36402 |
15:990a8b5664e1 | 18 | * contributors may be used to endorse or promote products derived from this |
| FSL\B36402 |
15:990a8b5664e1 | 19 | * software without specific prior written permission. |
| FSL\B36402 |
15:990a8b5664e1 | 20 | * |
| FSL\B36402 |
15:990a8b5664e1 | 21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| FSL\B36402 |
15:990a8b5664e1 | 22 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| FSL\B36402 |
15:990a8b5664e1 | 23 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| FSL\B36402 |
15:990a8b5664e1 | 24 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| FSL\B36402 |
15:990a8b5664e1 | 25 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| FSL\B36402 |
15:990a8b5664e1 | 26 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| FSL\B36402 |
15:990a8b5664e1 | 27 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| FSL\B36402 |
15:990a8b5664e1 | 28 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| FSL\B36402 |
15:990a8b5664e1 | 29 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| FSL\B36402 |
15:990a8b5664e1 | 30 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| FSL\B36402 |
15:990a8b5664e1 | 31 | */ |
| FSL\B36402 |
15:990a8b5664e1 | 32 | |
| FSL\B36402 |
15:990a8b5664e1 | 33 | #ifndef __XCVR_SPI_H__ |
| FSL\B36402 |
15:990a8b5664e1 | 34 | #define __XCVR_SPI_H__ |
| FSL\B36402 |
15:990a8b5664e1 | 35 | |
| FSL\B36402 |
15:990a8b5664e1 | 36 | |
| FSL\B36402 |
15:990a8b5664e1 | 37 | /***************************************************************************** |
| FSL\B36402 |
15:990a8b5664e1 | 38 | * INCLUDED HEADERS * |
| FSL\B36402 |
15:990a8b5664e1 | 39 | *---------------------------------------------------------------------------* |
| FSL\B36402 |
15:990a8b5664e1 | 40 | * Add to this section all the headers that this module needs to include. * |
| FSL\B36402 |
15:990a8b5664e1 | 41 | * Note that it is not a good practice to include header files into header * |
| FSL\B36402 |
15:990a8b5664e1 | 42 | * files, so use this section only if there is no other better solution. * |
| FSL\B36402 |
15:990a8b5664e1 | 43 | *---------------------------------------------------------------------------* |
| FSL\B36402 |
15:990a8b5664e1 | 44 | *****************************************************************************/ |
| FSL\B36402 |
15:990a8b5664e1 | 45 | |
| FSL\B36402 |
15:990a8b5664e1 | 46 | #include "EmbeddedTypes.h" |
| FSL\B36402 |
15:990a8b5664e1 | 47 | //#include "board.h" |
| FSL\B36402 |
15:990a8b5664e1 | 48 | |
| FSL\B36402 |
15:990a8b5664e1 | 49 | |
| FSL\B36402 |
15:990a8b5664e1 | 50 | /***************************************************************************** |
| FSL\B36402 |
15:990a8b5664e1 | 51 | * PUBLIC MACROS * |
| FSL\B36402 |
15:990a8b5664e1 | 52 | *---------------------------------------------------------------------------* |
| FSL\B36402 |
15:990a8b5664e1 | 53 | * Add to this section all the access macros, registers mappings, bit access * |
| FSL\B36402 |
15:990a8b5664e1 | 54 | * macros, masks, flags etc ... |
| FSL\B36402 |
15:990a8b5664e1 | 55 | *---------------------------------------------------------------------------* |
| FSL\B36402 |
15:990a8b5664e1 | 56 | *****************************************************************************/ |
| FSL\B36402 |
15:990a8b5664e1 | 57 | //#define gXcvrAssertCS_d() GPIO_DRV_ClearPinOutput(kGpioXcvrSpiCsPin) |
| FSL\B36402 |
15:990a8b5664e1 | 58 | //#define gXcvrDeassertCS_d() GPIO_DRV_SetPinOutput(kGpioXcvrSpiCsPin) |
| FSL\B36402 |
15:990a8b5664e1 | 59 | |
| FSL\B36402 |
15:990a8b5664e1 | 60 | #define gXcvrSpiInstance_c 0 |
| FSL\B36402 |
15:990a8b5664e1 | 61 | |
| FSL\B36402 |
15:990a8b5664e1 | 62 | /***************************************************************************** |
| FSL\B36402 |
15:990a8b5664e1 | 63 | * PUBLIC FUNCTIONS * |
| FSL\B36402 |
15:990a8b5664e1 | 64 | *---------------------------------------------------------------------------* |
| FSL\B36402 |
15:990a8b5664e1 | 65 | * Add to this section all the global functions prototype preceded (as a * |
| FSL\B36402 |
15:990a8b5664e1 | 66 | * good practice) by the keyword 'extern' * |
| FSL\B36402 |
15:990a8b5664e1 | 67 | *---------------------------------------------------------------------------* |
| FSL\B36402 |
15:990a8b5664e1 | 68 | *****************************************************************************/ |
| FSL\B36402 |
15:990a8b5664e1 | 69 | void RF_RST_Set(int state); |
| FSL\B36402 |
15:990a8b5664e1 | 70 | void RF_SLP_TR_Set(int state); |
| FSL\B36402 |
15:990a8b5664e1 | 71 | void RF_CS_while_active(void); |
| FSL\B36402 |
15:990a8b5664e1 | 72 | void RF_CS_Set(int state); |
| FSL\B36402 |
15:990a8b5664e1 | 73 | void RF_IRQ_Init(void); |
| FSL\B36402 |
15:990a8b5664e1 | 74 | void RF_IRQ_Disable(void); |
| FSL\B36402 |
15:990a8b5664e1 | 75 | void RF_IRQ_Enable(void); |
| FSL\B36402 |
15:990a8b5664e1 | 76 | bool_t RF_isIRQ_Pending(void); |
| FSL\B36402 |
15:990a8b5664e1 | 77 | |
| FSL\B36402 |
15:990a8b5664e1 | 78 | void gXcvrAssertCS_d(void); |
| FSL\B36402 |
15:990a8b5664e1 | 79 | void gXcvrDeassertCS_d(void); |
| FSL\B36402 |
15:990a8b5664e1 | 80 | |
| FSL\B36402 |
15:990a8b5664e1 | 81 | void spi_master_init(uint32_t instance); |
| FSL\B36402 |
15:990a8b5664e1 | 82 | void spi_master_configure_speed(uint32_t instance, uint32_t freq); |
| FSL\B36402 |
15:990a8b5664e1 | 83 | void spi_master_transfer(uint32_t instance, |
| FSL\B36402 |
15:990a8b5664e1 | 84 | uint8_t * sendBuffer, |
| FSL\B36402 |
15:990a8b5664e1 | 85 | uint8_t * receiveBuffer, |
| FSL\B36402 |
15:990a8b5664e1 | 86 | uint32_t transferByteCount); |
| FSL\B36402 |
15:990a8b5664e1 | 87 | |
| FSL\B36402 |
15:990a8b5664e1 | 88 | #endif /* __XCVR_SPI_H__ */ |