NXP / Mbed 2 deprecated mcr20_wireless_uart

The MCR20A Wireless UART application functions as an wireless UART bridge between two (one-to-one) or several (one to many) boards. The application can be used with both a TERM, or with software that is capable of opening a serial port and writing to or reading from it. The characters sent or received are not necessarily ASCII printable characters.

Dependencies:   fsl_phy_mcr20a fsl_smac mbed-rtos mbed

Fork of mcr20_wireless_uart by Freescale

By default, the application uses broadcast addresses for OTA communication. This way, the application can be directly downloaded and run without any user intervention. The following use case assumes no changes have been done to the project.

  • Two (or more) MCR20A platforms (plugged into the FRDM-K64F Freescale Freedom Development platform) have to be connected to the PC using the mini/micro-USB cables.
  • The code must be downloaded on the platforms via CMSIS-DAP (or other means).
  • After that, two or more TERM applications must be opened, and the serial ports must be configured with the same baud rate as the one in the project (default baud rate is 115200). Other necessary serial configurations are 8 bit, no parity, and 1 stop bit.
  • To start the setup, each platform must be reset, and one of the (user) push buttons found on the MCR20A platform must be pressed. The user can press any of the non-reset buttons on the FRDM-K64F Freescale Freedom Development platform as well. *This initiates the state machine of the application so user can start.

Documentation

SMAC Demo Applications User Guide

RF_Drivers_Freescale/MCR20Drv/XcvrSpi.cpp@15:990a8b5664e1, 2015-03-15 (annotated)

Committer:
FSL\B36402
Date:
Sun Mar 15 00:56:28 2015 -0500
Revision:
15:990a8b5664e1
Child:
17:52cfd7db8da3
Integrated PHY version from the official K64F+MCR20A package

Who changed what in which revision?

UserRevisionLine numberNew contents of line
FSL\B36402 15:990a8b5664e1 1 /*!
FSL\B36402 15:990a8b5664e1 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
FSL\B36402 15:990a8b5664e1 3 * All rights reserved.
FSL\B36402 15:990a8b5664e1 4 *
FSL\B36402 15:990a8b5664e1 5 * \file XcvrSpi.c
FSL\B36402 15:990a8b5664e1 6 *
FSL\B36402 15:990a8b5664e1 7 * Redistribution and use in source and binary forms, with or without modification,
FSL\B36402 15:990a8b5664e1 8 * are permitted provided that the following conditions are met:
FSL\B36402 15:990a8b5664e1 9 *
FSL\B36402 15:990a8b5664e1 10 * o Redistributions of source code must retain the above copyright notice, this list
FSL\B36402 15:990a8b5664e1 11 * of conditions and the following disclaimer.
FSL\B36402 15:990a8b5664e1 12 *
FSL\B36402 15:990a8b5664e1 13 * o Redistributions in binary form must reproduce the above copyright notice, this
FSL\B36402 15:990a8b5664e1 14 * list of conditions and the following disclaimer in the documentation and/or
FSL\B36402 15:990a8b5664e1 15 * other materials provided with the distribution.
FSL\B36402 15:990a8b5664e1 16 *
FSL\B36402 15:990a8b5664e1 17 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
FSL\B36402 15:990a8b5664e1 18 * contributors may be used to endorse or promote products derived from this
FSL\B36402 15:990a8b5664e1 19 * software without specific prior written permission.
FSL\B36402 15:990a8b5664e1 20 *
FSL\B36402 15:990a8b5664e1 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
FSL\B36402 15:990a8b5664e1 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
FSL\B36402 15:990a8b5664e1 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
FSL\B36402 15:990a8b5664e1 24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
FSL\B36402 15:990a8b5664e1 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
FSL\B36402 15:990a8b5664e1 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
FSL\B36402 15:990a8b5664e1 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
FSL\B36402 15:990a8b5664e1 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
FSL\B36402 15:990a8b5664e1 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
FSL\B36402 15:990a8b5664e1 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
FSL\B36402 15:990a8b5664e1 31 */
FSL\B36402 15:990a8b5664e1 32
FSL\B36402 15:990a8b5664e1 33
FSL\B36402 15:990a8b5664e1 34 /*****************************************************************************
FSL\B36402 15:990a8b5664e1 35 * INCLUDED HEADERS *
FSL\B36402 15:990a8b5664e1 36 *---------------------------------------------------------------------------*
FSL\B36402 15:990a8b5664e1 37 * Add to this section all the headers that this module needs to include. *
FSL\B36402 15:990a8b5664e1 38 * Note that it is not a good practice to include header files into header *
FSL\B36402 15:990a8b5664e1 39 * files, so use this section only if there is no other better solution. *
FSL\B36402 15:990a8b5664e1 40 *---------------------------------------------------------------------------*
FSL\B36402 15:990a8b5664e1 41 *****************************************************************************/
FSL\B36402 15:990a8b5664e1 42
FSL\B36402 15:990a8b5664e1 43 #include "mbed.h"
FSL\B36402 15:990a8b5664e1 44 #include "EmbeddedTypes.h"
FSL\B36402 15:990a8b5664e1 45
FSL\B36402 15:990a8b5664e1 46 #if defined(TARGET_K64F)
FSL\B36402 15:990a8b5664e1 47 SPI spi(PTD2, PTD3, PTD1);
FSL\B36402 15:990a8b5664e1 48 #elif defined(TARGET_NUCLEO_F401RE)
FSL\B36402 15:990a8b5664e1 49 SPI spi(SPI_MOSI, SPI_MISO, SPI_SCK);
FSL\B36402 15:990a8b5664e1 50 #else
FSL\B36402 15:990a8b5664e1 51 "SPI not defined for this platform"
FSL\B36402 15:990a8b5664e1 52 #endif
FSL\B36402 15:990a8b5664e1 53
FSL\B36402 15:990a8b5664e1 54 DigitalOut RF_CS(D10);
FSL\B36402 15:990a8b5664e1 55 DigitalOut RF_RST(D5);
FSL\B36402 15:990a8b5664e1 56 DigitalOut RF_SLP_TR(D7); // Not used in FSL
FSL\B36402 15:990a8b5664e1 57 InterruptIn RF_IRQ (D2); // FSL //(D9); // Atmel Radio
FSL\B36402 15:990a8b5664e1 58 DigitalIn RF_IRQ_PIN (D2);
FSL\B36402 15:990a8b5664e1 59
FSL\B36402 15:990a8b5664e1 60 extern "C" void PHY_InterruptHandler(void);
FSL\B36402 15:990a8b5664e1 61
FSL\B36402 15:990a8b5664e1 62 extern "C" void RF_IRQ_Init(void) {
FSL\B36402 15:990a8b5664e1 63 RF_IRQ.disable_irq();
FSL\B36402 15:990a8b5664e1 64 RF_IRQ.mode(PullDown);
FSL\B36402 15:990a8b5664e1 65 RF_IRQ.rise(&PHY_InterruptHandler);
FSL\B36402 15:990a8b5664e1 66 }
FSL\B36402 15:990a8b5664e1 67
FSL\B36402 15:990a8b5664e1 68 extern "C" void RF_IRQ_Enable(void) {
FSL\B36402 15:990a8b5664e1 69 RF_IRQ.enable_irq();
FSL\B36402 15:990a8b5664e1 70 }
FSL\B36402 15:990a8b5664e1 71 extern "C" void RF_IRQ_Disable(void) {
FSL\B36402 15:990a8b5664e1 72 RF_IRQ.disable_irq();
FSL\B36402 15:990a8b5664e1 73 }
FSL\B36402 15:990a8b5664e1 74
FSL\B36402 15:990a8b5664e1 75 extern "C" bool_t RF_isIRQ_Pending(void) {
FSL\B36402 15:990a8b5664e1 76 #if 0
FSL\B36402 15:990a8b5664e1 77 int state = RF_IRQ_PIN.read();
FSL\B36402 15:990a8b5664e1 78
FSL\B36402 15:990a8b5664e1 79 if (1 == state)
FSL\B36402 15:990a8b5664e1 80 {
FSL\B36402 15:990a8b5664e1 81 return 0;
FSL\B36402 15:990a8b5664e1 82 }
FSL\B36402 15:990a8b5664e1 83 else
FSL\B36402 15:990a8b5664e1 84 {
FSL\B36402 15:990a8b5664e1 85 return 1;
FSL\B36402 15:990a8b5664e1 86 }
FSL\B36402 15:990a8b5664e1 87 #endif
FSL\B36402 15:990a8b5664e1 88 return RF_IRQ_PIN.read();
FSL\B36402 15:990a8b5664e1 89 }
FSL\B36402 15:990a8b5664e1 90
FSL\B36402 15:990a8b5664e1 91 extern "C" void RF_RST_Set(int state) {
FSL\B36402 15:990a8b5664e1 92 RF_RST = state;
FSL\B36402 15:990a8b5664e1 93 }
FSL\B36402 15:990a8b5664e1 94
FSL\B36402 15:990a8b5664e1 95 extern "C" void RF_SLP_TR_Set(int state) {
FSL\B36402 15:990a8b5664e1 96 RF_SLP_TR = state;
FSL\B36402 15:990a8b5664e1 97 }
FSL\B36402 15:990a8b5664e1 98
FSL\B36402 15:990a8b5664e1 99 extern "C" void RF_CS_while_active(void) {
FSL\B36402 15:990a8b5664e1 100
FSL\B36402 15:990a8b5664e1 101 while(!RF_CS);
FSL\B36402 15:990a8b5664e1 102 }
FSL\B36402 15:990a8b5664e1 103
FSL\B36402 15:990a8b5664e1 104 /*****************************************************************************
FSL\B36402 15:990a8b5664e1 105 * PRIVATE MACROS *
FSL\B36402 15:990a8b5664e1 106 *---------------------------------------------------------------------------*
FSL\B36402 15:990a8b5664e1 107 * Add to this section all the access macros, registers mappings, bit access *
FSL\B36402 15:990a8b5664e1 108 * macros, masks, flags etc ...
FSL\B36402 15:990a8b5664e1 109 *---------------------------------------------------------------------------*
FSL\B36402 15:990a8b5664e1 110 *****************************************************************************/
FSL\B36402 15:990a8b5664e1 111
FSL\B36402 15:990a8b5664e1 112 /*****************************************************************************/
FSL\B36402 15:990a8b5664e1 113 /*****************************************************************************/
FSL\B36402 15:990a8b5664e1 114 extern "C" void spi_master_init(uint32_t instance)
FSL\B36402 15:990a8b5664e1 115 {
FSL\B36402 15:990a8b5664e1 116
FSL\B36402 15:990a8b5664e1 117 }
FSL\B36402 15:990a8b5664e1 118
FSL\B36402 15:990a8b5664e1 119 /*****************************************************************************/
FSL\B36402 15:990a8b5664e1 120 /*****************************************************************************/
FSL\B36402 15:990a8b5664e1 121 extern "C" void spi_master_configure_speed(uint32_t instance, uint32_t freq)
FSL\B36402 15:990a8b5664e1 122 {
FSL\B36402 15:990a8b5664e1 123 //spi.frequency(8000000);
FSL\B36402 15:990a8b5664e1 124 spi.frequency(freq);
FSL\B36402 15:990a8b5664e1 125 }
FSL\B36402 15:990a8b5664e1 126
FSL\B36402 15:990a8b5664e1 127 /*****************************************************************************/
FSL\B36402 15:990a8b5664e1 128 /*****************************************************************************/
FSL\B36402 15:990a8b5664e1 129 extern "C" void spi_master_transfer(uint32_t instance,
FSL\B36402 15:990a8b5664e1 130 uint8_t * sendBuffer,
FSL\B36402 15:990a8b5664e1 131 uint8_t * receiveBuffer,
FSL\B36402 15:990a8b5664e1 132 size_t transferByteCount)
FSL\B36402 15:990a8b5664e1 133 {
FSL\B36402 15:990a8b5664e1 134 volatile uint8_t dummy;
FSL\B36402 15:990a8b5664e1 135
FSL\B36402 15:990a8b5664e1 136 if( !transferByteCount )
FSL\B36402 15:990a8b5664e1 137 return;
FSL\B36402 15:990a8b5664e1 138
FSL\B36402 15:990a8b5664e1 139 if( !sendBuffer && !receiveBuffer )
FSL\B36402 15:990a8b5664e1 140 return;
FSL\B36402 15:990a8b5664e1 141
FSL\B36402 15:990a8b5664e1 142 while( transferByteCount-- )
FSL\B36402 15:990a8b5664e1 143 {
FSL\B36402 15:990a8b5664e1 144 if( sendBuffer )
FSL\B36402 15:990a8b5664e1 145 {
FSL\B36402 15:990a8b5664e1 146 dummy = *sendBuffer;
FSL\B36402 15:990a8b5664e1 147 sendBuffer++;
FSL\B36402 15:990a8b5664e1 148 }
FSL\B36402 15:990a8b5664e1 149 else
FSL\B36402 15:990a8b5664e1 150 {
FSL\B36402 15:990a8b5664e1 151 dummy = 0xFF;
FSL\B36402 15:990a8b5664e1 152 }
FSL\B36402 15:990a8b5664e1 153
FSL\B36402 15:990a8b5664e1 154 dummy = spi.write(dummy);
FSL\B36402 15:990a8b5664e1 155
FSL\B36402 15:990a8b5664e1 156 if( receiveBuffer )
FSL\B36402 15:990a8b5664e1 157 {
FSL\B36402 15:990a8b5664e1 158 *receiveBuffer = dummy;
FSL\B36402 15:990a8b5664e1 159 receiveBuffer++;
FSL\B36402 15:990a8b5664e1 160 }
FSL\B36402 15:990a8b5664e1 161 }
FSL\B36402 15:990a8b5664e1 162 }
FSL\B36402 15:990a8b5664e1 163
FSL\B36402 15:990a8b5664e1 164 extern "C" void gXcvrAssertCS_d(void)
FSL\B36402 15:990a8b5664e1 165 {
FSL\B36402 15:990a8b5664e1 166 RF_CS = 0;
FSL\B36402 15:990a8b5664e1 167 }
FSL\B36402 15:990a8b5664e1 168
FSL\B36402 15:990a8b5664e1 169 extern "C" void gXcvrDeassertCS_d(void)
FSL\B36402 15:990a8b5664e1 170 {
FSL\B36402 15:990a8b5664e1 171 RF_CS = 1;
FSL\B36402 15:990a8b5664e1 172 }