Microbug / nRF51822

bugfix for duplicate symbol

Fork of nRF51822 by Nordic Semiconductor

nordic-sdk/components/drivers_nrf/hal/nrf51.h@177:7a1917171a20, 2015-05-15 (annotated)

Committer:
finneyj
Date:
Fri May 15 12:12:21 2015 +0000
Revision:
177:7a1917171a20
Parent:
103:138bdc859cc9 
bug fix - redefined symbol

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rgrover1 103:138bdc859cc9 1
rgrover1 103:138bdc859cc9 2 /****************************************************************************************************//**
rgrover1 103:138bdc859cc9 3 * @file nRF51.h
rgrover1 103:138bdc859cc9 4 *
rgrover1 103:138bdc859cc9 5 * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
rgrover1 103:138bdc859cc9 6 * nRF51 from Nordic Semiconductor.
rgrover1 103:138bdc859cc9 7 *
rgrover1 103:138bdc859cc9 8 * @version V522
rgrover1 103:138bdc859cc9 9 * @date 31. October 2014
rgrover1 103:138bdc859cc9 10 *
rgrover1 103:138bdc859cc9 11 * @note Generated with SVDConv V2.81d
rgrover1 103:138bdc859cc9 12 * from CMSIS SVD File 'nRF51.xml' Version 522,
rgrover1 103:138bdc859cc9 13 *
rgrover1 103:138bdc859cc9 14 * @par Copyright (c) 2013, Nordic Semiconductor ASA
rgrover1 103:138bdc859cc9 15 * All rights reserved.
rgrover1 103:138bdc859cc9 16 *
rgrover1 103:138bdc859cc9 17 * Redistribution and use in source and binary forms, with or without
rgrover1 103:138bdc859cc9 18 * modification, are permitted provided that the following conditions are met:
rgrover1 103:138bdc859cc9 19 *
rgrover1 103:138bdc859cc9 20 * * Redistributions of source code must retain the above copyright notice, this
rgrover1 103:138bdc859cc9 21 * list of conditions and the following disclaimer.
rgrover1 103:138bdc859cc9 22 *
rgrover1 103:138bdc859cc9 23 * * Redistributions in binary form must reproduce the above copyright notice,
rgrover1 103:138bdc859cc9 24 * this list of conditions and the following disclaimer in the documentation
rgrover1 103:138bdc859cc9 25 * and/or other materials provided with the distribution.
rgrover1 103:138bdc859cc9 26 *
rgrover1 103:138bdc859cc9 27 * * Neither the name of Nordic Semiconductor ASA nor the names of its
rgrover1 103:138bdc859cc9 28 * contributors may be used to endorse or promote products derived from
rgrover1 103:138bdc859cc9 29 * this software without specific prior written permission.
rgrover1 103:138bdc859cc9 30 *
rgrover1 103:138bdc859cc9 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
rgrover1 103:138bdc859cc9 32 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
rgrover1 103:138bdc859cc9 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
rgrover1 103:138bdc859cc9 34 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
rgrover1 103:138bdc859cc9 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
rgrover1 103:138bdc859cc9 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
rgrover1 103:138bdc859cc9 37 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
rgrover1 103:138bdc859cc9 38 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
rgrover1 103:138bdc859cc9 39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
rgrover1 103:138bdc859cc9 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
rgrover1 103:138bdc859cc9 41 *
rgrover1 103:138bdc859cc9 42 *
rgrover1 103:138bdc859cc9 43 *******************************************************************************************************/
rgrover1 103:138bdc859cc9 44
rgrover1 103:138bdc859cc9 45
rgrover1 103:138bdc859cc9 46
rgrover1 103:138bdc859cc9 47 /** @addtogroup Nordic Semiconductor
rgrover1 103:138bdc859cc9 48 * @{
rgrover1 103:138bdc859cc9 49 */
rgrover1 103:138bdc859cc9 50
rgrover1 103:138bdc859cc9 51 /** @addtogroup nRF51
rgrover1 103:138bdc859cc9 52 * @{
rgrover1 103:138bdc859cc9 53 */
rgrover1 103:138bdc859cc9 54
rgrover1 103:138bdc859cc9 55 #ifndef NRF51_H
rgrover1 103:138bdc859cc9 56 #define NRF51_H
rgrover1 103:138bdc859cc9 57
rgrover1 103:138bdc859cc9 58 #ifdef __cplusplus
rgrover1 103:138bdc859cc9 59 extern "C" {
rgrover1 103:138bdc859cc9 60 #endif
rgrover1 103:138bdc859cc9 61
rgrover1 103:138bdc859cc9 62
rgrover1 103:138bdc859cc9 63 /* ------------------------- Interrupt Number Definition ------------------------ */
rgrover1 103:138bdc859cc9 64
rgrover1 103:138bdc859cc9 65 typedef enum {
rgrover1 103:138bdc859cc9 66 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
rgrover1 103:138bdc859cc9 67 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
rgrover1 103:138bdc859cc9 68 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
rgrover1 103:138bdc859cc9 69 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
rgrover1 103:138bdc859cc9 70 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
rgrover1 103:138bdc859cc9 71 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
rgrover1 103:138bdc859cc9 72 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
rgrover1 103:138bdc859cc9 73 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
rgrover1 103:138bdc859cc9 74 /* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
rgrover1 103:138bdc859cc9 75 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
rgrover1 103:138bdc859cc9 76 RADIO_IRQn = 1, /*!< 1 RADIO */
rgrover1 103:138bdc859cc9 77 UART0_IRQn = 2, /*!< 2 UART0 */
rgrover1 103:138bdc859cc9 78 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
rgrover1 103:138bdc859cc9 79 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
rgrover1 103:138bdc859cc9 80 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
rgrover1 103:138bdc859cc9 81 ADC_IRQn = 7, /*!< 7 ADC */
rgrover1 103:138bdc859cc9 82 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
rgrover1 103:138bdc859cc9 83 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
rgrover1 103:138bdc859cc9 84 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
rgrover1 103:138bdc859cc9 85 RTC0_IRQn = 11, /*!< 11 RTC0 */
rgrover1 103:138bdc859cc9 86 TEMP_IRQn = 12, /*!< 12 TEMP */
rgrover1 103:138bdc859cc9 87 RNG_IRQn = 13, /*!< 13 RNG */
rgrover1 103:138bdc859cc9 88 ECB_IRQn = 14, /*!< 14 ECB */
rgrover1 103:138bdc859cc9 89 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
rgrover1 103:138bdc859cc9 90 WDT_IRQn = 16, /*!< 16 WDT */
rgrover1 103:138bdc859cc9 91 RTC1_IRQn = 17, /*!< 17 RTC1 */
rgrover1 103:138bdc859cc9 92 QDEC_IRQn = 18, /*!< 18 QDEC */
rgrover1 103:138bdc859cc9 93 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
rgrover1 103:138bdc859cc9 94 SWI0_IRQn = 20, /*!< 20 SWI0 */
rgrover1 103:138bdc859cc9 95 SWI1_IRQn = 21, /*!< 21 SWI1 */
rgrover1 103:138bdc859cc9 96 SWI2_IRQn = 22, /*!< 22 SWI2 */
rgrover1 103:138bdc859cc9 97 SWI3_IRQn = 23, /*!< 23 SWI3 */
rgrover1 103:138bdc859cc9 98 SWI4_IRQn = 24, /*!< 24 SWI4 */
rgrover1 103:138bdc859cc9 99 SWI5_IRQn = 25 /*!< 25 SWI5 */
rgrover1 103:138bdc859cc9 100 } IRQn_Type;
rgrover1 103:138bdc859cc9 101
rgrover1 103:138bdc859cc9 102
rgrover1 103:138bdc859cc9 103 /** @addtogroup Configuration_of_CMSIS
rgrover1 103:138bdc859cc9 104 * @{
rgrover1 103:138bdc859cc9 105 */
rgrover1 103:138bdc859cc9 106
rgrover1 103:138bdc859cc9 107
rgrover1 103:138bdc859cc9 108 /* ================================================================================ */
rgrover1 103:138bdc859cc9 109 /* ================ Processor and Core Peripheral Section ================ */
rgrover1 103:138bdc859cc9 110 /* ================================================================================ */
rgrover1 103:138bdc859cc9 111
rgrover1 103:138bdc859cc9 112 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
rgrover1 103:138bdc859cc9 113 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
rgrover1 103:138bdc859cc9 114 #define __MPU_PRESENT 0 /*!< MPU present or not */
rgrover1 103:138bdc859cc9 115 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
rgrover1 103:138bdc859cc9 116 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
rgrover1 103:138bdc859cc9 117 /** @} */ /* End of group Configuration_of_CMSIS */
rgrover1 103:138bdc859cc9 118
rgrover1 103:138bdc859cc9 119 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
rgrover1 103:138bdc859cc9 120 #include "system_nrf51.h" /*!< nRF51 System */
rgrover1 103:138bdc859cc9 121
rgrover1 103:138bdc859cc9 122
rgrover1 103:138bdc859cc9 123 /* ================================================================================ */
rgrover1 103:138bdc859cc9 124 /* ================ Device Specific Peripheral Section ================ */
rgrover1 103:138bdc859cc9 125 /* ================================================================================ */
rgrover1 103:138bdc859cc9 126
rgrover1 103:138bdc859cc9 127
rgrover1 103:138bdc859cc9 128 /** @addtogroup Device_Peripheral_Registers
rgrover1 103:138bdc859cc9 129 * @{
rgrover1 103:138bdc859cc9 130 */
rgrover1 103:138bdc859cc9 131
rgrover1 103:138bdc859cc9 132
rgrover1 103:138bdc859cc9 133 /* ------------------- Start of section using anonymous unions ------------------ */
rgrover1 103:138bdc859cc9 134 #if defined(__CC_ARM)
rgrover1 103:138bdc859cc9 135 #pragma push
rgrover1 103:138bdc859cc9 136 #pragma anon_unions
rgrover1 103:138bdc859cc9 137 #elif defined(__ICCARM__)
rgrover1 103:138bdc859cc9 138 #pragma language=extended
rgrover1 103:138bdc859cc9 139 #elif defined(__GNUC__)
rgrover1 103:138bdc859cc9 140 /* anonymous unions are enabled by default */
rgrover1 103:138bdc859cc9 141 #elif defined(__TMS470__)
rgrover1 103:138bdc859cc9 142 /* anonymous unions are enabled by default */
rgrover1 103:138bdc859cc9 143 #elif defined(__TASKING__)
rgrover1 103:138bdc859cc9 144 #pragma warning 586
rgrover1 103:138bdc859cc9 145 #else
rgrover1 103:138bdc859cc9 146 #warning Not supported compiler type
rgrover1 103:138bdc859cc9 147 #endif
rgrover1 103:138bdc859cc9 148
rgrover1 103:138bdc859cc9 149
rgrover1 103:138bdc859cc9 150 typedef struct {
rgrover1 103:138bdc859cc9 151 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
rgrover1 103:138bdc859cc9 152 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
rgrover1 103:138bdc859cc9 153 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
rgrover1 103:138bdc859cc9 154 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
rgrover1 103:138bdc859cc9 155 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
rgrover1 103:138bdc859cc9 156 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
rgrover1 103:138bdc859cc9 157 } AMLI_RAMPRI_Type;
rgrover1 103:138bdc859cc9 158
rgrover1 103:138bdc859cc9 159 typedef struct {
rgrover1 103:138bdc859cc9 160 __IO uint32_t SCK; /*!< Pin select for SCK. */
rgrover1 103:138bdc859cc9 161 __IO uint32_t MOSI; /*!< Pin select for MOSI. */
rgrover1 103:138bdc859cc9 162 __IO uint32_t MISO; /*!< Pin select for MISO. */
rgrover1 103:138bdc859cc9 163 } SPIM_PSEL_Type;
rgrover1 103:138bdc859cc9 164
rgrover1 103:138bdc859cc9 165 typedef struct {
rgrover1 103:138bdc859cc9 166 __IO uint32_t PTR; /*!< Data pointer. */
rgrover1 103:138bdc859cc9 167 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
rgrover1 103:138bdc859cc9 168 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
rgrover1 103:138bdc859cc9 169 } SPIM_RXD_Type;
rgrover1 103:138bdc859cc9 170
rgrover1 103:138bdc859cc9 171 typedef struct {
rgrover1 103:138bdc859cc9 172 __IO uint32_t PTR; /*!< Data pointer. */
rgrover1 103:138bdc859cc9 173 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
rgrover1 103:138bdc859cc9 174 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
rgrover1 103:138bdc859cc9 175 } SPIM_TXD_Type;
rgrover1 103:138bdc859cc9 176
rgrover1 103:138bdc859cc9 177 typedef struct {
rgrover1 103:138bdc859cc9 178 __O uint32_t EN; /*!< Enable channel group. */
rgrover1 103:138bdc859cc9 179 __O uint32_t DIS; /*!< Disable channel group. */
rgrover1 103:138bdc859cc9 180 } PPI_TASKS_CHG_Type;
rgrover1 103:138bdc859cc9 181
rgrover1 103:138bdc859cc9 182 typedef struct {
rgrover1 103:138bdc859cc9 183 __IO uint32_t EEP; /*!< Channel event end-point. */
rgrover1 103:138bdc859cc9 184 __IO uint32_t TEP; /*!< Channel task end-point. */
rgrover1 103:138bdc859cc9 185 } PPI_CH_Type;
rgrover1 103:138bdc859cc9 186
rgrover1 103:138bdc859cc9 187 typedef struct {
rgrover1 103:138bdc859cc9 188 __I uint32_t PART; /*!< Part code */
rgrover1 103:138bdc859cc9 189 __I uint32_t VARIANT; /*!< Part variant */
rgrover1 103:138bdc859cc9 190 __I uint32_t PACKAGE; /*!< Package option */
rgrover1 103:138bdc859cc9 191 __I uint32_t RAM; /*!< RAM variant */
rgrover1 103:138bdc859cc9 192 __I uint32_t FLASH; /*!< Flash variant */
rgrover1 103:138bdc859cc9 193 __I uint32_t RESERVED[3]; /*!< Reserved */
rgrover1 103:138bdc859cc9 194 } FICR_INFO_Type;
rgrover1 103:138bdc859cc9 195
rgrover1 103:138bdc859cc9 196
rgrover1 103:138bdc859cc9 197 /* ================================================================================ */
rgrover1 103:138bdc859cc9 198 /* ================ POWER ================ */
rgrover1 103:138bdc859cc9 199 /* ================================================================================ */
rgrover1 103:138bdc859cc9 200
rgrover1 103:138bdc859cc9 201
rgrover1 103:138bdc859cc9 202 /**
rgrover1 103:138bdc859cc9 203 * @brief Power Control. (POWER)
rgrover1 103:138bdc859cc9 204 */
rgrover1 103:138bdc859cc9 205
rgrover1 103:138bdc859cc9 206 typedef struct { /*!< POWER Structure */
rgrover1 103:138bdc859cc9 207 __I uint32_t RESERVED0[30];
rgrover1 103:138bdc859cc9 208 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
rgrover1 103:138bdc859cc9 209 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
rgrover1 103:138bdc859cc9 210 __I uint32_t RESERVED1[34];
rgrover1 103:138bdc859cc9 211 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
rgrover1 103:138bdc859cc9 212 __I uint32_t RESERVED2[126];
rgrover1 103:138bdc859cc9 213 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 103:138bdc859cc9 214 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 103:138bdc859cc9 215 __I uint32_t RESERVED3[61];
rgrover1 103:138bdc859cc9 216 __IO uint32_t RESETREAS; /*!< Reset reason. */
rgrover1 103:138bdc859cc9 217 __I uint32_t RESERVED4[9];
rgrover1 103:138bdc859cc9 218 __I uint32_t RAMSTATUS; /*!< Ram status register. */
rgrover1 103:138bdc859cc9 219 __I uint32_t RESERVED5[53];
rgrover1 103:138bdc859cc9 220 __O uint32_t SYSTEMOFF; /*!< System off register. */
rgrover1 103:138bdc859cc9 221 __I uint32_t RESERVED6[3];
rgrover1 103:138bdc859cc9 222 __IO uint32_t POFCON; /*!< Power failure configuration. */
rgrover1 103:138bdc859cc9 223 __I uint32_t RESERVED7[2];
rgrover1 103:138bdc859cc9 224 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
rgrover1 103:138bdc859cc9 225 register. */
rgrover1 103:138bdc859cc9 226 __I uint32_t RESERVED8;
rgrover1 103:138bdc859cc9 227 __IO uint32_t RAMON; /*!< Ram on/off. */
rgrover1 103:138bdc859cc9 228 __I uint32_t RESERVED9[7];
rgrover1 103:138bdc859cc9 229 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
rgrover1 103:138bdc859cc9 230 is a retained register. */
rgrover1 103:138bdc859cc9 231 __I uint32_t RESERVED10[3];
rgrover1 103:138bdc859cc9 232 __IO uint32_t RAMONB; /*!< Ram on/off. */
rgrover1 103:138bdc859cc9 233 __I uint32_t RESERVED11[8];
rgrover1 103:138bdc859cc9 234 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
rgrover1 103:138bdc859cc9 235 __I uint32_t RESERVED12[291];
rgrover1 103:138bdc859cc9 236 __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
rgrover1 103:138bdc859cc9 237 } NRF_POWER_Type;
rgrover1 103:138bdc859cc9 238
rgrover1 103:138bdc859cc9 239
rgrover1 103:138bdc859cc9 240 /* ================================================================================ */
rgrover1 103:138bdc859cc9 241 /* ================ CLOCK ================ */
rgrover1 103:138bdc859cc9 242 /* ================================================================================ */
rgrover1 103:138bdc859cc9 243
rgrover1 103:138bdc859cc9 244
rgrover1 103:138bdc859cc9 245 /**
rgrover1 103:138bdc859cc9 246 * @brief Clock control. (CLOCK)
rgrover1 103:138bdc859cc9 247 */
rgrover1 103:138bdc859cc9 248
rgrover1 103:138bdc859cc9 249 typedef struct { /*!< CLOCK Structure */
rgrover1 103:138bdc859cc9 250 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
rgrover1 103:138bdc859cc9 251 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
rgrover1 103:138bdc859cc9 252 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
rgrover1 103:138bdc859cc9 253 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
rgrover1 103:138bdc859cc9 254 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
rgrover1 103:138bdc859cc9 255 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
rgrover1 103:138bdc859cc9 256 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
rgrover1 103:138bdc859cc9 257 __I uint32_t RESERVED0[57];
rgrover1 103:138bdc859cc9 258 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
rgrover1 103:138bdc859cc9 259 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
rgrover1 103:138bdc859cc9 260 __I uint32_t RESERVED1;
rgrover1 103:138bdc859cc9 261 __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
rgrover1 103:138bdc859cc9 262 __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
rgrover1 103:138bdc859cc9 263 __I uint32_t RESERVED2[124];
rgrover1 103:138bdc859cc9 264 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 103:138bdc859cc9 265 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 103:138bdc859cc9 266 __I uint32_t RESERVED3[63];
rgrover1 103:138bdc859cc9 267 __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
rgrover1 103:138bdc859cc9 268 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
rgrover1 103:138bdc859cc9 269 __I uint32_t RESERVED4;
rgrover1 103:138bdc859cc9 270 __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
rgrover1 103:138bdc859cc9 271 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
rgrover1 103:138bdc859cc9 272 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
rgrover1 103:138bdc859cc9 273 triggered. */
rgrover1 103:138bdc859cc9 274 __I uint32_t RESERVED5[62];
rgrover1 103:138bdc859cc9 275 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
rgrover1 103:138bdc859cc9 276 __I uint32_t RESERVED6[7];
rgrover1 103:138bdc859cc9 277 __IO uint32_t CTIV; /*!< Calibration timer interval. */
rgrover1 103:138bdc859cc9 278 __I uint32_t RESERVED7[5];
rgrover1 103:138bdc859cc9 279 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
rgrover1 103:138bdc859cc9 280 } NRF_CLOCK_Type;
rgrover1 103:138bdc859cc9 281
rgrover1 103:138bdc859cc9 282
rgrover1 103:138bdc859cc9 283 /* ================================================================================ */
rgrover1 103:138bdc859cc9 284 /* ================ MPU ================ */
rgrover1 103:138bdc859cc9 285 /* ================================================================================ */
rgrover1 103:138bdc859cc9 286
rgrover1 103:138bdc859cc9 287
rgrover1 103:138bdc859cc9 288 /**
rgrover1 103:138bdc859cc9 289 * @brief Memory Protection Unit. (MPU)
rgrover1 103:138bdc859cc9 290 */
rgrover1 103:138bdc859cc9 291
rgrover1 103:138bdc859cc9 292 typedef struct { /*!< MPU Structure */
rgrover1 103:138bdc859cc9 293 __I uint32_t RESERVED0[330];
rgrover1 103:138bdc859cc9 294 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
rgrover1 103:138bdc859cc9 295 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
rgrover1 103:138bdc859cc9 296 __I uint32_t RESERVED1[52];
rgrover1 103:138bdc859cc9 297 __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
rgrover1 103:138bdc859cc9 298 __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
rgrover1 103:138bdc859cc9 299 __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
rgrover1 103:138bdc859cc9 300 __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
rgrover1 103:138bdc859cc9 301 } NRF_MPU_Type;
rgrover1 103:138bdc859cc9 302
rgrover1 103:138bdc859cc9 303
rgrover1 103:138bdc859cc9 304 /* ================================================================================ */
rgrover1 103:138bdc859cc9 305 /* ================ PU ================ */
rgrover1 103:138bdc859cc9 306 /* ================================================================================ */
rgrover1 103:138bdc859cc9 307
rgrover1 103:138bdc859cc9 308
rgrover1 103:138bdc859cc9 309 /**
rgrover1 103:138bdc859cc9 310 * @brief Patch unit. (PU)
rgrover1 103:138bdc859cc9 311 */
rgrover1 103:138bdc859cc9 312
rgrover1 103:138bdc859cc9 313 typedef struct { /*!< PU Structure */
rgrover1 103:138bdc859cc9 314 __I uint32_t RESERVED0[448];
rgrover1 103:138bdc859cc9 315 __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
rgrover1 103:138bdc859cc9 316 __I uint32_t RESERVED1[24];
rgrover1 103:138bdc859cc9 317 __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
rgrover1 103:138bdc859cc9 318 __I uint32_t RESERVED2[24];
rgrover1 103:138bdc859cc9 319 __IO uint32_t PATCHEN; /*!< Patch enable register. */
rgrover1 103:138bdc859cc9 320 __IO uint32_t PATCHENSET; /*!< Patch enable register. */
rgrover1 103:138bdc859cc9 321 __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
rgrover1 103:138bdc859cc9 322 } NRF_PU_Type;
rgrover1 103:138bdc859cc9 323
rgrover1 103:138bdc859cc9 324
rgrover1 103:138bdc859cc9 325 /* ================================================================================ */
rgrover1 103:138bdc859cc9 326 /* ================ AMLI ================ */
rgrover1 103:138bdc859cc9 327 /* ================================================================================ */
rgrover1 103:138bdc859cc9 328
rgrover1 103:138bdc859cc9 329
rgrover1 103:138bdc859cc9 330 /**
rgrover1 103:138bdc859cc9 331 * @brief AHB Multi-Layer Interface. (AMLI)
rgrover1 103:138bdc859cc9 332 */
rgrover1 103:138bdc859cc9 333
rgrover1 103:138bdc859cc9 334 typedef struct { /*!< AMLI Structure */
rgrover1 103:138bdc859cc9 335 __I uint32_t RESERVED0[896];
rgrover1 103:138bdc859cc9 336 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
rgrover1 103:138bdc859cc9 337 } NRF_AMLI_Type;
rgrover1 103:138bdc859cc9 338
rgrover1 103:138bdc859cc9 339
rgrover1 103:138bdc859cc9 340 /* ================================================================================ */
rgrover1 103:138bdc859cc9 341 /* ================ RADIO ================ */
rgrover1 103:138bdc859cc9 342 /* ================================================================================ */
rgrover1 103:138bdc859cc9 343
rgrover1 103:138bdc859cc9 344
rgrover1 103:138bdc859cc9 345 /**
rgrover1 103:138bdc859cc9 346 * @brief The radio. (RADIO)
rgrover1 103:138bdc859cc9 347 */
rgrover1 103:138bdc859cc9 348
rgrover1 103:138bdc859cc9 349 typedef struct { /*!< RADIO Structure */
rgrover1 103:138bdc859cc9 350 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
rgrover1 103:138bdc859cc9 351 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
rgrover1 103:138bdc859cc9 352 __O uint32_t TASKS_START; /*!< Start radio. */
rgrover1 103:138bdc859cc9 353 __O uint32_t TASKS_STOP; /*!< Stop radio. */
rgrover1 103:138bdc859cc9 354 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
rgrover1 103:138bdc859cc9 355 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
rgrover1 103:138bdc859cc9 356 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
rgrover1 103:138bdc859cc9 357 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
rgrover1 103:138bdc859cc9 358 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
rgrover1 103:138bdc859cc9 359 __I uint32_t RESERVED0[55];
rgrover1 103:138bdc859cc9 360 __IO uint32_t EVENTS_READY; /*!< Ready event. */
rgrover1 103:138bdc859cc9 361 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
rgrover1 103:138bdc859cc9 362 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
rgrover1 103:138bdc859cc9 363 __IO uint32_t EVENTS_END; /*!< End event. */
rgrover1 103:138bdc859cc9 364 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
rgrover1 103:138bdc859cc9 365 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
rgrover1 103:138bdc859cc9 366 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
rgrover1 103:138bdc859cc9 367 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
rgrover1 103:138bdc859cc9 368 sample is ready for readout at the RSSISAMPLE register. */
rgrover1 103:138bdc859cc9 369 __I uint32_t RESERVED1[2];
rgrover1 103:138bdc859cc9 370 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */
rgrover1 103:138bdc859cc9 371 __I uint32_t RESERVED2[53];
rgrover1 103:138bdc859cc9 372 __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
rgrover1 103:138bdc859cc9 373 __I uint32_t RESERVED3[64];
rgrover1 103:138bdc859cc9 374 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 103:138bdc859cc9 375 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 103:138bdc859cc9 376 __I uint32_t RESERVED4[61];
rgrover1 103:138bdc859cc9 377 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
rgrover1 103:138bdc859cc9 378 __I uint32_t CD; /*!< Carrier detect. */
rgrover1 103:138bdc859cc9 379 __I uint32_t RXMATCH; /*!< Received address. */
rgrover1 103:138bdc859cc9 380 __I uint32_t RXCRC; /*!< Received CRC. */
rgrover1 103:138bdc859cc9 381 __I uint32_t DAI; /*!< Device address match index. */
rgrover1 103:138bdc859cc9 382 __I uint32_t RESERVED5[60];
rgrover1 103:138bdc859cc9 383 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
rgrover1 103:138bdc859cc9 384 __IO uint32_t FREQUENCY; /*!< Frequency. */
rgrover1 103:138bdc859cc9 385 __IO uint32_t TXPOWER; /*!< Output power. */
rgrover1 103:138bdc859cc9 386 __IO uint32_t MODE; /*!< Data rate and modulation. */
rgrover1 103:138bdc859cc9 387 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
rgrover1 103:138bdc859cc9 388 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
rgrover1 103:138bdc859cc9 389 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
rgrover1 103:138bdc859cc9 390 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
rgrover1 103:138bdc859cc9 391 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
rgrover1 103:138bdc859cc9 392 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
rgrover1 103:138bdc859cc9 393 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
rgrover1 103:138bdc859cc9 394 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
rgrover1 103:138bdc859cc9 395 __IO uint32_t CRCCNF; /*!< CRC configuration. */
rgrover1 103:138bdc859cc9 396 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
rgrover1 103:138bdc859cc9 397 __IO uint32_t CRCINIT; /*!< CRC initial value. */
rgrover1 103:138bdc859cc9 398 __IO uint32_t TEST; /*!< Test features enable register. */
rgrover1 103:138bdc859cc9 399 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
rgrover1 103:138bdc859cc9 400 __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
rgrover1 103:138bdc859cc9 401 __I uint32_t RESERVED6;
rgrover1 103:138bdc859cc9 402 __I uint32_t STATE; /*!< Current radio state. */
rgrover1 103:138bdc859cc9 403 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
rgrover1 103:138bdc859cc9 404 __I uint32_t RESERVED7[2];
rgrover1 103:138bdc859cc9 405 __IO uint32_t BCC; /*!< Bit counter compare. */
rgrover1 103:138bdc859cc9 406 __I uint32_t RESERVED8[39];
rgrover1 103:138bdc859cc9 407 __IO uint32_t DAB[8]; /*!< Device address base segment. */
rgrover1 103:138bdc859cc9 408 __IO uint32_t DAP[8]; /*!< Device address prefix. */
rgrover1 103:138bdc859cc9 409 __IO uint32_t DACNF; /*!< Device address match configuration. */
rgrover1 103:138bdc859cc9 410 __I uint32_t RESERVED9[56];
rgrover1 103:138bdc859cc9 411 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
rgrover1 103:138bdc859cc9 412 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
rgrover1 103:138bdc859cc9 413 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
rgrover1 103:138bdc859cc9 414 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
rgrover1 103:138bdc859cc9 415 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
rgrover1 103:138bdc859cc9 416 __I uint32_t RESERVED10[561];
rgrover1 103:138bdc859cc9 417 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 103:138bdc859cc9 418 } NRF_RADIO_Type;
rgrover1 103:138bdc859cc9 419
rgrover1 103:138bdc859cc9 420
rgrover1 103:138bdc859cc9 421 /* ================================================================================ */
rgrover1 103:138bdc859cc9 422 /* ================ UART ================ */
rgrover1 103:138bdc859cc9 423 /* ================================================================================ */
rgrover1 103:138bdc859cc9 424
rgrover1 103:138bdc859cc9 425
rgrover1 103:138bdc859cc9 426 /**
rgrover1 103:138bdc859cc9 427 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
rgrover1 103:138bdc859cc9 428 */
rgrover1 103:138bdc859cc9 429
rgrover1 103:138bdc859cc9 430 typedef struct { /*!< UART Structure */
rgrover1 103:138bdc859cc9 431 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
rgrover1 103:138bdc859cc9 432 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
rgrover1 103:138bdc859cc9 433 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
rgrover1 103:138bdc859cc9 434 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
rgrover1 103:138bdc859cc9 435 __I uint32_t RESERVED0[3];
rgrover1 103:138bdc859cc9 436 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
rgrover1 103:138bdc859cc9 437 __I uint32_t RESERVED1[56];
rgrover1 103:138bdc859cc9 438 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
rgrover1 103:138bdc859cc9 439 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
rgrover1 103:138bdc859cc9 440 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
rgrover1 103:138bdc859cc9 441 __I uint32_t RESERVED2[4];
rgrover1 103:138bdc859cc9 442 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
rgrover1 103:138bdc859cc9 443 __I uint32_t RESERVED3;
rgrover1 103:138bdc859cc9 444 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
rgrover1 103:138bdc859cc9 445 __I uint32_t RESERVED4[7];
rgrover1 103:138bdc859cc9 446 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
rgrover1 103:138bdc859cc9 447 __I uint32_t RESERVED5[46];
rgrover1 103:138bdc859cc9 448 __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
rgrover1 103:138bdc859cc9 449 __I uint32_t RESERVED6[64];
rgrover1 103:138bdc859cc9 450 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 103:138bdc859cc9 451 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 103:138bdc859cc9 452 __I uint32_t RESERVED7[93];
rgrover1 103:138bdc859cc9 453 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
rgrover1 103:138bdc859cc9 454 __I uint32_t RESERVED8[31];
rgrover1 103:138bdc859cc9 455 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
rgrover1 103:138bdc859cc9 456 __I uint32_t RESERVED9;
rgrover1 103:138bdc859cc9 457 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
rgrover1 103:138bdc859cc9 458 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
rgrover1 103:138bdc859cc9 459 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
rgrover1 103:138bdc859cc9 460 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
rgrover1 103:138bdc859cc9 461 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
rgrover1 103:138bdc859cc9 462 Once read the character is consumed. If read when no character
rgrover1 103:138bdc859cc9 463 available, the UART will stop working. */
rgrover1 103:138bdc859cc9 464 __O uint32_t TXD; /*!< TXD register. */
rgrover1 103:138bdc859cc9 465 __I uint32_t RESERVED10;
rgrover1 103:138bdc859cc9 466 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
rgrover1 103:138bdc859cc9 467 __I uint32_t RESERVED11[17];
rgrover1 103:138bdc859cc9 468 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
rgrover1 103:138bdc859cc9 469 __I uint32_t RESERVED12[675];
rgrover1 103:138bdc859cc9 470 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 103:138bdc859cc9 471 } NRF_UART_Type;
rgrover1 103:138bdc859cc9 472
rgrover1 103:138bdc859cc9 473
rgrover1 103:138bdc859cc9 474 /* ================================================================================ */
rgrover1 103:138bdc859cc9 475 /* ================ SPI ================ */
rgrover1 103:138bdc859cc9 476 /* ================================================================================ */
rgrover1 103:138bdc859cc9 477
rgrover1 103:138bdc859cc9 478
rgrover1 103:138bdc859cc9 479 /**
rgrover1 103:138bdc859cc9 480 * @brief SPI master 0. (SPI)
rgrover1 103:138bdc859cc9 481 */
rgrover1 103:138bdc859cc9 482
rgrover1 103:138bdc859cc9 483 typedef struct { /*!< SPI Structure */
rgrover1 103:138bdc859cc9 484 __I uint32_t RESERVED0[66];
rgrover1 103:138bdc859cc9 485 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
rgrover1 103:138bdc859cc9 486 __I uint32_t RESERVED1[126];
rgrover1 103:138bdc859cc9 487 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 103:138bdc859cc9 488 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 103:138bdc859cc9 489 __I uint32_t RESERVED2[125];
rgrover1 103:138bdc859cc9 490 __IO uint32_t ENABLE; /*!< Enable SPI. */
rgrover1 103:138bdc859cc9 491 __I uint32_t RESERVED3;
rgrover1 103:138bdc859cc9 492 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
rgrover1 103:138bdc859cc9 493 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
rgrover1 103:138bdc859cc9 494 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
rgrover1 103:138bdc859cc9 495 __I uint32_t RESERVED4;
rgrover1 103:138bdc859cc9 496 __I uint32_t RXD; /*!< RX data. */
rgrover1 103:138bdc859cc9 497 __IO uint32_t TXD; /*!< TX data. */
rgrover1 103:138bdc859cc9 498 __I uint32_t RESERVED5;
rgrover1 103:138bdc859cc9 499 __IO uint32_t FREQUENCY; /*!< SPI frequency */
rgrover1 103:138bdc859cc9 500 __I uint32_t RESERVED6[11];
rgrover1 103:138bdc859cc9 501 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 103:138bdc859cc9 502 __I uint32_t RESERVED7[681];
rgrover1 103:138bdc859cc9 503 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 103:138bdc859cc9 504 } NRF_SPI_Type;
rgrover1 103:138bdc859cc9 505
rgrover1 103:138bdc859cc9 506
rgrover1 103:138bdc859cc9 507 /* ================================================================================ */
rgrover1 103:138bdc859cc9 508 /* ================ TWI ================ */
rgrover1 103:138bdc859cc9 509 /* ================================================================================ */
rgrover1 103:138bdc859cc9 510
rgrover1 103:138bdc859cc9 511
rgrover1 103:138bdc859cc9 512 /**
rgrover1 103:138bdc859cc9 513 * @brief Two-wire interface master 0. (TWI)
rgrover1 103:138bdc859cc9 514 */
rgrover1 103:138bdc859cc9 515
rgrover1 103:138bdc859cc9 516 typedef struct { /*!< TWI Structure */
rgrover1 103:138bdc859cc9 517 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
rgrover1 103:138bdc859cc9 518 __I uint32_t RESERVED0;
rgrover1 103:138bdc859cc9 519 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
rgrover1 103:138bdc859cc9 520 __I uint32_t RESERVED1[2];
rgrover1 103:138bdc859cc9 521 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
rgrover1 103:138bdc859cc9 522 __I uint32_t RESERVED2;
rgrover1 103:138bdc859cc9 523 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
rgrover1 103:138bdc859cc9 524 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
rgrover1 103:138bdc859cc9 525 __I uint32_t RESERVED3[56];
rgrover1 103:138bdc859cc9 526 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
rgrover1 103:138bdc859cc9 527 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
rgrover1 103:138bdc859cc9 528 __I uint32_t RESERVED4[4];
rgrover1 103:138bdc859cc9 529 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
rgrover1 103:138bdc859cc9 530 __I uint32_t RESERVED5;
rgrover1 103:138bdc859cc9 531 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
rgrover1 103:138bdc859cc9 532 __I uint32_t RESERVED6[4];
rgrover1 103:138bdc859cc9 533 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
rgrover1 103:138bdc859cc9 534 __I uint32_t RESERVED7[3];
rgrover1 103:138bdc859cc9 535 __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
rgrover1 103:138bdc859cc9 536 __I uint32_t RESERVED8[45];
rgrover1 103:138bdc859cc9 537 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
rgrover1 103:138bdc859cc9 538 __I uint32_t RESERVED9[64];
rgrover1 103:138bdc859cc9 539 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 103:138bdc859cc9 540 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 103:138bdc859cc9 541 __I uint32_t RESERVED10[110];
rgrover1 103:138bdc859cc9 542 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
rgrover1 103:138bdc859cc9 543 __I uint32_t RESERVED11[14];
rgrover1 103:138bdc859cc9 544 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
rgrover1 103:138bdc859cc9 545 __I uint32_t RESERVED12;
rgrover1 103:138bdc859cc9 546 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
rgrover1 103:138bdc859cc9 547 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
rgrover1 103:138bdc859cc9 548 __I uint32_t RESERVED13[2];
rgrover1 103:138bdc859cc9 549 __I uint32_t RXD; /*!< RX data register. */
rgrover1 103:138bdc859cc9 550 __IO uint32_t TXD; /*!< TX data register. */
rgrover1 103:138bdc859cc9 551 __I uint32_t RESERVED14;
rgrover1 103:138bdc859cc9 552 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
rgrover1 103:138bdc859cc9 553 __I uint32_t RESERVED15[24];
rgrover1 103:138bdc859cc9 554 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
rgrover1 103:138bdc859cc9 555 __I uint32_t RESERVED16[668];
rgrover1 103:138bdc859cc9 556 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 103:138bdc859cc9 557 } NRF_TWI_Type;
rgrover1 103:138bdc859cc9 558
rgrover1 103:138bdc859cc9 559
rgrover1 103:138bdc859cc9 560 /* ================================================================================ */
rgrover1 103:138bdc859cc9 561 /* ================ SPIS ================ */
rgrover1 103:138bdc859cc9 562 /* ================================================================================ */
rgrover1 103:138bdc859cc9 563
rgrover1 103:138bdc859cc9 564
rgrover1 103:138bdc859cc9 565 /**
rgrover1 103:138bdc859cc9 566 * @brief SPI slave 1. (SPIS)
rgrover1 103:138bdc859cc9 567 */
rgrover1 103:138bdc859cc9 568
rgrover1 103:138bdc859cc9 569 typedef struct { /*!< SPIS Structure */
rgrover1 103:138bdc859cc9 570 __I uint32_t RESERVED0[9];
rgrover1 103:138bdc859cc9 571 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
rgrover1 103:138bdc859cc9 572 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
rgrover1 103:138bdc859cc9 573 __I uint32_t RESERVED1[54];
rgrover1 103:138bdc859cc9 574 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
rgrover1 103:138bdc859cc9 575 __I uint32_t RESERVED2[8];
rgrover1 103:138bdc859cc9 576 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
rgrover1 103:138bdc859cc9 577 __I uint32_t RESERVED3[53];
rgrover1 103:138bdc859cc9 578 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
rgrover1 103:138bdc859cc9 579 __I uint32_t RESERVED4[64];
rgrover1 103:138bdc859cc9 580 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 103:138bdc859cc9 581 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 103:138bdc859cc9 582 __I uint32_t RESERVED5[61];
rgrover1 103:138bdc859cc9 583 __I uint32_t SEMSTAT; /*!< Semaphore status. */
rgrover1 103:138bdc859cc9 584 __I uint32_t RESERVED6[15];
rgrover1 103:138bdc859cc9 585 __IO uint32_t STATUS; /*!< Status from last transaction. */
rgrover1 103:138bdc859cc9 586 __I uint32_t RESERVED7[47];
rgrover1 103:138bdc859cc9 587 __IO uint32_t ENABLE; /*!< Enable SPIS. */
rgrover1 103:138bdc859cc9 588 __I uint32_t RESERVED8;
rgrover1 103:138bdc859cc9 589 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
rgrover1 103:138bdc859cc9 590 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
rgrover1 103:138bdc859cc9 591 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
rgrover1 103:138bdc859cc9 592 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
rgrover1 103:138bdc859cc9 593 __I uint32_t RESERVED9[7];
rgrover1 103:138bdc859cc9 594 __IO uint32_t RXDPTR; /*!< RX data pointer. */
rgrover1 103:138bdc859cc9 595 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
rgrover1 103:138bdc859cc9 596 __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
rgrover1 103:138bdc859cc9 597 __I uint32_t RESERVED10;
rgrover1 103:138bdc859cc9 598 __IO uint32_t TXDPTR; /*!< TX data pointer. */
rgrover1 103:138bdc859cc9 599 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
rgrover1 103:138bdc859cc9 600 __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
rgrover1 103:138bdc859cc9 601 __I uint32_t RESERVED11;
rgrover1 103:138bdc859cc9 602 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 103:138bdc859cc9 603 __I uint32_t RESERVED12;
rgrover1 103:138bdc859cc9 604 __IO uint32_t DEF; /*!< Default character. */
rgrover1 103:138bdc859cc9 605 __I uint32_t RESERVED13[24];
rgrover1 103:138bdc859cc9 606 __IO uint32_t ORC; /*!< Over-read character. */
rgrover1 103:138bdc859cc9 607 __I uint32_t RESERVED14[654];
rgrover1 103:138bdc859cc9 608 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 103:138bdc859cc9 609 } NRF_SPIS_Type;
rgrover1 103:138bdc859cc9 610
rgrover1 103:138bdc859cc9 611
rgrover1 103:138bdc859cc9 612 /* ================================================================================ */
rgrover1 103:138bdc859cc9 613 /* ================ SPIM ================ */
rgrover1 103:138bdc859cc9 614 /* ================================================================================ */
rgrover1 103:138bdc859cc9 615
rgrover1 103:138bdc859cc9 616
rgrover1 103:138bdc859cc9 617 /**
rgrover1 103:138bdc859cc9 618 * @brief SPI master with easyDMA 1. (SPIM)
rgrover1 103:138bdc859cc9 619 */
rgrover1 103:138bdc859cc9 620
rgrover1 103:138bdc859cc9 621 typedef struct { /*!< SPIM Structure */
rgrover1 103:138bdc859cc9 622 __I uint32_t RESERVED0[4];
rgrover1 103:138bdc859cc9 623 __O uint32_t TASKS_START; /*!< Start SPI transaction. */
rgrover1 103:138bdc859cc9 624 __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
rgrover1 103:138bdc859cc9 625 __I uint32_t RESERVED1;
rgrover1 103:138bdc859cc9 626 __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
rgrover1 103:138bdc859cc9 627 __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
rgrover1 103:138bdc859cc9 628 __I uint32_t RESERVED2[56];
rgrover1 103:138bdc859cc9 629 __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
rgrover1 103:138bdc859cc9 630 __I uint32_t RESERVED3[2];
rgrover1 103:138bdc859cc9 631 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
rgrover1 103:138bdc859cc9 632 __I uint32_t RESERVED4;
rgrover1 103:138bdc859cc9 633 __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached. */
rgrover1 103:138bdc859cc9 634 __I uint32_t RESERVED5;
rgrover1 103:138bdc859cc9 635 __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
rgrover1 103:138bdc859cc9 636 __I uint32_t RESERVED6[10];
rgrover1 103:138bdc859cc9 637 __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
rgrover1 103:138bdc859cc9 638 __I uint32_t RESERVED7[44];
rgrover1 103:138bdc859cc9 639 __IO uint32_t SHORTS; /*!< Shortcuts for SPIM. */
rgrover1 103:138bdc859cc9 640 __I uint32_t RESERVED8[64];
rgrover1 103:138bdc859cc9 641 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 103:138bdc859cc9 642 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 103:138bdc859cc9 643 __I uint32_t RESERVED9[125];
rgrover1 103:138bdc859cc9 644 __IO uint32_t ENABLE; /*!< Enable SPIM. */
rgrover1 103:138bdc859cc9 645 __I uint32_t RESERVED10;
rgrover1 103:138bdc859cc9 646 SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
rgrover1 103:138bdc859cc9 647 __I uint32_t RESERVED11;
rgrover1 103:138bdc859cc9 648 __I uint32_t RXDDATA; /*!< RXD register. */
rgrover1 103:138bdc859cc9 649 __IO uint32_t TXDDATA; /*!< TXD register. */
rgrover1 103:138bdc859cc9 650 __I uint32_t RESERVED12;
rgrover1 103:138bdc859cc9 651 __IO uint32_t FREQUENCY; /*!< SPI frequency. */
rgrover1 103:138bdc859cc9 652 __I uint32_t RESERVED13[3];
rgrover1 103:138bdc859cc9 653 SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
rgrover1 103:138bdc859cc9 654 __I uint32_t RESERVED14;
rgrover1 103:138bdc859cc9 655 SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
rgrover1 103:138bdc859cc9 656 __I uint32_t RESERVED15;
rgrover1 103:138bdc859cc9 657 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 103:138bdc859cc9 658 __I uint32_t RESERVED16[26];
rgrover1 103:138bdc859cc9 659 __IO uint32_t ORC; /*!< Over-read character. */
rgrover1 103:138bdc859cc9 660 __I uint32_t RESERVED17[654];
rgrover1 103:138bdc859cc9 661 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 103:138bdc859cc9 662 } NRF_SPIM_Type;
rgrover1 103:138bdc859cc9 663
rgrover1 103:138bdc859cc9 664
rgrover1 103:138bdc859cc9 665 /* ================================================================================ */
rgrover1 103:138bdc859cc9 666 /* ================ GPIOTE ================ */
rgrover1 103:138bdc859cc9 667 /* ================================================================================ */
rgrover1 103:138bdc859cc9 668
rgrover1 103:138bdc859cc9 669
rgrover1 103:138bdc859cc9 670 /**
rgrover1 103:138bdc859cc9 671 * @brief GPIO tasks and events. (GPIOTE)
rgrover1 103:138bdc859cc9 672 */
rgrover1 103:138bdc859cc9 673
rgrover1 103:138bdc859cc9 674 typedef struct { /*!< GPIOTE Structure */
rgrover1 103:138bdc859cc9 675 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
rgrover1 103:138bdc859cc9 676 __I uint32_t RESERVED0[60];
rgrover1 103:138bdc859cc9 677 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
rgrover1 103:138bdc859cc9 678 __I uint32_t RESERVED1[27];
rgrover1 103:138bdc859cc9 679 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
rgrover1 103:138bdc859cc9 680 __I uint32_t RESERVED2[97];
rgrover1 103:138bdc859cc9 681 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 103:138bdc859cc9 682 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 103:138bdc859cc9 683 __I uint32_t RESERVED3[129];
rgrover1 103:138bdc859cc9 684 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
rgrover1 103:138bdc859cc9 685 __I uint32_t RESERVED4[695];
rgrover1 103:138bdc859cc9 686 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 103:138bdc859cc9 687 } NRF_GPIOTE_Type;
rgrover1 103:138bdc859cc9 688
rgrover1 103:138bdc859cc9 689
rgrover1 103:138bdc859cc9 690 /* ================================================================================ */
rgrover1 103:138bdc859cc9 691 /* ================ ADC ================ */
rgrover1 103:138bdc859cc9 692 /* ================================================================================ */
rgrover1 103:138bdc859cc9 693
rgrover1 103:138bdc859cc9 694
rgrover1 103:138bdc859cc9 695 /**
rgrover1 103:138bdc859cc9 696 * @brief Analog to digital converter. (ADC)
rgrover1 103:138bdc859cc9 697 */
rgrover1 103:138bdc859cc9 698
rgrover1 103:138bdc859cc9 699 typedef struct { /*!< ADC Structure */
rgrover1 103:138bdc859cc9 700 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
rgrover1 103:138bdc859cc9 701 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
rgrover1 103:138bdc859cc9 702 __I uint32_t RESERVED0[62];
rgrover1 103:138bdc859cc9 703 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
rgrover1 103:138bdc859cc9 704 __I uint32_t RESERVED1[128];
rgrover1 103:138bdc859cc9 705 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 103:138bdc859cc9 706 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 103:138bdc859cc9 707 __I uint32_t RESERVED2[61];
rgrover1 103:138bdc859cc9 708 __I uint32_t BUSY; /*!< ADC busy register. */
rgrover1 103:138bdc859cc9 709 __I uint32_t RESERVED3[63];
rgrover1 103:138bdc859cc9 710 __IO uint32_t ENABLE; /*!< ADC enable. */
rgrover1 103:138bdc859cc9 711 __IO uint32_t CONFIG; /*!< ADC configuration register. */
rgrover1 103:138bdc859cc9 712 __I uint32_t RESULT; /*!< Result of ADC conversion. */
rgrover1 103:138bdc859cc9 713 __I uint32_t RESERVED4[700];
rgrover1 103:138bdc859cc9 714 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 103:138bdc859cc9 715 } NRF_ADC_Type;
rgrover1 103:138bdc859cc9 716
rgrover1 103:138bdc859cc9 717
rgrover1 103:138bdc859cc9 718 /* ================================================================================ */
rgrover1 103:138bdc859cc9 719 /* ================ TIMER ================ */
rgrover1 103:138bdc859cc9 720 /* ================================================================================ */
rgrover1 103:138bdc859cc9 721
rgrover1 103:138bdc859cc9 722
rgrover1 103:138bdc859cc9 723 /**
rgrover1 103:138bdc859cc9 724 * @brief Timer 0. (TIMER)
rgrover1 103:138bdc859cc9 725 */
rgrover1 103:138bdc859cc9 726
rgrover1 103:138bdc859cc9 727 typedef struct { /*!< TIMER Structure */
rgrover1 103:138bdc859cc9 728 __O uint32_t TASKS_START; /*!< Start Timer. */
rgrover1 103:138bdc859cc9 729 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
rgrover1 103:138bdc859cc9 730 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
rgrover1 103:138bdc859cc9 731 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
rgrover1 103:138bdc859cc9 732 __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
rgrover1 103:138bdc859cc9 733 __I uint32_t RESERVED0[11];
rgrover1 103:138bdc859cc9 734 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
rgrover1 103:138bdc859cc9 735 __I uint32_t RESERVED1[60];
rgrover1 103:138bdc859cc9 736 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
rgrover1 103:138bdc859cc9 737 __I uint32_t RESERVED2[44];
rgrover1 103:138bdc859cc9 738 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
rgrover1 103:138bdc859cc9 739 __I uint32_t RESERVED3[64];
rgrover1 103:138bdc859cc9 740 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 103:138bdc859cc9 741 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 103:138bdc859cc9 742 __I uint32_t RESERVED4[126];
rgrover1 103:138bdc859cc9 743 __IO uint32_t MODE; /*!< Timer Mode selection. */
rgrover1 103:138bdc859cc9 744 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
rgrover1 103:138bdc859cc9 745 __I uint32_t RESERVED5;
rgrover1 103:138bdc859cc9 746 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
rgrover1 103:138bdc859cc9 747 clock frequency is divided by 2^SCALE. */
rgrover1 103:138bdc859cc9 748 __I uint32_t RESERVED6[11];
rgrover1 103:138bdc859cc9 749 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
rgrover1 103:138bdc859cc9 750 __I uint32_t RESERVED7[683];
rgrover1 103:138bdc859cc9 751 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 103:138bdc859cc9 752 } NRF_TIMER_Type;
rgrover1 103:138bdc859cc9 753
rgrover1 103:138bdc859cc9 754
rgrover1 103:138bdc859cc9 755 /* ================================================================================ */
rgrover1 103:138bdc859cc9 756 /* ================ RTC ================ */
rgrover1 103:138bdc859cc9 757 /* ================================================================================ */
rgrover1 103:138bdc859cc9 758
rgrover1 103:138bdc859cc9 759
rgrover1 103:138bdc859cc9 760 /**
rgrover1 103:138bdc859cc9 761 * @brief Real time counter 0. (RTC)
rgrover1 103:138bdc859cc9 762 */
rgrover1 103:138bdc859cc9 763
rgrover1 103:138bdc859cc9 764 typedef struct { /*!< RTC Structure */
rgrover1 103:138bdc859cc9 765 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
rgrover1 103:138bdc859cc9 766 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
rgrover1 103:138bdc859cc9 767 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
rgrover1 103:138bdc859cc9 768 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
rgrover1 103:138bdc859cc9 769 __I uint32_t RESERVED0[60];
rgrover1 103:138bdc859cc9 770 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
rgrover1 103:138bdc859cc9 771 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
rgrover1 103:138bdc859cc9 772 __I uint32_t RESERVED1[14];
rgrover1 103:138bdc859cc9 773 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
rgrover1 103:138bdc859cc9 774 __I uint32_t RESERVED2[109];
rgrover1 103:138bdc859cc9 775 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 103:138bdc859cc9 776 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 103:138bdc859cc9 777 __I uint32_t RESERVED3[13];
rgrover1 103:138bdc859cc9 778 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
rgrover1 103:138bdc859cc9 779 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
rgrover1 103:138bdc859cc9 780 the value of EVTEN. */
rgrover1 103:138bdc859cc9 781 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
rgrover1 103:138bdc859cc9 782 gives the value of EVTEN. */
rgrover1 103:138bdc859cc9 783 __I uint32_t RESERVED4[110];
rgrover1 103:138bdc859cc9 784 __I uint32_t COUNTER; /*!< Current COUNTER value. */
rgrover1 103:138bdc859cc9 785 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
rgrover1 103:138bdc859cc9 786 Must be written when RTC is STOPed. */
rgrover1 103:138bdc859cc9 787 __I uint32_t RESERVED5[13];
rgrover1 103:138bdc859cc9 788 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
rgrover1 103:138bdc859cc9 789 __I uint32_t RESERVED6[683];
rgrover1 103:138bdc859cc9 790 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 103:138bdc859cc9 791 } NRF_RTC_Type;
rgrover1 103:138bdc859cc9 792
rgrover1 103:138bdc859cc9 793
rgrover1 103:138bdc859cc9 794 /* ================================================================================ */
rgrover1 103:138bdc859cc9 795 /* ================ TEMP ================ */
rgrover1 103:138bdc859cc9 796 /* ================================================================================ */
rgrover1 103:138bdc859cc9 797
rgrover1 103:138bdc859cc9 798
rgrover1 103:138bdc859cc9 799 /**
rgrover1 103:138bdc859cc9 800 * @brief Temperature Sensor. (TEMP)
rgrover1 103:138bdc859cc9 801 */
rgrover1 103:138bdc859cc9 802
rgrover1 103:138bdc859cc9 803 typedef struct { /*!< TEMP Structure */
rgrover1 103:138bdc859cc9 804 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
rgrover1 103:138bdc859cc9 805 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
rgrover1 103:138bdc859cc9 806 __I uint32_t RESERVED0[62];
rgrover1 103:138bdc859cc9 807 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
rgrover1 103:138bdc859cc9 808 __I uint32_t RESERVED1[128];
rgrover1 103:138bdc859cc9 809 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 103:138bdc859cc9 810 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 103:138bdc859cc9 811 __I uint32_t RESERVED2[127];
rgrover1 103:138bdc859cc9 812 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
rgrover1 103:138bdc859cc9 813 __I uint32_t RESERVED3[700];
rgrover1 103:138bdc859cc9 814 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 103:138bdc859cc9 815 } NRF_TEMP_Type;
rgrover1 103:138bdc859cc9 816
rgrover1 103:138bdc859cc9 817
rgrover1 103:138bdc859cc9 818 /* ================================================================================ */
rgrover1 103:138bdc859cc9 819 /* ================ RNG ================ */
rgrover1 103:138bdc859cc9 820 /* ================================================================================ */
rgrover1 103:138bdc859cc9 821
rgrover1 103:138bdc859cc9 822
rgrover1 103:138bdc859cc9 823 /**
rgrover1 103:138bdc859cc9 824 * @brief Random Number Generator. (RNG)
rgrover1 103:138bdc859cc9 825 */
rgrover1 103:138bdc859cc9 826
rgrover1 103:138bdc859cc9 827 typedef struct { /*!< RNG Structure */
rgrover1 103:138bdc859cc9 828 __O uint32_t TASKS_START; /*!< Start the random number generator. */
rgrover1 103:138bdc859cc9 829 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
rgrover1 103:138bdc859cc9 830 __I uint32_t RESERVED0[62];
rgrover1 103:138bdc859cc9 831 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
rgrover1 103:138bdc859cc9 832 __I uint32_t RESERVED1[63];
rgrover1 103:138bdc859cc9 833 __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
rgrover1 103:138bdc859cc9 834 __I uint32_t RESERVED2[64];
rgrover1 103:138bdc859cc9 835 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
rgrover1 103:138bdc859cc9 836 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
rgrover1 103:138bdc859cc9 837 __I uint32_t RESERVED3[126];
rgrover1 103:138bdc859cc9 838 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 103:138bdc859cc9 839 __I uint32_t VALUE; /*!< RNG random number. */
rgrover1 103:138bdc859cc9 840 __I uint32_t RESERVED4[700];
rgrover1 103:138bdc859cc9 841 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 103:138bdc859cc9 842 } NRF_RNG_Type;
rgrover1 103:138bdc859cc9 843
rgrover1 103:138bdc859cc9 844
rgrover1 103:138bdc859cc9 845 /* ================================================================================ */
rgrover1 103:138bdc859cc9 846 /* ================ ECB ================ */
rgrover1 103:138bdc859cc9 847 /* ================================================================================ */
rgrover1 103:138bdc859cc9 848
rgrover1 103:138bdc859cc9 849
rgrover1 103:138bdc859cc9 850 /**
rgrover1 103:138bdc859cc9 851 * @brief AES ECB Mode Encryption. (ECB)
rgrover1 103:138bdc859cc9 852 */
rgrover1 103:138bdc859cc9 853
rgrover1 103:138bdc859cc9 854 typedef struct { /*!< ECB Structure */
rgrover1 103:138bdc859cc9 855 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
rgrover1 103:138bdc859cc9 856 will not initiate a new encryption and the ERRORECB event will
rgrover1 103:138bdc859cc9 857 be triggered. */
rgrover1 103:138bdc859cc9 858 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
rgrover1 103:138bdc859cc9 859 this will will trigger the ERRORECB event. */
rgrover1 103:138bdc859cc9 860 __I uint32_t RESERVED0[62];
rgrover1 103:138bdc859cc9 861 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
rgrover1 103:138bdc859cc9 862 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
rgrover1 103:138bdc859cc9 863 error. */
rgrover1 103:138bdc859cc9 864 __I uint32_t RESERVED1[127];
rgrover1 103:138bdc859cc9 865 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 103:138bdc859cc9 866 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 103:138bdc859cc9 867 __I uint32_t RESERVED2[126];
rgrover1 103:138bdc859cc9 868 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
rgrover1 103:138bdc859cc9 869 __I uint32_t RESERVED3[701];
rgrover1 103:138bdc859cc9 870 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 103:138bdc859cc9 871 } NRF_ECB_Type;
rgrover1 103:138bdc859cc9 872
rgrover1 103:138bdc859cc9 873
rgrover1 103:138bdc859cc9 874 /* ================================================================================ */
rgrover1 103:138bdc859cc9 875 /* ================ AAR ================ */
rgrover1 103:138bdc859cc9 876 /* ================================================================================ */
rgrover1 103:138bdc859cc9 877
rgrover1 103:138bdc859cc9 878
rgrover1 103:138bdc859cc9 879 /**
rgrover1 103:138bdc859cc9 880 * @brief Accelerated Address Resolver. (AAR)
rgrover1 103:138bdc859cc9 881 */
rgrover1 103:138bdc859cc9 882
rgrover1 103:138bdc859cc9 883 typedef struct { /*!< AAR Structure */
rgrover1 103:138bdc859cc9 884 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
rgrover1 103:138bdc859cc9 885 data structure. */
rgrover1 103:138bdc859cc9 886 __I uint32_t RESERVED0;
rgrover1 103:138bdc859cc9 887 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
rgrover1 103:138bdc859cc9 888 __I uint32_t RESERVED1[61];
rgrover1 103:138bdc859cc9 889 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
rgrover1 103:138bdc859cc9 890 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
rgrover1 103:138bdc859cc9 891 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
rgrover1 103:138bdc859cc9 892 __I uint32_t RESERVED2[126];
rgrover1 103:138bdc859cc9 893 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 103:138bdc859cc9 894 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 103:138bdc859cc9 895 __I uint32_t RESERVED3[61];
rgrover1 103:138bdc859cc9 896 __I uint32_t STATUS; /*!< Resolution status. */
rgrover1 103:138bdc859cc9 897 __I uint32_t RESERVED4[63];
rgrover1 103:138bdc859cc9 898 __IO uint32_t ENABLE; /*!< Enable AAR. */
rgrover1 103:138bdc859cc9 899 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
rgrover1 103:138bdc859cc9 900 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
rgrover1 103:138bdc859cc9 901 __I uint32_t RESERVED5;
rgrover1 103:138bdc859cc9 902 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
rgrover1 103:138bdc859cc9 903 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
rgrover1 103:138bdc859cc9 904 during resolution. A minimum of 3 bytes must be reserved. */
rgrover1 103:138bdc859cc9 905 __I uint32_t RESERVED6[697];
rgrover1 103:138bdc859cc9 906 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 103:138bdc859cc9 907 } NRF_AAR_Type;
rgrover1 103:138bdc859cc9 908
rgrover1 103:138bdc859cc9 909
rgrover1 103:138bdc859cc9 910 /* ================================================================================ */
rgrover1 103:138bdc859cc9 911 /* ================ CCM ================ */
rgrover1 103:138bdc859cc9 912 /* ================================================================================ */
rgrover1 103:138bdc859cc9 913
rgrover1 103:138bdc859cc9 914
rgrover1 103:138bdc859cc9 915 /**
rgrover1 103:138bdc859cc9 916 * @brief AES CCM Mode Encryption. (CCM)
rgrover1 103:138bdc859cc9 917 */
rgrover1 103:138bdc859cc9 918
rgrover1 103:138bdc859cc9 919 typedef struct { /*!< CCM Structure */
rgrover1 103:138bdc859cc9 920 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
rgrover1 103:138bdc859cc9 921 itself when completed. */
rgrover1 103:138bdc859cc9 922 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
rgrover1 103:138bdc859cc9 923 completed. */
rgrover1 103:138bdc859cc9 924 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
rgrover1 103:138bdc859cc9 925 __I uint32_t RESERVED0[61];
rgrover1 103:138bdc859cc9 926 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
rgrover1 103:138bdc859cc9 927 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
rgrover1 103:138bdc859cc9 928 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
rgrover1 103:138bdc859cc9 929 __I uint32_t RESERVED1[61];
rgrover1 103:138bdc859cc9 930 __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
rgrover1 103:138bdc859cc9 931 __I uint32_t RESERVED2[64];
rgrover1 103:138bdc859cc9 932 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 103:138bdc859cc9 933 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 103:138bdc859cc9 934 __I uint32_t RESERVED3[61];
rgrover1 103:138bdc859cc9 935 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
rgrover1 103:138bdc859cc9 936 __I uint32_t RESERVED4[63];
rgrover1 103:138bdc859cc9 937 __IO uint32_t ENABLE; /*!< CCM enable. */
rgrover1 103:138bdc859cc9 938 __IO uint32_t MODE; /*!< Operation mode. */
rgrover1 103:138bdc859cc9 939 __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
rgrover1 103:138bdc859cc9 940 __IO uint32_t INPTR; /*!< Pointer to the input packet. */
rgrover1 103:138bdc859cc9 941 __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
rgrover1 103:138bdc859cc9 942 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
rgrover1 103:138bdc859cc9 943 during resolution. A minimum of 43 bytes must be reserved. */
rgrover1 103:138bdc859cc9 944 __I uint32_t RESERVED5[697];
rgrover1 103:138bdc859cc9 945 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 103:138bdc859cc9 946 } NRF_CCM_Type;
rgrover1 103:138bdc859cc9 947
rgrover1 103:138bdc859cc9 948
rgrover1 103:138bdc859cc9 949 /* ================================================================================ */
rgrover1 103:138bdc859cc9 950 /* ================ WDT ================ */
rgrover1 103:138bdc859cc9 951 /* ================================================================================ */
rgrover1 103:138bdc859cc9 952
rgrover1 103:138bdc859cc9 953
rgrover1 103:138bdc859cc9 954 /**
rgrover1 103:138bdc859cc9 955 * @brief Watchdog Timer. (WDT)
rgrover1 103:138bdc859cc9 956 */
rgrover1 103:138bdc859cc9 957
rgrover1 103:138bdc859cc9 958 typedef struct { /*!< WDT Structure */
rgrover1 103:138bdc859cc9 959 __O uint32_t TASKS_START; /*!< Start the watchdog. */
rgrover1 103:138bdc859cc9 960 __I uint32_t RESERVED0[63];
rgrover1 103:138bdc859cc9 961 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
rgrover1 103:138bdc859cc9 962 __I uint32_t RESERVED1[128];
rgrover1 103:138bdc859cc9 963 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 103:138bdc859cc9 964 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 103:138bdc859cc9 965 __I uint32_t RESERVED2[61];
rgrover1 103:138bdc859cc9 966 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
rgrover1 103:138bdc859cc9 967 __I uint32_t REQSTATUS; /*!< Request status. */
rgrover1 103:138bdc859cc9 968 __I uint32_t RESERVED3[63];
rgrover1 103:138bdc859cc9 969 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
rgrover1 103:138bdc859cc9 970 __IO uint32_t RREN; /*!< Reload request enable. */
rgrover1 103:138bdc859cc9 971 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 103:138bdc859cc9 972 __I uint32_t RESERVED4[60];
rgrover1 103:138bdc859cc9 973 __O uint32_t RR[8]; /*!< Reload requests registers. */
rgrover1 103:138bdc859cc9 974 __I uint32_t RESERVED5[631];
rgrover1 103:138bdc859cc9 975 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 103:138bdc859cc9 976 } NRF_WDT_Type;
rgrover1 103:138bdc859cc9 977
rgrover1 103:138bdc859cc9 978
rgrover1 103:138bdc859cc9 979 /* ================================================================================ */
rgrover1 103:138bdc859cc9 980 /* ================ QDEC ================ */
rgrover1 103:138bdc859cc9 981 /* ================================================================================ */
rgrover1 103:138bdc859cc9 982
rgrover1 103:138bdc859cc9 983
rgrover1 103:138bdc859cc9 984 /**
rgrover1 103:138bdc859cc9 985 * @brief Rotary decoder. (QDEC)
rgrover1 103:138bdc859cc9 986 */
rgrover1 103:138bdc859cc9 987
rgrover1 103:138bdc859cc9 988 typedef struct { /*!< QDEC Structure */
rgrover1 103:138bdc859cc9 989 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
rgrover1 103:138bdc859cc9 990 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
rgrover1 103:138bdc859cc9 991 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
rgrover1 103:138bdc859cc9 992 and clears the ACC registers. */
rgrover1 103:138bdc859cc9 993 __I uint32_t RESERVED0[61];
rgrover1 103:138bdc859cc9 994 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
rgrover1 103:138bdc859cc9 995 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
rgrover1 103:138bdc859cc9 996 ACC register different than zero. */
rgrover1 103:138bdc859cc9 997 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
rgrover1 103:138bdc859cc9 998 __I uint32_t RESERVED1[61];
rgrover1 103:138bdc859cc9 999 __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
rgrover1 103:138bdc859cc9 1000 __I uint32_t RESERVED2[64];
rgrover1 103:138bdc859cc9 1001 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 103:138bdc859cc9 1002 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 103:138bdc859cc9 1003 __I uint32_t RESERVED3[125];
rgrover1 103:138bdc859cc9 1004 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
rgrover1 103:138bdc859cc9 1005 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
rgrover1 103:138bdc859cc9 1006 __IO uint32_t SAMPLEPER; /*!< Sample period. */
rgrover1 103:138bdc859cc9 1007 __I int32_t SAMPLE; /*!< Motion sample value. */
rgrover1 103:138bdc859cc9 1008 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
rgrover1 103:138bdc859cc9 1009 __I int32_t ACC; /*!< Accumulated valid transitions register. */
rgrover1 103:138bdc859cc9 1010 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
rgrover1 103:138bdc859cc9 1011 task. */
rgrover1 103:138bdc859cc9 1012 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
rgrover1 103:138bdc859cc9 1013 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
rgrover1 103:138bdc859cc9 1014 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
rgrover1 103:138bdc859cc9 1015 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
rgrover1 103:138bdc859cc9 1016 __I uint32_t RESERVED4[5];
rgrover1 103:138bdc859cc9 1017 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
rgrover1 103:138bdc859cc9 1018 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
rgrover1 103:138bdc859cc9 1019 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
rgrover1 103:138bdc859cc9 1020 task. */
rgrover1 103:138bdc859cc9 1021 __I uint32_t RESERVED5[684];
rgrover1 103:138bdc859cc9 1022 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 103:138bdc859cc9 1023 } NRF_QDEC_Type;
rgrover1 103:138bdc859cc9 1024
rgrover1 103:138bdc859cc9 1025
rgrover1 103:138bdc859cc9 1026 /* ================================================================================ */
rgrover1 103:138bdc859cc9 1027 /* ================ LPCOMP ================ */
rgrover1 103:138bdc859cc9 1028 /* ================================================================================ */
rgrover1 103:138bdc859cc9 1029
rgrover1 103:138bdc859cc9 1030
rgrover1 103:138bdc859cc9 1031 /**
rgrover1 103:138bdc859cc9 1032 * @brief Low power comparator. (LPCOMP)
rgrover1 103:138bdc859cc9 1033 */
rgrover1 103:138bdc859cc9 1034
rgrover1 103:138bdc859cc9 1035 typedef struct { /*!< LPCOMP Structure */
rgrover1 103:138bdc859cc9 1036 __O uint32_t TASKS_START; /*!< Start the comparator. */
rgrover1 103:138bdc859cc9 1037 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
rgrover1 103:138bdc859cc9 1038 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
rgrover1 103:138bdc859cc9 1039 __I uint32_t RESERVED0[61];
rgrover1 103:138bdc859cc9 1040 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
rgrover1 103:138bdc859cc9 1041 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
rgrover1 103:138bdc859cc9 1042 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
rgrover1 103:138bdc859cc9 1043 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
rgrover1 103:138bdc859cc9 1044 __I uint32_t RESERVED1[60];
rgrover1 103:138bdc859cc9 1045 __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
rgrover1 103:138bdc859cc9 1046 __I uint32_t RESERVED2[64];
rgrover1 103:138bdc859cc9 1047 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 103:138bdc859cc9 1048 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 103:138bdc859cc9 1049 __I uint32_t RESERVED3[61];
rgrover1 103:138bdc859cc9 1050 __I uint32_t RESULT; /*!< Result of last compare. */
rgrover1 103:138bdc859cc9 1051 __I uint32_t RESERVED4[63];
rgrover1 103:138bdc859cc9 1052 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
rgrover1 103:138bdc859cc9 1053 __IO uint32_t PSEL; /*!< Input pin select. */
rgrover1 103:138bdc859cc9 1054 __IO uint32_t REFSEL; /*!< Reference select. */
rgrover1 103:138bdc859cc9 1055 __IO uint32_t EXTREFSEL; /*!< External reference select. */
rgrover1 103:138bdc859cc9 1056 __I uint32_t RESERVED5[4];
rgrover1 103:138bdc859cc9 1057 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
rgrover1 103:138bdc859cc9 1058 __I uint32_t RESERVED6[694];
rgrover1 103:138bdc859cc9 1059 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 103:138bdc859cc9 1060 } NRF_LPCOMP_Type;
rgrover1 103:138bdc859cc9 1061
rgrover1 103:138bdc859cc9 1062
rgrover1 103:138bdc859cc9 1063 /* ================================================================================ */
rgrover1 103:138bdc859cc9 1064 /* ================ SWI ================ */
rgrover1 103:138bdc859cc9 1065 /* ================================================================================ */
rgrover1 103:138bdc859cc9 1066
rgrover1 103:138bdc859cc9 1067
rgrover1 103:138bdc859cc9 1068 /**
rgrover1 103:138bdc859cc9 1069 * @brief SW Interrupts. (SWI)
rgrover1 103:138bdc859cc9 1070 */
rgrover1 103:138bdc859cc9 1071
rgrover1 103:138bdc859cc9 1072 typedef struct { /*!< SWI Structure */
rgrover1 103:138bdc859cc9 1073 __I uint32_t UNUSED; /*!< Unused. */
rgrover1 103:138bdc859cc9 1074 } NRF_SWI_Type;
rgrover1 103:138bdc859cc9 1075
rgrover1 103:138bdc859cc9 1076
rgrover1 103:138bdc859cc9 1077 /* ================================================================================ */
rgrover1 103:138bdc859cc9 1078 /* ================ NVMC ================ */
rgrover1 103:138bdc859cc9 1079 /* ================================================================================ */
rgrover1 103:138bdc859cc9 1080
rgrover1 103:138bdc859cc9 1081
rgrover1 103:138bdc859cc9 1082 /**
rgrover1 103:138bdc859cc9 1083 * @brief Non Volatile Memory Controller. (NVMC)
rgrover1 103:138bdc859cc9 1084 */
rgrover1 103:138bdc859cc9 1085
rgrover1 103:138bdc859cc9 1086 typedef struct { /*!< NVMC Structure */
rgrover1 103:138bdc859cc9 1087 __I uint32_t RESERVED0[256];
rgrover1 103:138bdc859cc9 1088 __I uint32_t READY; /*!< Ready flag. */
rgrover1 103:138bdc859cc9 1089 __I uint32_t RESERVED1[64];
rgrover1 103:138bdc859cc9 1090 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 103:138bdc859cc9 1091 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
rgrover1 103:138bdc859cc9 1092 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
rgrover1 103:138bdc859cc9 1093 __IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
rgrover1 103:138bdc859cc9 1094 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
rgrover1 103:138bdc859cc9 1095 } NRF_NVMC_Type;
rgrover1 103:138bdc859cc9 1096
rgrover1 103:138bdc859cc9 1097
rgrover1 103:138bdc859cc9 1098 /* ================================================================================ */
rgrover1 103:138bdc859cc9 1099 /* ================ PPI ================ */
rgrover1 103:138bdc859cc9 1100 /* ================================================================================ */
rgrover1 103:138bdc859cc9 1101
rgrover1 103:138bdc859cc9 1102
rgrover1 103:138bdc859cc9 1103 /**
rgrover1 103:138bdc859cc9 1104 * @brief PPI controller. (PPI)
rgrover1 103:138bdc859cc9 1105 */
rgrover1 103:138bdc859cc9 1106
rgrover1 103:138bdc859cc9 1107 typedef struct { /*!< PPI Structure */
rgrover1 103:138bdc859cc9 1108 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
rgrover1 103:138bdc859cc9 1109 __I uint32_t RESERVED0[312];
rgrover1 103:138bdc859cc9 1110 __IO uint32_t CHEN; /*!< Channel enable. */
rgrover1 103:138bdc859cc9 1111 __IO uint32_t CHENSET; /*!< Channel enable set. */
rgrover1 103:138bdc859cc9 1112 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
rgrover1 103:138bdc859cc9 1113 __I uint32_t RESERVED1;
rgrover1 103:138bdc859cc9 1114 PPI_CH_Type CH[16]; /*!< PPI Channel. */
rgrover1 103:138bdc859cc9 1115 __I uint32_t RESERVED2[156];
rgrover1 103:138bdc859cc9 1116 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
rgrover1 103:138bdc859cc9 1117 } NRF_PPI_Type;
rgrover1 103:138bdc859cc9 1118
rgrover1 103:138bdc859cc9 1119
rgrover1 103:138bdc859cc9 1120 /* ================================================================================ */
rgrover1 103:138bdc859cc9 1121 /* ================ FICR ================ */
rgrover1 103:138bdc859cc9 1122 /* ================================================================================ */
rgrover1 103:138bdc859cc9 1123
rgrover1 103:138bdc859cc9 1124
rgrover1 103:138bdc859cc9 1125 /**
rgrover1 103:138bdc859cc9 1126 * @brief Factory Information Configuration. (FICR)
rgrover1 103:138bdc859cc9 1127 */
rgrover1 103:138bdc859cc9 1128
rgrover1 103:138bdc859cc9 1129 typedef struct { /*!< FICR Structure */
rgrover1 103:138bdc859cc9 1130 __I uint32_t RESERVED0[4];
rgrover1 103:138bdc859cc9 1131 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
rgrover1 103:138bdc859cc9 1132 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
rgrover1 103:138bdc859cc9 1133 __I uint32_t RESERVED1[4];
rgrover1 103:138bdc859cc9 1134 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
rgrover1 103:138bdc859cc9 1135 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
rgrover1 103:138bdc859cc9 1136 __I uint32_t RESERVED2;
rgrover1 103:138bdc859cc9 1137 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
rgrover1 103:138bdc859cc9 1138
rgrover1 103:138bdc859cc9 1139 union {
rgrover1 103:138bdc859cc9 1140 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
rgrover1 103:138bdc859cc9 1141 kept for backward compatinility purposes. Use SIZERAMBLOCKS
rgrover1 103:138bdc859cc9 1142 instead. */
rgrover1 103:138bdc859cc9 1143 __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
rgrover1 103:138bdc859cc9 1144 };
rgrover1 103:138bdc859cc9 1145 __I uint32_t RESERVED3[5];
rgrover1 103:138bdc859cc9 1146 __I uint32_t CONFIGID; /*!< Configuration identifier. */
rgrover1 103:138bdc859cc9 1147 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
rgrover1 103:138bdc859cc9 1148 __I uint32_t RESERVED4[6];
rgrover1 103:138bdc859cc9 1149 __I uint32_t ER[4]; /*!< Encryption root. */
rgrover1 103:138bdc859cc9 1150 __I uint32_t IR[4]; /*!< Identity root. */
rgrover1 103:138bdc859cc9 1151 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
rgrover1 103:138bdc859cc9 1152 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
rgrover1 103:138bdc859cc9 1153 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
rgrover1 103:138bdc859cc9 1154 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
rgrover1 103:138bdc859cc9 1155 mode. */
rgrover1 103:138bdc859cc9 1156 __I uint32_t RESERVED5[10];
rgrover1 103:138bdc859cc9 1157 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
rgrover1 103:138bdc859cc9 1158 mode. */
rgrover1 103:138bdc859cc9 1159 FICR_INFO_Type INFO; /*!< Device info */
rgrover1 103:138bdc859cc9 1160 } NRF_FICR_Type;
rgrover1 103:138bdc859cc9 1161
rgrover1 103:138bdc859cc9 1162
rgrover1 103:138bdc859cc9 1163 /* ================================================================================ */
rgrover1 103:138bdc859cc9 1164 /* ================ UICR ================ */
rgrover1 103:138bdc859cc9 1165 /* ================================================================================ */
rgrover1 103:138bdc859cc9 1166
rgrover1 103:138bdc859cc9 1167
rgrover1 103:138bdc859cc9 1168 /**
rgrover1 103:138bdc859cc9 1169 * @brief User Information Configuration. (UICR)
rgrover1 103:138bdc859cc9 1170 */
rgrover1 103:138bdc859cc9 1171
rgrover1 103:138bdc859cc9 1172 typedef struct { /*!< UICR Structure */
rgrover1 103:138bdc859cc9 1173 __IO uint32_t CLENR0; /*!< Length of code region 0. */
rgrover1 103:138bdc859cc9 1174 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
rgrover1 103:138bdc859cc9 1175 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
rgrover1 103:138bdc859cc9 1176 __I uint32_t RESERVED0;
rgrover1 103:138bdc859cc9 1177 __I uint32_t FWID; /*!< Firmware ID. */
rgrover1 103:138bdc859cc9 1178 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
rgrover1 103:138bdc859cc9 1179 } NRF_UICR_Type;
rgrover1 103:138bdc859cc9 1180
rgrover1 103:138bdc859cc9 1181
rgrover1 103:138bdc859cc9 1182 /* ================================================================================ */
rgrover1 103:138bdc859cc9 1183 /* ================ GPIO ================ */
rgrover1 103:138bdc859cc9 1184 /* ================================================================================ */
rgrover1 103:138bdc859cc9 1185
rgrover1 103:138bdc859cc9 1186
rgrover1 103:138bdc859cc9 1187 /**
rgrover1 103:138bdc859cc9 1188 * @brief General purpose input and output. (GPIO)
rgrover1 103:138bdc859cc9 1189 */
rgrover1 103:138bdc859cc9 1190
rgrover1 103:138bdc859cc9 1191 typedef struct { /*!< GPIO Structure */
rgrover1 103:138bdc859cc9 1192 __I uint32_t RESERVED0[321];
rgrover1 103:138bdc859cc9 1193 __IO uint32_t OUT; /*!< Write GPIO port. */
rgrover1 103:138bdc859cc9 1194 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
rgrover1 103:138bdc859cc9 1195 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
rgrover1 103:138bdc859cc9 1196 __I uint32_t IN; /*!< Read GPIO port. */
rgrover1 103:138bdc859cc9 1197 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
rgrover1 103:138bdc859cc9 1198 __IO uint32_t DIRSET; /*!< DIR set register. */
rgrover1 103:138bdc859cc9 1199 __IO uint32_t DIRCLR; /*!< DIR clear register. */
rgrover1 103:138bdc859cc9 1200 __I uint32_t RESERVED1[120];
rgrover1 103:138bdc859cc9 1201 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
rgrover1 103:138bdc859cc9 1202 } NRF_GPIO_Type;
rgrover1 103:138bdc859cc9 1203
rgrover1 103:138bdc859cc9 1204
rgrover1 103:138bdc859cc9 1205 /* -------------------- End of section using anonymous unions ------------------- */
rgrover1 103:138bdc859cc9 1206 #if defined(__CC_ARM)
rgrover1 103:138bdc859cc9 1207 #pragma pop
rgrover1 103:138bdc859cc9 1208 #elif defined(__ICCARM__)
rgrover1 103:138bdc859cc9 1209 /* leave anonymous unions enabled */
rgrover1 103:138bdc859cc9 1210 #elif defined(__GNUC__)
rgrover1 103:138bdc859cc9 1211 /* anonymous unions are enabled by default */
rgrover1 103:138bdc859cc9 1212 #elif defined(__TMS470__)
rgrover1 103:138bdc859cc9 1213 /* anonymous unions are enabled by default */
rgrover1 103:138bdc859cc9 1214 #elif defined(__TASKING__)
rgrover1 103:138bdc859cc9 1215 #pragma warning restore
rgrover1 103:138bdc859cc9 1216 #else
rgrover1 103:138bdc859cc9 1217 #warning Not supported compiler type
rgrover1 103:138bdc859cc9 1218 #endif
rgrover1 103:138bdc859cc9 1219
rgrover1 103:138bdc859cc9 1220
rgrover1 103:138bdc859cc9 1221
rgrover1 103:138bdc859cc9 1222
rgrover1 103:138bdc859cc9 1223 /* ================================================================================ */
rgrover1 103:138bdc859cc9 1224 /* ================ Peripheral memory map ================ */
rgrover1 103:138bdc859cc9 1225 /* ================================================================================ */
rgrover1 103:138bdc859cc9 1226
rgrover1 103:138bdc859cc9 1227 #define NRF_POWER_BASE 0x40000000UL
rgrover1 103:138bdc859cc9 1228 #define NRF_CLOCK_BASE 0x40000000UL
rgrover1 103:138bdc859cc9 1229 #define NRF_MPU_BASE 0x40000000UL
rgrover1 103:138bdc859cc9 1230 #define NRF_PU_BASE 0x40000000UL
rgrover1 103:138bdc859cc9 1231 #define NRF_AMLI_BASE 0x40000000UL
rgrover1 103:138bdc859cc9 1232 #define NRF_RADIO_BASE 0x40001000UL
rgrover1 103:138bdc859cc9 1233 #define NRF_UART0_BASE 0x40002000UL
rgrover1 103:138bdc859cc9 1234 #define NRF_SPI0_BASE 0x40003000UL
rgrover1 103:138bdc859cc9 1235 #define NRF_TWI0_BASE 0x40003000UL
rgrover1 103:138bdc859cc9 1236 #define NRF_SPI1_BASE 0x40004000UL
rgrover1 103:138bdc859cc9 1237 #define NRF_TWI1_BASE 0x40004000UL
rgrover1 103:138bdc859cc9 1238 #define NRF_SPIS1_BASE 0x40004000UL
rgrover1 103:138bdc859cc9 1239 #define NRF_SPIM1_BASE 0x40004000UL
rgrover1 103:138bdc859cc9 1240 #define NRF_GPIOTE_BASE 0x40006000UL
rgrover1 103:138bdc859cc9 1241 #define NRF_ADC_BASE 0x40007000UL
rgrover1 103:138bdc859cc9 1242 #define NRF_TIMER0_BASE 0x40008000UL
rgrover1 103:138bdc859cc9 1243 #define NRF_TIMER1_BASE 0x40009000UL
rgrover1 103:138bdc859cc9 1244 #define NRF_TIMER2_BASE 0x4000A000UL
rgrover1 103:138bdc859cc9 1245 #define NRF_RTC0_BASE 0x4000B000UL
rgrover1 103:138bdc859cc9 1246 #define NRF_TEMP_BASE 0x4000C000UL
rgrover1 103:138bdc859cc9 1247 #define NRF_RNG_BASE 0x4000D000UL
rgrover1 103:138bdc859cc9 1248 #define NRF_ECB_BASE 0x4000E000UL
rgrover1 103:138bdc859cc9 1249 #define NRF_AAR_BASE 0x4000F000UL
rgrover1 103:138bdc859cc9 1250 #define NRF_CCM_BASE 0x4000F000UL
rgrover1 103:138bdc859cc9 1251 #define NRF_WDT_BASE 0x40010000UL
rgrover1 103:138bdc859cc9 1252 #define NRF_RTC1_BASE 0x40011000UL
rgrover1 103:138bdc859cc9 1253 #define NRF_QDEC_BASE 0x40012000UL
rgrover1 103:138bdc859cc9 1254 #define NRF_LPCOMP_BASE 0x40013000UL
rgrover1 103:138bdc859cc9 1255 #define NRF_SWI_BASE 0x40014000UL
rgrover1 103:138bdc859cc9 1256 #define NRF_NVMC_BASE 0x4001E000UL
rgrover1 103:138bdc859cc9 1257 #define NRF_PPI_BASE 0x4001F000UL
rgrover1 103:138bdc859cc9 1258 #define NRF_FICR_BASE 0x10000000UL
rgrover1 103:138bdc859cc9 1259 #define NRF_UICR_BASE 0x10001000UL
rgrover1 103:138bdc859cc9 1260 #define NRF_GPIO_BASE 0x50000000UL
rgrover1 103:138bdc859cc9 1261
rgrover1 103:138bdc859cc9 1262
rgrover1 103:138bdc859cc9 1263 /* ================================================================================ */
rgrover1 103:138bdc859cc9 1264 /* ================ Peripheral declaration ================ */
rgrover1 103:138bdc859cc9 1265 /* ================================================================================ */
rgrover1 103:138bdc859cc9 1266
rgrover1 103:138bdc859cc9 1267 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
rgrover1 103:138bdc859cc9 1268 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
rgrover1 103:138bdc859cc9 1269 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
rgrover1 103:138bdc859cc9 1270 #define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
rgrover1 103:138bdc859cc9 1271 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
rgrover1 103:138bdc859cc9 1272 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
rgrover1 103:138bdc859cc9 1273 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
rgrover1 103:138bdc859cc9 1274 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
rgrover1 103:138bdc859cc9 1275 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
rgrover1 103:138bdc859cc9 1276 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
rgrover1 103:138bdc859cc9 1277 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
rgrover1 103:138bdc859cc9 1278 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
rgrover1 103:138bdc859cc9 1279 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
rgrover1 103:138bdc859cc9 1280 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
rgrover1 103:138bdc859cc9 1281 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
rgrover1 103:138bdc859cc9 1282 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
rgrover1 103:138bdc859cc9 1283 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
rgrover1 103:138bdc859cc9 1284 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
rgrover1 103:138bdc859cc9 1285 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
rgrover1 103:138bdc859cc9 1286 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
rgrover1 103:138bdc859cc9 1287 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
rgrover1 103:138bdc859cc9 1288 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
rgrover1 103:138bdc859cc9 1289 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
rgrover1 103:138bdc859cc9 1290 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
rgrover1 103:138bdc859cc9 1291 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
rgrover1 103:138bdc859cc9 1292 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
rgrover1 103:138bdc859cc9 1293 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
rgrover1 103:138bdc859cc9 1294 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
rgrover1 103:138bdc859cc9 1295 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
rgrover1 103:138bdc859cc9 1296 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
rgrover1 103:138bdc859cc9 1297 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
rgrover1 103:138bdc859cc9 1298 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
rgrover1 103:138bdc859cc9 1299 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
rgrover1 103:138bdc859cc9 1300 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
rgrover1 103:138bdc859cc9 1301
rgrover1 103:138bdc859cc9 1302
rgrover1 103:138bdc859cc9 1303 /** @} */ /* End of group Device_Peripheral_Registers */
rgrover1 103:138bdc859cc9 1304 /** @} */ /* End of group nRF51 */
rgrover1 103:138bdc859cc9 1305 /** @} */ /* End of group Nordic Semiconductor */
rgrover1 103:138bdc859cc9 1306
rgrover1 103:138bdc859cc9 1307 #ifdef __cplusplus
rgrover1 103:138bdc859cc9 1308 }
rgrover1 103:138bdc859cc9 1309 #endif
rgrover1 103:138bdc859cc9 1310
rgrover1 103:138bdc859cc9 1311
rgrover1 103:138bdc859cc9 1312 #endif /* nRF51_H */
rgrover1 103:138bdc859cc9 1313