Maxim Integrated
SIMO PMIC with 300mA Switching Charger
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MAX77659.cpp
00001 /******************************************************************************* 00002 * Copyright (C) 2022 Analog Devices, Inc., All rights Reserved. 00003 * 00004 * This software is protected by copyright laws of the United States and 00005 * of foreign countries. This material may also be protected by patent laws 00006 * and technology transfer regulations of the United States and of foreign 00007 * countries. This software is furnished under a license agreement and/or a 00008 * nondisclosure agreement and may only be used or reproduced in accordance 00009 * with the terms of those agreements. Dissemination of this information to 00010 * any party or parties not specified in the license agreement and/or 00011 * nondisclosure agreement is expressly prohibited. 00012 * 00013 * The above copyright notice and this permission notice shall be included 00014 * in all copies or substantial portions of the Software. 00015 * 00016 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 00017 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 00018 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 00019 * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY CLAIM, DAMAGES 00020 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 00021 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 00022 * OTHER DEALINGS IN THE SOFTWARE. 00023 * 00024 * Except as contained in this notice, the name of Maxim Integrated 00025 * Products, Inc. shall not be used except as stated in the Maxim Integrated 00026 * Products, Inc. Branding Policy. 00027 * 00028 * The mere transfer of this software does not imply any licenses 00029 * of trade secrets, proprietary technology, copyrights, patents, 00030 * trademarks, maskwork rights, or any other form of intellectual 00031 * property whatsoever. Analog Devices, Inc. retains all 00032 * ownership rights. 00033 ******************************************************************************* 00034 */ 00035 00036 #include <Thread.h> 00037 #include "MAX77659.h" 00038 #include <math.h> 00039 00040 #define POST_INTR_WORK_SIGNAL_ID 0x1 00041 #define TO_UINT8 0xFF 00042 #define TO_UINT16 0xFFFF 00043 00044 MAX77659::MAX77659(I2C *i2c, PinName IRQPin) 00045 { 00046 if (i2c == NULL) 00047 return; 00048 00049 i2c_handler = i2c; 00050 00051 interrupt_handler_list = new handler[INT_CHG_END] {}; 00052 00053 if (IRQPin != NC) { 00054 irq_disable_all(); 00055 post_intr_work_thread = new Thread(); 00056 post_intr_work_thread->start(Callback<void()>(this, &MAX77659::post_interrupt_work)); 00057 00058 this->irq_pin = new InterruptIn(IRQPin); 00059 this->irq_pin->fall(Callback<void()>(this, &MAX77659::interrupt_handler)); 00060 this->irq_pin->enable_irq(); 00061 } else { 00062 this->irq_pin = NULL; 00063 } 00064 } 00065 00066 MAX77659::~MAX77659() 00067 { 00068 if (post_intr_work_thread) 00069 delete post_intr_work_thread; 00070 00071 if (irq_pin) 00072 delete irq_pin; 00073 00074 if (interrupt_handler_list) 00075 delete [] interrupt_handler_list; 00076 } 00077 00078 int MAX77659::read_register(uint8_t reg, uint8_t *value) 00079 { 00080 int rtn_val; 00081 00082 if (value == NULL) 00083 return MAX77659_VALUE_NULL; 00084 00085 rtn_val = i2c_handler->write(MAX77659_I2C_ADDRESS, (const char *)®, 1, true); 00086 if (rtn_val != MAX77659_NO_ERROR) 00087 return MAX77659_WRITE_DATA_FAILED; 00088 00089 rtn_val = i2c_handler->read(MAX77659_I2C_ADDRESS, (char *) value, 1, false); 00090 if (rtn_val != MAX77659_NO_ERROR) 00091 return MAX77659_READ_DATA_FAILED; 00092 00093 return MAX77659_NO_ERROR; 00094 } 00095 00096 int MAX77659::write_register(uint8_t reg, const uint8_t *value) 00097 { 00098 int rtn_val; 00099 unsigned char local_data[2] = {0}; 00100 00101 if (value == NULL) 00102 return MAX77659_VALUE_NULL; 00103 00104 local_data[0] = reg; 00105 00106 memcpy(&local_data[1], value, 1); 00107 00108 rtn_val = i2c_handler->write(MAX77659_I2C_ADDRESS, (const char *)local_data, sizeof(local_data)); 00109 if (rtn_val != MAX77659_NO_ERROR) 00110 return MAX77659_WRITE_DATA_FAILED; 00111 00112 return MAX77659_NO_ERROR; 00113 } 00114 00115 #define SET_BIT_FIELD(address, reg_name, bit_field_name, value) \ 00116 int ret_val; \ 00117 ret_val = read_register(address, (uint8_t *)&(reg_name)); \ 00118 if (ret_val) { \ 00119 return ret_val; \ 00120 } \ 00121 bit_field_name = value; \ 00122 ret_val = write_register(address, (uint8_t *)&(reg_name)); \ 00123 if (ret_val) { \ 00124 return ret_val; \ 00125 } 00126 00127 int MAX77659::get_ercflag(reg_bit_ercflag_t bit_field, uint8_t *flag) 00128 { 00129 int ret; 00130 reg_ercflag_t reg_ercflag = {0}; 00131 00132 ret = read_register(ERCFLAG, (uint8_t *)&(reg_ercflag)); 00133 if (ret != MAX77659_NO_ERROR) return ret; 00134 00135 switch (bit_field) 00136 { 00137 case ERCFLAG_TOVLD: 00138 *flag = (uint8_t)reg_ercflag.bits.tovld; 00139 break; 00140 case ERCFLAG_SYSOVLO: 00141 *flag = (uint8_t)reg_ercflag.bits.sysovlo; 00142 break; 00143 case ERCFLAG_AVLUVLO: 00144 *flag = (uint8_t)reg_ercflag.bits.avluvlo; 00145 break; 00146 case ERCFLAG_MRST: 00147 *flag = (uint8_t)reg_ercflag.bits.mrst; 00148 break; 00149 case ERCFLAG_SFT_OFF_F: 00150 *flag = (uint8_t)reg_ercflag.bits.sft_off_f; 00151 break; 00152 case ERCFLAG_SFT_CRST_F: 00153 *flag = (uint8_t)reg_ercflag.bits.sft_crst_f; 00154 break; 00155 case ERCFLAG_WDT_OFF: 00156 *flag = (uint8_t)reg_ercflag.bits.wdt_off; 00157 break; 00158 case ERCFLAG_WDT_RST: 00159 *flag = (uint8_t)reg_ercflag.bits.wdt_rst; 00160 break; 00161 default: 00162 ret = MAX77659_INVALID_DATA; 00163 break; 00164 } 00165 00166 return ret; 00167 } 00168 00169 int MAX77659::get_stat_glbl(reg_bit_stat_glbl_t bit_field, uint8_t *status) 00170 { 00171 int ret; 00172 reg_stat_glbl_t reg_stat_glbl = {0}; 00173 00174 ret = read_register(STAT_GLBL, (uint8_t *)&(reg_stat_glbl)); 00175 if (ret != MAX77659_NO_ERROR) return ret; 00176 00177 switch (bit_field) 00178 { 00179 case STAT_GLBL_STAT_IRQ: 00180 *status = (uint8_t)reg_stat_glbl.bits.stat_irq; 00181 break; 00182 case STAT_GLBL_STAT_EN: 00183 *status = (uint8_t)reg_stat_glbl.bits.stat_en; 00184 break; 00185 case STAT_GLBL_TJAL1_S: 00186 *status = (uint8_t)reg_stat_glbl.bits.tjal1_s; 00187 break; 00188 case STAT_GLBL_TJAL2_S: 00189 *status = (uint8_t)reg_stat_glbl.bits.tjal2_s; 00190 break; 00191 case STAT_GLBL_RSVD: 00192 *status = (uint8_t)reg_stat_glbl.bits.rsvd; 00193 break; 00194 case STAT_GLBL_DOD_S: 00195 *status = (uint8_t)reg_stat_glbl.bits.dod_s; 00196 break; 00197 case STAT_GLBL_BOK: 00198 *status = (uint8_t)reg_stat_glbl.bits.bok; 00199 break; 00200 case STAT_GLBL_DIDM: 00201 *status = (uint8_t)reg_stat_glbl.bits.didm; 00202 break; 00203 default: 00204 ret = MAX77659_INVALID_DATA; 00205 break; 00206 } 00207 00208 return ret; 00209 } 00210 00211 int MAX77659::set_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t maskBit) 00212 { 00213 int ret; 00214 uint8_t reg_addr; 00215 reg_int_m_chg_t reg_int_m_chg = {0}; 00216 reg_intm_glbl0_t reg_intm_glbl0 = {0}; 00217 reg_intm_glbl1_t reg_intm_glbl1 = {0}; 00218 00219 //INT_M_CHG (0x07), INTM_GLBL1 (0x08) and INTM_GLBL0 (0x09) 00220 reg_addr = (uint8_t)floor((static_cast<uint8_t>(bit_field)) / 8) + 0x07; 00221 00222 if (reg_addr == INT_M_CHG) 00223 ret = read_register(INT_M_CHG, (uint8_t *)&(reg_int_m_chg)); 00224 else if (reg_addr == INTM_GLBL0) 00225 ret = read_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0)); 00226 else if (reg_addr == INTM_GLBL1) 00227 ret = read_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1)); 00228 else 00229 return MAX77659_INVALID_DATA; 00230 00231 if (ret != MAX77659_NO_ERROR) return ret; 00232 00233 switch (bit_field) 00234 { 00235 case INT_M_CHG_THM_M: 00236 reg_int_m_chg.bits.thm_m = maskBit; 00237 break; 00238 case INT_M_CHG_CHG_M: 00239 reg_int_m_chg.bits.chg_m = maskBit; 00240 break; 00241 case INT_M_CHG_CHGIN_M: 00242 reg_int_m_chg.bits.chgin_m = maskBit; 00243 break; 00244 case INT_M_CHG_TJ_REG_M: 00245 reg_int_m_chg.bits.tj_reg_m = maskBit; 00246 break; 00247 case INT_M_CHG_SYS_CTRL_M: 00248 reg_int_m_chg.bits.sys_ctrl_m = maskBit; 00249 break; 00250 case INTM_GLBL0_GPI0_FM: 00251 reg_intm_glbl0.bits.gpi0_fm = maskBit; 00252 break; 00253 case INTM_GLBL1_GPI1_FM: 00254 reg_intm_glbl1.bits.gpi1_fm = maskBit; 00255 break; 00256 case INTM_GLBL1_GPI1_RM: 00257 reg_intm_glbl1.bits.gpi1_rm = maskBit; 00258 break; 00259 case INTM_GLBL1_SBB_TO_M: 00260 reg_intm_glbl1.bits.sbb_to_m = maskBit; 00261 break; 00262 case INTM_GLBL1_LDO_M: 00263 reg_intm_glbl1.bits.ldo_m = maskBit; 00264 break; 00265 case INTM_GLBL0_GPI0_RM: 00266 reg_intm_glbl0.bits.gpi0_rm = maskBit; 00267 break; 00268 case INTM_GLBL0_nEN_FM: 00269 reg_intm_glbl0.bits.nen_fm = maskBit; 00270 break; 00271 case INTM_GLBL0_nEN_RM: 00272 reg_intm_glbl0.bits.nen_rm = maskBit; 00273 break; 00274 case INTM_GLBL0_TJAL1_RM: 00275 reg_intm_glbl0.bits.tjal1_rm = maskBit; 00276 break; 00277 case INTM_GLBL0_TJAL2_RM: 00278 reg_intm_glbl0.bits.tjal2_rm = maskBit; 00279 break; 00280 case INTM_GLBL0_DOD_RM: 00281 reg_intm_glbl0.bits.dod_rm = maskBit; 00282 break; 00283 default: 00284 return MAX77659_INVALID_DATA; 00285 break; 00286 } 00287 00288 if (reg_addr == INT_M_CHG) 00289 return write_register(INT_M_CHG, (uint8_t *)&(reg_int_m_chg)); 00290 else if (reg_addr == INTM_GLBL0) 00291 return write_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0)); 00292 else if (reg_addr == INTM_GLBL1) 00293 return write_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1)); 00294 else 00295 return MAX77659_INVALID_DATA; 00296 } 00297 00298 int MAX77659::get_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t *maskBit) 00299 { 00300 int ret; 00301 uint8_t reg_addr; 00302 reg_int_m_chg_t reg_int_m_chg = {0}; 00303 reg_intm_glbl0_t reg_intm_glbl0 = {0}; 00304 reg_intm_glbl1_t reg_intm_glbl1 = {0}; 00305 00306 //INT_M_CHG (0x07), INTM_GLBL1 (0x08) and INTM_GLBL0 (0x09) 00307 reg_addr = (uint8_t)floor((static_cast<uint8_t>(bit_field)) / 8) + 0x07; 00308 00309 if (reg_addr == INT_M_CHG) 00310 ret = read_register(INT_M_CHG, (uint8_t *)&(reg_int_m_chg)); 00311 else if (reg_addr == INTM_GLBL0) 00312 ret = read_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0)); 00313 else if (reg_addr == INTM_GLBL1) 00314 ret = read_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1)); 00315 else 00316 return MAX77659_INVALID_DATA; 00317 00318 if (ret != MAX77659_NO_ERROR) return ret; 00319 00320 switch (bit_field) 00321 { 00322 case INT_M_CHG_THM_M: 00323 *maskBit = (uint8_t)reg_int_m_chg.bits.thm_m; 00324 break; 00325 case INT_M_CHG_CHG_M: 00326 *maskBit = (uint8_t)reg_int_m_chg.bits.chg_m; 00327 break; 00328 case INT_M_CHG_CHGIN_M: 00329 *maskBit = (uint8_t)reg_int_m_chg.bits.chgin_m; 00330 break; 00331 case INT_M_CHG_TJ_REG_M: 00332 *maskBit = (uint8_t)reg_int_m_chg.bits.tj_reg_m; 00333 break; 00334 case INT_M_CHG_SYS_CTRL_M: 00335 *maskBit = (uint8_t)reg_int_m_chg.bits.sys_ctrl_m; 00336 break; 00337 case INTM_GLBL1_GPI1_FM: 00338 *maskBit = (uint8_t)reg_intm_glbl1.bits.gpi1_fm; 00339 break; 00340 case INTM_GLBL1_GPI1_RM: 00341 *maskBit = (uint8_t)reg_intm_glbl1.bits.gpi1_rm; 00342 break; 00343 case INTM_GLBL1_SBB_TO_M: 00344 *maskBit = (uint8_t)reg_intm_glbl1.bits.sbb_to_m; 00345 break; 00346 case INTM_GLBL1_LDO_M: 00347 *maskBit = (uint8_t)reg_intm_glbl1.bits.ldo_m; 00348 break; 00349 case INTM_GLBL0_GPI0_FM: 00350 *maskBit = (uint8_t)reg_intm_glbl0.bits.gpi0_fm; 00351 break; 00352 case INTM_GLBL0_GPI0_RM: 00353 *maskBit = (uint8_t)reg_intm_glbl0.bits.gpi0_rm; 00354 break; 00355 case INTM_GLBL0_nEN_FM: 00356 *maskBit = (uint8_t)reg_intm_glbl0.bits.nen_fm; 00357 break; 00358 case INTM_GLBL0_nEN_RM: 00359 *maskBit = (uint8_t)reg_intm_glbl0.bits.nen_rm; 00360 break; 00361 case INTM_GLBL0_TJAL1_RM: 00362 *maskBit = (uint8_t)reg_intm_glbl0.bits.tjal1_rm; 00363 break; 00364 case INTM_GLBL0_TJAL2_RM: 00365 *maskBit = (uint8_t)reg_intm_glbl0.bits.tjal2_rm; 00366 break; 00367 case INTM_GLBL0_DOD_RM: 00368 *maskBit = (uint8_t)reg_intm_glbl0.bits.dod_rm; 00369 break; 00370 default: 00371 return MAX77659_INVALID_DATA; 00372 break; 00373 } 00374 00375 return MAX77659_NO_ERROR; 00376 } 00377 00378 int MAX77659::set_cnfg_glbl(reg_bit_cnfg_glbl_t bit_field, uint8_t config) 00379 { 00380 int ret; 00381 reg_cnfg_glbl_t reg_cnfg_glbl = {0}; 00382 00383 ret = read_register(CNFG_GLBL, (uint8_t *)&(reg_cnfg_glbl)); 00384 if (ret != MAX77659_NO_ERROR) return ret; 00385 00386 switch (bit_field) 00387 { 00388 case CNFG_GLBL_SFT_CTRL: 00389 reg_cnfg_glbl.bits.sft_ctrl = config; 00390 break; 00391 case CNFG_GLBL_DBEN_nEN: 00392 reg_cnfg_glbl.bits.dben_nen = config; 00393 break; 00394 case CNFG_GLBL_nEN_MODE: 00395 reg_cnfg_glbl.bits.nen_mode = config; 00396 break; 00397 case CNFG_GLBL_SBIA_EN: 00398 reg_cnfg_glbl.bits.sbia_en = config; 00399 break; 00400 case CNFG_GLBL_SBIA_LPM: 00401 reg_cnfg_glbl.bits.sbia_lpm = config; 00402 break; 00403 case CNFG_GLBL_T_MRST: 00404 reg_cnfg_glbl.bits.t_mrst = config; 00405 break; 00406 case CNFG_GLBL_PU_DIS: 00407 reg_cnfg_glbl.bits.pu_dis = config; 00408 break; 00409 default: 00410 return MAX77659_INVALID_DATA; 00411 break; 00412 } 00413 00414 return write_register(CNFG_GLBL, (uint8_t *)&(reg_cnfg_glbl)); 00415 } 00416 00417 int MAX77659::get_cnfg_glbl(reg_bit_cnfg_glbl_t bit_field, uint8_t *config) 00418 { 00419 int ret; 00420 reg_cnfg_glbl_t reg_cnfg_glbl = {0}; 00421 00422 ret = read_register(CNFG_GLBL, (uint8_t *)&(reg_cnfg_glbl)); 00423 if (ret != MAX77659_NO_ERROR) return ret; 00424 00425 switch (bit_field) 00426 { 00427 case CNFG_GLBL_SFT_CTRL: 00428 *config = (uint8_t)reg_cnfg_glbl.bits.sft_ctrl; 00429 break; 00430 case CNFG_GLBL_DBEN_nEN: 00431 *config = (uint8_t)reg_cnfg_glbl.bits.dben_nen; 00432 break; 00433 case CNFG_GLBL_nEN_MODE: 00434 *config = (uint8_t)reg_cnfg_glbl.bits.nen_mode; 00435 break; 00436 case CNFG_GLBL_SBIA_EN: 00437 *config = (uint8_t)reg_cnfg_glbl.bits.sbia_en; 00438 break; 00439 case CNFG_GLBL_SBIA_LPM: 00440 *config = (uint8_t)reg_cnfg_glbl.bits.sbia_lpm; 00441 break; 00442 case CNFG_GLBL_T_MRST: 00443 *config = (uint8_t)reg_cnfg_glbl.bits.t_mrst; 00444 break; 00445 case CNFG_GLBL_PU_DIS: 00446 *config = (uint8_t)reg_cnfg_glbl.bits.pu_dis; 00447 break; 00448 default: 00449 ret = MAX77659_INVALID_DATA; 00450 break; 00451 } 00452 00453 return ret; 00454 } 00455 00456 int MAX77659::set_cnfg_gpio(reg_bit_cnfg_gpio_t bit_field, uint8_t channel, uint8_t config) 00457 { 00458 int ret; 00459 reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0}; 00460 reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0}; 00461 00462 if (channel == 0) 00463 { 00464 ret = read_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0)); 00465 if (ret != MAX77659_NO_ERROR) return ret; 00466 00467 switch (bit_field) 00468 { 00469 case CNFG_GPIO_DIR: 00470 reg_cnfg_gpio0.bits.gpo_dir = config; 00471 break; 00472 case CNFG_GPIO_DI: 00473 reg_cnfg_gpio0.bits.gpo_di = config; 00474 break; 00475 case CNFG_GPIO_DRV: 00476 reg_cnfg_gpio0.bits.gpo_drv = config; 00477 break; 00478 case CNFG_GPIO_DO: 00479 reg_cnfg_gpio0.bits.gpo_do = config; 00480 break; 00481 case CNFG_GPIO_DBEN_GPI: 00482 reg_cnfg_gpio0.bits.dben_gpi = config; 00483 break; 00484 case CNFG_GPIO_ALT_GPIO: 00485 reg_cnfg_gpio0.bits.alt_gpio = config; 00486 break; 00487 default: 00488 return MAX77659_INVALID_DATA; 00489 break; 00490 } 00491 00492 return write_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0)); 00493 } 00494 else if (channel == 1) 00495 { 00496 ret = read_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1)); 00497 if (ret != MAX77659_NO_ERROR) return ret; 00498 00499 switch (bit_field) 00500 { 00501 case CNFG_GPIO_DIR: 00502 reg_cnfg_gpio1.bits.gpo_dir = config; 00503 break; 00504 case CNFG_GPIO_DI: 00505 reg_cnfg_gpio1.bits.gpo_di = config; 00506 break; 00507 case CNFG_GPIO_DRV: 00508 reg_cnfg_gpio1.bits.gpo_drv = config; 00509 break; 00510 case CNFG_GPIO_DO: 00511 reg_cnfg_gpio1.bits.gpo_do = config; 00512 break; 00513 case CNFG_GPIO_DBEN_GPI: 00514 reg_cnfg_gpio1.bits.dben_gpi = config; 00515 break; 00516 case CNFG_GPIO_ALT_GPIO: 00517 reg_cnfg_gpio1.bits.alt_gpio = config; 00518 break; 00519 default: 00520 return MAX77659_INVALID_DATA; 00521 break; 00522 } 00523 00524 return write_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1)); 00525 } 00526 else { 00527 return MAX77659_INVALID_DATA; 00528 } 00529 } 00530 00531 int MAX77659::get_cnfg_gpio(reg_bit_cnfg_gpio_t bit_field, uint8_t channel, uint8_t *config) 00532 { 00533 int ret; 00534 reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0}; 00535 reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0}; 00536 00537 if (channel == 0) 00538 { 00539 ret = read_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0)); 00540 if (ret != MAX77659_NO_ERROR) return ret; 00541 00542 switch (bit_field) 00543 { 00544 case CNFG_GPIO_DIR: 00545 *config = (uint8_t)reg_cnfg_gpio0.bits.gpo_dir; 00546 break; 00547 case CNFG_GPIO_DI: 00548 *config = (uint8_t)reg_cnfg_gpio0.bits.gpo_di; 00549 break; 00550 case CNFG_GPIO_DRV: 00551 *config = (uint8_t)reg_cnfg_gpio0.bits.gpo_drv; 00552 break; 00553 case CNFG_GPIO_DO: 00554 *config = (uint8_t)reg_cnfg_gpio0.bits.gpo_do; 00555 break; 00556 case CNFG_GPIO_DBEN_GPI: 00557 *config = (uint8_t)reg_cnfg_gpio0.bits.dben_gpi; 00558 break; 00559 case CNFG_GPIO_ALT_GPIO: 00560 *config = (uint8_t)reg_cnfg_gpio0.bits.alt_gpio; 00561 break; 00562 default: 00563 return MAX77659_INVALID_DATA; 00564 break; 00565 } 00566 } 00567 else if (channel == 1) 00568 { 00569 ret = read_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1)); 00570 if (ret != MAX77659_NO_ERROR) return ret; 00571 00572 switch (bit_field) 00573 { 00574 case CNFG_GPIO_DIR: 00575 *config = (uint8_t)reg_cnfg_gpio1.bits.gpo_dir; 00576 break; 00577 case CNFG_GPIO_DI: 00578 *config = (uint8_t)reg_cnfg_gpio1.bits.gpo_di; 00579 break; 00580 case CNFG_GPIO_DRV: 00581 *config = (uint8_t)reg_cnfg_gpio1.bits.gpo_drv; 00582 break; 00583 case CNFG_GPIO_DO: 00584 *config = (uint8_t)reg_cnfg_gpio1.bits.gpo_do; 00585 break; 00586 case CNFG_GPIO_DBEN_GPI: 00587 *config = (uint8_t)reg_cnfg_gpio1.bits.dben_gpi; 00588 break; 00589 case CNFG_GPIO_ALT_GPIO: 00590 *config = (uint8_t)reg_cnfg_gpio1.bits.alt_gpio; 00591 break; 00592 default: 00593 return MAX77659_INVALID_DATA; 00594 break; 00595 } 00596 } 00597 else { 00598 return MAX77659_INVALID_DATA; 00599 } 00600 00601 return ret; 00602 } 00603 00604 int MAX77659::get_cid(void) { 00605 char rbuf[1] = {0}; 00606 int ret; 00607 00608 ret = read_register(CID, (uint8_t *)&(rbuf)); 00609 if (ret != MAX77659_NO_ERROR) return ret; 00610 00611 return *rbuf; 00612 } 00613 00614 int MAX77659::set_cnfg_wdt(reg_bit_cnfg_wdt_t bit_field, uint8_t config) 00615 { 00616 int ret; 00617 reg_cnfg_wdt_t reg_cnfg_wdt = {0}; 00618 00619 ret = read_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt)); 00620 if (ret != MAX77659_NO_ERROR) return ret; 00621 00622 switch (bit_field) 00623 { 00624 case CNFG_WDT_WDT_LOCK: 00625 reg_cnfg_wdt.bits.wdt_lock = config; 00626 break; 00627 case CNFG_WDT_WDT_EN: 00628 reg_cnfg_wdt.bits.wdt_en = config; 00629 break; 00630 case CNFG_WDT_WDT_CLR: 00631 reg_cnfg_wdt.bits.wdt_clr = config; 00632 break; 00633 case CNFG_WDT_WDT_MODE: 00634 reg_cnfg_wdt.bits.wdt_mode = config; 00635 break; 00636 case CNFG_WDT_WDT_PER: 00637 reg_cnfg_wdt.bits.wdt_per = config; 00638 break; 00639 default: 00640 return MAX77659_INVALID_DATA; 00641 break; 00642 } 00643 00644 return write_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt)); 00645 } 00646 00647 int MAX77659::get_cnfg_wdt(reg_bit_cnfg_wdt_t bit_field, uint8_t *config) 00648 { 00649 int ret; 00650 reg_cnfg_wdt_t reg_cnfg_wdt = {0}; 00651 00652 ret = read_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt)); 00653 if (ret != MAX77659_NO_ERROR) return ret; 00654 00655 switch (bit_field) 00656 { 00657 case CNFG_WDT_WDT_LOCK: 00658 *config = (uint8_t)reg_cnfg_wdt.bits.wdt_lock; 00659 break; 00660 case CNFG_WDT_WDT_EN: 00661 *config = (uint8_t)reg_cnfg_wdt.bits.wdt_en; 00662 break; 00663 case CNFG_WDT_WDT_CLR: 00664 *config = (uint8_t)reg_cnfg_wdt.bits.wdt_clr; 00665 break; 00666 case CNFG_WDT_WDT_MODE: 00667 *config = (uint8_t)reg_cnfg_wdt.bits.wdt_mode; 00668 break; 00669 case CNFG_WDT_WDT_PER: 00670 *config = (uint8_t)reg_cnfg_wdt.bits.wdt_per; 00671 break; 00672 default: 00673 return MAX77659_INVALID_DATA; 00674 break; 00675 } 00676 00677 return MAX77659_NO_ERROR; 00678 } 00679 00680 int MAX77659::get_stat_chg_a(reg_bit_stat_chg_a_t bit_field, uint8_t *status) 00681 { 00682 int ret; 00683 reg_stat_chg_a_t reg_stat_chg_a = {0}; 00684 00685 ret = read_register(STAT_CHG_A, (uint8_t *)&(reg_stat_chg_a)); 00686 if (ret != MAX77659_NO_ERROR) return ret; 00687 00688 switch (bit_field) 00689 { 00690 case STAT_CHG_A_THM_DTLS: 00691 *status = (uint8_t)reg_stat_chg_a.bits.thm_dtls; 00692 break; 00693 case STAT_CHG_A_TJ_REG_STAT: 00694 *status = (uint8_t)reg_stat_chg_a.bits.tj_reg_stat; 00695 break; 00696 case STAT_CHG_A_VSYS_MIN_STAT: 00697 *status = (uint8_t)reg_stat_chg_a.bits.vsys_min_stat; 00698 break; 00699 default: 00700 return MAX77659_INVALID_DATA; 00701 break; 00702 } 00703 00704 return MAX77659_NO_ERROR; 00705 } 00706 00707 int MAX77659::get_thm_dtls(decode_thm_dtls_t *thm_dtls) 00708 { 00709 int ret; 00710 reg_stat_chg_a_t reg_stat_chg_a = {0}; 00711 00712 ret = read_register(STAT_CHG_A, (uint8_t *)&(reg_stat_chg_a)); 00713 if (ret != MAX77659_NO_ERROR) return ret; 00714 00715 *thm_dtls = (decode_thm_dtls_t)reg_stat_chg_a.bits.thm_dtls; 00716 00717 return MAX77659_NO_ERROR; 00718 } 00719 00720 int MAX77659::get_stat_chg_b(reg_bit_stat_chg_b_t bit_field, uint8_t *status) 00721 { 00722 int ret; 00723 reg_stat_chg_b_t reg_stat_chg_b = {0}; 00724 00725 ret = read_register(STAT_CHG_B, (uint8_t *)&(reg_stat_chg_b)); 00726 if (ret != MAX77659_NO_ERROR) return ret; 00727 00728 switch (bit_field) 00729 { 00730 case STAT_CHG_B_TIME_SUS: 00731 *status = (uint8_t)reg_stat_chg_b.bits.time_sus; 00732 break; 00733 case STAT_CHG_B_CHG: 00734 *status = (uint8_t)reg_stat_chg_b.bits.chg; 00735 break; 00736 case STAT_CHG_B_CHGIN_DTLS: 00737 *status = (uint8_t)reg_stat_chg_b.bits.chgin_dtls; 00738 break; 00739 case STAT_CHG_B_CHG_DTLS: 00740 *status = (uint8_t)reg_stat_chg_b.bits.chg_dtls; 00741 break; 00742 default: 00743 return MAX77659_INVALID_DATA; 00744 break; 00745 } 00746 00747 return MAX77659_NO_ERROR; 00748 } 00749 00750 int MAX77659::get_chg_dtls(decode_chg_dtls_t *chg_dtls) 00751 { 00752 int ret; 00753 reg_stat_chg_b_t reg_stat_chg_b = {0}; 00754 00755 ret = read_register(STAT_CHG_B, (uint8_t *)&(reg_stat_chg_b)); 00756 if (ret != MAX77659_NO_ERROR) return ret; 00757 00758 *chg_dtls = (decode_chg_dtls_t)reg_stat_chg_b.bits.chg_dtls; 00759 00760 return MAX77659_NO_ERROR; 00761 } 00762 00763 int MAX77659::set_thm_hot(decode_thm_hot_t thm_hot) 00764 { 00765 reg_cnfg_chg_a_t reg_cnfg_chg_a = {0}; 00766 00767 SET_BIT_FIELD(CNFG_CHG_A, reg_cnfg_chg_a, reg_cnfg_chg_a.bits.thm_hot, thm_hot); 00768 00769 return MAX77659_NO_ERROR; 00770 } 00771 00772 int MAX77659::get_thm_hot(decode_thm_hot_t *thm_hot) 00773 { 00774 int ret; 00775 reg_cnfg_chg_a_t reg_cnfg_chg_a = {0}; 00776 00777 ret = read_register(CNFG_CHG_A, (uint8_t *)&(reg_cnfg_chg_a)); 00778 if (ret != MAX77659_NO_ERROR) return ret; 00779 00780 *thm_hot = (decode_thm_hot_t)reg_cnfg_chg_a.bits.thm_hot; 00781 00782 return MAX77659_NO_ERROR; 00783 } 00784 00785 int MAX77659::set_thm_warm(decode_thm_warm_t thm_warm) 00786 { 00787 reg_cnfg_chg_a_t reg_cnfg_chg_a = {0}; 00788 00789 SET_BIT_FIELD(CNFG_CHG_A, reg_cnfg_chg_a, reg_cnfg_chg_a.bits.thm_warm, thm_warm); 00790 00791 return MAX77659_NO_ERROR; 00792 } 00793 00794 int MAX77659::get_thm_warm(decode_thm_warm_t *thm_warm) 00795 { 00796 int ret; 00797 reg_cnfg_chg_a_t reg_cnfg_chg_a = {0}; 00798 00799 ret = read_register(CNFG_CHG_A, (uint8_t *)&(reg_cnfg_chg_a)); 00800 if (ret != MAX77659_NO_ERROR) return ret; 00801 00802 *thm_warm = (decode_thm_warm_t)reg_cnfg_chg_a.bits.thm_warm; 00803 00804 return MAX77659_NO_ERROR; 00805 } 00806 00807 int MAX77659::set_thm_cool(decode_thm_cool_t thm_cool) 00808 { 00809 reg_cnfg_chg_a_t reg_cnfg_chg_a = {0}; 00810 00811 SET_BIT_FIELD(CNFG_CHG_A, reg_cnfg_chg_a, reg_cnfg_chg_a.bits.thm_cool, thm_cool); 00812 00813 return MAX77659_NO_ERROR; 00814 } 00815 00816 int MAX77659::get_thm_cool(decode_thm_cool_t *thm_cool) 00817 { 00818 int ret; 00819 reg_cnfg_chg_a_t reg_cnfg_chg_a = {0}; 00820 00821 ret = read_register(CNFG_CHG_A, (uint8_t *)&(reg_cnfg_chg_a)); 00822 if (ret != MAX77659_NO_ERROR) return ret; 00823 00824 *thm_cool = (decode_thm_cool_t)reg_cnfg_chg_a.bits.thm_cool; 00825 00826 return MAX77659_NO_ERROR; 00827 } 00828 00829 int MAX77659::set_thm_cold(decode_thm_cold_t thm_cold) 00830 { 00831 reg_cnfg_chg_a_t reg_cnfg_chg_a = {0}; 00832 00833 SET_BIT_FIELD(CNFG_CHG_A, reg_cnfg_chg_a, reg_cnfg_chg_a.bits.thm_cold, thm_cold); 00834 00835 return MAX77659_NO_ERROR; 00836 } 00837 00838 int MAX77659:: get_thm_cold(decode_thm_cold_t *thm_cold) 00839 { 00840 int ret; 00841 reg_cnfg_chg_a_t reg_cnfg_chg_a = {0}; 00842 00843 ret = read_register(CNFG_CHG_A, (uint8_t *)&(reg_cnfg_chg_a)); 00844 if (ret != MAX77659_NO_ERROR) return ret; 00845 00846 *thm_cold = (decode_thm_cold_t)reg_cnfg_chg_a.bits.thm_cold; 00847 00848 return MAX77659_NO_ERROR; 00849 } 00850 00851 int MAX77659::set_cnfg_chg_b(reg_bit_cnfg_chg_b_t bit_field, uint8_t config) 00852 { 00853 int ret; 00854 reg_cnfg_chg_b_t reg_cnfg_chg_b = {0}; 00855 00856 ret = read_register(CNFG_CHG_B, (uint8_t *)&(reg_cnfg_chg_b)); 00857 if (ret != MAX77659_NO_ERROR) return ret; 00858 00859 switch (bit_field) 00860 { 00861 case CNFG_CHG_B_CHG_EN: 00862 reg_cnfg_chg_b.bits.chg_en = config; 00863 break; 00864 case CNFG_CHG_B_I_PQ: 00865 reg_cnfg_chg_b.bits.i_pq = config; 00866 break; 00867 case CNFG_CHG_B_RSVD: 00868 reg_cnfg_chg_b.bits.rsvd = config; 00869 break; 00870 default: 00871 return MAX77659_INVALID_DATA; 00872 break; 00873 } 00874 00875 return write_register(CNFG_CHG_B, (uint8_t *)&(reg_cnfg_chg_b)); 00876 } 00877 00878 int MAX77659::get_cnfg_chg_b(reg_bit_cnfg_chg_b_t bit_field, uint8_t *config) 00879 { 00880 int ret; 00881 reg_cnfg_chg_b_t reg_cnfg_chg_b = {0}; 00882 00883 ret = read_register(CNFG_CHG_B, (uint8_t *)&(reg_cnfg_chg_b)); 00884 if (ret != MAX77659_NO_ERROR) return ret; 00885 00886 switch (bit_field) 00887 { 00888 case CNFG_CHG_B_CHG_EN: 00889 *config = (uint8_t)reg_cnfg_chg_b.bits.chg_en; 00890 break; 00891 case CNFG_CHG_B_I_PQ: 00892 *config = (uint8_t)reg_cnfg_chg_b.bits.i_pq; 00893 break; 00894 case CNFG_CHG_B_RSVD: 00895 *config = (uint8_t)reg_cnfg_chg_b.bits.rsvd; 00896 break; 00897 default: 00898 return MAX77659_INVALID_DATA; 00899 break; 00900 } 00901 00902 return MAX77659_NO_ERROR; 00903 } 00904 00905 int MAX77659::set_chg_pq(float voltV) 00906 { 00907 uint8_t value; 00908 reg_cnfg_chg_c_t reg_cnfg_chg_c = {0}; 00909 float voltmV = voltV * 1000; 00910 00911 if (voltmV < 2300) voltmV = 2300; 00912 else if (voltmV > 3000) voltmV = 3000; 00913 00914 value = (voltmV - 2300) / 100; 00915 00916 SET_BIT_FIELD(CNFG_CHG_C, reg_cnfg_chg_c, reg_cnfg_chg_c.bits.chg_pq, value); 00917 return MAX77659_NO_ERROR; 00918 } 00919 00920 int MAX77659::get_chg_pq(float *voltV) 00921 { 00922 int ret; 00923 uint8_t bit_value; 00924 reg_cnfg_chg_c_t reg_cnfg_chg_c = {0}; 00925 00926 ret = read_register(CNFG_CHG_C, (uint8_t *)&(reg_cnfg_chg_c)); 00927 if (ret != MAX77659_NO_ERROR) return ret; 00928 00929 bit_value = (uint8_t)reg_cnfg_chg_c.bits.chg_pq; 00930 *voltV = (bit_value * 0.1f) + 2.3f; 00931 return MAX77659_NO_ERROR; 00932 } 00933 00934 int MAX77659::set_i_term(float percent) 00935 { 00936 uint8_t value; 00937 reg_cnfg_chg_c_t reg_cnfg_chg_c = {0}; 00938 00939 if (percent < 7.5f) value = 0; 00940 else if ((percent >= 7.5f) && (percent < 10)) value = 1; 00941 else if ((percent >= 10) && (percent < 15)) value = 2; 00942 else if (percent >= 15) value = 3; 00943 00944 SET_BIT_FIELD(CNFG_CHG_C, reg_cnfg_chg_c, reg_cnfg_chg_c.bits.i_term, value); 00945 return MAX77659_NO_ERROR; 00946 } 00947 00948 int MAX77659::get_i_term(float *percent) 00949 { 00950 int ret; 00951 uint8_t bit_value; 00952 reg_cnfg_chg_c_t reg_cnfg_chg_c = {0}; 00953 00954 ret = read_register(CNFG_CHG_C, (uint8_t *)&(reg_cnfg_chg_c)); 00955 if (ret != MAX77659_NO_ERROR) return ret; 00956 00957 bit_value = (uint8_t)reg_cnfg_chg_c.bits.i_term; 00958 00959 if (bit_value == 0) *percent = 5.0f; 00960 else if (bit_value == 1) *percent = 7.5f; 00961 else if (bit_value == 2) *percent = 10.0f; 00962 else if (bit_value == 3) *percent = 15.0f; 00963 else return MAX77659_INVALID_DATA; 00964 00965 return MAX77659_NO_ERROR; 00966 } 00967 00968 int MAX77659::set_t_topoff(uint8_t minute) 00969 { 00970 uint8_t value; 00971 reg_cnfg_chg_c_t reg_cnfg_chg_c = {0}; 00972 00973 if (minute > 35) minute = 35; 00974 00975 value = (uint8_t)(minute / 5); 00976 00977 SET_BIT_FIELD(CNFG_CHG_C, reg_cnfg_chg_c, reg_cnfg_chg_c.bits.t_topoff, value); 00978 return MAX77659_NO_ERROR; 00979 } 00980 00981 int MAX77659::get_t_topoff(uint8_t *minute) 00982 { 00983 int ret; 00984 uint8_t bit_value; 00985 reg_cnfg_chg_c_t reg_cnfg_chg_c = {0}; 00986 00987 ret = read_register(CNFG_CHG_C, (uint8_t *)&(reg_cnfg_chg_c)); 00988 if (ret != MAX77659_NO_ERROR) return ret; 00989 00990 bit_value = (uint8_t)reg_cnfg_chg_c.bits.t_topoff; 00991 *minute = (bit_value * 5); 00992 return MAX77659_NO_ERROR; 00993 } 00994 00995 int MAX77659::set_tj_reg(uint8_t tempDegC) 00996 { 00997 uint8_t value; 00998 reg_cnfg_chg_d_t reg_cnfg_chg_d = {0}; 00999 01000 if (tempDegC < 60) tempDegC = 60; 01001 else if (tempDegC > 100) tempDegC = 100; 01002 01003 value = (tempDegC - 60) / 10; 01004 01005 SET_BIT_FIELD(CNFG_CHG_D, reg_cnfg_chg_d, reg_cnfg_chg_d.bits.tj_reg, value); 01006 return MAX77659_NO_ERROR; 01007 } 01008 01009 int MAX77659::get_tj_reg(uint8_t *tempDegC) 01010 { 01011 int ret; 01012 uint8_t bit_value; 01013 reg_cnfg_chg_d_t reg_cnfg_chg_d = {0}; 01014 01015 ret = read_register(CNFG_CHG_D, (uint8_t *)&(reg_cnfg_chg_d)); 01016 if (ret != MAX77659_NO_ERROR) return ret; 01017 01018 bit_value = (uint8_t)reg_cnfg_chg_d.bits.tj_reg; 01019 *tempDegC = (bit_value * 10) + 60; 01020 return MAX77659_NO_ERROR; 01021 } 01022 01023 int MAX77659::set_vsys_hdrm(decode_vsys_hdrm_t vsys_hdrm) 01024 { 01025 reg_cnfg_chg_d_t reg_cnfg_chg_d = {0}; 01026 01027 SET_BIT_FIELD(CNFG_CHG_D, reg_cnfg_chg_d, reg_cnfg_chg_d.bits.vsys_hdrm, vsys_hdrm); 01028 01029 return MAX77659_NO_ERROR; 01030 } 01031 01032 int MAX77659::get_vsys_hdrm(decode_vsys_hdrm_t *vsys_hdrm) 01033 { 01034 int ret; 01035 reg_cnfg_chg_d_t reg_cnfg_chg_d = {0}; 01036 01037 ret = read_register(CNFG_CHG_D, (uint8_t *)&(reg_cnfg_chg_d)); 01038 if (ret != MAX77659_NO_ERROR) return ret; 01039 01040 *vsys_hdrm = (decode_vsys_hdrm_t)reg_cnfg_chg_d.bits.vsys_hdrm; 01041 01042 return MAX77659_NO_ERROR; 01043 } 01044 01045 int MAX77659::set_vsys_min(decode_vsys_min_t vsys_min) 01046 { 01047 reg_cnfg_chg_d_t reg_cnfg_chg_d = {0}; 01048 01049 SET_BIT_FIELD(CNFG_CHG_D, reg_cnfg_chg_d, reg_cnfg_chg_d.bits.vsys_min, vsys_min); 01050 01051 return MAX77659_NO_ERROR; 01052 } 01053 01054 int MAX77659::get_vsys_min(decode_vsys_min_t *vsys_min) 01055 { 01056 int ret; 01057 reg_cnfg_chg_d_t reg_cnfg_chg_d = {0}; 01058 01059 ret = read_register(CNFG_CHG_D, (uint8_t *)&(reg_cnfg_chg_d)); 01060 if (ret != MAX77659_NO_ERROR) return ret; 01061 01062 *vsys_min = (decode_vsys_min_t)reg_cnfg_chg_d.bits.vsys_min; 01063 01064 return MAX77659_NO_ERROR; 01065 } 01066 01067 int MAX77659::set_chg_cc(float currentmA) 01068 { 01069 uint8_t value; 01070 reg_cnfg_chg_e_t reg_cnfg_chg_e = {0}; 01071 float currentuA = currentmA * 1000; 01072 01073 if (currentuA < 7500) currentuA = 7500; 01074 if (currentuA > 300000) currentuA = 300000; 01075 01076 value = (currentuA - 7500) / 7500; 01077 01078 SET_BIT_FIELD(CNFG_CHG_E, reg_cnfg_chg_e, reg_cnfg_chg_e.bits.chg_cc, value); 01079 return MAX77659_NO_ERROR; 01080 } 01081 01082 int MAX77659::get_chg_cc(float *currentmA) 01083 { 01084 int ret; 01085 uint8_t bit_value; 01086 reg_cnfg_chg_e_t reg_cnfg_chg_e = {0}; 01087 01088 ret = read_register(CNFG_CHG_E, (uint8_t *)&(reg_cnfg_chg_e)); 01089 if (ret != MAX77659_NO_ERROR) return ret; 01090 01091 bit_value = (uint8_t)reg_cnfg_chg_e.bits.chg_cc; 01092 if (bit_value >= 39) bit_value = 39; //0x27 to 0x3F = 300.0mA 01093 01094 *currentmA = (bit_value * 7.5f) + 7.5f; 01095 01096 return MAX77659_NO_ERROR; 01097 } 01098 01099 int MAX77659::set_t_fast_chg(decode_t_fast_chg_t t_fast_chg) 01100 { 01101 reg_cnfg_chg_e_t reg_cnfg_chg_e = {0}; 01102 01103 SET_BIT_FIELD(CNFG_CHG_E, reg_cnfg_chg_e, reg_cnfg_chg_e.bits.t_fast_chg, t_fast_chg); 01104 return MAX77659_NO_ERROR; 01105 } 01106 01107 int MAX77659::get_t_fast_chg(decode_t_fast_chg_t *t_fast_chg) 01108 { 01109 int ret; 01110 reg_cnfg_chg_e_t reg_cnfg_chg_e = {0}; 01111 01112 ret = read_register(CNFG_CHG_E, (uint8_t *)&(reg_cnfg_chg_e)); 01113 if (ret != MAX77659_NO_ERROR) return ret; 01114 01115 *t_fast_chg = (decode_t_fast_chg_t)reg_cnfg_chg_e.bits.t_fast_chg; 01116 01117 return MAX77659_NO_ERROR; 01118 } 01119 01120 int MAX77659::set_chg_cc_jeita(float currentmA) 01121 { 01122 uint8_t value; 01123 reg_cnfg_chg_f_t reg_cnfg_chg_f = {0}; 01124 float currentuA = currentmA * 1000; 01125 01126 if (currentuA < 7500) currentuA = 7500; 01127 else if (currentuA > 300000) currentuA = 300000; 01128 01129 value = round(currentuA - 7500) / 7500; 01130 01131 SET_BIT_FIELD(CNFG_CHG_F, reg_cnfg_chg_f, reg_cnfg_chg_f.bits.chg_cc_jeita, value); 01132 return MAX77659_NO_ERROR; 01133 } 01134 01135 int MAX77659::get_chg_cc_jeita(float *currentmA) 01136 { 01137 int ret; 01138 uint8_t bit_value; 01139 reg_cnfg_chg_f_t reg_cnfg_chg_f = {0}; 01140 01141 ret = read_register(CNFG_CHG_F, (uint8_t *)&(reg_cnfg_chg_f)); 01142 if (ret != MAX77659_NO_ERROR) return ret; 01143 01144 bit_value = (uint8_t)reg_cnfg_chg_f.bits.chg_cc_jeita; 01145 if (bit_value >= 39) bit_value = 39; //0x27 to 0x3F = 300.0mA 01146 01147 *currentmA = (bit_value * 7.5f) + 7.5f; 01148 return MAX77659_NO_ERROR; 01149 } 01150 01151 01152 01153 int MAX77659::set_thm_en(decode_thm_en_t thm_en) 01154 { 01155 reg_cnfg_chg_f_t reg_cnfg_chg_f = {0}; 01156 01157 SET_BIT_FIELD(CNFG_CHG_F, reg_cnfg_chg_f, reg_cnfg_chg_f.bits.thm_en, thm_en); 01158 01159 return MAX77659_NO_ERROR; 01160 } 01161 01162 int MAX77659::get_thm_en(decode_thm_en_t *thm_en) 01163 { 01164 int ret; 01165 reg_cnfg_chg_f_t reg_cnfg_chg_f = {0}; 01166 01167 ret = read_register(CNFG_CHG_F, (uint8_t *)&(reg_cnfg_chg_f)); 01168 if (ret != MAX77659_NO_ERROR) return ret; 01169 01170 *thm_en = (decode_thm_en_t)reg_cnfg_chg_f.bits.thm_en; 01171 01172 return MAX77659_NO_ERROR; 01173 } 01174 01175 int MAX77659::set_chg_cv(float voltV) 01176 { 01177 uint8_t value; 01178 reg_cnfg_chg_g_t reg_cnfg_chg_g = {0}; 01179 float voltmV = voltV * 1000; 01180 01181 if (voltmV < 3600) voltmV = 3600; 01182 else if (voltmV > 4600) voltmV = 4600; 01183 01184 value = (voltmV - 3600) / 25; 01185 01186 SET_BIT_FIELD(CNFG_CHG_G, reg_cnfg_chg_g, reg_cnfg_chg_g.bits.chg_cv, value); 01187 return MAX77659_NO_ERROR; 01188 } 01189 01190 int MAX77659::get_chg_cv(float *voltV) 01191 { 01192 int ret; 01193 uint8_t bit_value; 01194 reg_cnfg_chg_g_t reg_cnfg_chg_g = {0}; 01195 01196 ret = read_register(CNFG_CHG_G, (uint8_t *)&(reg_cnfg_chg_g)); 01197 if (ret != MAX77659_NO_ERROR) return ret; 01198 01199 bit_value = (uint8_t)reg_cnfg_chg_g.bits.chg_cv; 01200 *voltV = (bit_value * 0.025f) + 3.6f; 01201 return MAX77659_NO_ERROR; 01202 } 01203 01204 int MAX77659::set_usbs(decode_usbs_t usbs) 01205 { 01206 reg_cnfg_chg_g_t reg_cnfg_chg_g = {0}; 01207 01208 SET_BIT_FIELD(CNFG_CHG_G, reg_cnfg_chg_g, reg_cnfg_chg_g.bits.usbs, usbs); 01209 01210 return MAX77659_NO_ERROR; 01211 } 01212 01213 int MAX77659::get_usbs(decode_usbs_t *usbs) 01214 { 01215 int ret; 01216 reg_cnfg_chg_g_t reg_cnfg_chg_g = {0}; 01217 01218 ret = read_register(CNFG_CHG_G, (uint8_t *)&(reg_cnfg_chg_g)); 01219 if (ret != MAX77659_NO_ERROR) return ret; 01220 01221 *usbs = (decode_usbs_t)reg_cnfg_chg_g.bits.usbs; 01222 01223 return MAX77659_NO_ERROR; 01224 } 01225 01226 int MAX77659::set_chg_cv_jeita(float voltV) 01227 { 01228 uint8_t value; 01229 reg_cnfg_chg_h_t reg_cnfg_chg_h = {0}; 01230 float voltmV = voltV * 1000; 01231 01232 if (voltmV < 3600) voltmV = 3600; 01233 else if (voltmV > 4600) voltmV = 4600; 01234 01235 value = round(voltmV - 3600) / 25; 01236 01237 SET_BIT_FIELD(CNFG_CHG_H, reg_cnfg_chg_h, reg_cnfg_chg_h.bits.chg_cv_jeita, value); 01238 return MAX77659_NO_ERROR; 01239 } 01240 01241 int MAX77659::get_chg_cv_jeita(float *voltV) 01242 { 01243 int ret; 01244 uint8_t bit_value; 01245 reg_cnfg_chg_h_t reg_cnfg_chg_h = {0}; 01246 01247 ret = read_register(CNFG_CHG_H, (uint8_t *)&(reg_cnfg_chg_h)); 01248 if (ret != MAX77659_NO_ERROR) return ret; 01249 01250 bit_value = (uint8_t)reg_cnfg_chg_h.bits.chg_cv_jeita; 01251 *voltV = (bit_value * 0.025f) + 3.6f; 01252 return MAX77659_NO_ERROR; 01253 } 01254 01255 int MAX77659::set_imon_dischg_scale(float currentmA) 01256 { 01257 uint8_t value; 01258 reg_cnfg_chg_i_t reg_cnfg_chg_i = {0}; 01259 01260 if (currentmA < 40.5f) value = 0; 01261 else if ((currentmA >= 40.5f) && (currentmA < 72.3f)) value = 1; 01262 else if ((currentmA >= 72.3f) && (currentmA < 103.4f)) value = 2; 01263 else if ((currentmA >= 103.4f) && (currentmA < 134.1f)) value = 3; 01264 else if ((currentmA >= 134.1f) && (currentmA < 164.1f)) value = 4; 01265 else if ((currentmA >= 164.1f) && (currentmA < 193.7f)) value = 5; 01266 else if ((currentmA >= 193.7f) && (currentmA < 222.7f)) value = 6; 01267 else if ((currentmA >= 222.7f) && (currentmA < 251.2f)) value = 7; 01268 else if ((currentmA >= 251.2f) && (currentmA < 279.3f)) value = 8; 01269 else if ((currentmA >= 279.3f) && (currentmA < 300.0f)) value = 9; 01270 else if (currentmA >= 300.0f) value = 10; 01271 01272 SET_BIT_FIELD(CNFG_CHG_I, reg_cnfg_chg_i, reg_cnfg_chg_i.bits.imon_dischg_scale, value); 01273 return MAX77659_NO_ERROR; 01274 } 01275 01276 int MAX77659::get_imon_dischg_scale(float *currentmA) 01277 { 01278 int ret; 01279 uint8_t bit_value; 01280 reg_cnfg_chg_i_t reg_cnfg_chg_i = {0}; 01281 01282 ret = read_register(CNFG_CHG_I, (uint8_t *)&(reg_cnfg_chg_i)); 01283 if (ret != MAX77659_NO_ERROR) return ret; 01284 01285 bit_value = (uint8_t)reg_cnfg_chg_i.bits.imon_dischg_scale; 01286 01287 if (bit_value == 0) *currentmA = 8.2f; 01288 else if (bit_value == 1) *currentmA = 40.5f; 01289 else if (bit_value == 2) *currentmA = 72.3f; 01290 else if (bit_value == 3) *currentmA = 103.4f; 01291 else if (bit_value == 4) *currentmA = 134.1f; 01292 else if (bit_value == 5) *currentmA = 164.1f; 01293 else if (bit_value == 6) *currentmA = 193.7f; 01294 else if (bit_value == 7) *currentmA = 222.7f; 01295 else if (bit_value == 8) *currentmA = 251.2f; 01296 else if (bit_value == 9) *currentmA = 279.3f; 01297 else *currentmA = 300.0f; //0xA to 0xF = 300.0mA 01298 01299 return MAX77659_NO_ERROR; 01300 } 01301 01302 int MAX77659::set_mux_sel(decode_mux_sel_t selection) 01303 { 01304 reg_cnfg_chg_i_t reg_cnfg_chg_i = {0}; 01305 01306 SET_BIT_FIELD(CNFG_CHG_I, reg_cnfg_chg_i, reg_cnfg_chg_i.bits.mux_sel, selection); 01307 return MAX77659_NO_ERROR; 01308 } 01309 01310 int MAX77659::get_mux_sel(decode_mux_sel_t *selection) 01311 { 01312 int ret; 01313 reg_cnfg_chg_i_t reg_cnfg_chg_i = {0}; 01314 01315 ret = read_register(CNFG_CHG_I, (uint8_t *)&(reg_cnfg_chg_i)); 01316 if (ret != MAX77659_NO_ERROR) return ret; 01317 01318 *selection = (decode_mux_sel_t)reg_cnfg_chg_i.bits.mux_sel; 01319 return MAX77659_NO_ERROR; 01320 } 01321 01322 int MAX77659::set_tv_sbb(uint8_t channel, float voltV) 01323 { 01324 uint8_t value; 01325 reg_cnfg_sbb0_a_t reg_cnfg_sbb0_a = {0}; 01326 reg_cnfg_sbb1_a_t reg_cnfg_sbb1_a = {0}; 01327 reg_cnfg_sbb2_a_t reg_cnfg_sbb2_a = {0}; 01328 float voltmV = voltV * 1000; 01329 01330 if (voltmV < 500) voltmV = 500; 01331 else if (voltmV > 5500) voltmV = 5500; 01332 01333 value = (voltmV - 500) / 25; 01334 01335 if (channel == 0) { 01336 SET_BIT_FIELD(CNFG_SBB0_A, reg_cnfg_sbb0_a, reg_cnfg_sbb0_a.bits.tv_sbb0, value); 01337 } 01338 else if (channel == 1) { 01339 SET_BIT_FIELD(CNFG_SBB1_A, reg_cnfg_sbb1_a, reg_cnfg_sbb1_a.bits.tv_sbb1, value); 01340 } 01341 else if (channel == 2) { 01342 SET_BIT_FIELD(CNFG_SBB2_A, reg_cnfg_sbb2_a, reg_cnfg_sbb2_a.bits.tv_sbb2, value); 01343 } 01344 else { 01345 return MAX77659_INVALID_DATA; 01346 } 01347 01348 return MAX77659_NO_ERROR; 01349 } 01350 01351 int MAX77659::get_tv_sbb(uint8_t channel, float *voltV) 01352 { 01353 int ret; 01354 uint8_t bit_value; 01355 reg_cnfg_sbb0_a_t reg_cnfg_sbb0_a = {0}; 01356 reg_cnfg_sbb1_a_t reg_cnfg_sbb1_a = {0}; 01357 reg_cnfg_sbb2_a_t reg_cnfg_sbb2_a = {0}; 01358 01359 if (channel == 0) { 01360 ret = read_register(CNFG_SBB0_A, (uint8_t *)&(reg_cnfg_sbb0_a)); 01361 if (ret != MAX77659_NO_ERROR) return ret; 01362 01363 bit_value = (uint8_t)reg_cnfg_sbb0_a.bits.tv_sbb0; 01364 } 01365 else if (channel == 1) { 01366 ret = read_register(CNFG_SBB1_A, (uint8_t *)&(reg_cnfg_sbb1_a)); 01367 if (ret != MAX77659_NO_ERROR) return ret; 01368 01369 bit_value = (uint8_t)reg_cnfg_sbb1_a.bits.tv_sbb1; 01370 } 01371 else if (channel == 2) { 01372 ret = read_register(CNFG_SBB2_A, (uint8_t *)&(reg_cnfg_sbb2_a)); 01373 if (ret != MAX77659_NO_ERROR) return ret; 01374 01375 bit_value = (uint8_t)reg_cnfg_sbb2_a.bits.tv_sbb2; 01376 } 01377 else { 01378 return MAX77659_INVALID_DATA; 01379 } 01380 01381 if (bit_value > 200) bit_value = 200; 01382 *voltV = (bit_value * 0.025f) + 0.5f; 01383 01384 return MAX77659_NO_ERROR; 01385 } 01386 01387 int MAX77659::set_op_mode(uint8_t channel, decode_op_mode_t mode) 01388 { 01389 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0}; 01390 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0}; 01391 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0}; 01392 01393 if (channel == 0) { 01394 SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.op_mode, mode); 01395 } 01396 else if (channel == 1) { 01397 SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.op_mode, mode); 01398 } 01399 else if (channel == 2) { 01400 SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.op_mode, mode); 01401 } 01402 else { 01403 return MAX77659_INVALID_DATA; 01404 } 01405 01406 return MAX77659_NO_ERROR; 01407 } 01408 01409 int MAX77659::get_op_mode(uint8_t channel, decode_op_mode_t *mode) 01410 { 01411 int ret; 01412 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0}; 01413 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0}; 01414 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0}; 01415 01416 if (channel == 0) { 01417 ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b)); 01418 if (ret != MAX77659_NO_ERROR) return ret; 01419 01420 *mode = (decode_op_mode_t)reg_cnfg_sbb0_b.bits.op_mode; 01421 } 01422 else if (channel == 1) { 01423 ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b)); 01424 if (ret != MAX77659_NO_ERROR) return ret; 01425 01426 *mode = (decode_op_mode_t)reg_cnfg_sbb1_b.bits.op_mode; 01427 } 01428 else if (channel == 2) { 01429 ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b)); 01430 if (ret != MAX77659_NO_ERROR) return ret; 01431 01432 *mode = (decode_op_mode_t)reg_cnfg_sbb2_b.bits.op_mode; 01433 } 01434 else { 01435 return MAX77659_INVALID_DATA; 01436 } 01437 01438 return MAX77659_NO_ERROR; 01439 } 01440 01441 int MAX77659::set_ade_sbb(uint8_t channel, decode_ade_sbb_t ade_sbb) 01442 { 01443 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0}; 01444 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0}; 01445 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0}; 01446 01447 if (channel == 0) { 01448 SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.ade_sbb0, ade_sbb); 01449 } 01450 else if (channel == 1) { 01451 SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.ade_sbb1, ade_sbb); 01452 } 01453 else if (channel == 2) { 01454 SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.ade_sbb2, ade_sbb); 01455 } 01456 else { 01457 return MAX77659_INVALID_DATA; 01458 } 01459 01460 return MAX77659_NO_ERROR; 01461 } 01462 01463 int MAX77659::get_ade_sbb(uint8_t channel, decode_ade_sbb_t *ade_sbb) 01464 { 01465 int ret; 01466 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0}; 01467 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0}; 01468 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0}; 01469 01470 if (channel == 0) { 01471 ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b)); 01472 if (ret != MAX77659_NO_ERROR) return ret; 01473 01474 *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb0_b.bits.ade_sbb0; 01475 } 01476 else if (channel == 1) { 01477 ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b)); 01478 if (ret != MAX77659_NO_ERROR) return ret; 01479 01480 *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb1_b.bits.ade_sbb1; 01481 } 01482 else if (channel == 2) { 01483 ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b)); 01484 if (ret != MAX77659_NO_ERROR) return ret; 01485 01486 *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb2_b.bits.ade_sbb2; 01487 } 01488 else { 01489 return MAX77659_INVALID_DATA; 01490 } 01491 01492 return MAX77659_NO_ERROR; 01493 } 01494 01495 int MAX77659::set_en_sbb(uint8_t channel, decode_en_sbb_t en_sbb) 01496 { 01497 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0}; 01498 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0}; 01499 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0}; 01500 01501 if (channel == 0) { 01502 SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.en_sbb0, en_sbb); 01503 } 01504 else if (channel == 1) { 01505 SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.en_sbb1, en_sbb); 01506 } 01507 else if (channel == 2) { 01508 SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.en_sbb2, en_sbb); 01509 } 01510 else { 01511 return MAX77659_INVALID_DATA; 01512 } 01513 01514 return MAX77659_NO_ERROR; 01515 } 01516 01517 int MAX77659::get_en_sbb(uint8_t channel, decode_en_sbb_t *en_sbb) 01518 { 01519 int ret; 01520 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0}; 01521 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0}; 01522 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0}; 01523 01524 if (channel == 0) { 01525 ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b)); 01526 if (ret != MAX77659_NO_ERROR) return ret; 01527 01528 *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb0_b.bits.en_sbb0; 01529 } 01530 else if (channel == 1) { 01531 ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b)); 01532 if (ret != MAX77659_NO_ERROR) return ret; 01533 01534 *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb1_b.bits.en_sbb1; 01535 } 01536 else if (channel == 2) { 01537 ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b)); 01538 if (ret != MAX77659_NO_ERROR) return ret; 01539 01540 *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb2_b.bits.en_sbb2; 01541 } 01542 else { 01543 return MAX77659_INVALID_DATA; 01544 } 01545 01546 return MAX77659_NO_ERROR; 01547 } 01548 01549 int MAX77659::set_op_mode_chg(decode_op_mode_chg_t op_mode_chg) 01550 { 01551 reg_cnfg_sbb_top_t reg_cnfg_sbb_top = {0}; 01552 01553 SET_BIT_FIELD(CNFG_SBB_TOP, reg_cnfg_sbb_top, reg_cnfg_sbb_top.bits.op_mode_chg, op_mode_chg); 01554 01555 return MAX77659_NO_ERROR; 01556 } 01557 01558 int MAX77659::get_op_mode_chg(decode_op_mode_chg_t *op_mode_chg) 01559 { 01560 int ret; 01561 reg_cnfg_sbb_top_t reg_cnfg_sbb_top = {0}; 01562 01563 ret = read_register(CNFG_SBB_TOP, (uint8_t *)&(reg_cnfg_sbb_top)); 01564 if (ret != MAX77659_NO_ERROR) return ret; 01565 01566 *op_mode_chg = (decode_op_mode_chg_t)reg_cnfg_sbb_top.bits.op_mode_chg; 01567 01568 return MAX77659_NO_ERROR; 01569 } 01570 01571 int MAX77659::set_drv_sbb(decode_drv_sbb_t drv_sbb) 01572 { 01573 reg_cnfg_sbb_top_t reg_cnfg_sbb_top = {0}; 01574 01575 SET_BIT_FIELD(CNFG_SBB_TOP, reg_cnfg_sbb_top, reg_cnfg_sbb_top.bits.drv_sbb, drv_sbb); 01576 01577 return MAX77659_NO_ERROR; 01578 } 01579 01580 int MAX77659::get_drv_sbb(decode_drv_sbb_t *drv_sbb) 01581 { 01582 int ret; 01583 reg_cnfg_sbb_top_t reg_cnfg_sbb_top = {0}; 01584 01585 ret = read_register(CNFG_SBB_TOP, (uint8_t *)&(reg_cnfg_sbb_top)); 01586 if (ret != MAX77659_NO_ERROR) return ret; 01587 01588 *drv_sbb = (decode_drv_sbb_t)reg_cnfg_sbb_top.bits.drv_sbb; 01589 01590 return MAX77659_NO_ERROR; 01591 } 01592 01593 int MAX77659::set_ip_chg(decode_ip_chg_t ip_chg) 01594 { 01595 reg_cnfg_sbb_top_b_t reg_cnfg_sbb_top_b = {0}; 01596 01597 SET_BIT_FIELD(CNFG_SBB_TOP_B, reg_cnfg_sbb_top_b, reg_cnfg_sbb_top_b.bits.ip_chg, ip_chg); 01598 01599 return MAX77659_NO_ERROR; 01600 } 01601 01602 int MAX77659::get_ip_chg(decode_ip_chg_t *ip_chg) 01603 { 01604 int ret; 01605 reg_cnfg_sbb_top_b_t reg_cnfg_sbb_top_b = {0}; 01606 01607 ret = read_register(CNFG_SBB_TOP_B, (uint8_t *)&(reg_cnfg_sbb_top_b)); 01608 if (ret != MAX77659_NO_ERROR) return ret; 01609 01610 *ip_chg = (decode_ip_chg_t)reg_cnfg_sbb_top_b.bits.ip_chg; 01611 01612 return MAX77659_NO_ERROR; 01613 } 01614 01615 int MAX77659::set_ip_sbb(uint8_t channel, decode_ip_sbb_t ip_sbb) 01616 { 01617 reg_cnfg_sbb_top_b_t reg_cnfg_sbb_top_b = {0}; 01618 01619 if (channel == 0) { 01620 SET_BIT_FIELD(CNFG_SBB_TOP_B, reg_cnfg_sbb_top_b, reg_cnfg_sbb_top_b.bits.ip_sbb0, ip_sbb); 01621 } 01622 else if (channel == 1) { 01623 SET_BIT_FIELD(CNFG_SBB_TOP_B, reg_cnfg_sbb_top_b, reg_cnfg_sbb_top_b.bits.ip_sbb1, ip_sbb); 01624 } 01625 else if (channel == 2) { 01626 SET_BIT_FIELD(CNFG_SBB_TOP_B, reg_cnfg_sbb_top_b, reg_cnfg_sbb_top_b.bits.ip_sbb2, ip_sbb); 01627 } 01628 else { 01629 return MAX77659_INVALID_DATA; 01630 } 01631 01632 return MAX77659_NO_ERROR; 01633 } 01634 01635 int MAX77659::get_ip_sbb(uint8_t channel, decode_ip_sbb_t *ip_sbb) 01636 { 01637 int ret; 01638 reg_cnfg_sbb_top_b_t reg_cnfg_sbb_top_b = {0}; 01639 01640 ret = read_register(CNFG_SBB_TOP_B, (uint8_t *)&(reg_cnfg_sbb_top_b)); 01641 if (ret != MAX77659_NO_ERROR) return ret; 01642 01643 if (channel == 0) 01644 *ip_sbb = (decode_ip_sbb_t)reg_cnfg_sbb_top_b.bits.ip_sbb0; 01645 else if (channel == 1) 01646 *ip_sbb = (decode_ip_sbb_t)reg_cnfg_sbb_top_b.bits.ip_sbb1; 01647 else if (channel == 2) 01648 *ip_sbb = (decode_ip_sbb_t)reg_cnfg_sbb_top_b.bits.ip_sbb2; 01649 else 01650 return MAX77659_INVALID_DATA; 01651 01652 return MAX77659_NO_ERROR; 01653 } 01654 01655 int MAX77659::set_tv_ldo_offset(decode_tv_ldo_offset_t offset) 01656 { 01657 reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0}; 01658 01659 SET_BIT_FIELD(CNFG_LDO0_A, reg_cnfg_ldo0_a, reg_cnfg_ldo0_a.bits.tv_ldo_offset, offset); 01660 01661 return MAX77659_NO_ERROR; 01662 } 01663 01664 int MAX77659::get_tv_ldo_offset(decode_tv_ldo_offset_t *offset) 01665 { 01666 int ret; 01667 reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0}; 01668 01669 ret = read_register(CNFG_LDO0_A, (uint8_t *)&(reg_cnfg_ldo0_a)); 01670 if (ret != MAX77659_NO_ERROR) return ret; 01671 01672 *offset = (decode_tv_ldo_offset_t)reg_cnfg_ldo0_a.bits.tv_ldo_offset; 01673 01674 return MAX77659_NO_ERROR; 01675 } 01676 01677 int MAX77659::set_tv_ldo_volt(float voltV) 01678 { 01679 int ret; 01680 uint8_t value; 01681 reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0}; 01682 float voltmV = voltV * 1000; 01683 01684 ret = read_register(CNFG_LDO0_A, (uint8_t *)&(reg_cnfg_ldo0_a)); 01685 if (ret != MAX77659_NO_ERROR) return ret; 01686 01687 if (reg_cnfg_ldo0_a.bits.tv_ldo_offset == 0) { //No Offset 01688 if (voltmV < 500) voltmV = 500; 01689 else if (voltmV > 3675) voltmV = 3675; 01690 01691 value = (voltmV - 500) / 25; 01692 } 01693 else { //1.325V Offset 01694 if (voltmV < 1825) voltmV = 1825; 01695 else if (voltmV > 5000) voltmV = 5000; 01696 01697 value = (voltmV - 1825) / 25; 01698 } 01699 01700 SET_BIT_FIELD(CNFG_LDO0_A, reg_cnfg_ldo0_a, reg_cnfg_ldo0_a.bits.tv_ldo_volt, value); 01701 01702 return MAX77659_NO_ERROR; 01703 } 01704 01705 int MAX77659::get_tv_ldo_volt(float *voltV) 01706 { 01707 int ret; 01708 uint8_t bit_value; 01709 reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0}; 01710 01711 ret = read_register(CNFG_LDO0_A, (uint8_t *)&(reg_cnfg_ldo0_a)); 01712 if (ret != MAX77659_NO_ERROR) return ret; 01713 01714 bit_value = (uint8_t)reg_cnfg_ldo0_a.bits.tv_ldo_volt; 01715 if (reg_cnfg_ldo0_a.bits.tv_ldo_offset == 0) //No Offset 01716 *voltV = (bit_value * 0.025f) + 0.5f; 01717 else //1.325V Offset 01718 *voltV = (bit_value * 0.025f) + 1.825f; 01719 01720 return MAX77659_NO_ERROR; 01721 } 01722 01723 int MAX77659::set_en_ldo(decode_en_ldo_t en_ldo) 01724 { 01725 reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0}; 01726 01727 SET_BIT_FIELD(CNFG_LDO0_B, reg_cnfg_ldo0_b, reg_cnfg_ldo0_b.bits.en_ldo, en_ldo); 01728 01729 return MAX77659_NO_ERROR; 01730 } 01731 01732 int MAX77659::get_en_ldo( decode_en_ldo_t *en_ldo) 01733 { 01734 int ret; 01735 reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0}; 01736 01737 ret = read_register(CNFG_LDO0_B, (uint8_t *)&(reg_cnfg_ldo0_b)); 01738 if (ret != MAX77659_NO_ERROR) return ret; 01739 01740 *en_ldo = (decode_en_ldo_t)reg_cnfg_ldo0_b.bits.en_ldo; 01741 01742 return MAX77659_NO_ERROR; 01743 } 01744 01745 int MAX77659::set_ade_ldo(decode_ade_ldo_t ade_ldo) 01746 { 01747 reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0}; 01748 01749 SET_BIT_FIELD(CNFG_LDO0_B, reg_cnfg_ldo0_b, reg_cnfg_ldo0_b.bits.ade_ldo, ade_ldo); 01750 01751 return MAX77659_NO_ERROR; 01752 } 01753 01754 int MAX77659::get_ade_ldo(decode_ade_ldo_t *ade_ldo) 01755 { 01756 int ret; 01757 reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0}; 01758 01759 ret = read_register(CNFG_LDO0_B, (uint8_t *)&(reg_cnfg_ldo0_b)); 01760 if (ret != MAX77659_NO_ERROR) return ret; 01761 01762 *ade_ldo = (decode_ade_ldo_t)reg_cnfg_ldo0_b.bits.ade_ldo; 01763 01764 return MAX77659_NO_ERROR; 01765 } 01766 01767 int MAX77659::set_ldo_md(decode_ldo_md_t mode) 01768 { 01769 reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0}; 01770 01771 SET_BIT_FIELD(CNFG_LDO0_B, reg_cnfg_ldo0_b, reg_cnfg_ldo0_b.bits.ldo_md, mode); 01772 01773 return MAX77659_NO_ERROR; 01774 } 01775 01776 int MAX77659::get_ldo_md(decode_ldo_md_t *mode) 01777 { 01778 int ret; 01779 reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0}; 01780 01781 ret = read_register(CNFG_LDO0_B, (uint8_t *)&(reg_cnfg_ldo0_b)); 01782 if (ret != MAX77659_NO_ERROR) return ret; 01783 01784 *mode = (decode_ldo_md_t)reg_cnfg_ldo0_b.bits.ldo_md; 01785 01786 return MAX77659_NO_ERROR; 01787 } 01788 01789 int MAX77659::irq_disable_all() 01790 { 01791 int ret; 01792 uint8_t reg = 0; 01793 uint8_t status = 0; 01794 01795 //Disable Masks in INTM_GLBL1 01796 ret = write_register(INTM_GLBL1, ®); 01797 if (ret != MAX77659_NO_ERROR) return ret; 01798 01799 //Disable Masks in INTM_GLBL0 01800 ret = write_register(INTM_GLBL0, ®); 01801 if (ret != MAX77659_NO_ERROR) return ret; 01802 01803 //Disable Masks in INT_M_CHG 01804 ret = write_register(INT_M_CHG, ®); 01805 if (ret != MAX77659_NO_ERROR) return ret; 01806 01807 // Clear Interrupt Flags in INT_GLBL1 01808 ret = read_register(INT_GLBL1, &status); 01809 if (ret != MAX77659_NO_ERROR) return ret; 01810 01811 // Clear Interrupt Flags in INT_GLBL0 01812 ret = read_register(INT_GLBL0, &status); 01813 if (ret != MAX77659_NO_ERROR) return ret; 01814 01815 // Clear Interrupt Flags in INT_CHG 01816 ret = read_register(INT_CHG, &status); 01817 if (ret != MAX77659_NO_ERROR) return ret; 01818 01819 return MAX77659_NO_ERROR; 01820 } 01821 01822 void MAX77659::set_interrupt_handler(reg_bit_int_glbl_t id, interrupt_handler_function func, void *cb) 01823 { 01824 interrupt_handler_list[id].func = func; 01825 interrupt_handler_list[id].cb = cb; 01826 } 01827 01828 void MAX77659::post_interrupt_work() 01829 { 01830 int ret; 01831 uint8_t reg = 0, inten = 0, not_inten = 0, mask = 0; 01832 01833 01834 while (true) { 01835 01836 ThisThread::flags_wait_any(POST_INTR_WORK_SIGNAL_ID); 01837 01838 // Check Interrupt Flags in INT_GLBL0 01839 ret = read_register(INT_GLBL0, ®); 01840 if (ret != MAX77659_NO_ERROR) return; 01841 01842 ret = read_register(INTM_GLBL0, &inten); 01843 if (ret != MAX77659_NO_ERROR) return; 01844 01845 not_inten = ~inten; // 0 means unmasked. 01846 01847 for (int i = 0; i < INT_GLBL1_GPI1_F; i++) { 01848 mask = (1 << i); 01849 if ((reg & mask) && (not_inten & mask)) { 01850 if (interrupt_handler_list[i].func != NULL) { 01851 interrupt_handler_list[i] 01852 .func(interrupt_handler_list[i].cb); 01853 } 01854 } 01855 } 01856 01857 // Check Interrupt Flags in INT_GLBL1 01858 ret = read_register(INT_GLBL1, ®); 01859 if (ret != MAX77659_NO_ERROR) return; 01860 01861 ret = read_register(INTM_GLBL1, &inten); 01862 if (ret != MAX77659_NO_ERROR) return; 01863 01864 not_inten = ~inten; // 0 means unmasked. 01865 01866 for (int i = INT_GLBL1_GPI1_F; i < INT_CHG_THM_I; i++) { 01867 mask = (1 << (i - INT_GLBL1_GPI1_F)); 01868 if ((reg & mask) && (not_inten & mask)) { 01869 if (interrupt_handler_list[i].func != NULL) { 01870 interrupt_handler_list[i] 01871 .func(interrupt_handler_list[i].cb); 01872 } 01873 } 01874 } 01875 01876 // Check Interrupt Flags in INT_CHG 01877 ret = read_register(INT_CHG, ®); 01878 if (ret != MAX77659_NO_ERROR) return; 01879 01880 ret = read_register(INT_M_CHG, &inten); 01881 if (ret != MAX77659_NO_ERROR) return; 01882 not_inten = ~inten; // 0 means unmasked. 01883 01884 for (int i = INT_CHG_THM_I; i < INT_CHG_END; i++) { 01885 mask = (1 << (i - INT_CHG_THM_I)); 01886 if ((reg & mask) && (not_inten & mask)) { 01887 if (interrupt_handler_list[i].func != NULL) { 01888 interrupt_handler_list[i] 01889 .func(interrupt_handler_list[i].cb); 01890 } 01891 } 01892 } 01893 } 01894 } 01895 01896 void MAX77659::interrupt_handler() 01897 { 01898 post_intr_work_thread->flags_set(POST_INTR_WORK_SIGNAL_ID); 01899 }
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