Diff: max17055.cpp

Revision:

6:5ced10109ebf

Parent:

5:a18a189588dc

Child:

7:479a36909ced

--- a/max17055.cpp	Mon Oct 02 21:59:00 2017 +0000
+++ b/max17055.cpp	Thu Oct 05 02:37:59 2017 +0000
@@ -81,10 +81,7 @@
 #define MAX17055_VMAX_TOLERANCE     50 /* 50 mV */
 
 
-//struct battery_priv {
-//        struct power_supply battery;
-//    };
-
+///////////////////////////////////////////////////////////////////////////////
 
 MAX17055::MAX17055(I2C &i2c):
     m_i2cBus(i2c)
@@ -92,19 +89,13 @@
     //empty block
 }
 
+///////////////////////////////////////////////////////////////////////////////
 MAX17055::~MAX17055()
 {
     //empty block
 }
 
 
-
-
-
-
-
-
-
 ///////////////////////////////////////////////////////////////////////////////
 
 /**
@@ -207,11 +198,10 @@
         }
     } while (retries && read_data != reg_data);
 
-    if (ret<0) {
+    if (ret<0)
         return ret;
-    } else {
+     else 
         return 1;
-    }
 }
 
 ////////////////////////////////////////////////////////////////////////////////
@@ -227,11 +217,11 @@
 */
 
 
-int MAX17055::init(struct max17055_platform_data *pri)
+int MAX17055::init(max17055_platform_data des_data)
 {
-    //*batt_con = batt_info;
+
     int status, ret;
-    uint16_t read_data, hibcfg_value,dpacc, reg;
+    uint16_t read_data, hibcfg_value, dpacc, reg;
 
 
     status = readReg(MAX17055_VERSION_REG, read_data);
@@ -248,30 +238,35 @@
 
     /* Step 1: Check if FStat.DNR == 0 */
     // Do not continue until FSTAT.DNR == 0
-
-    while(readReg(MAX17055_FSTAT_REG, read_data)&1) {
-        wait_ms(10);//10 ms wait empty loop
+    printf("step 0 check \r\n");
+    
+    int time_out = 500;
+    ret = max17055_poll_flag_clear (MAX17055_FSTAT_REG, MAX17055_FSTAT_DNR, time_out);
+    if (ret < 0){
+        printf("Unsuccessful init: Data Not Ready!\n");
+        return ret;
     }
 
     /* Force exit from hibernate */
     hibcfg_value = forcedExitHyberMode();
-
+    
+    printf("step 1 check \r\n");
 
     /* Step 2: Initialize configuration */
     switch (1) {
         case MODEL_LOADING_OPTION1:
             /* Step 2.1: Option 1 EZ Config */
-            writeReg(MAX17055_DESIGNCAP_REG, designcap);
-            writeReg(MAX17055_DQACC_REG, pri.designcap >> 5);
-            writeReg(MAX17055_ICHGTERM_REG, pri.ichgterm);
-            writeReg(MAX17055_VEMPTY_REG, pri.vempty);
+            writeReg(MAX17055_DESIGNCAP_REG, des_data.designcap);
+            writeReg(MAX17055_DQACC_REG, des_data.designcap >> 5);
+            writeReg(MAX17055_ICHGTERM_REG, des_data.ichgterm);
+            writeReg(MAX17055_VEMPTY_REG, des_data.vempty);
 
-            if (pri.vcharge > 4275) { //Need to know what this 4275 is
-                dpacc = (pri.designcap >> 5) * 0xC800 / pri.designcap;
+            if (design_data.vcharge > 4275) { //Need to know what this 4275 is
+                dpacc = (des_data.designcap >> 5) * 0xC800 / des_data.designcap;
                 writeReg(MAX17055_DPACC_REG, dpacc);
                 writeReg(MAX17055_MODELCFG_REG, 0x8400); //Why 0x8400
             } else {
-                dpacc = (pri.designcap >> 5) * 0xAC6A / pri.designcap;
+                dpacc = (des_data.designcap >> 5) * 0xAC6A / des_data.designcap;
                 writeReg(MAX17055_DPACC_REG, dpacc);
                 writeReg(MAX17055_MODELCFG_REG, 0x8000);
             }
@@ -286,6 +281,8 @@
     }
     /* Restore original HibCfg */
     writeReg(MAX17055_HIBCFG_REG, hibcfg_value);
+    printf("Last section check \r\n");
+
 
     /* Optional step - alert threshold initialization */
     //max17055_set_alert_thresholds(priv);
@@ -313,14 +310,14 @@
 *              -1 on Failure
 */
 
-int max17055_poll_flag_clear(Registers_e reg_addr, int mask, int timeout)
+int MAX17055::max17055_poll_flag_clear (Registers_e reg_addr, int mask, int timeout)
 {
     uint16_t data;
     int ret;
 
     do {
         wait(50);
-        ret = readReg(red_addr, data);
+        ret = readReg(reg_addr, data);
         if(ret < 0)
             return ret;