Maxim Integrated / MAX17055_EZconfig

This is a library for the MAX17055 Li+ Battery Fuel Gauge.

Dependents:   Low_Power_Long_Distance_IR_Vision_Robot MAX17055_EZconfig MAX17055_EZconfig_Sample Low_Power_Long_Distance_IR_Vision_Robot

Fork of max17055 by Maxim Integrated

max17055.cpp@5:a18a189588dc, 2017-10-02 (annotated)

Committer:
fneirab
Date:
Mon Oct 02 21:59:00 2017 +0000
Revision:
5:a18a189588dc
Parent:
4:a4d6ae2182c2
Child:
6:5ced10109ebf
changes might have affected the compile. Saved for safety.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
fneirab 4:a4d6ae2182c2 1 /******************************************************************//**
fneirab 4:a4d6ae2182c2 2 * @file max17055.cpp
fneirab 4:a4d6ae2182c2 3 *
fneirab 4:a4d6ae2182c2 4 * @author Felipe Neira - Maxim Integrated - TTS
fneirab 4:a4d6ae2182c2 5 *
fneirab 4:a4d6ae2182c2 6 * @version 1.0
fneirab 4:a4d6ae2182c2 7 *
fneirab 4:a4d6ae2182c2 8 * Started: 11SEP17
fneirab 4:a4d6ae2182c2 9 *
fneirab 5:a18a189588dc 10 * Updated:
fneirab 4:a4d6ae2182c2 11 *
fneirab 4:a4d6ae2182c2 12 * @brief Source file for MAX31855 class
fneirab 4:a4d6ae2182c2 13 *
fneirab 4:a4d6ae2182c2 14 ********************************************************************************
fneirab 4:a4d6ae2182c2 15 * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
fneirab 4:a4d6ae2182c2 16 *
fneirab 4:a4d6ae2182c2 17 * Permission is hereby granted, free of charge, to any person obtaining a
fneirab 4:a4d6ae2182c2 18 * copy of this software and associated documentation files (the "Software"),
fneirab 4:a4d6ae2182c2 19 * to deal in the Software without restriction, including without limitation
fneirab 4:a4d6ae2182c2 20 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
fneirab 4:a4d6ae2182c2 21 * and/or sell copies of the Software, and to permit persons to whom the
fneirab 4:a4d6ae2182c2 22 * Software is furnished to do so, subject to the following conditions:
fneirab 4:a4d6ae2182c2 23 *
fneirab 4:a4d6ae2182c2 24 * The above copyright notice and this permission notice shall be included
fneirab 4:a4d6ae2182c2 25 * in all copies or substantial portions of the Software.
fneirab 4:a4d6ae2182c2 26 *
fneirab 4:a4d6ae2182c2 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
fneirab 4:a4d6ae2182c2 28 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
fneirab 4:a4d6ae2182c2 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
fneirab 4:a4d6ae2182c2 30 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
fneirab 4:a4d6ae2182c2 31 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
fneirab 4:a4d6ae2182c2 32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
fneirab 4:a4d6ae2182c2 33 * OTHER DEALINGS IN THE SOFTWARE.
fneirab 4:a4d6ae2182c2 34 *
fneirab 4:a4d6ae2182c2 35 * Except as contained in this notice, the name of Maxim Integrated
fneirab 4:a4d6ae2182c2 36 * Products, Inc. shall not be used except as stated in the Maxim Integrated
fneirab 4:a4d6ae2182c2 37 * Products, Inc. Branding Policy.
fneirab 4:a4d6ae2182c2 38 *
fneirab 4:a4d6ae2182c2 39 * The mere transfer of this software does not imply any licenses
fneirab 4:a4d6ae2182c2 40 * of trade secrets, proprietary technology, copyrights, patents,
fneirab 4:a4d6ae2182c2 41 * trademarks, maskwork rights, or any other form of intellectual
fneirab 4:a4d6ae2182c2 42 * property whatsoever. Maxim Integrated Products, Inc. retains all
fneirab 4:a4d6ae2182c2 43 * ownership rights.
fneirab 4:a4d6ae2182c2 44 *
fneirab 4:a4d6ae2182c2 45 ******************************************************************************/
fneirab 0:80c39eb8f3ba 46
fneirab 0:80c39eb8f3ba 47 #include "mbed.h"
fneirab 0:80c39eb8f3ba 48 #include "max17055.h"
fneirab 0:80c39eb8f3ba 49
fneirab 5:a18a189588dc 50 #define DRV_NAME "max17055"
fneirab 5:a18a189588dc 51
fneirab 5:a18a189588dc 52 /* CONFIG register bits */
fneirab 5:a18a189588dc 53 #define MAX17055_CONFIG_ALRT_EN (1 << 2)
fneirab 5:a18a189588dc 54 #define MAX17055_CONFIG2_LDMDL (1 << 5)
fneirab 5:a18a189588dc 55
fneirab 5:a18a189588dc 56 /* STATUS register bits */
fneirab 5:a18a189588dc 57 #define MAX17055_STATUS_BST (1 << 3)
fneirab 5:a18a189588dc 58 #define MAX17055_STATUS_POR (1 << 1)
fneirab 5:a18a189588dc 59
fneirab 5:a18a189588dc 60 /* MODELCFG register bits */
fneirab 5:a18a189588dc 61 #define MAX17055_MODELCFG_REFRESH (1 << 15)
fneirab 5:a18a189588dc 62
fneirab 5:a18a189588dc 63 /* TALRTTH register bits */
fneirab 5:a18a189588dc 64 #define MIN_TEMP_ALERT 0
fneirab 5:a18a189588dc 65 #define MAX_TEMP_ALERT 8
fneirab 5:a18a189588dc 66
fneirab 5:a18a189588dc 67 /* FSTAT register bits */
fneirab 5:a18a189588dc 68 #define MAX17055_FSTAT_DNR (1)
fneirab 5:a18a189588dc 69
fneirab 5:a18a189588dc 70 /* STATUS interrupt status bits */
fneirab 5:a18a189588dc 71 #define MAX17055_STATUS_ALRT_CLR_MASK (0x88BB)
fneirab 5:a18a189588dc 72 #define MAX17055_STATUS_SOC_MAX_ALRT (1 << 14)
fneirab 5:a18a189588dc 73 #define MAX17055_STATUS_TEMP_MAX_ALRT (1 << 13)
fneirab 5:a18a189588dc 74 #define MAX17055_STATUS_VOLT_MAX_ALRT (1 << 12)
fneirab 5:a18a189588dc 75 #define MAX17055_STATUS_SOC_MIN_ALRT (1 << 10)
fneirab 5:a18a189588dc 76 #define MAX17055_STATUS_TEMP_MIN_ALRT (1 << 9)
fneirab 5:a18a189588dc 77 #define MAX17055_STATUS_VOLT_MIN_ALRT (1 << 8)
fneirab 5:a18a189588dc 78 #define MAX17055_STATUS_CURR_MAX_ALRT (1 << 6)
fneirab 5:a18a189588dc 79 #define MAX17055_STATUS_CURR_MIN_ALRT (1 << 2)
fneirab 5:a18a189588dc 80
fneirab 5:a18a189588dc 81 #define MAX17055_VMAX_TOLERANCE 50 /* 50 mV */
fneirab 4:a4d6ae2182c2 82
fneirab 0:80c39eb8f3ba 83
fneirab 5:a18a189588dc 84 //struct battery_priv {
fneirab 5:a18a189588dc 85 // struct power_supply battery;
fneirab 5:a18a189588dc 86 // };
fneirab 5:a18a189588dc 87
fneirab 5:a18a189588dc 88
fneirab 5:a18a189588dc 89 MAX17055::MAX17055(I2C &i2c):
fneirab 5:a18a189588dc 90 m_i2cBus(i2c)
fneirab 0:80c39eb8f3ba 91 {
fneirab 5:a18a189588dc 92 //empty block
fneirab 0:80c39eb8f3ba 93 }
fneirab 0:80c39eb8f3ba 94
fneirab 0:80c39eb8f3ba 95 MAX17055::~MAX17055()
fneirab 0:80c39eb8f3ba 96 {
fneirab 0:80c39eb8f3ba 97 //empty block
fneirab 0:80c39eb8f3ba 98 }
fneirab 5:a18a189588dc 99
fneirab 5:a18a189588dc 100
fneirab 5:a18a189588dc 101
fneirab 5:a18a189588dc 102
fneirab 5:a18a189588dc 103
fneirab 5:a18a189588dc 104
fneirab 5:a18a189588dc 105
fneirab 5:a18a189588dc 106
fneirab 5:a18a189588dc 107
fneirab 1:a031f0c6a71e 108 ///////////////////////////////////////////////////////////////////////////////
fneirab 0:80c39eb8f3ba 109
fneirab 0:80c39eb8f3ba 110 /**
fneirab 0:80c39eb8f3ba 111 * \brief Write a value to a MAX17055 register
fneirab 0:80c39eb8f3ba 112 * \par Details
fneirab 0:80c39eb8f3ba 113 * This function writes a value to a MAX17055 register
fneirab 0:80c39eb8f3ba 114 *
fneirab 1:a031f0c6a71e 115 * \param[in] reg_addr - register address
fneirab 1:a031f0c6a71e 116 * \param[in] reg_data - register data
fneirab 0:80c39eb8f3ba 117 *
fneirab 1:a031f0c6a71e 118 * \retval 1 on success
fneirab 0:80c39eb8f3ba 119 */
fneirab 0:80c39eb8f3ba 120
fneirab 0:80c39eb8f3ba 121 int MAX17055::writeReg(Registers_e reg_addr, uint16_t reg_data)
fneirab 0:80c39eb8f3ba 122 {
fneirab 0:80c39eb8f3ba 123
fneirab 5:a18a189588dc 124
fneirab 1:a031f0c6a71e 125 uint8_t dataLSB;
fneirab 1:a031f0c6a71e 126 uint8_t dataMSB;
fneirab 5:a18a189588dc 127
fneirab 1:a031f0c6a71e 128 dataLSB = reg_data & 0x00FF;
fneirab 5:a18a189588dc 129 dataMSB = (reg_data >> 8) & 0x00FF;
fneirab 5:a18a189588dc 130
fneirab 1:a031f0c6a71e 131 char add_plus_data[3] = {reg_addr, dataLSB, dataMSB};
fneirab 5:a18a189588dc 132
fneirab 1:a031f0c6a71e 133 if ( m_i2cBus.write(I2C_W_ADRS, add_plus_data, 3, false) == 0)
fneirab 0:80c39eb8f3ba 134 return 1;
fneirab 0:80c39eb8f3ba 135 else
fneirab 0:80c39eb8f3ba 136 return 0;
fneirab 0:80c39eb8f3ba 137
fneirab 0:80c39eb8f3ba 138 }
fneirab 1:a031f0c6a71e 139 ///////////////////////////////////////////////////////////////////////////////
fneirab 0:80c39eb8f3ba 140 /**
fneirab 0:80c39eb8f3ba 141 * \brief Read a MAX17055 register
fneirab 0:80c39eb8f3ba 142 * \par Details
fneirab 0:80c39eb8f3ba 143 * This function reads a MAX17055 register
fneirab 0:80c39eb8f3ba 144 *
fneirab 1:a031f0c6a71e 145 * \param[in] reg_addr - register address
fneirab 1:a031f0c6a71e 146 * \param[out] &value - pointer that stores the register data
fneirab 0:80c39eb8f3ba 147 *
fneirab 0:80c39eb8f3ba 148 * \retval 1 on success
fneirab 0:80c39eb8f3ba 149 */
fneirab 0:80c39eb8f3ba 150
fneirab 0:80c39eb8f3ba 151
fneirab 1:a031f0c6a71e 152 int32_t MAX17055::readReg(Registers_e reg_addr, uint16_t &value)
fneirab 0:80c39eb8f3ba 153 {
fneirab 0:80c39eb8f3ba 154 int32_t result;
fneirab 1:a031f0c6a71e 155 //int16_t value2;
fneirab 1:a031f0c6a71e 156 //int16_t twoBytes;
fneirab 1:a031f0c6a71e 157 char local_data[1];
fneirab 0:80c39eb8f3ba 158 local_data[0] = reg_addr;
fneirab 1:a031f0c6a71e 159 char read_data[2];
fneirab 5:a18a189588dc 160
fneirab 0:80c39eb8f3ba 161 result = m_i2cBus.write(I2C_W_ADRS, local_data, 1);
fneirab 5:a18a189588dc 162 if(result == 0) {
fneirab 1:a031f0c6a71e 163 result = m_i2cBus.read(I2C_R_ADRS, read_data , 2, false);
fneirab 5:a18a189588dc 164 if (result == 0) {
fneirab 1:a031f0c6a71e 165 value = ( ((read_data[1] & 0x00FF) << 8) + (read_data[0]));
fneirab 1:a031f0c6a71e 166 result = 1;
fneirab 5:a18a189588dc 167 }
fneirab 0:80c39eb8f3ba 168 }
fneirab 5:a18a189588dc 169
fneirab 0:80c39eb8f3ba 170 return result;
fneirab 5:a18a189588dc 171
fneirab 0:80c39eb8f3ba 172 }
fneirab 0:80c39eb8f3ba 173
fneirab 2:ff7db397b70f 174 ///////////////////////////////////////////////////////////////////////////////
fneirab 1:a031f0c6a71e 175 /**
fneirab 1:a031f0c6a71e 176 * \brief Write and Verify a MAX17055 register
fneirab 1:a031f0c6a71e 177 * \par Details
fneirab 1:a031f0c6a71e 178 * This function wites and verifies if the writing process was successful
fneirab 1:a031f0c6a71e 179 *
fneirab 1:a031f0c6a71e 180 * \param[in] reg_addr - register address
fneirab 5:a18a189588dc 181 * \param[out] reg_data - the variable that contains the data to write
fneirab 1:a031f0c6a71e 182 * to the register address
fneirab 1:a031f0c6a71e 183 *
fneirab 1:a031f0c6a71e 184 * \retval 1 on success
fneirab 1:a031f0c6a71e 185 */
fneirab 1:a031f0c6a71e 186
fneirab 1:a031f0c6a71e 187
fneirab 5:a18a189588dc 188 int MAX17055::write_and_verify_reg(Registers_e reg_addr, uint16_t reg_data)
fneirab 5:a18a189588dc 189 {
fneirab 1:a031f0c6a71e 190 int retries = 8;
fneirab 1:a031f0c6a71e 191 int ret;
fneirab 1:a031f0c6a71e 192 int statusRead;
fneirab 1:a031f0c6a71e 193 int statusWrite;
fneirab 1:a031f0c6a71e 194 uint16_t read_data;
fneirab 5:a18a189588dc 195
fneirab 1:a031f0c6a71e 196 do {
fneirab 1:a031f0c6a71e 197 statusWrite = writeReg(reg_addr, reg_data);
fneirab 1:a031f0c6a71e 198 if (statusWrite != 1)
fneirab 1:a031f0c6a71e 199 ret = -1;
fneirab 1:a031f0c6a71e 200 wait_ms(3);
fneirab 5:a18a189588dc 201 statusRead = readReg(reg_addr, read_data);
fneirab 1:a031f0c6a71e 202 if (statusRead != 1)
fneirab 1:a031f0c6a71e 203 ret = -2;
fneirab 5:a18a189588dc 204 if (read_data != reg_data) {
fneirab 1:a031f0c6a71e 205 ret = -3;
fneirab 1:a031f0c6a71e 206 retries--;
fneirab 1:a031f0c6a71e 207 }
fneirab 5:a18a189588dc 208 } while (retries && read_data != reg_data);
fneirab 5:a18a189588dc 209
fneirab 5:a18a189588dc 210 if (ret<0) {
fneirab 1:a031f0c6a71e 211 return ret;
fneirab 5:a18a189588dc 212 } else {
fneirab 1:a031f0c6a71e 213 return 1;
fneirab 5:a18a189588dc 214 }
fneirab 1:a031f0c6a71e 215 }
fneirab 2:ff7db397b70f 216
fneirab 2:ff7db397b70f 217 ////////////////////////////////////////////////////////////////////////////////
fneirab 2:ff7db397b70f 218
fneirab 2:ff7db397b70f 219 /**
fneirab 3:f77a8345b0e3 220 * \brief Initialise Function for MAX17055
fneirab 3:f77a8345b0e3 221 * \par Details
fneirab 3:f77a8345b0e3 222 * This function intitializes the MAX17055
fneirab 3:f77a8345b0e3 223 *
fneirab 5:a18a189588dc 224 * \retval 1 on success
fneirab 3:f77a8345b0e3 225 * 0 if device is not present
fneirab 3:f77a8345b0e3 226 * -1 if errors exist
fneirab 3:f77a8345b0e3 227 */
fneirab 5:a18a189588dc 228
fneirab 5:a18a189588dc 229
fneirab 5:a18a189588dc 230 int MAX17055::init(struct max17055_platform_data *pri)
fneirab 2:ff7db397b70f 231 {
fneirab 5:a18a189588dc 232 //*batt_con = batt_info;
fneirab 5:a18a189588dc 233 int status, ret;
fneirab 5:a18a189588dc 234 uint16_t read_data, hibcfg_value,dpacc, reg;
fneirab 5:a18a189588dc 235
fneirab 5:a18a189588dc 236
fneirab 2:ff7db397b70f 237 status = readReg(MAX17055_VERSION_REG, read_data);
fneirab 2:ff7db397b70f 238 if (status == 0)
fneirab 2:ff7db397b70f 239 return status; //Device is not present in the i2c Bus
fneirab 5:a18a189588dc 240
fneirab 2:ff7db397b70f 241 /* Step 0: Check for POR */
fneirab 2:ff7db397b70f 242 /* Skip load model if POR bit is cleared */
fneirab 5:a18a189588dc 243
fneirab 2:ff7db397b70f 244 readReg(MAX17055_STATUS_REG, read_data);
fneirab 2:ff7db397b70f 245
fneirab 2:ff7db397b70f 246 if (!(read_data & MAX17055_STATUS_POR ) )
fneirab 5:a18a189588dc 247 return -1; //POR is not set. Skip Initialization.
fneirab 2:ff7db397b70f 248
fneirab 2:ff7db397b70f 249 /* Step 1: Check if FStat.DNR == 0 */
fneirab 3:f77a8345b0e3 250 // Do not continue until FSTAT.DNR == 0
fneirab 5:a18a189588dc 251
fneirab 5:a18a189588dc 252 while(readReg(MAX17055_FSTAT_REG, read_data)&1) {
fneirab 3:f77a8345b0e3 253 wait_ms(10);//10 ms wait empty loop
fneirab 3:f77a8345b0e3 254 }
fneirab 5:a18a189588dc 255
fneirab 5:a18a189588dc 256 /* Force exit from hibernate */
fneirab 5:a18a189588dc 257 hibcfg_value = forcedExitHyberMode();
fneirab 5:a18a189588dc 258
fneirab 5:a18a189588dc 259
fneirab 5:a18a189588dc 260 /* Step 2: Initialize configuration */
fneirab 5:a18a189588dc 261 switch (1) {
fneirab 5:a18a189588dc 262 case MODEL_LOADING_OPTION1:
fneirab 5:a18a189588dc 263 /* Step 2.1: Option 1 EZ Config */
fneirab 5:a18a189588dc 264 writeReg(MAX17055_DESIGNCAP_REG, designcap);
fneirab 5:a18a189588dc 265 writeReg(MAX17055_DQACC_REG, pri.designcap >> 5);
fneirab 5:a18a189588dc 266 writeReg(MAX17055_ICHGTERM_REG, pri.ichgterm);
fneirab 5:a18a189588dc 267 writeReg(MAX17055_VEMPTY_REG, pri.vempty);
fneirab 5:a18a189588dc 268
fneirab 5:a18a189588dc 269 if (pri.vcharge > 4275) { //Need to know what this 4275 is
fneirab 5:a18a189588dc 270 dpacc = (pri.designcap >> 5) * 0xC800 / pri.designcap;
fneirab 5:a18a189588dc 271 writeReg(MAX17055_DPACC_REG, dpacc);
fneirab 5:a18a189588dc 272 writeReg(MAX17055_MODELCFG_REG, 0x8400); //Why 0x8400
fneirab 5:a18a189588dc 273 } else {
fneirab 5:a18a189588dc 274 dpacc = (pri.designcap >> 5) * 0xAC6A / pri.designcap;
fneirab 5:a18a189588dc 275 writeReg(MAX17055_DPACC_REG, dpacc);
fneirab 5:a18a189588dc 276 writeReg(MAX17055_MODELCFG_REG, 0x8000);
fneirab 5:a18a189588dc 277 }
fneirab 5:a18a189588dc 278
fneirab 5:a18a189588dc 279 /* Poll ModelCFG.ModelRefresh bit for clear */
fneirab 5:a18a189588dc 280 ret = max17055_poll_flag_clear(MAX17055_MODELCFG_REG, MAX17055_MODELCFG_REFRESH, 500);
fneirab 5:a18a189588dc 281 if(ret < 0) {
fneirab 5:a18a189588dc 282 //dev_err(priv->dev, "Option1 model refresh not completed!\n");
fneirab 5:a18a189588dc 283 return ret;
fneirab 5:a18a189588dc 284 }
fneirab 5:a18a189588dc 285 break;
fneirab 5:a18a189588dc 286 }
fneirab 5:a18a189588dc 287 /* Restore original HibCfg */
fneirab 5:a18a189588dc 288 writeReg(MAX17055_HIBCFG_REG, hibcfg_value);
fneirab 5:a18a189588dc 289
fneirab 5:a18a189588dc 290 /* Optional step - alert threshold initialization */
fneirab 5:a18a189588dc 291 //max17055_set_alert_thresholds(priv);
fneirab 5:a18a189588dc 292
fneirab 5:a18a189588dc 293 /* Clear Status.POR */
fneirab 5:a18a189588dc 294 readReg(MAX17055_STATUS_REG, reg);
fneirab 5:a18a189588dc 295 write_and_verify_reg(MAX17055_STATUS_REG, (reg & ~MAX17055_STATUS_POR));
fneirab 5:a18a189588dc 296
fneirab 2:ff7db397b70f 297 return 1;
fneirab 5:a18a189588dc 298 }
fneirab 5:a18a189588dc 299
fneirab 5:a18a189588dc 300
fneirab 5:a18a189588dc 301 ///////////////////////////////////////////////////////////////////////////////
fneirab 5:a18a189588dc 302
fneirab 5:a18a189588dc 303 /**
fneirab 5:a18a189588dc 304 * \brief Poll Flag clear
fneirab 5:a18a189588dc 305 * \par Details
fneirab 5:a18a189588dc 306 * This function clears status flags for the MAX17055
fneirab 5:a18a189588dc 307 *
fneirab 5:a18a189588dc 308 * \param[in] reg_addr - register address
fneirab 5:a18a189588dc 309 * \param[in] mask - register address
fneirab 5:a18a189588dc 310 * \param[in] timeout - register data
fneirab 5:a18a189588dc 311 *
fneirab 5:a18a189588dc 312 * \retval 1 on success
fneirab 5:a18a189588dc 313 * -1 on Failure
fneirab 5:a18a189588dc 314 */
fneirab 5:a18a189588dc 315
fneirab 5:a18a189588dc 316 int max17055_poll_flag_clear(Registers_e reg_addr, int mask, int timeout)
fneirab 5:a18a189588dc 317 {
fneirab 5:a18a189588dc 318 uint16_t data;
fneirab 5:a18a189588dc 319 int ret;
fneirab 5:a18a189588dc 320
fneirab 5:a18a189588dc 321 do {
fneirab 5:a18a189588dc 322 wait(50);
fneirab 5:a18a189588dc 323 ret = readReg(red_addr, data);
fneirab 5:a18a189588dc 324 if(ret < 0)
fneirab 5:a18a189588dc 325 return ret;
fneirab 5:a18a189588dc 326
fneirab 5:a18a189588dc 327 if(!(data & mask))
fneirab 5:a18a189588dc 328 return 1;
fneirab 5:a18a189588dc 329
fneirab 5:a18a189588dc 330 timeout -= 50;
fneirab 5:a18a189588dc 331 } while(timeout > 0);
fneirab 5:a18a189588dc 332
fneirab 5:a18a189588dc 333 return -1;
fneirab 5:a18a189588dc 334 }
fneirab 5:a18a189588dc 335
fneirab 5:a18a189588dc 336
fneirab 2:ff7db397b70f 337
fneirab 2:ff7db397b70f 338 ////////////////////////////////////////////////////////////////////////////////
fneirab 2:ff7db397b70f 339
fneirab 2:ff7db397b70f 340 /**
fneirab 3:f77a8345b0e3 341 * \brief Get Internal Temperature Function for MAX17055
fneirab 3:f77a8345b0e3 342 * \par Details
fneirab 3:f77a8345b0e3 343 * This function sends a request to access the internal
fneirab 3:f77a8345b0e3 344 * of the MAX17055
fneirab 3:f77a8345b0e3 345 *
fneirab 3:f77a8345b0e3 346 * \param[in] reg_addr - register address
fneirab 5:a18a189588dc 347 * \param[out] reg_data - the variable that contains the data to write
fneirab 3:f77a8345b0e3 348 * to the register address
fneirab 5:a18a189588dc 349 * \retval 1 on success
fneirab 5:a18a189588dc 350 *
fneirab 3:f77a8345b0e3 351 * -1 if errors exist
fneirab 3:f77a8345b0e3 352 */
fneirab 5:a18a189588dc 353
fneirab 5:a18a189588dc 354
fneirab 2:ff7db397b70f 355 int MAX17055::get_temperature(int *temp)
fneirab 2:ff7db397b70f 356 {
fneirab 5:a18a189588dc 357
fneirab 2:ff7db397b70f 358 int ret;
fneirab 2:ff7db397b70f 359 uint16_t data;
fneirab 5:a18a189588dc 360
fneirab 2:ff7db397b70f 361 ret = readReg(MAX17055_TEMP_REG, data);
fneirab 2:ff7db397b70f 362 if (ret < 0)
fneirab 2:ff7db397b70f 363 return ret;
fneirab 2:ff7db397b70f 364
fneirab 2:ff7db397b70f 365 *temp = data;
fneirab 2:ff7db397b70f 366 /* The value is signed. */
fneirab 2:ff7db397b70f 367 if (*temp & 0x8000)
fneirab 2:ff7db397b70f 368 *temp |= 0xFFFF0000;
fneirab 2:ff7db397b70f 369
fneirab 2:ff7db397b70f 370 /* The value is converted into centigrade scale */
fneirab 2:ff7db397b70f 371 /* Units of LSB = 1 / 256 degree Celsius */
fneirab 2:ff7db397b70f 372 *temp >>= 8;
fneirab 2:ff7db397b70f 373
fneirab 2:ff7db397b70f 374 return 1;
fneirab 5:a18a189588dc 375 }
fneirab 3:f77a8345b0e3 376
fneirab 3:f77a8345b0e3 377
fneirab 3:f77a8345b0e3 378 ////////////////////////////////////////////////////////////////////////////////
fneirab 3:f77a8345b0e3 379
fneirab 3:f77a8345b0e3 380 /**
fneirab 3:f77a8345b0e3 381 * \brief Forced Exit Hibernate Mode Function for MAX17055
fneirab 3:f77a8345b0e3 382 * \par Details
fneirab 5:a18a189588dc 383 * This function executes a force exit from hibernate mode.
fneirab 3:f77a8345b0e3 384 *
fneirab 3:f77a8345b0e3 385 * \retval returns HibCFG original value before forced Exit Hybernate mode
fneirab 3:f77a8345b0e3 386 *
fneirab 3:f77a8345b0e3 387 */
fneirab 5:a18a189588dc 388
fneirab 5:a18a189588dc 389
fneirab 3:f77a8345b0e3 390 uint16_t MAX17055::forcedExitHyberMode()
fneirab 3:f77a8345b0e3 391 {
fneirab 3:f77a8345b0e3 392 uint16_t hibcfg;
fneirab 5:a18a189588dc 393
fneirab 5:a18a189588dc 394 /* Force exit from hibernate */
fneirab 3:f77a8345b0e3 395
fneirab 3:f77a8345b0e3 396 //STEP 0: Store original HibCFG value
fneirab 3:f77a8345b0e3 397 readReg(MAX17055_HIBCFG_REG, hibcfg);
fneirab 3:f77a8345b0e3 398
fneirab 3:f77a8345b0e3 399 //STEP 1: Write to Soft-Wakeup Commannd Register
fneirab 3:f77a8345b0e3 400 writeReg(MAX17055_VFSOC0_QH0_LOCK_REG, 0x90); //Soft-Wakeup from hybernate
fneirab 5:a18a189588dc 401
fneirab 3:f77a8345b0e3 402 //STEP 2: Write to Hibernate Configuration register
fneirab 3:f77a8345b0e3 403 writeReg(MAX17055_HIBCFG_REG, 0x0); //disable hibernate mode
fneirab 5:a18a189588dc 404
fneirab 3:f77a8345b0e3 405 //STEP 3:Write to Soft-Wakeup Commannd Register
fneirab 3:f77a8345b0e3 406 writeReg(MAX17055_VFSOC0_QH0_LOCK_REG, 0x0); //Clear All commnads
fneirab 5:a18a189588dc 407
fneirab 3:f77a8345b0e3 408 return hibcfg;
fneirab 5:a18a189588dc 409 }