MAX11410 1.9ksps, Low-Power, Serial SPI 24-Bit, 10-Channel, Differential/Single-Ended Input, SAR ADC. More...

#include <MAX11410.h>

Public Types
enum	MAX11410_CMDOP_enum_t { CMDOP_0aaa_aaaa_WriteRegister = 0x00, CMDOP_1aaa_aaaa_ReadRegister = 0x80 }
	Command Operation Format (see function DecodeCommand) More...
enum	MAX11410_CMD_enum_t { CMD_r000_0000_xxxx_xxdd_PD = 0x00, CMD_r000_0001_xddd_xxdd_CONV_START = 0x01, CMD_r000_0010_xddd_dddd_SEQ_START = 0x02, CMD_r000_0011_xxxx_xddd_CAL_START = 0x03, CMD_r000_0100_dddd_xddd_GP0_CTRL = 0x04, CMD_r000_0101_dddd_xddd_GP1_CTRL = 0x05, CMD_r000_0110_xddd_xxdd_GP_CONV = 0x06, CMD_r000_0111_xddd_dddd_GP_SEQ_ADDR = 0x07, CMD_r000_1000_x0dd_dddd_FILTER = 0x08, CMD_r000_1001_dddd_dddd_CTRL = 0x09, CMD_r000_1010_dddd_dddd_SOURCE = 0x0a, CMD_r000_1011_dddd_dddd_MUX_CTRL0 = 0x0b, CMD_r000_1100_dddd_dddd_MUX_CTRL1 = 0x0c, CMD_r000_1101_dddd_dddd_MUX_CTRL2 = 0x0d, CMD_r000_1110_00ss_0ggg_PGA = 0x0e, CMD_r000_1111_dddd_dddd_WAIT_EXT = 0x0f, CMD_r001_0000_xxxx_xxxx_WAIT_START = 0x10, CMD_r001_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xddd_PART_ID = 0x11, CMD_r001_0010_xxxx_xxxx_dddd_xxdd_dddd_dddd_SYSC_SEL = 0x12, CMD_r001_0011_dddd_dddd_dddd_dddd_dddd_dddd_SYS_OFF_A = 0x13, CMD_r001_0100_dddd_dddd_dddd_dddd_dddd_dddd_SYS_OFF_B = 0x14, CMD_r001_0101_dddd_dddd_dddd_dddd_dddd_dddd_SYS_GAIN_A = 0x15, CMD_r001_0110_dddd_dddd_dddd_dddd_dddd_dddd_SYS_GAIN_B = 0x16, CMD_r001_0111_dddd_dddd_dddd_dddd_dddd_dddd_SELF_OFF = 0x17, CMD_r001_1000_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_1 = 0x18, CMD_r001_1001_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_2 = 0x19, CMD_r001_1010_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_4 = 0x1a, CMD_r001_1011_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_8 = 0x1b, CMD_r001_1100_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_16 = 0x1c, CMD_r001_1101_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_32 = 0x1d, CMD_r001_1110_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_64 = 0x1e, CMD_r001_1111_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_128 = 0x1f, CMD_r010_0000_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH0 = 0x20, CMD_r010_0001_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH1 = 0x21, CMD_r010_0010_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH2 = 0x22, CMD_r010_0011_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH3 = 0x23, CMD_r010_0100_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH4 = 0x24, CMD_r010_0101_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH5 = 0x25, CMD_r010_0110_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH6 = 0x26, CMD_r010_0111_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH7 = 0x27, CMD_r010_1000_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH0 = 0x28, CMD_r010_1001_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH1 = 0x29, CMD_r010_1010_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH2 = 0x2a, CMD_r010_1011_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH3 = 0x2b, CMD_r010_1100_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH4 = 0x2c, CMD_r010_1101_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH5 = 0x2d, CMD_r010_1110_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH6 = 0x2e, CMD_r010_1111_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH7 = 0x2f, CMD_r011_0000_dddd_dddd_dddd_dddd_dddd_dddd_DATA0 = 0x30, CMD_r011_0001_dddd_dddd_dddd_dddd_dddd_dddd_DATA1 = 0x31, CMD_r011_0010_dddd_dddd_dddd_dddd_dddd_dddd_DATA2 = 0x32, CMD_r011_0011_dddd_dddd_dddd_dddd_dddd_dddd_DATA3 = 0x33, CMD_r011_0100_dddd_dddd_dddd_dddd_dddd_dddd_DATA4 = 0x34, CMD_r011_0101_dddd_dddd_dddd_dddd_dddd_dddd_DATA5 = 0x35, CMD_r011_0110_dddd_dddd_dddd_dddd_dddd_dddd_DATA6 = 0x36, CMD_r011_0111_dddd_dddd_dddd_dddd_dddd_dddd_DATA7 = 0x37, CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS = 0x38, CMD_r011_1001_dddd_dddd_dddd_dddd_dxxd_dddd_STATUS_IE = 0x39, CMD_r011_1010_xaaa_aaaa_dddd_dddd_UC_0 = 0x3a, CMD_r011_1011_xaaa_aaaa_dddd_dddd_UC_1 = 0x3b, CMD_r011_1100_xaaa_aaaa_dddd_dddd_UC_2 = 0x3c, CMD_r011_1101_xaaa_aaaa_dddd_dddd_UC_3 = 0x3d, CMD_r011_1110_xaaa_aaaa_dddd_dddd_UC_4 = 0x3e, CMD_r011_1111_xaaa_aaaa_dddd_dddd_UC_5 = 0x3f, CMD_r100_0000_xaaa_aaaa_dddd_dddd_UC_6 = 0x40, CMD_r100_0001_xaaa_aaaa_dddd_dddd_UC_7 = 0x41, CMD_r100_0010_xaaa_aaaa_dddd_dddd_UC_8 = 0x42, CMD_r100_0011_xaaa_aaaa_dddd_dddd_UC_9 = 0x43, CMD_r100_0100_xaaa_aaaa_dddd_dddd_UC_10 = 0x44, CMD_r100_0101_xaaa_aaaa_dddd_dddd_UC_11 = 0x45, CMD_r100_0110_xaaa_aaaa_dddd_dddd_UC_12 = 0x46, CMD_r100_0111_xaaa_aaaa_dddd_dddd_UC_13 = 0x47, CMD_r100_1000_xaaa_aaaa_dddd_dddd_UC_14 = 0x48, CMD_r100_1001_xaaa_aaaa_dddd_dddd_UC_15 = 0x49, CMD_r100_1010_xaaa_aaaa_dddd_dddd_UC_16 = 0x4a, CMD_r100_1011_xaaa_aaaa_dddd_dddd_UC_17 = 0x4b, CMD_r100_1100_xaaa_aaaa_dddd_dddd_UC_18 = 0x4c, CMD_r100_1101_xaaa_aaaa_dddd_dddd_UC_19 = 0x4d, CMD_r100_1110_xaaa_aaaa_dddd_dddd_UC_20 = 0x4e, CMD_r100_1111_xaaa_aaaa_dddd_dddd_UC_21 = 0x4f, CMD_r101_0000_xaaa_aaaa_dddd_dddd_UC_22 = 0x50, CMD_r101_0001_xaaa_aaaa_dddd_dddd_UC_23 = 0x51, CMD_r101_0010_xaaa_aaaa_dddd_dddd_UC_24 = 0x52, CMD_r101_0011_xaaa_aaaa_dddd_dddd_UC_25 = 0x53, CMD_r101_0100_xaaa_aaaa_dddd_dddd_UC_26 = 0x54, CMD_r101_0101_xaaa_aaaa_dddd_dddd_UC_27 = 0x55, CMD_r101_0110_xaaa_aaaa_dddd_dddd_UC_28 = 0x56, CMD_r101_0111_xaaa_aaaa_dddd_dddd_UC_29 = 0x57, CMD_r101_1000_xaaa_aaaa_dddd_dddd_UC_30 = 0x58, CMD_r101_1001_xaaa_aaaa_dddd_dddd_UC_31 = 0x59, CMD_r101_1010_xaaa_aaaa_dddd_dddd_UC_32 = 0x5a, CMD_r101_1011_xaaa_aaaa_dddd_dddd_UC_33 = 0x5b, CMD_r101_1100_xaaa_aaaa_dddd_dddd_UC_34 = 0x5c, CMD_r101_1101_xaaa_aaaa_dddd_dddd_UC_35 = 0x5d, CMD_r101_1110_xaaa_aaaa_dddd_dddd_UC_36 = 0x5e, CMD_r101_1111_xaaa_aaaa_dddd_dddd_UC_37 = 0x5f, CMD_r110_0000_xaaa_aaaa_dddd_dddd_UC_38 = 0x60, CMD_r110_0001_xaaa_aaaa_dddd_dddd_UC_39 = 0x61, CMD_r110_0010_xaaa_aaaa_dddd_dddd_UC_40 = 0x62, CMD_r110_0011_xaaa_aaaa_dddd_dddd_UC_41 = 0x63, CMD_r110_0100_xaaa_aaaa_dddd_dddd_UC_42 = 0x64, CMD_r110_0101_xaaa_aaaa_dddd_dddd_UC_43 = 0x65, CMD_r110_0110_xaaa_aaaa_dddd_dddd_UC_44 = 0x66, CMD_r110_0111_xaaa_aaaa_dddd_dddd_UC_45 = 0x67, CMD_r110_1000_xaaa_aaaa_dddd_dddd_UC_46 = 0x68, CMD_r110_1001_xaaa_aaaa_dddd_dddd_UC_47 = 0x69, CMD_r110_1010_xaaa_aaaa_dddd_dddd_UC_48 = 0x6a, CMD_r110_1011_xaaa_aaaa_dddd_dddd_UC_49 = 0x6b, CMD_r110_1100_xaaa_aaaa_dddd_dddd_UC_50 = 0x6c, CMD_r110_1101_xaaa_aaaa_dddd_dddd_UC_51 = 0x6d, CMD_r110_1110_xaaa_aaaa_dddd_dddd_UC_52 = 0x6e, CMD_r110_1111_xxxx_xxxx_xaaa_aaaa_UCADDR = 0x6f }
	Register Addresses. More...
enum	MAX11410_SEQ_ADDR_enum_t { SEQ_ADDR_r011_1010_xaaa_aaaa_dddd_dddd_UC_0 = 0x3a, SEQ_ADDR_r011_1011_xaaa_aaaa_dddd_dddd_UC_1 = 0x3b, SEQ_ADDR_r011_1100_xaaa_aaaa_dddd_dddd_UC_2 = 0x3c, SEQ_ADDR_r011_1101_xaaa_aaaa_dddd_dddd_UC_3 = 0x3d, SEQ_ADDR_r011_1110_xaaa_aaaa_dddd_dddd_UC_4 = 0x3e, SEQ_ADDR_r011_1111_xaaa_aaaa_dddd_dddd_UC_5 = 0x3f, SEQ_ADDR_r100_0000_xaaa_aaaa_dddd_dddd_UC_6 = 0x40, SEQ_ADDR_r100_0001_xaaa_aaaa_dddd_dddd_UC_7 = 0x41, SEQ_ADDR_r100_0010_xaaa_aaaa_dddd_dddd_UC_8 = 0x42, SEQ_ADDR_r100_0011_xaaa_aaaa_dddd_dddd_UC_9 = 0x43, SEQ_ADDR_r100_0100_xaaa_aaaa_dddd_dddd_UC_10 = 0x44, SEQ_ADDR_r100_0101_xaaa_aaaa_dddd_dddd_UC_11 = 0x45, SEQ_ADDR_r100_0110_xaaa_aaaa_dddd_dddd_UC_12 = 0x46, SEQ_ADDR_r100_0111_xaaa_aaaa_dddd_dddd_UC_13 = 0x47, SEQ_ADDR_r100_1000_xaaa_aaaa_dddd_dddd_UC_14 = 0x48, SEQ_ADDR_r100_1001_xaaa_aaaa_dddd_dddd_UC_15 = 0x49, SEQ_ADDR_r100_1010_xaaa_aaaa_dddd_dddd_UC_16 = 0x4a, SEQ_ADDR_r100_1011_xaaa_aaaa_dddd_dddd_UC_17 = 0x4b, SEQ_ADDR_r100_1100_xaaa_aaaa_dddd_dddd_UC_18 = 0x4c, SEQ_ADDR_r100_1101_xaaa_aaaa_dddd_dddd_UC_19 = 0x4d, SEQ_ADDR_r100_1110_xaaa_aaaa_dddd_dddd_UC_20 = 0x4e, SEQ_ADDR_r100_1111_xaaa_aaaa_dddd_dddd_UC_21 = 0x4f, SEQ_ADDR_r101_0000_xaaa_aaaa_dddd_dddd_UC_22 = 0x50, SEQ_ADDR_r101_0001_xaaa_aaaa_dddd_dddd_UC_23 = 0x51, SEQ_ADDR_r101_0010_xaaa_aaaa_dddd_dddd_UC_24 = 0x52, SEQ_ADDR_r101_0011_xaaa_aaaa_dddd_dddd_UC_25 = 0x53, SEQ_ADDR_r101_0100_xaaa_aaaa_dddd_dddd_UC_26 = 0x54, SEQ_ADDR_r101_0101_xaaa_aaaa_dddd_dddd_UC_27 = 0x55, SEQ_ADDR_r101_0110_xaaa_aaaa_dddd_dddd_UC_28 = 0x56, SEQ_ADDR_r101_0111_xaaa_aaaa_dddd_dddd_UC_29 = 0x57, SEQ_ADDR_r101_1000_xaaa_aaaa_dddd_dddd_UC_30 = 0x58, SEQ_ADDR_r101_1001_xaaa_aaaa_dddd_dddd_UC_31 = 0x59, SEQ_ADDR_r101_1010_xaaa_aaaa_dddd_dddd_UC_32 = 0x5a, SEQ_ADDR_r101_1011_xaaa_aaaa_dddd_dddd_UC_33 = 0x5b, SEQ_ADDR_r101_1100_xaaa_aaaa_dddd_dddd_UC_34 = 0x5c, SEQ_ADDR_r101_1101_xaaa_aaaa_dddd_dddd_UC_35 = 0x5d, SEQ_ADDR_r101_1110_xaaa_aaaa_dddd_dddd_UC_36 = 0x5e, SEQ_ADDR_r101_1111_xaaa_aaaa_dddd_dddd_UC_37 = 0x5f, SEQ_ADDR_r110_0000_xaaa_aaaa_dddd_dddd_UC_38 = 0x60, SEQ_ADDR_r110_0001_xaaa_aaaa_dddd_dddd_UC_39 = 0x61, SEQ_ADDR_r110_0010_xaaa_aaaa_dddd_dddd_UC_40 = 0x62, SEQ_ADDR_r110_0011_xaaa_aaaa_dddd_dddd_UC_41 = 0x63, SEQ_ADDR_r110_0100_xaaa_aaaa_dddd_dddd_UC_42 = 0x64, SEQ_ADDR_r110_0101_xaaa_aaaa_dddd_dddd_UC_43 = 0x65, SEQ_ADDR_r110_0110_xaaa_aaaa_dddd_dddd_UC_44 = 0x66, SEQ_ADDR_r110_0111_xaaa_aaaa_dddd_dddd_UC_45 = 0x67, SEQ_ADDR_r110_1000_xaaa_aaaa_dddd_dddd_UC_46 = 0x68, SEQ_ADDR_r110_1001_xaaa_aaaa_dddd_dddd_UC_47 = 0x69, SEQ_ADDR_r110_1010_xaaa_aaaa_dddd_dddd_UC_48 = 0x6a, SEQ_ADDR_r110_1011_xaaa_aaaa_dddd_dddd_UC_49 = 0x6b, SEQ_ADDR_r110_1100_xaaa_aaaa_dddd_dddd_UC_50 = 0x6c, SEQ_ADDR_r110_1101_xaaa_aaaa_dddd_dddd_UC_51 = 0x6d, SEQ_ADDR_r110_1110_xaaa_aaaa_dddd_dddd_UC_52 = 0x6e }
	Microcode Sequencer Addresses. More...
enum	MAX11410_STATUS_enum_t { STATUS_000001_CONV_RDY = 0x00000001, STATUS_000002_SEQ_RDY = 0x00000002, STATUS_000004_CAL_RDY = 0x00000004, STATUS_000008_WAIT_DONE = 0x00000008, STATUS_000010_DATA_RDY = 0x00000010, STATUS_000020_reserved = 0x00000020, STATUS_000040_reserved = 0x00000040, STATUS_000080_SYSGOR = 0x00000080, STATUS_000100_TUR_0 = 0x00000100, STATUS_000200_TUR_1 = 0x00000200, STATUS_000400_TUR_2 = 0x00000400, STATUS_000800_TUR_3 = 0x00000800, STATUS_001000_TUR_4 = 0x00001000, STATUS_002000_TUR_5 = 0x00002000, STATUS_004000_TUR_6 = 0x00004000, STATUS_008000_TUR_7 = 0x00008000, STATUS_010000_TOR_0 = 0x00010000, STATUS_020000_TOR_1 = 0x00020000, STATUS_040000_TOR_2 = 0x00040000, STATUS_080000_TOR_3 = 0x00080000, STATUS_100000_TOR_4 = 0x00100000, STATUS_200000_TOR_5 = 0x00200000, STATUS_400000_TOR_6 = 0x00400000, STATUS_800000_TOR_7 = 0x00800000 }
	Status indicator bits CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS fields. More...
enum	MAX11410_PD_enum_t { PD_00_Normal = 0x00, PD_01_Standby = 0x01, PD_10_Sleep = 0x02, PD_11_Reset = 0x03 }
	Power-down state command CMD_r000_0000_xxxx_xxdd_PD PD[1:0] field. More...
enum	MAX11410_DEST_enum_t { DEST_000_DATA0 = 0x00, DEST_001_DATA1 = 0x01, DEST_010_DATA2 = 0x02, DEST_011_DATA3 = 0x03, DEST_100_DATA4 = 0x04, DEST_101_DATA5 = 0x05, DEST_110_DATA6 = 0x06, DEST_111_DATA7 = 0x07 }
	Conversion / seqeuncer start command CMD_r000_0001_xddd_xxdd_CONV_START DEST[2:0] field. More...
enum	MAX11410_CONV_TYPE_enum_t { CONV_TYPE_00_Single = 0x00, CONV_TYPE_01_Continuous = 0x01, CONV_TYPE_10_DutyCycle_1_4 = 0x02, CONV_TYPE_11_DutyCycle_1_4 = 0x03 }
	Conversion / seqeuncer start command CMD_r000_0001_xddd_xxdd_CONV_START CONV_TYPE[1:0] field. More...
enum	MAX11410_CAL_TYPE_enum_t { CAL_TYPE_000_SELF_CAL = 0x00, CAL_TYPE_001_PGA_GAIN = 0x01, CAL_TYPE_010_reserved = 0x02, CAL_TYPE_011_reserved = 0x03, CAL_TYPE_100_SYS_OFF_A = 0x04, CAL_TYPE_101_SYS_GAIN_A = 0x05, CAL_TYPE_110_SYS_OFF_B = 0x06, CAL_TYPE_111_SYS_GAIN_B = 0x07 }
	Calbration command CMD_r000_0011_xxxx_xddd_CAL_START CAL_TYPE[2:0] field. More...
enum	MAX11410_GP0_DIR_enum_t { GP0_DIR_00_Input = 0x00, GP0_DIR_01_reserved = 0x01, GP0_DIR_10_OutputOpenDrain = 0x02, GP0_DIR_11_Output = 0x03 }
	GPIO0 pin command CMD_r000_0100_dddd_xddd_GP0_CTRL GP0_DIR[1:0] field (bits 7:6) More...
enum	MAX11410_GP0_ISEL_enum_t { GP0_ISEL_00_disabled = 0x00, GP0_ISEL_01_TRIGGER_CONV_START = 0x01, GP0_ISEL_10_TRIGGER_SEQ_START = 0x02, GP0_ISEL_11_reserved = 0x03 }
	GPIO0 pin command CMD_r000_0100_dddd_xddd_GP0_CTRL GP0_ISEL[1:0] field (bits 5:4) More...
enum	MAX11410_GP0_OSEL_enum_t { GP0_OSEL_000_disabled = 0x00, GP0_OSEL_001_INTRB = 0x01, GP0_OSEL_010_INTR = 0x02, GP0_OSEL_011_LOGIC_0 = 0x03, GP0_OSEL_100_LOGIC_1 = 0x04, GP0_OSEL_101_AUTO_LOWSIDE_SWITCH = 0x05, GP0_OSEL_110_MODULATOR_ACTIVE_STATUS = 0x06, GP0_OSEL_111_CLOCK_2M456 = 0x07 }
	GPIO0 pin command CMD_r000_0100_dddd_xddd_GP0_CTRL GP0_OSEL[2:0] field (bits 2:0) More...
enum	MAX11410_GP1_DIR_enum_t { GP1_DIR_00_Input = 0x00, GP1_DIR_01_reserved = 0x01, GP1_DIR_10_OutputOpenDrain = 0x02, GP1_DIR_11_Output = 0x03 }
	GPIO1 pin command CMD_r000_0101_dddd_xddd_GP1_CTRL GP1_DIR[1:0] field (bits 7:6) More...
enum	MAX11410_GP1_ISEL_enum_t { GP1_ISEL_00_disabled = 0x00, GP1_ISEL_01_TRIGGER_CONV_START = 0x01, GP1_ISEL_10_TRIGGER_SEQ_START = 0x02, GP1_ISEL_11_reserved = 0x03 }
	GPIO1 pin command CMD_r000_0101_dddd_xddd_GP1_CTRL GP1_ISEL[1:0] field (bits 5:4) More...
enum	MAX11410_GP1_OSEL_enum_t { GP1_OSEL_000_disabled = 0x00, GP1_OSEL_001_INTRB = 0x01, GP1_OSEL_010_INTR = 0x02, GP1_OSEL_011_LOGIC_0 = 0x03, GP1_OSEL_100_LOGIC_1 = 0x04, GP1_OSEL_101_AUTO_LOWSIDE_SWITCH = 0x05, GP1_OSEL_110_MODULATOR_ACTIVE_STATUS = 0x06, GP1_OSEL_111_CLOCK_2M456 = 0x07 }
	GPIO1 pin command CMD_r000_0101_dddd_xddd_GP1_CTRL GP1_OSEL[2:0] field (bits 2:0) More...
enum	MAX11410_LINEF_enum_t { LINEF_00_50Hz_60Hz_FIR = 0x00, LINEF_01_50Hz_FIR = 0x01, LINEF_10_60Hz_FIR = 0x02, LINEF_11_SINC4 = 0x03 }
	Filter command CMD_r000_1000_x0dd_dddd_FILTER LINEF[1:0] field. More...
enum	MAX11410_RATE_enum_t { RATE_0000 = 0x00, RATE_0001 = 0x01, RATE_0010 = 0x02, RATE_0011 = 0x03, RATE_0100 = 0x04, RATE_0101 = 0x05, RATE_0110 = 0x06, RATE_0111 = 0x07, RATE_1000 = 0x08, RATE_1001 = 0x09, RATE_1010 = 0x0a, RATE_1011 = 0x0b, RATE_1100 = 0x0c, RATE_1101 = 0x0d, RATE_1110 = 0x0e, RATE_1111 = 0x0f }
	Filter command CMD_r000_1000_x0dd_dddd_FILTER RATE[3:0] field. More...
enum	MAX11410_REF_SEL_enum_t { REF_SEL_000_AIN0_AIN1 = 0x00, REF_SEL_001_REF1P_REF1N = 0x01, REF_SEL_010_REF2P_REF2N = 0x02, REF_SEL_011_AVDD_AGND = 0x03, REF_SEL_100_AIN0_AGND = 0x04, REF_SEL_101_REF1P_AGND = 0x05, REF_SEL_110_REF2P_AGND = 0x06, REF_SEL_111_AVDD_AGND = 0x07 }
	Filter command CMD_r000_1001_dddd_dddd_CTRL REF_SEL[2:0] field. More...
enum	MAX11410_VBIAS_MODE_enum_t { VBIAS_MODE_00_Active = 0x00, VBIAS_MODE_01_125kOhm = 0x01, VBIAS_MODE_10_20kOhm = 0x02, VBIAS_MODE_11_20kOhm = 0x03 }
	Source command CMD_r000_1010_dddd_dddd_SOURCE VBIAS_MODE[1:0] field. More...
enum	MAX11410_BRN_MODE_enum_t { BRN_MODE_00_disabled = 0x00, BRN_MODE_01_0u5A = 0x01, BRN_MODE_10_1uA = 0x02, BRN_MODE_11_10uA = 0x03 }
	Source command CMD_r000_1010_dddd_dddd_SOURCE BRN_MODE[1:0] field. More...
enum	MAX11410_IDAC_MODE_enum_t { IDAC_MODE_0000_10uA = 0x00, IDAC_MODE_0001_50uA = 0x01, IDAC_MODE_0010_75uA = 0x02, IDAC_MODE_0011_100uA = 0x03, IDAC_MODE_0100_125uA = 0x04, IDAC_MODE_0101_150uA = 0x05, IDAC_MODE_0110_175uA = 0x06, IDAC_MODE_0111_200uA = 0x07, IDAC_MODE_1000_225uA = 0x08, IDAC_MODE_1001_250uA = 0x09, IDAC_MODE_1010_300uA = 0x0a, IDAC_MODE_1011_400uA = 0x0b, IDAC_MODE_1100_600uA = 0x0c, IDAC_MODE_1101_800uA = 0x0d, IDAC_MODE_1110_1200uA = 0x0e, IDAC_MODE_1111_1600uA = 0x0f }
	Source command CMD_r000_1010_dddd_dddd_SOURCE IDAC_MODE[3:0] field. More...
enum	MAX11410_AINP_SEL_enum_t { AINP_SEL_0000_AIN0 = 0x00, AINP_SEL_0001_AIN1 = 0x01, AINP_SEL_0010_AIN2 = 0x02, AINP_SEL_0011_AIN3 = 0x03, AINP_SEL_0100_AIN4 = 0x04, AINP_SEL_0101_AIN5 = 0x05, AINP_SEL_0110_AIN6 = 0x06, AINP_SEL_0111_AIN7 = 0x07, AINP_SEL_1000_AIN8 = 0x08, AINP_SEL_1001_AIN9 = 0x09, AINP_SEL_1010_AVDD = 0x0a, AINP_SEL_1011_unconnected = 0x0b, AINP_SEL_1100_unconnected = 0x0c, AINP_SEL_1101_unconnected = 0x0d, AINP_SEL_1110_unconnected = 0x0e, AINP_SEL_1111_unconnected = 0x0f }
	Input multiplexer channel selection CMD_r000_1011_dddd_dddd_MUX_CTRL0 field AINP_SEL[3:0]. More...
enum	MAX11410_AINN_SEL_enum_t { AINN_SEL_0000_AIN0 = 0x00, AINN_SEL_0001_AIN1 = 0x01, AINN_SEL_0010_AIN2 = 0x02, AINN_SEL_0011_AIN3 = 0x03, AINN_SEL_0100_AIN4 = 0x04, AINN_SEL_0101_AIN5 = 0x05, AINN_SEL_0110_AIN6 = 0x06, AINN_SEL_0111_AIN7 = 0x07, AINN_SEL_1000_AIN8 = 0x08, AINN_SEL_1001_AIN9 = 0x09, AINN_SEL_1010_GND = 0x0a, AINN_SEL_1011_unconnected = 0x0b, AINN_SEL_1100_unconnected = 0x0c, AINN_SEL_1101_unconnected = 0x0d, AINN_SEL_1110_unconnected = 0x0e, AINN_SEL_1111_unconnected = 0x0f }
	Input multiplexer channel selection CMD_r000_1011_dddd_dddd_MUX_CTRL0 field AINN_SEL[3:0]. More...
enum	MAX11410_IDAC1_SEL_enum_t { IDAC1_SEL_0000_AIN0 = 0x00, IDAC1_SEL_0001_AIN1 = 0x01, IDAC1_SEL_0010_AIN2 = 0x02, IDAC1_SEL_0011_AIN3 = 0x03, IDAC1_SEL_0100_AIN4 = 0x04, IDAC1_SEL_0101_AIN5 = 0x05, IDAC1_SEL_0110_AIN6 = 0x06, IDAC1_SEL_0111_AIN7 = 0x07, IDAC1_SEL_1000_AIN8 = 0x08, IDAC1_SEL_1001_AIN9 = 0x09, IDAC1_SEL_1010_unconnected = 0x0a, IDAC1_SEL_1011_unconnected = 0x0b, IDAC1_SEL_1100_unconnected = 0x0c, IDAC1_SEL_1101_unconnected = 0x0d, IDAC1_SEL_1110_unconnected = 0x0e, IDAC1_SEL_1111_unconnected = 0x0f }
	Input multiplexer channel selection CMD_r000_1100_dddd_dddd_MUX_CTRL1 field IDAC1_SEL[3:0]. More...
enum	MAX11410_IDAC0_SEL_enum_t { IDAC0_SEL_0000_AIN0 = 0x00, IDAC0_SEL_0001_AIN1 = 0x01, IDAC0_SEL_0010_AIN2 = 0x02, IDAC0_SEL_0011_AIN3 = 0x03, IDAC0_SEL_0100_AIN4 = 0x04, IDAC0_SEL_0101_AIN5 = 0x05, IDAC0_SEL_0110_AIN6 = 0x06, IDAC0_SEL_0111_AIN7 = 0x07, IDAC0_SEL_1000_AIN8 = 0x08, IDAC0_SEL_1001_AIN9 = 0x09, IDAC0_SEL_1010_unconnected = 0x0a, IDAC0_SEL_1011_unconnected = 0x0b, IDAC0_SEL_1100_unconnected = 0x0c, IDAC0_SEL_1101_unconnected = 0x0d, IDAC0_SEL_1110_unconnected = 0x0e, IDAC0_SEL_1111_unconnected = 0x0f }
	Input multiplexer channel selection CMD_r000_1100_dddd_dddd_MUX_CTRL1 field IDAC0_SEL[3:0]. More...
enum	MAX11410_SIG_PATH_enum_t { SIG_PATH_00_BUFFERED = 0x00, SIG_PATH_01_BYPASS = 0x01, SIG_PATH_10_PGA = 0x02, SIG_PATH_11_reserved = 0x03 }
	Input multiplexer channel selection CMD_r000_1110_00ss_0ggg_PGA field SIG_PATH[1:0]. More...
enum	MAX11410_GAIN_enum_t { GAIN_000_1 = 0x00, GAIN_001_2 = 0x01, GAIN_010_4 = 0x02, GAIN_011_8 = 0x03, GAIN_100_16 = 0x04, GAIN_101_32 = 0x05, GAIN_110_64 = 0x06, GAIN_111_128 = 0x07 }
	Input multiplexer channel selection CMD_r000_1110_00ss_0ggg_PGA field GAIN[2:0]. More...
enum	MAX11410_ic_t
	IC's supported with this driver. More...
typedef enum MAX11410::MAX11410_CMDOP_enum_t	MAX11410_CMDOP_enum_t
	Command Operation Format (see function DecodeCommand)
typedef enum MAX11410::MAX11410_CMD_enum_t	MAX11410_CMD_enum_t
	Register Addresses.
typedef enum MAX11410::MAX11410_SEQ_ADDR_enum_t	MAX11410_SEQ_ADDR_enum_t
	Microcode Sequencer Addresses.
typedef enum MAX11410::MAX11410_STATUS_enum_t	MAX11410_STATUS_enum_t
	Status indicator bits CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS fields.
typedef enum MAX11410::MAX11410_PD_enum_t	MAX11410_PD_enum_t
	Power-down state command CMD_r000_0000_xxxx_xxdd_PD PD[1:0] field.
typedef enum MAX11410::MAX11410_DEST_enum_t	MAX11410_DEST_enum_t
	Conversion / seqeuncer start command CMD_r000_0001_xddd_xxdd_CONV_START DEST[2:0] field.
typedef enum MAX11410::MAX11410_CONV_TYPE_enum_t	MAX11410_CONV_TYPE_enum_t
	Conversion / seqeuncer start command CMD_r000_0001_xddd_xxdd_CONV_START CONV_TYPE[1:0] field.
typedef enum MAX11410::MAX11410_CAL_TYPE_enum_t	MAX11410_CAL_TYPE_enum_t
	Calbration command CMD_r000_0011_xxxx_xddd_CAL_START CAL_TYPE[2:0] field.
typedef enum MAX11410::MAX11410_GP0_DIR_enum_t	MAX11410_GP0_DIR_enum_t
	GPIO0 pin command CMD_r000_0100_dddd_xddd_GP0_CTRL GP0_DIR[1:0] field (bits 7:6)
typedef enum MAX11410::MAX11410_GP0_ISEL_enum_t	MAX11410_GP0_ISEL_enum_t
	GPIO0 pin command CMD_r000_0100_dddd_xddd_GP0_CTRL GP0_ISEL[1:0] field (bits 5:4)
typedef enum MAX11410::MAX11410_GP0_OSEL_enum_t	MAX11410_GP0_OSEL_enum_t
	GPIO0 pin command CMD_r000_0100_dddd_xddd_GP0_CTRL GP0_OSEL[2:0] field (bits 2:0)
typedef enum MAX11410::MAX11410_GP1_DIR_enum_t	MAX11410_GP1_DIR_enum_t
	GPIO1 pin command CMD_r000_0101_dddd_xddd_GP1_CTRL GP1_DIR[1:0] field (bits 7:6)
typedef enum MAX11410::MAX11410_GP1_ISEL_enum_t	MAX11410_GP1_ISEL_enum_t
	GPIO1 pin command CMD_r000_0101_dddd_xddd_GP1_CTRL GP1_ISEL[1:0] field (bits 5:4)
typedef enum MAX11410::MAX11410_GP1_OSEL_enum_t	MAX11410_GP1_OSEL_enum_t
	GPIO1 pin command CMD_r000_0101_dddd_xddd_GP1_CTRL GP1_OSEL[2:0] field (bits 2:0)
typedef enum MAX11410::MAX11410_LINEF_enum_t	MAX11410_LINEF_enum_t
	Filter command CMD_r000_1000_x0dd_dddd_FILTER LINEF[1:0] field.
typedef enum MAX11410::MAX11410_RATE_enum_t	MAX11410_RATE_enum_t
	Filter command CMD_r000_1000_x0dd_dddd_FILTER RATE[3:0] field.
typedef enum MAX11410::MAX11410_REF_SEL_enum_t	MAX11410_REF_SEL_enum_t
	Filter command CMD_r000_1001_dddd_dddd_CTRL REF_SEL[2:0] field.
typedef enum MAX11410::MAX11410_VBIAS_MODE_enum_t	MAX11410_VBIAS_MODE_enum_t
	Source command CMD_r000_1010_dddd_dddd_SOURCE VBIAS_MODE[1:0] field.
typedef enum MAX11410::MAX11410_BRN_MODE_enum_t	MAX11410_BRN_MODE_enum_t
	Source command CMD_r000_1010_dddd_dddd_SOURCE BRN_MODE[1:0] field.
typedef enum MAX11410::MAX11410_IDAC_MODE_enum_t	MAX11410_IDAC_MODE_enum_t
	Source command CMD_r000_1010_dddd_dddd_SOURCE IDAC_MODE[3:0] field.
typedef enum MAX11410::MAX11410_AINP_SEL_enum_t	MAX11410_AINP_SEL_enum_t
	Input multiplexer channel selection CMD_r000_1011_dddd_dddd_MUX_CTRL0 field AINP_SEL[3:0].
typedef enum MAX11410::MAX11410_AINN_SEL_enum_t	MAX11410_AINN_SEL_enum_t
	Input multiplexer channel selection CMD_r000_1011_dddd_dddd_MUX_CTRL0 field AINN_SEL[3:0].
typedef enum MAX11410::MAX11410_IDAC1_SEL_enum_t	MAX11410_IDAC1_SEL_enum_t
	Input multiplexer channel selection CMD_r000_1100_dddd_dddd_MUX_CTRL1 field IDAC1_SEL[3:0].
typedef enum MAX11410::MAX11410_IDAC0_SEL_enum_t	MAX11410_IDAC0_SEL_enum_t
	Input multiplexer channel selection CMD_r000_1100_dddd_dddd_MUX_CTRL1 field IDAC0_SEL[3:0].
typedef enum MAX11410::MAX11410_SIG_PATH_enum_t	MAX11410_SIG_PATH_enum_t
	Input multiplexer channel selection CMD_r000_1110_00ss_0ggg_PGA field SIG_PATH[1:0].
typedef enum MAX11410::MAX11410_GAIN_enum_t	MAX11410_GAIN_enum_t
	Input multiplexer channel selection CMD_r000_1110_00ss_0ggg_PGA field GAIN[2:0].
Public Member Functions
	MAX11410 (SPI &spi, DigitalOut &cs_pin, MAX11410_ic_t ic_variant)
	Constructor for MAX11410 Class.
void	spi_frequency (int spi_sclk_Hz)
	set SPI SCLK frequency
int	get_spi_frequency () const
	get SPI SCLK frequency
int	get_spi_dataMode () const
	get SPI mode
uint8_t	Init (void)
	Menu item '!' Initialize device.
double	VoltageOfCode_Unipolar (uint32_t value_u24)
	Return the physical voltage corresponding to conversion result, for unipolar mode.
double	VoltageOfCode_Bipolar_OffsetBinary (uint32_t value_u24)
	Return the physical voltage corresponding to conversion result, when conversion format is Bipolar mode, offset binary.
double	VoltageOfCode_Bipolar_2sComplement (uint32_t value_u24)
	Return the physical voltage corresponding to conversion result, when conversion format is Bipolar mode, 2's complement.
double	VoltageOfCode (uint32_t value_u24)
	Return the physical voltage corresponding to conversion result, when conversion format is determined by the CTRL register.
uint8_t	RegWrite (MAX11410_CMD_enum_t commandByte, uint32_t regData)
	Write a MAX11410 register.
uint8_t	RegRead (MAX11410_CMD_enum_t commandByte, uint32_t *ptrRegData)
	Read an 8-bit MAX11410 register.
uint8_t	RegSize (MAX11410_CMD_enum_t commandByte)
	Return the size of a MAX11410 register.
MAX11410::MAX11410_CMDOP_enum_t	DecodeCommand (MAX11410_CMD_enum_t commandByte)
	Decode operation from commandByte.
uint8_t	RegAddrOfCommand (MAX11410_CMD_enum_t commandByte)
	Return the address field of a MAX11410 register.
uint8_t	IsRegReadCommand (MAX11410_CMD_enum_t commandByte)
	Test whether a command byte is a register read command.
uint8_t	IsRegWriteCommand (MAX11410_CMD_enum_t commandByte)
	Test whether a command byte is a register write command.
const char *	RegName (MAX11410_CMD_enum_t commandByte)
	Return the name of a MAX11410 register.
uint8_t	Configure_FILTER (uint8_t linef, uint8_t rate)
	Menu item 'XF'.
uint8_t	Configure_PGA (uint8_t sigpath, uint8_t gain)
	Menu item 'XP'.
uint8_t	Configure_CTRL (uint8_t extclk, uint8_t u_bn, uint8_t format, uint8_t refbufp_en, uint8_t refbufn_en, uint8_t ref_sel)
	Menu item 'XC'.
uint8_t	Configure_CTRL_REF (uint8_t ref_sel)
	Menu item 'XR'.
uint8_t	Configure_SOURCE (uint8_t vbias_mode, uint8_t brn_mode, uint8_t idac_mode)
	Menu item 'XS'.
uint8_t	Configure_MUX_CTRL0 (uint8_t ainp, uint8_t ainn)
	Menu item 'XM'.
uint8_t	Configure_MUX_CTRL1 (uint8_t idac1_sel, uint8_t idac0_sel)
	Menu item 'XI'.
uint8_t	Configure_MUX_CTRL2 (uint8_t vbias_ain7_ain0_bitmap)
	Menu item 'XV'.
uint8_t	Calibrate_Self_Offset_Gain (void)
	Menu item 'X0'.
uint8_t	Calibrate_PGA_Gain (void)
	Menu item 'X1'.
uint8_t	Calibrate_System_Offset_A (void)
	CAL_START Calibrate System Offset A.
uint8_t	Calibrate_System_Gain_A (void)
	CAL_START Calibrate System Gain A.
uint8_t	Calibrate_System_Offset_B (void)
	CAL_START Calibrate System Offset B.
uint8_t	Calibrate_System_Gain_B (void)
	CAL_START Calibrate System Gain B.
uint8_t	Read_All_Voltages (void)
	Menu item '$' -> AINcode[0], AINcode[1], AINcode[2], AINcode[3], AINcode[4], AINcode[5], AINcode[6], AINcode[7], AINcode[8], AINcode[9], AINcode[10].
double	Measure_Voltage (MAX11410_AINP_SEL_enum_t ainp, MAX11410_AINN_SEL_enum_t ainn)
	Menu item 'V' Trigger Measurement for voltage input.
double	Measure_RTD (MAX11410_AINP_SEL_enum_t rtd_iout, MAX11410_AINP_SEL_enum_t rtd_ainp, MAX11410_AINN_SEL_enum_t rtd_ainn)
	Menu item 'R' -> rtd_ohm, rtd_degc Trigger Measurement for Resistive Temperature Device (RTD).
double	TemperatureOfRTD_PT1000 (double rtd_ohm)
	Return the physical temperature corresponding to measured resistance of a PT1000 type Resistive Temperature Device (RTD).
double	TemperatureOfRTD_PT100 (double rtd_ohm)
	Return the physical temperature corresponding to measured resistance of a PT100 type Resistive Temperature Device (RTD).
double	TemperatureOfRTD (double rtd_ohm)
	Return the physical temperature corresponding to measured resistance of a PT100 or PT1000 type Resistive Temperature Device (RTD).
double	Measure_Thermocouple (MAX11410_AINP_SEL_enum_t tc_ainp, MAX11410_AINN_SEL_enum_t tc_ainn, MAX11410_AINP_SEL_enum_t rtd_iout, MAX11410_AINP_SEL_enum_t rtd_ainp, MAX11410_AINN_SEL_enum_t rtd_ainn)
	Menu item 'TM' -> tc_v, tc_delta_degc, tc_degc Trigger Measurement for Thermocouple.
double	TemperatureOfTC_TypeK (double tc_v)
	Return the physical temperature corresponding to measured voltage of a type K Thermocouple (TC).
double	temperatureDegC_polynomial (double thermocouple_voltage_uV, int num_coefficients, double coefficients[])
	Calculate temperature in degrees C from input voltage, using a given set of polynomial coefficients.
Data Fields
Callback< void(size_t, uint8_t , uint8_t )	onSPIprint )
	Function pointer void f(size_t byteCount, uint8_t mosiData[], uint8_t misoData[])
double	ref0_v
	AIN0-AIN1 reference voltage, in Volts.
double	ref1_v
	REF1P-REF1N reference voltage, in Volts.
double	ref2_v
	REF2P-REF2N reference voltage, in Volts.
double	avdd_v
	AVDD-AGND reference voltage, in Volts.
uint32_t	ctrl
	shadow of register ctrl CMD_r000_1001_dddd_dddd_CTRL
uint8_t	pgaGain
	read-only pga gain 1, 2, 4, 8, 16, 32, 64, or 128 set by Configure_PGA gain index register pga CMD_r000_1110_00ss_0ggg_PGA
uint32_t	status
	shadow of read-only register status CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS
uint32_t	data0
	shadow of read-only register data0 CMD_r011_0000_dddd_dddd_dddd_dddd_dddd_dddd_DATA0
uint32_t	AINcode [11]
	Each channel's most recent value in LSBs.
int	loop_limit
	When driver polls status of a pin signal or a register status bit, and there is no device physically connected, the driver must be able to halt and report failure if too many tries.
MAX11410::MAX11410_CMD_enum_t *	readAllStatusList
	read-only constant list of registers to be read by menu item * with no arguments
uint8_t	readAllStatusListLen
	read-only constant number of registers to be read by menu item * with no arguments
int	rtd_ms
	timing delay after enable RTD bias current in Measure_RTD()
double	rtd_ohm
	RTD Resistance measurement; Thermocouple Cold Junction, in Ohms.
double	rtd_degc
	Temperature calculated from RTD Resistance; Thermocouple Cold Junction, in degrees C.
uint8_t	rtd_filter
	filter register configuration in Measure_RTD()
uint8_t	rtd_ctrl
	ctrl register configuration in Measure_RTD()
uint8_t	rtd_source
	source register configuration in Measure_RTD()
uint8_t	rtd_pga
	pga register configuration in Measure_RTD()
uint8_t	v_filter
	filter register configuration in Measure_Voltage()
uint8_t	v_ctrl
	ctrl register configuration in Measure_Voltage()
uint8_t	v_pga
	pga register configuration in Measure_Voltage()
double	tc_v
	Thermocouple voltage measurement, in Volts.
double	tc_delta_degc
	Temperature calculated from Thermocouple voltage, in degrees C.
double	tc_degc
	Temperature calculated from Thermocouple voltage, in degrees C.

Detailed Description

MAX11410 1.9ksps, Low-Power, Serial SPI 24-Bit, 10-Channel, Differential/Single-Ended Input, SAR ADC.

Datasheet: https://www.maximintegrated.com/MAX11410

//---------- CODE GENERATOR: helloCppCodeList

 // CODE GENERATOR: example code includes

 // example code includes
 // standard include for target platform -- Platform_Include_Boilerplate
 #include "mbed.h"
 // Platforms:
 //   - MAX32625MBED
 //      - supports mbed-os-5.11, requires USBDevice library
 //      - add https://developer.mbed.org/teams/MaximIntegrated/code/USBDevice/
 //      - remove max32630fthr library (if present)
 //      - remove MAX32620FTHR library (if present)
 //   - MAX32600MBED
 //      - remove max32630fthr library (if present)
 //      - remove MAX32620FTHR library (if present)
 //      - Windows 10 note:  Don't connect HDK until you are ready to load new firmware into the board.
 //   - NUCLEO_F446RE
 //      - remove USBDevice library
 //      - remove max32630fthr library (if present)
 //      - remove MAX32620FTHR library (if present)
 //   - NUCLEO_F401RE
 //      - remove USBDevice library
 //      - remove max32630fthr library (if present)
 //      - remove MAX32620FTHR library (if present)
 //   - MAX32630FTHR
 //      - #include "max32630fthr.h"
 //      - add http://os.mbed.org/teams/MaximIntegrated/code/max32630fthr/
 //      - remove MAX32620FTHR library (if present)
 //   - MAX32620FTHR
 //      - #include "MAX32620FTHR.h"
 //      - remove max32630fthr library (if present)
 //      - add https://os.mbed.com/teams/MaximIntegrated/code/MAX32620FTHR/
 //      - not tested yet
 //   - MAX32625PICO
 //      - #include "max32625pico.h"
 //      - add https://os.mbed.com/users/switches/code/max32625pico/
 //      - remove max32630fthr library (if present)
 //      - remove MAX32620FTHR library (if present)
 //      - not tested yet
 //      - see https://os.mbed.com/users/switches/code/max32625pico/
 //      - see https://os.mbed.com/users/switches/code/PICO_board_demo/
 //      - see https://os.mbed.com/users/switches/code/PICO_USB_I2C_SPI/
 //      - see https://os.mbed.com/users/switches/code/SerialInterface/
 //      - Note: To load the MAX32625PICO firmware, hold the button while
 //        connecting the USB cable, then copy firmware bin file
 //        to the MAINTENANCE drive.
 //      - see https://os.mbed.com/platforms/MAX32625PICO/
 //      - see https://os.mbed.com/teams/MaximIntegrated/wiki/MAX32625PICO-Firmware-Updates
 //
 // end Platform_Include_Boilerplate
 #include "MAX11410.h"

 // example code board support
 //MAX32630FTHR pegasus(MAX32630FTHR::VIO_3V3);
 //DigitalOut rLED(LED1);
 //DigitalOut gLED(LED2);
 //DigitalOut bLED(LED3);
 //
 // Arduino "shield" connector port definitions (MAX32625MBED shown)
 #if defined(TARGET_MAX32625MBED)
 #define A0 AIN_0
 #define A1 AIN_1
 #define A2 AIN_2
 #define A3 AIN_3
 #define D0 P0_0
 #define D1 P0_1
 #define D2 P0_2
 #define D3 P0_3
 #define D4 P0_4
 #define D5 P0_5
 #define D6 P0_6
 #define D7 P0_7
 #define D8 P1_4
 #define D9 P1_5
 #define D10 P1_3
 #define D11 P1_1
 #define D12 P1_2
 #define D13 P1_0
 #elif defined(TARGET_MAX32625PICO)
 #warning "TARGET_MAX32625PICO not previously tested; need to define pins..."
 #define A0 AIN_1
 #define A1 AIN_2
 // #define A2 AIN_3
 // #define A3 AIN_0
 #define D0 P0_0
 #define D1 P0_1
 #define D2 P0_2
 #define D3 P0_3
 #define D4 P1_7
 #define D5 P1_6
 #define D6 P4_4
 #define D7 P4_5
 #define D8 P4_6
 #define D9 P4_7
 #define D10 P0_7
 #define D11 P0_6
 #define D12 P0_5
 #define D13 P0_4
 #endif

 // example code declare SPI interface (GPIO controlled CS)
 #if defined(TARGET_MAX32625MBED)
 SPI spi(SPI1_MOSI, SPI1_MISO, SPI1_SCK); // mosi, miso, sclk spi1 TARGET_MAX32625MBED: P1_1 P1_2 P1_0 Arduino 10-pin header D11 D12 D13
 DigitalOut spi_cs(SPI1_SS); // TARGET_MAX32625MBED: P1_3 Arduino 10-pin header D10
 #elif defined(TARGET_MAX32625PICO)
 #warning "TARGET_MAX32625PICO not previously tested; need to define pins..."
 SPI spi(SPI0_MOSI, SPI0_MISO, SPI0_SCK); // mosi, miso, sclk spi1 TARGET_MAX32625PICO: pin P0_5 P0_6 P0_4
 DigitalOut spi_cs(SPI0_SS); // TARGET_MAX32625PICO: pin P0_7
 #elif defined(TARGET_MAX32600MBED)
 SPI spi(SPI2_MOSI, SPI2_MISO, SPI2_SCK); // mosi, miso, sclk spi1 TARGET_MAX32600MBED: Arduino 10-pin header D11 D12 D13
 DigitalOut spi_cs(SPI2_SS); // Generic: Arduino 10-pin header D10
 #elif defined(TARGET_NUCLEO_F446RE) || defined(TARGET_NUCLEO_F401RE)
 // TODO1: avoid resource conflict between P5_0, P5_1, P5_2 SPI and DigitalInOut
 // void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
 //
 // TODO1: NUCLEO_F446RE SPI not working; CS and MOSI data looks OK but no SCLK clock pulses.
 SPI spi(SPI_MOSI, SPI_MISO, SPI_SCK); // mosi, miso, sclk spi1 TARGET_NUCLEO_F446RE: Arduino 10-pin header D11 D12 D13
 DigitalOut spi_cs(SPI_CS); // TARGET_NUCLEO_F446RE: PB_6 Arduino 10-pin header D10
 //
 #else
 SPI spi(D11, D12, D13); // mosi, miso, sclk spi1 TARGET_MAX32600MBED: Arduino 10-pin header D11 D12 D13
 DigitalOut spi_cs(D10); // Generic: Arduino 10-pin header D10
 #endif

 // example code declare GPIO interface pins
 // example code declare device instance
 MAX11410 g_MAX11410_device(spi, spi_cs, MAX11410::MAX11410_IC);

 // CODE GENERATOR: example code for ADC: serial port declaration
 //--------------------------------------------------
 // Declare the Serial driver
 // default baud rate settings are 9600 8N1
 // install device driver from http://developer.mbed.org/media/downloads/drivers/mbedWinSerial_16466.exe
 // see docs https://docs.mbed.com/docs/mbed-os-handbook/en/5.5/getting_started/what_need/
 #if defined(TARGET_MAX32630)
     #include "USBSerial.h"
 // Hardware serial port over DAPLink
 // The default baud rate for the DapLink UART is 9600
 //Serial DAPLINKserial(P2_1, P2_0);     // tx, rx
 //    #define HAS_DAPLINK_SERIAL 1
 // Virtual serial port over USB
 // The baud rate does not affect the virtual USBSerial UART.
 USBSerial serial;
 //--------------------------------------------------
 #elif defined(TARGET_MAX32625MBED)
     #include "USBSerial.h"
 // Hardware serial port over DAPLink
 // The default baud rate for the DapLink UART is 9600
 //Serial DAPLINKserial(P2_1, P2_0);     // tx, rx
 //    #define HAS_DAPLINK_SERIAL 1
 // Virtual serial port over USB
 // The baud rate does not affect the virtual USBSerial UART.
 USBSerial serial;
 //--------------------------------------------------
 #elif defined(TARGET_MAX32600)
     #include "USBSerial.h"
 // Hardware serial port over DAPLink
 // The default baud rate for the DapLink UART is 9600
 Serial DAPLINKserial(P1_1, P1_0);     // tx, rx
     #define HAS_DAPLINK_SERIAL 1
 // Virtual serial port over USB
 // The baud rate does not affect the virtual USBSerial UART.
 USBSerial serial;
 //--------------------------------------------------
 #elif defined(TARGET_NUCLEO_F446RE) || defined(TARGET_NUCLEO_F401RE)
 Serial serial(SERIAL_TX, SERIAL_RX);     // tx, rx
 //--------------------------------------------------
 #else
 #if defined(SERIAL_TX)
 #warning "target not previously tested; guess serial pins are SERIAL_TX, SERIAL_RX..."
 Serial serial(SERIAL_TX, SERIAL_RX);     // tx, rx
 #elif defined(USBTX)
 #warning "target not previously tested; guess serial pins are USBTX, USBRX..."
 Serial serial(USBTX, USBRX);     // tx, rx
 #elif defined(UART_TX)
 #warning "target not previously tested; guess serial pins are UART_TX, UART_RX..."
 Serial serial(UART_TX, UART_RX);     // tx, rx
 #else
 #warning "target not previously tested; need to define serial pins..."
 #endif
 #endif
 //
 #include "CmdLine.h"
 CmdLine cmdLine(serial, "serial");

 // example code main function
 int main()
 {
     // setup: put your setup code here, to run once

     // example code: serial port banner message
     wait(3); // 3000ms timing delay function, platform-specific
     cmdLine.serial().printf("\r\nHello_MAX11410\r\n");

     // CODE GENERATOR: example code: member function Init
     // Initialize MAX11410 and verify device ID
     uint32_t g_SPI_SCLK_Hz = 24000000; // platform limit 24MHz intSPI_SCLK_Platform_Max_MHz * 1000000
     if (g_MAX11410_device.Init() == 0)
     {  // init failed; try "safe mode" SPI at slower SCLK rate
         cmdLine.serial().printf("\r\nMAX11410 Init failed; retry at SPI SCLK frequency 2000000 Hz\r\n");

         g_SPI_SCLK_Hz = 2000000;
         g_MAX11410_device.spi_frequency(2000000);
         g_MAX11410_device.Init();
     }
     // CODE GENERATOR: get spi properties from device
     if (g_SPI_SCLK_Hz > g_MAX11410_device.get_spi_frequency())
     {  // Device limits SPI SCLK frequency
         g_SPI_SCLK_Hz = g_MAX11410_device.get_spi_frequency();
         cmdLine.serial().printf("\r\nMAX11410 limits SPI SCLK frequency to %ld Hz\r\n", g_SPI_SCLK_Hz);

         g_MAX11410_device.Init();
     }
     if (g_MAX11410_device.get_spi_frequency() > g_SPI_SCLK_Hz)
     {  // Platform limits SPI SCLK frequency
         g_MAX11410_device.spi_frequency(g_SPI_SCLK_Hz);
         cmdLine.serial().printf("\r\nPlatform limits MAX11410 SPI SCLK frequency to %ld Hz\r\n", g_SPI_SCLK_Hz);

         g_MAX11410_device.Init();
     }
     // g_SPI_dataMode = g_MAX11410_device.get_spi_dataMode();
     while (g_MAX11410_device.Init() == 0)
     {
         wait(3); // 3000ms timing delay function, platform-specific
         cmdLine.serial().printf("\r\nMAX11410 Init failed; retry...\r\n");

     }

     while (1)
     {
         // loop: put your main code here, to run repeatedly

         // CODE GENERATOR: example code: has no member function REF
         // CODE GENERATOR: example code for ADC: repeat-forever convert and print conversion result, one record per line
         // CODE GENERATOR: ResolutionBits = 24
         // CODE GENERATOR: FScode = 0xffffff
         // CODE GENERATOR: NumChannels = 10
         // CODE GENERATOR: banner before helloCppCodeList while(1)
         cmdLine.serial().printf("v_filter = 0x%2.2x\r\n", g_MAX11410_device.v_filter);

         cmdLine.serial().printf("v_pga = 0x%2.2x\r\n", g_MAX11410_device.v_pga);

         cmdLine.serial().printf("v_ctrl = 0x%2.2x\r\n", g_MAX11410_device.v_ctrl);

         // banner for csv data columns
         cmdLine.serial().printf("\"AIN0_LSB\",\"AIN1_LSB\",\"AIN2_LSB\",\"AIN3_LSB\",\"AIN4_LSB\",\"AIN5_LSB\",\"AIN6_LSB\",\"AIN7_LSB\",\"AIN8_LSB\",\"AIN9_LSB\"");

         cmdLine.serial().printf("\r\n");

         while(1) { // this code repeats forever
             // this code repeats forever
             // CODE GENERATOR: example code: has no member function ScanStandardExternalClock
             // CODE GENERATOR: example code: has no member function ReadAINcode
             // CODE GENERATOR: example code: member function Read_All_Voltages
             // Measure ADC channels in sequence from AIN0 to channelNumber_0_9.
             // @param[in] g_MAX11410_device.channelNumber_0_15: AIN Channel Number
             // @param[in] g_MAX11410_device.PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
             // @param[in] g_MAX11410_device.chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
             int channelId_0_9 = 9;
             //g_MAX11410_device.channelNumber_0_15 = channelId_0_9;
             //g_MAX11410_device.PowerManagement_0_2 = 0;
             //g_MAX11410_device.chan_id_0_1 = 1;
             g_MAX11410_device.Read_All_Voltages();

             // wait(3.0);
             // CODE GENERATOR: print conversion result
             // Use Arduino Serial Plotter to view output: Tools | Serial Plotter
             cmdLine.serial().printf("%d", g_MAX11410_device.AINcode[0]);
             for (int index = 1; index <= channelId_0_9; index++) {
                 cmdLine.serial().printf(",%d", g_MAX11410_device.AINcode[index]);
             }
             cmdLine.serial().printf("\r\n");

         } // this code repeats forever
     }
 }

//---------- CODE GENERATOR: end helloCppCodeList

Definition at line 405 of file MAX11410.h.

Member Typedef Documentation

typedef enum MAX11410::MAX11410_AINN_SEL_enum_t MAX11410_AINN_SEL_enum_t

Input multiplexer channel selection CMD_r000_1011_dddd_dddd_MUX_CTRL0 field AINN_SEL[3:0].

0000: AINN = AIN0
0001: AINN = AIN1
0010: AINN = AIN2
0011: AINN = AIN3
0100: AINN = AIN4
0101: AINN = AIN5
0110: AINN = AIN6
0111: AINN = AIN7
1000: AINN = AIN8
1001: AINN = AIN9
1010: AINN = GND
1011: AINN = Unconnected
1100: AINN = Unconnected
1101: AINN = Unconnected
1110: AINN = Unconnected
1111: AINN = Unconnected (default)

typedef enum MAX11410::MAX11410_AINP_SEL_enum_t MAX11410_AINP_SEL_enum_t

Input multiplexer channel selection CMD_r000_1011_dddd_dddd_MUX_CTRL0 field AINP_SEL[3:0].

0000: AINP = AIN0
0001: AINP = AIN1
0010: AINP = AIN2
0011: AINP = AIN3
0100: AINP = AIN4
0101: AINP = AIN5
0110: AINP = AIN6
0111: AINP = AIN7
1000: AINP = AIN8
1001: AINP = AIN9
1010: AINP = AVDD
1011: AINN = Unconnected
1100: AINN = Unconnected
1101: AINN = Unconnected
1110: AINN = Unconnected
1111: AINN = Unconnected (default)

typedef enum MAX11410::MAX11410_BRN_MODE_enum_t MAX11410_BRN_MODE_enum_t

Source command CMD_r000_1010_dddd_dddd_SOURCE BRN_MODE[1:0] field.

00: Powered down, burnout sources disabled (default)
01: 0.5uA burnout current sources enabled
10: 1uA burnout current sources enabled
11: 10uA burnout current sources enabled

typedef enum MAX11410::MAX11410_CAL_TYPE_enum_t MAX11410_CAL_TYPE_enum_t

Calbration command CMD_r000_0011_xxxx_xddd_CAL_START CAL_TYPE[2:0] field.

000: Performs a self-calibration. Resulting offset calibration value is stored in the SELF_OFF register, and the 1x gain calibration value is stored in the SELF_GAIN_1 register.
001: Performs a PGA gain calibration at the currently programmed PGA gain. A 'No Op' will result if PGA Gain calibration is executed with the PGA disabled via the SIG_PATH register, or with the GAIN register set to 1x.The resulting gain calibration value is stored in the SELF_GAIN_[2-128] register corresponding to the currently programmed PGA GAIN setting.
010: Reserved
011: Reserved
100: Performs a system offset calibration. The resulting calibration value is stored in the SYS_OFF_A register.
101: Performs a system gain calibration. The resulting calibration value is stored in the SYS_GAIN_A register.
110: Performs a system offset calibration. The resulting calibration value is stored in the SYS_OFF_B register.
111: Performs a system gain calibration. The resulting calibration value is stored in the SYS_GAIN_B register.

typedef enum MAX11410::MAX11410_CMD_enum_t MAX11410_CMD_enum_t

Register Addresses.

Naming convention is CMD_bitstream_FUNCTION_NAME

r = read/write bit (1=read, 0=write)
xaaa_aaaa = 7-bit register address field
dddd_dddd = 8-bit register data field
dddd_dddd_dddd_dddd = 16-bit register data field
dddd_dddd_dddd_dddd_dddd_dddd = 24-bit register data field
xxxx = don't care

typedef enum MAX11410::MAX11410_CMDOP_enum_t MAX11410_CMDOP_enum_t

Command Operation Format (see function DecodeCommand)

Naming convention is CMDOP_bitstream_OPERATION_NAME

rxxx_xxxx = read/write bit (1=read, 0=write)
xaaa_aaaa = 7-bit register address field -- see MAX11410_CMD_enum_t
xxxx = don't care

typedef enum MAX11410::MAX11410_CONV_TYPE_enum_t MAX11410_CONV_TYPE_enum_t

Conversion / seqeuncer start command CMD_r000_0001_xddd_xxdd_CONV_START CONV_TYPE[1:0] field.

CMD_r000_0110_xddd_xxdd_GP_CONV GP_CONV_TYPE[2:0] field.

00: Single conversion
01: Continuous conversions
10, 11: 1:4 Duty cycled conversions (modulator low-power mode)

typedef enum MAX11410::MAX11410_DEST_enum_t MAX11410_DEST_enum_t

Conversion / seqeuncer start command CMD_r000_0001_xddd_xxdd_CONV_START DEST[2:0] field.

CMD_r000_0110_xddd_xxdd_GP_CONV GP_DEST[2:0] field.

000: Store result in DATA0
001: Store result in DATA1
010: Store result in DATA2
011: Store result in DATA3
100: Store result in DATA4
101: Store result in DATA5
110: Store result in DATA6
111: Store result in DATA7

typedef enum MAX11410::MAX11410_GAIN_enum_t MAX11410_GAIN_enum_t

Input multiplexer channel selection CMD_r000_1110_00ss_0ggg_PGA field GAIN[2:0].

000: 1 (default)
001: 2
010: 4
011: 8
100: 16
101: 32
110: 64
111: 128

typedef enum MAX11410::MAX11410_GP0_DIR_enum_t MAX11410_GP0_DIR_enum_t

GPIO0 pin command CMD_r000_0100_dddd_xddd_GP0_CTRL GP0_DIR[1:0] field (bits 7:6)

00: Input mode, reference to VDDIO (default)
01: Reserved
10: Output mode, open-drain output
11: Output mode, CMOS output

typedef enum MAX11410::MAX11410_GP0_ISEL_enum_t MAX11410_GP0_ISEL_enum_t

GPIO0 pin command CMD_r000_0100_dddd_xddd_GP0_CTRL GP0_ISEL[1:0] field (bits 5:4)

00: GPIO_0 input disabled (default)
01: GPIO_0 input configured as rising-edge-triggered conversion start
10: GPIO_0 input configured as rising-edge-triggered sequence start from GP_SEQ_ADDR
11: Reserved

typedef enum MAX11410::MAX11410_GP0_OSEL_enum_t MAX11410_GP0_OSEL_enum_t

GPIO0 pin command CMD_r000_0100_dddd_xddd_GP0_CTRL GP0_OSEL[2:0] field (bits 2:0)

000: GPIO_0 output disabled, high Z (default)
001: GPIO_0 output is configured as INTRB (active low)
010: GPIO_0 output is configured as INTR (active high)
011: GPIO_0 output is configured as state Logic 0
100: GPIO_0 output is configured as state Logic 1
101: GPIO_0 output is configured as automatic low-side switch operation (CMOS output mode overridden)
110: GPIO_0 output is configured as modulator active status
111: GPIO_0 output is configured as system clock (2.456Mhz Nominal)

typedef enum MAX11410::MAX11410_GP1_DIR_enum_t MAX11410_GP1_DIR_enum_t

GPIO1 pin command CMD_r000_0101_dddd_xddd_GP1_CTRL GP1_DIR[1:0] field (bits 7:6)

00: Input mode, reference to VDDIO (default)
01: Reserved
10: Output mode, open-drain output
11: Output mode, CMOS output

typedef enum MAX11410::MAX11410_GP1_ISEL_enum_t MAX11410_GP1_ISEL_enum_t

GPIO1 pin command CMD_r000_0101_dddd_xddd_GP1_CTRL GP1_ISEL[1:0] field (bits 5:4)

00: GPIO_1 input disabled (default)
01: GPIO_1 input configured as rising-edge-triggered conversion start
10: GPIO_1 input configured as rising-edge-triggered sequence start from GP_SEQ_ADDR
11: Reserved

typedef enum MAX11410::MAX11410_GP1_OSEL_enum_t MAX11410_GP1_OSEL_enum_t

GPIO1 pin command CMD_r000_0101_dddd_xddd_GP1_CTRL GP1_OSEL[2:0] field (bits 2:0)

000: GPIO_1 output disabled, high Z (default)
001: GPIO_1 output is configured as INTRB (active low)
010: GPIO_1 output is configured as INTR (active high)
011: GPIO_1 output is configured as state Logic 0
100: GPIO_1 output is configured as state Logic 1
101: GPIO_1 output is configured as system clock (2.456Mhz Nominal)
110: GPIO_1 output is configured as modulator active status
111: GPIO_1 output is configured as automatic low-side switch operation (CMOS output mode overridden)

typedef enum MAX11410::MAX11410_IDAC0_SEL_enum_t MAX11410_IDAC0_SEL_enum_t

Input multiplexer channel selection CMD_r000_1100_dddd_dddd_MUX_CTRL1 field IDAC0_SEL[3:0].

0000: AIN0
0001: AIN1
0010: AIN2
0011: AIN3
0100: AIN4
0101: AIN5
0110: AIN6
0111: AIN7
1000: AIN8
1001: AIN9
1010: Unconnected; IDAC0 powered down.
1011: Unconnected; IDAC0 powered down.
1100: Unconnected; IDAC0 powered down.
1101: Unconnected; IDAC0 powered down.
1110: Unconnected; IDAC0 powered down.
1111: Unconnected; IDAC0 powered down.(Default)

typedef enum MAX11410::MAX11410_IDAC1_SEL_enum_t MAX11410_IDAC1_SEL_enum_t

Input multiplexer channel selection CMD_r000_1100_dddd_dddd_MUX_CTRL1 field IDAC1_SEL[3:0].

0000: AIN0
0001: AIN1
0010: AIN2
0011: AIN3
0100: AIN4
0101: AIN5
0110: AIN6
0111: AIN7
1000: AIN8
1001: AIN9
1010: Unconnected; IDAC1 powered down.
1011: Unconnected; IDAC1 powered down.
1100: Unconnected; IDAC1 powered down.
1101: Unconnected; IDAC1 powered down.
1110: Unconnected; IDAC1 powered down.
1111: Unconnected; IDAC1 powered down.(Default)

typedef enum MAX11410::MAX11410_IDAC_MODE_enum_t MAX11410_IDAC_MODE_enum_t

Source command CMD_r000_1010_dddd_dddd_SOURCE IDAC_MODE[3:0] field.

0000: 10uA (default)
0001: 50uA
0010: 75uA
0011: 100uA
0100: 125uA
0101: 150uA
0110: 175uA
0111: 200uA
1000: 225uA
1001: 250uA
1010: 300uA
1011: 400uA
1100: 600uA
1101: 800uA
1110: 1200uA
1111: 1600uA

typedef enum MAX11410::MAX11410_LINEF_enum_t MAX11410_LINEF_enum_t

Filter command CMD_r000_1000_x0dd_dddd_FILTER LINEF[1:0] field.

00: Simultaneous 50/60Hz FIR rejection (default)
01: 50Hz FIR rejection
10: 60Hz FIR rejection
11: SINC4

typedef enum MAX11410::MAX11410_PD_enum_t MAX11410_PD_enum_t

Power-down state command CMD_r000_0000_xxxx_xxdd_PD PD[1:0] field.

00: Normal mode
01: Standby mode -- Powers down all analog circuity, but not the internal voltage regulator
10: Sleep mode -- Powers down all analog circuitry including the internal voltage regulator
11: Reset -- all registers reset to POR state (Self Clearing to 01 Standby mode)

typedef enum MAX11410::MAX11410_RATE_enum_t MAX11410_RATE_enum_t

Filter command CMD_r000_1000_x0dd_dddd_FILTER RATE[3:0] field.

Sets conversion rate based on LINEF value. See Table 9a through Table 9d for details.

Table 9a. LINEF = 00 Data Rate and Filter Rejection Settings

Rate | LINEF | CONV_TYPE | Rate -----------|------------------------|----------------------------|---------- RATE_0000 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_00_Single | 1.0SPS RATE_0001 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_00_Single | 2.0SPS RATE_0010 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_00_Single | 4.0SPS RATE_0011 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_00_Single | 8.0SPS RATE_0100 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_00_Single | 16.0SPS RATE_0000 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_01_Continuous | 1.1SPS RATE_0001 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_01_Continuous | 2.1SPS RATE_0010 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_01_Continuous | 4.2SPS RATE_0011 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_01_Continuous | 8.4SPS RATE_0100 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_01_Continuous | 16.8SPS RATE_0000 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 0.3SPS RATE_0001 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 0.5SPS RATE_0010 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 1.1SPS RATE_0011 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 2.1SPS RATE_0100 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 4.2SPS

Table 9b. LINEF = 01 Data Rate and Filter Rejection Settings

Rate | LINEF | CONV_TYPE | Rate ----------|------------------------|----------------------------|---------- RATE_0000 | LINEF_01_50Hz_FIR | CONV_TYPE_00_Single | 1.3SPS RATE_0001 | LINEF_01_50Hz_FIR | CONV_TYPE_00_Single | 2.5SPS RATE_0010 | LINEF_01_50Hz_FIR | CONV_TYPE_00_Single | 5.0SPS RATE_0011 | LINEF_01_50Hz_FIR | CONV_TYPE_00_Single | 10.0SPS RATE_0100 | LINEF_01_50Hz_FIR | CONV_TYPE_00_Single | 20.0SPS RATE_0101 | LINEF_01_50Hz_FIR | CONV_TYPE_00_Single | 35.6SPS RATE_0000 | LINEF_01_50Hz_FIR | CONV_TYPE_01_Continuous | 1.3SPS RATE_0001 | LINEF_01_50Hz_FIR | CONV_TYPE_01_Continuous | 2.7SPS RATE_0010 | LINEF_01_50Hz_FIR | CONV_TYPE_01_Continuous | 5.3SPS RATE_0011 | LINEF_01_50Hz_FIR | CONV_TYPE_01_Continuous | 10.7SPS RATE_0100 | LINEF_01_50Hz_FIR | CONV_TYPE_01_Continuous | 21.3SPS RATE_0101 | LINEF_01_50Hz_FIR | CONV_TYPE_01_Continuous | 40.0SPS RATE_0000 | LINEF_01_50Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 0.3SPS RATE_0001 | LINEF_01_50Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 0.7SPS RATE_0010 | LINEF_01_50Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 1.3SPS RATE_0011 | LINEF_01_50Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 2.7SPS RATE_0100 | LINEF_01_50Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 5.3SPS RATE_0101 | LINEF_01_50Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 10.0SPS

Table 9c. LINEF = 10 Data Rate and Filter Rejection Settings

Rate | LINEF | CONV_TYPE | Rate ----------|------------------------|----------------------------|---------- RATE_0000 | LINEF_10_60Hz_FIR | CONV_TYPE_00_Single | 1.3SPS RATE_0001 | LINEF_10_60Hz_FIR | CONV_TYPE_00_Single | 2.5SPS RATE_0010 | LINEF_10_60Hz_FIR | CONV_TYPE_00_Single | 5.0SPS RATE_0011 | LINEF_10_60Hz_FIR | CONV_TYPE_00_Single | 10.0SPS RATE_0100 | LINEF_10_60Hz_FIR | CONV_TYPE_00_Single | 20.0SPS RATE_0101 | LINEF_10_60Hz_FIR | CONV_TYPE_00_Single | 35.6SPS RATE_0000 | LINEF_10_60Hz_FIR | CONV_TYPE_01_Continuous | 1.3SPS RATE_0001 | LINEF_10_60Hz_FIR | CONV_TYPE_01_Continuous | 2.7SPS RATE_0010 | LINEF_10_60Hz_FIR | CONV_TYPE_01_Continuous | 5.3SPS RATE_0011 | LINEF_10_60Hz_FIR | CONV_TYPE_01_Continuous | 10.7SPS RATE_0100 | LINEF_10_60Hz_FIR | CONV_TYPE_01_Continuous | 21.3SPS RATE_0101 | LINEF_10_60Hz_FIR | CONV_TYPE_01_Continuous | 40.0SPS RATE_0000 | LINEF_10_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 0.3SPS RATE_0001 | LINEF_10_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 0.7SPS RATE_0010 | LINEF_10_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 1.3SPS RATE_0011 | LINEF_10_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 2.7SPS RATE_0100 | LINEF_10_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 5.3SPS RATE_0101 | LINEF_10_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 10.0SPS

Table 9d. LINEF = 11 Data Rate and Filter Rejection Settings

Rate | LINEF | CONV_TYPE | Rate ----------|------------------------|----------------------------|---------- RATE_0000 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 1SPS RATE_0001 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 2.5SPS RATE_0010 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 5SPS RATE_0011 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 10SPS RATE_0100 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 15SPS RATE_0101 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 30SPS RATE_0110 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 60SPS RATE_0111 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 120SPS RATE_1000 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 240SPS RATE_1001 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 480SPS RATE_0000 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 4SPS RATE_0001 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 10SPS RATE_0010 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 20SPS RATE_0011 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 40SPS RATE_0100 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 60SPS RATE_0101 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 120SPS RATE_0110 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 240SPS RATE_0111 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 480SPS RATE_1000 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 960SPS RATE_1001 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 1920SPS RATE_0000 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 1SPS RATE_0001 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 2.5SPS RATE_0010 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 5SPS RATE_0011 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 10SPS RATE_0100 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 15SPS RATE_0101 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 30SPS RATE_0110 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 60SPS RATE_0111 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 120SPS RATE_1000 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 240SPS RATE_1001 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 480SPS

typedef enum MAX11410::MAX11410_REF_SEL_enum_t MAX11410_REF_SEL_enum_t

Filter command CMD_r000_1001_dddd_dddd_CTRL REF_SEL[2:0] field.

000: AIN0(REF0P)/AIN1(REF0N)
001: REF1P/REF1N (default)
010: REF2P/REF2N
011: AVDD/AGND
100: AIN0(REF0P)/AGND (single-ended mode)
101: REF1P/AGND (single-ended mode)
110: REF2P/AGND (single-ended mode)
111: AVDD/AGND

typedef enum MAX11410::MAX11410_SEQ_ADDR_enum_t MAX11410_SEQ_ADDR_enum_t

Microcode Sequencer Addresses.

CMD_r000_0010_xddd_dddd_SEQ_START CMD_r000_0111_xddd_dddd_GP_SEQ_ADDR

Naming convention is CMD_bitstream_FUNCTION_NAME

xaaa_aaaa = 7-bit register address field
dddd_dddd = 8-bit register data field
xxxx = don't care

typedef enum MAX11410::MAX11410_SIG_PATH_enum_t MAX11410_SIG_PATH_enum_t

Input multiplexer channel selection CMD_r000_1110_00ss_0ggg_PGA field SIG_PATH[1:0].

00: Buffered, low-power, unity-gain path (PGA disabled, digital gain) [default]
01: Bypass path (signal buffer disabled,PGA disabled, digital gain)
10: PGA path (signal buffer disabled, analog gain)
11: Reserved

typedef enum MAX11410::MAX11410_STATUS_enum_t MAX11410_STATUS_enum_t

Status indicator bits CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS fields.

typedef enum MAX11410::MAX11410_VBIAS_MODE_enum_t MAX11410_VBIAS_MODE_enum_t

Source command CMD_r000_1010_dddd_dddd_SOURCE VBIAS_MODE[1:0] field.

00: Active mode (default)
01: High impedance; 125kOhm output impedance
10: Low impedance; 20kOhm output impedance
11: Low impedance; 20kOhm output impedance

Member Enumeration Documentation

enum MAX11410_AINN_SEL_enum_t

Input multiplexer channel selection CMD_r000_1011_dddd_dddd_MUX_CTRL0 field AINN_SEL[3:0].

0000: AINN = AIN0
0001: AINN = AIN1
0010: AINN = AIN2
0011: AINN = AIN3
0100: AINN = AIN4
0101: AINN = AIN5
0110: AINN = AIN6
0111: AINN = AIN7
1000: AINN = AIN8
1001: AINN = AIN9
1010: AINN = GND
1011: AINN = Unconnected
1100: AINN = Unconnected
1101: AINN = Unconnected
1110: AINN = Unconnected
1111: AINN = Unconnected (default)

Enumerator:

AINN_SEL_0000_AIN0	0b0000
AINN_SEL_0001_AIN1	0b0001
AINN_SEL_0010_AIN2	0b0010
AINN_SEL_0011_AIN3	0b0011
AINN_SEL_0100_AIN4	0b0100
AINN_SEL_0101_AIN5	0b0101
AINN_SEL_0110_AIN6	0b0110
AINN_SEL_0111_AIN7	0b0111
AINN_SEL_1000_AIN8	0b1000
AINN_SEL_1001_AIN9	0b1001
AINN_SEL_1010_GND	0b1010
AINN_SEL_1011_unconnected	0b1011
AINN_SEL_1100_unconnected	0b1100
AINN_SEL_1101_unconnected	0b1101
AINN_SEL_1110_unconnected	0b1110
AINN_SEL_1111_unconnected	0b1111

Definition at line 1138 of file MAX11410.h.

enum MAX11410_AINP_SEL_enum_t

Input multiplexer channel selection CMD_r000_1011_dddd_dddd_MUX_CTRL0 field AINP_SEL[3:0].

0000: AINP = AIN0
0001: AINP = AIN1
0010: AINP = AIN2
0011: AINP = AIN3
0100: AINP = AIN4
0101: AINP = AIN5
0110: AINP = AIN6
0111: AINP = AIN7
1000: AINP = AIN8
1001: AINP = AIN9
1010: AINP = AVDD
1011: AINN = Unconnected
1100: AINN = Unconnected
1101: AINN = Unconnected
1110: AINN = Unconnected
1111: AINN = Unconnected (default)

Enumerator:

AINP_SEL_0000_AIN0	0b0000
AINP_SEL_0001_AIN1	0b0001
AINP_SEL_0010_AIN2	0b0010
AINP_SEL_0011_AIN3	0b0011
AINP_SEL_0100_AIN4	0b0100
AINP_SEL_0101_AIN5	0b0101
AINP_SEL_0110_AIN6	0b0110
AINP_SEL_0111_AIN7	0b0111
AINP_SEL_1000_AIN8	0b1000
AINP_SEL_1001_AIN9	0b1001
AINP_SEL_1010_AVDD	0b1010
AINP_SEL_1011_unconnected	0b1011
AINP_SEL_1100_unconnected	0b1100
AINP_SEL_1101_unconnected	0b1101
AINP_SEL_1110_unconnected	0b1110
AINP_SEL_1111_unconnected	0b1111

Definition at line 1098 of file MAX11410.h.

enum MAX11410_BRN_MODE_enum_t

Source command CMD_r000_1010_dddd_dddd_SOURCE BRN_MODE[1:0] field.

00: Powered down, burnout sources disabled (default)
01: 0.5uA burnout current sources enabled
10: 1uA burnout current sources enabled
11: 10uA burnout current sources enabled

Enumerator:

BRN_MODE_00_disabled	0b00
BRN_MODE_01_0u5A	0b01
BRN_MODE_10_1uA	0b10
BRN_MODE_11_10uA	0b11

Definition at line 1030 of file MAX11410.h.

enum MAX11410_CAL_TYPE_enum_t

Calbration command CMD_r000_0011_xxxx_xddd_CAL_START CAL_TYPE[2:0] field.

000: Performs a self-calibration. Resulting offset calibration value is stored in the SELF_OFF register, and the 1x gain calibration value is stored in the SELF_GAIN_1 register.
001: Performs a PGA gain calibration at the currently programmed PGA gain. A 'No Op' will result if PGA Gain calibration is executed with the PGA disabled via the SIG_PATH register, or with the GAIN register set to 1x.The resulting gain calibration value is stored in the SELF_GAIN_[2-128] register corresponding to the currently programmed PGA GAIN setting.
010: Reserved
011: Reserved
100: Performs a system offset calibration. The resulting calibration value is stored in the SYS_OFF_A register.
101: Performs a system gain calibration. The resulting calibration value is stored in the SYS_GAIN_A register.
110: Performs a system offset calibration. The resulting calibration value is stored in the SYS_OFF_B register.
111: Performs a system gain calibration. The resulting calibration value is stored in the SYS_GAIN_B register.

Enumerator:

CAL_TYPE_000_SELF_CAL	0b000
CAL_TYPE_001_PGA_GAIN	0b001
CAL_TYPE_010_reserved	0b010
CAL_TYPE_011_reserved	0b011
CAL_TYPE_100_SYS_OFF_A	0b100
CAL_TYPE_101_SYS_GAIN_A	0b101
CAL_TYPE_110_SYS_OFF_B	0b110
CAL_TYPE_111_SYS_GAIN_B	0b111

Definition at line 715 of file MAX11410.h.

enum MAX11410_CMD_enum_t

Register Addresses.

Naming convention is CMD_bitstream_FUNCTION_NAME

r = read/write bit (1=read, 0=write)
xaaa_aaaa = 7-bit register address field
dddd_dddd = 8-bit register data field
dddd_dddd_dddd_dddd = 16-bit register data field
dddd_dddd_dddd_dddd_dddd_dddd = 24-bit register data field
xxxx = don't care

Enumerator:

CMD_r000_0000_xxxx_xxdd_PD	0b0000000
CMD_r000_0001_xddd_xxdd_CONV_START	0b0000001
CMD_r000_0010_xddd_dddd_SEQ_START	0b0000010
CMD_r000_0011_xxxx_xddd_CAL_START	0b0000011
CMD_r000_0100_dddd_xddd_GP0_CTRL	0b0000100
CMD_r000_0101_dddd_xddd_GP1_CTRL	0b0000101
CMD_r000_0110_xddd_xxdd_GP_CONV	0b0000110
CMD_r000_0111_xddd_dddd_GP_SEQ_ADDR	0b0000111
CMD_r000_1000_x0dd_dddd_FILTER	0b0001000
CMD_r000_1001_dddd_dddd_CTRL	0b0001001
CMD_r000_1010_dddd_dddd_SOURCE	0b0001010
CMD_r000_1011_dddd_dddd_MUX_CTRL0	0b0001011
CMD_r000_1100_dddd_dddd_MUX_CTRL1	0b0001100
CMD_r000_1101_dddd_dddd_MUX_CTRL2	0b0001101
CMD_r000_1110_00ss_0ggg_PGA	0b0001110
CMD_r000_1111_dddd_dddd_WAIT_EXT	0b0001111
CMD_r001_0000_xxxx_xxxx_WAIT_START	0b0010000
CMD_r001_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xddd_PART_ID	0b0010001
CMD_r001_0010_xxxx_xxxx_dddd_xxdd_dddd_dddd_SYSC_SEL	0b0010010
CMD_r001_0011_dddd_dddd_dddd_dddd_dddd_dddd_SYS_OFF_A	0b0010011
CMD_r001_0100_dddd_dddd_dddd_dddd_dddd_dddd_SYS_OFF_B	0b0010100
CMD_r001_0101_dddd_dddd_dddd_dddd_dddd_dddd_SYS_GAIN_A	0b0010101
CMD_r001_0110_dddd_dddd_dddd_dddd_dddd_dddd_SYS_GAIN_B	0b0010110
CMD_r001_0111_dddd_dddd_dddd_dddd_dddd_dddd_SELF_OFF	0b0010111
CMD_r001_1000_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_1	0b0011000
CMD_r001_1001_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_2	0b0011001
CMD_r001_1010_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_4	0b0011010
CMD_r001_1011_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_8	0b0011011
CMD_r001_1100_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_16	0b0011100
CMD_r001_1101_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_32	0b0011101
CMD_r001_1110_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_64	0b0011110
CMD_r001_1111_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_128	0b0011111
CMD_r010_0000_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH0	0b0100000
CMD_r010_0001_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH1	0b0100001
CMD_r010_0010_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH2	0b0100010
CMD_r010_0011_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH3	0b0100011
CMD_r010_0100_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH4	0b0100100
CMD_r010_0101_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH5	0b0100101
CMD_r010_0110_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH6	0b0100110
CMD_r010_0111_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH7	0b0100111
CMD_r010_1000_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH0	0b0101000
CMD_r010_1001_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH1	0b0101001
CMD_r010_1010_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH2	0b0101010
CMD_r010_1011_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH3	0b0101011
CMD_r010_1100_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH4	0b0101100
CMD_r010_1101_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH5	0b0101101
CMD_r010_1110_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH6	0b0101110
CMD_r010_1111_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH7	0b0101111
CMD_r011_0000_dddd_dddd_dddd_dddd_dddd_dddd_DATA0	0b0110000
CMD_r011_0001_dddd_dddd_dddd_dddd_dddd_dddd_DATA1	0b0110001
CMD_r011_0010_dddd_dddd_dddd_dddd_dddd_dddd_DATA2	0b0110010
CMD_r011_0011_dddd_dddd_dddd_dddd_dddd_dddd_DATA3	0b0110011
CMD_r011_0100_dddd_dddd_dddd_dddd_dddd_dddd_DATA4	0b0110100
CMD_r011_0101_dddd_dddd_dddd_dddd_dddd_dddd_DATA5	0b0110101
CMD_r011_0110_dddd_dddd_dddd_dddd_dddd_dddd_DATA6	0b0110110
CMD_r011_0111_dddd_dddd_dddd_dddd_dddd_dddd_DATA7	0b0110111
CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS	0b0111000
CMD_r011_1001_dddd_dddd_dddd_dddd_dxxd_dddd_STATUS_IE	0b0111001
CMD_r011_1010_xaaa_aaaa_dddd_dddd_UC_0	0b0111010
CMD_r011_1011_xaaa_aaaa_dddd_dddd_UC_1	0b0111011
CMD_r011_1100_xaaa_aaaa_dddd_dddd_UC_2	0b0111100
CMD_r011_1101_xaaa_aaaa_dddd_dddd_UC_3	0b0111101
CMD_r011_1110_xaaa_aaaa_dddd_dddd_UC_4	0b0111110
CMD_r011_1111_xaaa_aaaa_dddd_dddd_UC_5	0b0111111
CMD_r100_0000_xaaa_aaaa_dddd_dddd_UC_6	0b1000000
CMD_r100_0001_xaaa_aaaa_dddd_dddd_UC_7	0b1000001
CMD_r100_0010_xaaa_aaaa_dddd_dddd_UC_8	0b1000010
CMD_r100_0011_xaaa_aaaa_dddd_dddd_UC_9	0b1000011
CMD_r100_0100_xaaa_aaaa_dddd_dddd_UC_10	0b1000100
CMD_r100_0101_xaaa_aaaa_dddd_dddd_UC_11	0b1000101
CMD_r100_0110_xaaa_aaaa_dddd_dddd_UC_12	0b1000110
CMD_r100_0111_xaaa_aaaa_dddd_dddd_UC_13	0b1000111
CMD_r100_1000_xaaa_aaaa_dddd_dddd_UC_14	0b1001000
CMD_r100_1001_xaaa_aaaa_dddd_dddd_UC_15	0b1001001
CMD_r100_1010_xaaa_aaaa_dddd_dddd_UC_16	0b1001010
CMD_r100_1011_xaaa_aaaa_dddd_dddd_UC_17	0b1001011
CMD_r100_1100_xaaa_aaaa_dddd_dddd_UC_18	0b1001100
CMD_r100_1101_xaaa_aaaa_dddd_dddd_UC_19	0b1001101
CMD_r100_1110_xaaa_aaaa_dddd_dddd_UC_20	0b1001110
CMD_r100_1111_xaaa_aaaa_dddd_dddd_UC_21	0b1001111
CMD_r101_0000_xaaa_aaaa_dddd_dddd_UC_22	0b1010000
CMD_r101_0001_xaaa_aaaa_dddd_dddd_UC_23	0b1010001
CMD_r101_0010_xaaa_aaaa_dddd_dddd_UC_24	0b1010010
CMD_r101_0011_xaaa_aaaa_dddd_dddd_UC_25	0b1010011
CMD_r101_0100_xaaa_aaaa_dddd_dddd_UC_26	0b1010100
CMD_r101_0101_xaaa_aaaa_dddd_dddd_UC_27	0b1010101
CMD_r101_0110_xaaa_aaaa_dddd_dddd_UC_28	0b1010110
CMD_r101_0111_xaaa_aaaa_dddd_dddd_UC_29	0b1010111
CMD_r101_1000_xaaa_aaaa_dddd_dddd_UC_30	0b1011000
CMD_r101_1001_xaaa_aaaa_dddd_dddd_UC_31	0b1011001
CMD_r101_1010_xaaa_aaaa_dddd_dddd_UC_32	0b1011010
CMD_r101_1011_xaaa_aaaa_dddd_dddd_UC_33	0b1011011
CMD_r101_1100_xaaa_aaaa_dddd_dddd_UC_34	0b1011100
CMD_r101_1101_xaaa_aaaa_dddd_dddd_UC_35	0b1011101
CMD_r101_1110_xaaa_aaaa_dddd_dddd_UC_36	0b1011110
CMD_r101_1111_xaaa_aaaa_dddd_dddd_UC_37	0b1011111
CMD_r110_0000_xaaa_aaaa_dddd_dddd_UC_38	0b1100000
CMD_r110_0001_xaaa_aaaa_dddd_dddd_UC_39	0b1100001
CMD_r110_0010_xaaa_aaaa_dddd_dddd_UC_40	0b1100010
CMD_r110_0011_xaaa_aaaa_dddd_dddd_UC_41	0b1100011
CMD_r110_0100_xaaa_aaaa_dddd_dddd_UC_42	0b1100100
CMD_r110_0101_xaaa_aaaa_dddd_dddd_UC_43	0b1100101
CMD_r110_0110_xaaa_aaaa_dddd_dddd_UC_44	0b1100110
CMD_r110_0111_xaaa_aaaa_dddd_dddd_UC_45	0b1100111
CMD_r110_1000_xaaa_aaaa_dddd_dddd_UC_46	0b1101000
CMD_r110_1001_xaaa_aaaa_dddd_dddd_UC_47	0b1101001
CMD_r110_1010_xaaa_aaaa_dddd_dddd_UC_48	0b1101010
CMD_r110_1011_xaaa_aaaa_dddd_dddd_UC_49	0b1101011
CMD_r110_1100_xaaa_aaaa_dddd_dddd_UC_50	0b1101100
CMD_r110_1101_xaaa_aaaa_dddd_dddd_UC_51	0b1101101
CMD_r110_1110_xaaa_aaaa_dddd_dddd_UC_52	0b1101110
CMD_r110_1111_xxxx_xxxx_xaaa_aaaa_UCADDR	0b1101111

Definition at line 432 of file MAX11410.h.

enum MAX11410_CMDOP_enum_t

Command Operation Format (see function DecodeCommand)

Naming convention is CMDOP_bitstream_OPERATION_NAME

rxxx_xxxx = read/write bit (1=read, 0=write)
xaaa_aaaa = 7-bit register address field -- see MAX11410_CMD_enum_t
xxxx = don't care

Enumerator:

CMDOP_0aaa_aaaa_WriteRegister	0b00000000
CMDOP_1aaa_aaaa_ReadRegister	0b10000000

Definition at line 416 of file MAX11410.h.

enum MAX11410_CONV_TYPE_enum_t

Conversion / seqeuncer start command CMD_r000_0001_xddd_xxdd_CONV_START CONV_TYPE[1:0] field.

CMD_r000_0110_xddd_xxdd_GP_CONV GP_CONV_TYPE[2:0] field.

00: Single conversion
01: Continuous conversions
10, 11: 1:4 Duty cycled conversions (modulator low-power mode)

Enumerator:

CONV_TYPE_00_Single	0b00
CONV_TYPE_01_Continuous	0b01
CONV_TYPE_10_DutyCycle_1_4	0b10
CONV_TYPE_11_DutyCycle_1_4	0b11

Definition at line 695 of file MAX11410.h.

enum MAX11410_DEST_enum_t

Conversion / seqeuncer start command CMD_r000_0001_xddd_xxdd_CONV_START DEST[2:0] field.

CMD_r000_0110_xddd_xxdd_GP_CONV GP_DEST[2:0] field.

000: Store result in DATA0
001: Store result in DATA1
010: Store result in DATA2
011: Store result in DATA3
100: Store result in DATA4
101: Store result in DATA5
110: Store result in DATA6
111: Store result in DATA7

Enumerator:

DEST_000_DATA0	0b000
DEST_001_DATA1	0b001
DEST_010_DATA2	0b010
DEST_011_DATA3	0b011
DEST_100_DATA4	0b100
DEST_101_DATA5	0b101
DEST_110_DATA6	0b110
DEST_111_DATA7	0b111

Definition at line 675 of file MAX11410.h.

enum MAX11410_GAIN_enum_t

Input multiplexer channel selection CMD_r000_1110_00ss_0ggg_PGA field GAIN[2:0].

000: 1 (default)
001: 2
010: 4
011: 8
100: 16
101: 32
110: 64
111: 128

Enumerator:

GAIN_000_1	0b000
GAIN_001_2	0b001
GAIN_010_4	0b010
GAIN_011_8	0b011
GAIN_100_16	0b100
GAIN_101_32	0b101
GAIN_110_64	0b110
GAIN_111_128	0b111

Definition at line 1266 of file MAX11410.h.

enum MAX11410_GP0_DIR_enum_t

GPIO0 pin command CMD_r000_0100_dddd_xddd_GP0_CTRL GP0_DIR[1:0] field (bits 7:6)

00: Input mode, reference to VDDIO (default)
01: Reserved
10: Output mode, open-drain output
11: Output mode, CMOS output

Enumerator:

GP0_DIR_00_Input	0b00
GP0_DIR_01_reserved	0b01
GP0_DIR_10_OutputOpenDrain	0b10
GP0_DIR_11_Output	0b11

Definition at line 735 of file MAX11410.h.

enum MAX11410_GP0_ISEL_enum_t

GPIO0 pin command CMD_r000_0100_dddd_xddd_GP0_CTRL GP0_ISEL[1:0] field (bits 5:4)

00: GPIO_0 input disabled (default)
01: GPIO_0 input configured as rising-edge-triggered conversion start
10: GPIO_0 input configured as rising-edge-triggered sequence start from GP_SEQ_ADDR
11: Reserved

Enumerator:

GP0_ISEL_00_disabled	0b00
GP0_ISEL_01_TRIGGER_CONV_START	0b01
GP0_ISEL_10_TRIGGER_SEQ_START	0b10
GP0_ISEL_11_reserved	0b11

Definition at line 751 of file MAX11410.h.

enum MAX11410_GP0_OSEL_enum_t

GPIO0 pin command CMD_r000_0100_dddd_xddd_GP0_CTRL GP0_OSEL[2:0] field (bits 2:0)

000: GPIO_0 output disabled, high Z (default)
001: GPIO_0 output is configured as INTRB (active low)
010: GPIO_0 output is configured as INTR (active high)
011: GPIO_0 output is configured as state Logic 0
100: GPIO_0 output is configured as state Logic 1
101: GPIO_0 output is configured as automatic low-side switch operation (CMOS output mode overridden)
110: GPIO_0 output is configured as modulator active status
111: GPIO_0 output is configured as system clock (2.456Mhz Nominal)

Enumerator:

GP0_OSEL_000_disabled	0b000
GP0_OSEL_001_INTRB	0b001
GP0_OSEL_010_INTR	0b010
GP0_OSEL_011_LOGIC_0	0b011
GP0_OSEL_100_LOGIC_1	0b100
GP0_OSEL_101_AUTO_LOWSIDE_SWITCH	0b101
GP0_OSEL_110_MODULATOR_ACTIVE_STATUS	0b110
GP0_OSEL_111_CLOCK_2M456	0b111

Definition at line 771 of file MAX11410.h.

enum MAX11410_GP1_DIR_enum_t

GPIO1 pin command CMD_r000_0101_dddd_xddd_GP1_CTRL GP1_DIR[1:0] field (bits 7:6)

00: Input mode, reference to VDDIO (default)
01: Reserved
10: Output mode, open-drain output
11: Output mode, CMOS output

Enumerator:

GP1_DIR_00_Input	0b00
GP1_DIR_01_reserved	0b01
GP1_DIR_10_OutputOpenDrain	0b10
GP1_DIR_11_Output	0b11

Definition at line 791 of file MAX11410.h.

enum MAX11410_GP1_ISEL_enum_t

GPIO1 pin command CMD_r000_0101_dddd_xddd_GP1_CTRL GP1_ISEL[1:0] field (bits 5:4)

00: GPIO_1 input disabled (default)
01: GPIO_1 input configured as rising-edge-triggered conversion start
10: GPIO_1 input configured as rising-edge-triggered sequence start from GP_SEQ_ADDR
11: Reserved

Enumerator:

GP1_ISEL_00_disabled	0b00
GP1_ISEL_01_TRIGGER_CONV_START	0b01
GP1_ISEL_10_TRIGGER_SEQ_START	0b10
GP1_ISEL_11_reserved	0b11

Definition at line 807 of file MAX11410.h.

enum MAX11410_GP1_OSEL_enum_t

GPIO1 pin command CMD_r000_0101_dddd_xddd_GP1_CTRL GP1_OSEL[2:0] field (bits 2:0)

000: GPIO_1 output disabled, high Z (default)
001: GPIO_1 output is configured as INTRB (active low)
010: GPIO_1 output is configured as INTR (active high)
011: GPIO_1 output is configured as state Logic 0
100: GPIO_1 output is configured as state Logic 1
101: GPIO_1 output is configured as system clock (2.456Mhz Nominal)
110: GPIO_1 output is configured as modulator active status
111: GPIO_1 output is configured as automatic low-side switch operation (CMOS output mode overridden)

Enumerator:

GP1_OSEL_000_disabled	0b000
GP1_OSEL_001_INTRB	0b001
GP1_OSEL_010_INTR	0b010
GP1_OSEL_011_LOGIC_0	0b011
GP1_OSEL_100_LOGIC_1	0b100
GP1_OSEL_101_AUTO_LOWSIDE_SWITCH	0b101
GP1_OSEL_110_MODULATOR_ACTIVE_STATUS	0b110
GP1_OSEL_111_CLOCK_2M456	0b111

Definition at line 827 of file MAX11410.h.

enum MAX11410_ic_t

IC's supported with this driver.

MAX11410

Definition at line 1282 of file MAX11410.h.

enum MAX11410_IDAC0_SEL_enum_t

Input multiplexer channel selection CMD_r000_1100_dddd_dddd_MUX_CTRL1 field IDAC0_SEL[3:0].

0000: AIN0
0001: AIN1
0010: AIN2
0011: AIN3
0100: AIN4
0101: AIN5
0110: AIN6
0111: AIN7
1000: AIN8
1001: AIN9
1010: Unconnected; IDAC0 powered down.
1011: Unconnected; IDAC0 powered down.
1100: Unconnected; IDAC0 powered down.
1101: Unconnected; IDAC0 powered down.
1110: Unconnected; IDAC0 powered down.
1111: Unconnected; IDAC0 powered down.(Default)

Enumerator:

IDAC0_SEL_0000_AIN0	0b0000
IDAC0_SEL_0001_AIN1	0b0001
IDAC0_SEL_0010_AIN2	0b0010
IDAC0_SEL_0011_AIN3	0b0011
IDAC0_SEL_0100_AIN4	0b0100
IDAC0_SEL_0101_AIN5	0b0101
IDAC0_SEL_0110_AIN6	0b0110
IDAC0_SEL_0111_AIN7	0b0111
IDAC0_SEL_1000_AIN8	0b1000
IDAC0_SEL_1001_AIN9	0b1001
IDAC0_SEL_1010_unconnected	0b1010
IDAC0_SEL_1011_unconnected	0b1011
IDAC0_SEL_1100_unconnected	0b1100
IDAC0_SEL_1101_unconnected	0b1101
IDAC0_SEL_1110_unconnected	0b1110
IDAC0_SEL_1111_unconnected	0b1111

Definition at line 1218 of file MAX11410.h.

enum MAX11410_IDAC1_SEL_enum_t

Input multiplexer channel selection CMD_r000_1100_dddd_dddd_MUX_CTRL1 field IDAC1_SEL[3:0].

0000: AIN0
0001: AIN1
0010: AIN2
0011: AIN3
0100: AIN4
0101: AIN5
0110: AIN6
0111: AIN7
1000: AIN8
1001: AIN9
1010: Unconnected; IDAC1 powered down.
1011: Unconnected; IDAC1 powered down.
1100: Unconnected; IDAC1 powered down.
1101: Unconnected; IDAC1 powered down.
1110: Unconnected; IDAC1 powered down.
1111: Unconnected; IDAC1 powered down.(Default)

Enumerator:

IDAC1_SEL_0000_AIN0	0b0000
IDAC1_SEL_0001_AIN1	0b0001
IDAC1_SEL_0010_AIN2	0b0010
IDAC1_SEL_0011_AIN3	0b0011
IDAC1_SEL_0100_AIN4	0b0100
IDAC1_SEL_0101_AIN5	0b0101
IDAC1_SEL_0110_AIN6	0b0110
IDAC1_SEL_0111_AIN7	0b0111
IDAC1_SEL_1000_AIN8	0b1000
IDAC1_SEL_1001_AIN9	0b1001
IDAC1_SEL_1010_unconnected	0b1010
IDAC1_SEL_1011_unconnected	0b1011
IDAC1_SEL_1100_unconnected	0b1100
IDAC1_SEL_1101_unconnected	0b1101
IDAC1_SEL_1110_unconnected	0b1110
IDAC1_SEL_1111_unconnected	0b1111

Definition at line 1178 of file MAX11410.h.

enum MAX11410_IDAC_MODE_enum_t

Source command CMD_r000_1010_dddd_dddd_SOURCE IDAC_MODE[3:0] field.

0000: 10uA (default)
0001: 50uA
0010: 75uA
0011: 100uA
0100: 125uA
0101: 150uA
0110: 175uA
0111: 200uA
1000: 225uA
1001: 250uA
1010: 300uA
1011: 400uA
1100: 600uA
1101: 800uA
1110: 1200uA
1111: 1600uA

Enumerator:

IDAC_MODE_0000_10uA	0b0000
IDAC_MODE_0001_50uA	0b0001
IDAC_MODE_0010_75uA	0b0010
IDAC_MODE_0011_100uA	0b0011
IDAC_MODE_0100_125uA	0b0100
IDAC_MODE_0101_150uA	0b0101
IDAC_MODE_0110_175uA	0b0110
IDAC_MODE_0111_200uA	0b0111
IDAC_MODE_1000_225uA	0b1000
IDAC_MODE_1001_250uA	0b1001
IDAC_MODE_1010_300uA	0b1010
IDAC_MODE_1011_400uA	0b1011
IDAC_MODE_1100_600uA	0b1100
IDAC_MODE_1101_800uA	0b1101
IDAC_MODE_1110_1200uA	0b1110
IDAC_MODE_1111_1600uA	0b1111

Definition at line 1058 of file MAX11410.h.

enum MAX11410_LINEF_enum_t

Filter command CMD_r000_1000_x0dd_dddd_FILTER LINEF[1:0] field.

00: Simultaneous 50/60Hz FIR rejection (default)
01: 50Hz FIR rejection
10: 60Hz FIR rejection
11: SINC4

Enumerator:

LINEF_00_50Hz_60Hz_FIR	0b00
LINEF_01_50Hz_FIR	0b01
LINEF_10_60Hz_FIR	0b10
LINEF_11_SINC4	0b11

Definition at line 847 of file MAX11410.h.

enum MAX11410_PD_enum_t

Power-down state command CMD_r000_0000_xxxx_xxdd_PD PD[1:0] field.

00: Normal mode
01: Standby mode -- Powers down all analog circuity, but not the internal voltage regulator
10: Sleep mode -- Powers down all analog circuitry including the internal voltage regulator
11: Reset -- all registers reset to POR state (Self Clearing to 01 Standby mode)

Enumerator:

PD_00_Normal	0b00
PD_01_Standby	0b01
PD_10_Sleep	0b10
PD_11_Reset	0b11

Definition at line 654 of file MAX11410.h.

enum MAX11410_RATE_enum_t