MAX11131 - Maxim Integrated MAX11131 SPI 12-bit 16-channel A…

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Maxim Integrated MAX11131 SPI 12-bit 16-channel ADC with SampleSet

Dependents: MAX11131BOB_Tester MAX11131BOB_12bit_16ch_SampleSet_SPI_ADC MAX11131BOB_Serial_Tester

MAX11131.cpp@8:2171c1889a84, 2019-10-30 (annotated)

Committer:: whismanoid
Date:: Wed Oct 30 15:36:07 2019 -0700
Revision:: 8:2171c1889a84
Parent:: 6:cb7bdeb185d0
Child:: 9:8d47cb713984

update example doc

Who changed what in which revision?

User	Revision	Line number	New contents of line
whismanoid	1:77f1ee332e4a	1	// /*******************************************************************************
whismanoid	1:77f1ee332e4a	2	// * Copyright (C) 2019 Maxim Integrated Products, Inc., All Rights Reserved.
whismanoid	1:77f1ee332e4a	3	// *
whismanoid	1:77f1ee332e4a	4	// * Permission is hereby granted, free of charge, to any person obtaining a
whismanoid	1:77f1ee332e4a	5	// * copy of this software and associated documentation files (the "Software"),
whismanoid	1:77f1ee332e4a	6	// * to deal in the Software without restriction, including without limitation
whismanoid	1:77f1ee332e4a	7	// * the rights to use, copy, modify, merge, publish, distribute, sublicense,
whismanoid	1:77f1ee332e4a	8	// * and/or sell copies of the Software, and to permit persons to whom the
whismanoid	1:77f1ee332e4a	9	// * Software is furnished to do so, subject to the following conditions:
whismanoid	1:77f1ee332e4a	10	// *
whismanoid	1:77f1ee332e4a	11	// * The above copyright notice and this permission notice shall be included
whismanoid	1:77f1ee332e4a	12	// * in all copies or substantial portions of the Software.
whismanoid	1:77f1ee332e4a	13	// *
whismanoid	1:77f1ee332e4a	14	// * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
whismanoid	1:77f1ee332e4a	15	// * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
whismanoid	1:77f1ee332e4a	16	// * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
whismanoid	1:77f1ee332e4a	17	// * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
whismanoid	1:77f1ee332e4a	18	// * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
whismanoid	1:77f1ee332e4a	19	// * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
whismanoid	1:77f1ee332e4a	20	// * OTHER DEALINGS IN THE SOFTWARE.
whismanoid	1:77f1ee332e4a	21	// *
whismanoid	1:77f1ee332e4a	22	// * Except as contained in this notice, the name of Maxim Integrated
whismanoid	1:77f1ee332e4a	23	// * Products, Inc. shall not be used except as stated in the Maxim Integrated
whismanoid	1:77f1ee332e4a	24	// * Products, Inc. Branding Policy.
whismanoid	1:77f1ee332e4a	25	// *
whismanoid	1:77f1ee332e4a	26	// * The mere transfer of this software does not imply any licenses
whismanoid	1:77f1ee332e4a	27	// * of trade secrets, proprietary technology, copyrights, patents,
whismanoid	1:77f1ee332e4a	28	// * trademarks, maskwork rights, or any other form of intellectual
whismanoid	1:77f1ee332e4a	29	// * property whatsoever. Maxim Integrated Products, Inc. retains all
whismanoid	1:77f1ee332e4a	30	// * ownership rights.
whismanoid	1:77f1ee332e4a	31	// *******************************************************************************
whismanoid	1:77f1ee332e4a	32	// */
whismanoid	1:77f1ee332e4a	33	// *********************************************************************
whismanoid	1:77f1ee332e4a	34	// @file MAX11131.cpp
whismanoid	1:77f1ee332e4a	35	// *********************************************************************
whismanoid	1:77f1ee332e4a	36	// Device Driver file
whismanoid	1:77f1ee332e4a	37	// DO NOT EDIT; except areas designated "CUSTOMIZE". Automatically generated file.
whismanoid	1:77f1ee332e4a	38	// generated by XMLSystemOfDevicesToMBED.py
whismanoid	1:77f1ee332e4a	39	// System Name = ExampleSystem
whismanoid	1:77f1ee332e4a	40	// System Description = Device driver example
whismanoid	1:77f1ee332e4a	41
whismanoid	1:77f1ee332e4a	42	#include "MAX11131.h"
whismanoid	1:77f1ee332e4a	43
whismanoid	1:77f1ee332e4a	44	// Device Name = MAX11131
whismanoid	1:77f1ee332e4a	45	// Device Description = 3Msps, Low-Power, Serial SPI 12-Bit, 16-Channel, Differential/Single-Ended Input, SAR ADC
whismanoid	6:cb7bdeb185d0	46	// Device DeviceBriefDescription = 12-bit 3Msps 16-ch ADC
whismanoid	1:77f1ee332e4a	47	// Device Manufacturer = Maxim Integrated
whismanoid	1:77f1ee332e4a	48	// Device PartNumber = MAX11131ATI+
whismanoid	1:77f1ee332e4a	49	// Device RegValue_Width = DataWidth16bit_HL
whismanoid	1:77f1ee332e4a	50	//
whismanoid	1:77f1ee332e4a	51	// ADC MaxOutputDataRate = 3Msps
whismanoid	1:77f1ee332e4a	52	// ADC NumChannels = 16
whismanoid	1:77f1ee332e4a	53	// ADC ResolutionBits = 12
whismanoid	1:77f1ee332e4a	54	//
whismanoid	1:77f1ee332e4a	55	// SPI CS = ActiveLow
whismanoid	1:77f1ee332e4a	56	// SPI FrameStart = CS
whismanoid	1:77f1ee332e4a	57	// SPI CPOL = 1
whismanoid	1:77f1ee332e4a	58	// SPI CPHA = 1
whismanoid	1:77f1ee332e4a	59	// SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid	1:77f1ee332e4a	60	// SPI SCLK Idle High
whismanoid	1:77f1ee332e4a	61	// SPI SCLKMaxMHz = 48
whismanoid	1:77f1ee332e4a	62	// SPI SCLKMinMHz = 0.48
whismanoid	1:77f1ee332e4a	63	//
whismanoid	1:77f1ee332e4a	64	// InputPin Name = CNVST
whismanoid	1:77f1ee332e4a	65	// InputPin Description = Active-Low Conversion Start Input/Analog Input 14
whismanoid	1:77f1ee332e4a	66	// InputPin Function = Trigger
whismanoid	1:77f1ee332e4a	67	//
whismanoid	1:77f1ee332e4a	68	// InputPin Name = REF+
whismanoid	1:77f1ee332e4a	69	// InputPin Description = External Positive Reference Input. Apply a reference voltage at REF+. Bypass to GND with a 0.47uF capacitor.
whismanoid	1:77f1ee332e4a	70	// InputPin Function = Reference
whismanoid	1:77f1ee332e4a	71	//
whismanoid	1:77f1ee332e4a	72	// InputPin Name = REF-/AIN15
whismanoid	1:77f1ee332e4a	73	// InputPin Description = External Differential Reference Negative Input/Analog Input 15
whismanoid	1:77f1ee332e4a	74	// InputPin Function = Reference
whismanoid	1:77f1ee332e4a	75	//
whismanoid	1:77f1ee332e4a	76	// OutputPin Name = EOC
whismanoid	1:77f1ee332e4a	77	// OutputPin Description = End of Conversion Output. Data is valid after EOC pulls low (Internal clock mode only).
whismanoid	1:77f1ee332e4a	78	// OutputPin Function = Event
whismanoid	1:77f1ee332e4a	79	//
whismanoid	1:77f1ee332e4a	80	// SupplyPin Name = VDD
whismanoid	1:77f1ee332e4a	81	// SupplyPin Description = Power-Supply Input. Bypass to GND with a 10uF in parallel with a 0.1uF capacitors.
whismanoid	1:77f1ee332e4a	82	// SupplyPin VinMax = 3.6
whismanoid	1:77f1ee332e4a	83	// SupplyPin VinMin = 2.35
whismanoid	1:77f1ee332e4a	84	// SupplyPin Function = Analog
whismanoid	1:77f1ee332e4a	85	//
whismanoid	1:77f1ee332e4a	86	// SupplyPin Name = OVDD
whismanoid	1:77f1ee332e4a	87	// SupplyPin Description = Interface Digital Power-Supply Input. Bypass to GND with a 10uF in parallel with a 0.1uF capacitors.
whismanoid	1:77f1ee332e4a	88	// SupplyPin VinMax = 3.6
whismanoid	1:77f1ee332e4a	89	// SupplyPin VinMin = 1.5
whismanoid	1:77f1ee332e4a	90	// SupplyPin Function = Digital
whismanoid	1:77f1ee332e4a	91	//
whismanoid	1:77f1ee332e4a	92
whismanoid	1:77f1ee332e4a	93	MAX11131::MAX11131(SPI &spi, DigitalOut &cs_pin, // SPI interface
whismanoid	1:77f1ee332e4a	94	DigitalOut &CNVST_pin, // Digital Trigger Input to MAX11131 device
whismanoid	6:cb7bdeb185d0	95	// AnalogOut &REF_plus_pin, // Reference Input to MAX11131 device
whismanoid	6:cb7bdeb185d0	96	// AnalogOut &REF_minus_slash_AIN15_pin, // Reference Input to MAX11131 device
whismanoid	1:77f1ee332e4a	97	DigitalIn &EOC_pin, // Digital Event Output from MAX11131 device
whismanoid	1:77f1ee332e4a	98	MAX11131_ic_t ic_variant)
whismanoid	1:77f1ee332e4a	99	: m_spi(spi), m_cs_pin(cs_pin), // SPI interface
whismanoid	1:77f1ee332e4a	100	m_CNVST_pin(CNVST_pin), // Digital Trigger Input to MAX11131 device
whismanoid	6:cb7bdeb185d0	101	// m_REF_plus_pin(REF_plus_pin), // Reference Input to MAX11131 device
whismanoid	6:cb7bdeb185d0	102	// m_REF_minus_slash_AIN15_pin(REF_minus_slash_AIN15_pin), // Reference Input to MAX11131 device
whismanoid	1:77f1ee332e4a	103	m_EOC_pin(EOC_pin), // Digital Event Output from MAX11131 device
whismanoid	1:77f1ee332e4a	104	m_ic_variant(ic_variant)
whismanoid	1:77f1ee332e4a	105	{
whismanoid	1:77f1ee332e4a	106	// SPI CS = ActiveLow
whismanoid	1:77f1ee332e4a	107	// SPI FrameStart = CS
whismanoid	1:77f1ee332e4a	108	m_SPI_cs_state = 1;
whismanoid	1:77f1ee332e4a	109	m_cs_pin = m_SPI_cs_state;
whismanoid	1:77f1ee332e4a	110
whismanoid	1:77f1ee332e4a	111	// SPI CPOL = 1
whismanoid	1:77f1ee332e4a	112	// SPI CPHA = 1
whismanoid	1:77f1ee332e4a	113	// SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid	1:77f1ee332e4a	114	// SPI SCLK Idle High
whismanoid	6:cb7bdeb185d0	115	m_SPI_dataMode = 3; //SPI_MODE3; // CPOL=1,CPHA=1: Rising Edge stable; SCLK idle High
whismanoid	1:77f1ee332e4a	116	m_spi.format(8,m_SPI_dataMode); // int bits_must_be_8, int mode=0_3 CPOL=0,CPHA=0
whismanoid	1:77f1ee332e4a	117
whismanoid	1:77f1ee332e4a	118	// SPI SCLKMaxMHz = 48
whismanoid	1:77f1ee332e4a	119	// SPI SCLKMinMHz = 0.48
whismanoid	1:77f1ee332e4a	120	//#define SPI_SCLK_Hz 48000000 // 48MHz
whismanoid	1:77f1ee332e4a	121	//#define SPI_SCLK_Hz 24000000 // 24MHz
whismanoid	1:77f1ee332e4a	122	//#define SPI_SCLK_Hz 12000000 // 12MHz
whismanoid	3:621191a7e3fd	123	//#define SPI_SCLK_Hz 6000000 // 6MHz
whismanoid	1:77f1ee332e4a	124	//#define SPI_SCLK_Hz 4000000 // 4MHz
whismanoid	1:77f1ee332e4a	125	//#define SPI_SCLK_Hz 2000000 // 2MHz
whismanoid	1:77f1ee332e4a	126	//#define SPI_SCLK_Hz 1000000 // 1MHz
whismanoid	3:621191a7e3fd	127	#if defined(TARGET_MAX32600)
whismanoid	3:621191a7e3fd	128	// MAX11131BOB_Serial_Tester on MAX32600MBED limit SCLK=6MHz
whismanoid	3:621191a7e3fd	129	m_SPI_SCLK_Hz = 6000000; // 6MHz; MAX11131 limit is 48MHz
whismanoid	3:621191a7e3fd	130	#else
whismanoid	3:621191a7e3fd	131	// all other platforms
whismanoid	1:77f1ee332e4a	132	m_SPI_SCLK_Hz = 12000000; // 12MHz; MAX11131 limit is 48MHz
whismanoid	3:621191a7e3fd	133	#endif
whismanoid	1:77f1ee332e4a	134	m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid	1:77f1ee332e4a	135
whismanoid	6:cb7bdeb185d0	136	//
whismanoid	6:cb7bdeb185d0	137	// CNVST Trigger Input to MAX11131 device
whismanoid	6:cb7bdeb185d0	138	m_CNVST_pin = 1; // output logic high -- initial value in constructor
whismanoid	1:77f1ee332e4a	139	//
whismanoid	6:cb7bdeb185d0	140	// REF_plus Reference Input to MAX11131 device
whismanoid	6:cb7bdeb185d0	141	//
whismanoid	6:cb7bdeb185d0	142	// REF_minus_slash_AIN15 Reference Input to MAX11131 device
whismanoid	6:cb7bdeb185d0	143	//
whismanoid	6:cb7bdeb185d0	144	// EOC Event Output from device
whismanoid	1:77f1ee332e4a	145	}
whismanoid	1:77f1ee332e4a	146
whismanoid	1:77f1ee332e4a	147	MAX11131::~MAX11131()
whismanoid	1:77f1ee332e4a	148	{
whismanoid	1:77f1ee332e4a	149	// do nothing
whismanoid	1:77f1ee332e4a	150	}
whismanoid	1:77f1ee332e4a	151
whismanoid	6:cb7bdeb185d0	152	/// set SPI SCLK frequency
whismanoid	1:77f1ee332e4a	153	void MAX11131::spi_frequency(int spi_sclk_Hz)
whismanoid	1:77f1ee332e4a	154	{
whismanoid	1:77f1ee332e4a	155	m_SPI_SCLK_Hz = spi_sclk_Hz;
whismanoid	1:77f1ee332e4a	156	m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid	1:77f1ee332e4a	157	}
whismanoid	1:77f1ee332e4a	158
whismanoid	1:77f1ee332e4a	159	// Assert SPI Chip Select
whismanoid	1:77f1ee332e4a	160	// SPI chip-select for MAX11131
whismanoid	1:77f1ee332e4a	161	//
whismanoid	1:77f1ee332e4a	162	void MAX11131::SPIoutputCS(int isLogicHigh)
whismanoid	1:77f1ee332e4a	163	{
whismanoid	1:77f1ee332e4a	164	m_SPI_cs_state = isLogicHigh;
whismanoid	1:77f1ee332e4a	165	m_cs_pin = m_SPI_cs_state;
whismanoid	1:77f1ee332e4a	166	}
whismanoid	1:77f1ee332e4a	167
whismanoid	1:77f1ee332e4a	168	// SPI write 16 bits
whismanoid	1:77f1ee332e4a	169	// SPI interface to MAX11131 shift 16 bits mosiData16 into MAX11131 DIN
whismanoid	1:77f1ee332e4a	170	// ignoring MAX11131 DOUT
whismanoid	1:77f1ee332e4a	171	//
whismanoid	1:77f1ee332e4a	172	void MAX11131::SPIwrite16bits(int16_t mosiData16)
whismanoid	1:77f1ee332e4a	173	{
whismanoid	1:77f1ee332e4a	174	size_t byteCount = 2;
whismanoid	1:77f1ee332e4a	175	static char mosiData[2];
whismanoid	1:77f1ee332e4a	176	static char misoData[2];
whismanoid	1:77f1ee332e4a	177	mosiData[0] = (char)((mosiData16 >> 8) & 0xFF); // MSByte
whismanoid	1:77f1ee332e4a	178	mosiData[1] = (char)((mosiData16 >> 0) & 0xFF); // LSByte
whismanoid	1:77f1ee332e4a	179	//
whismanoid	1:77f1ee332e4a	180	// Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid	1:77f1ee332e4a	181	//~ noInterrupts();
whismanoid	1:77f1ee332e4a	182	//
whismanoid	1:77f1ee332e4a	183	//~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid	1:77f1ee332e4a	184	//
whismanoid	1:77f1ee332e4a	185	unsigned int numBytesTransferred = m_spi.write(mosiData, byteCount, misoData, byteCount);
whismanoid	1:77f1ee332e4a	186	//~ m_spi.transfer(mosiData8_FF0000);
whismanoid	1:77f1ee332e4a	187	//~ m_spi.transfer(mosiData16_00FF00);
whismanoid	1:77f1ee332e4a	188	//~ m_spi.transfer(mosiData16_0000FF);
whismanoid	1:77f1ee332e4a	189	//
whismanoid	1:77f1ee332e4a	190	//~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid	1:77f1ee332e4a	191	//
whismanoid	1:77f1ee332e4a	192	// Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid	1:77f1ee332e4a	193	//~ interrupts();
whismanoid	6:cb7bdeb185d0	194	// Optional Diagnostic function to print SPI transactions
whismanoid	6:cb7bdeb185d0	195	if (onSPIprint)
whismanoid	6:cb7bdeb185d0	196	{
whismanoid	6:cb7bdeb185d0	197	onSPIprint(byteCount, (uint8_t)mosiData, (uint8_t)misoData);
whismanoid	6:cb7bdeb185d0	198	}
whismanoid	1:77f1ee332e4a	199	//
whismanoid	1:77f1ee332e4a	200	// VERIFY: SPIwrite24bits print diagnostic information
whismanoid	1:77f1ee332e4a	201	//cmdLine.serial().printf(" MOSI->"));
whismanoid	1:77f1ee332e4a	202	//cmdLine.serial().printf(" 0x"));
whismanoid	1:77f1ee332e4a	203	//Serial.print( (mosiData8_FF0000 & 0xFF), HEX);
whismanoid	1:77f1ee332e4a	204	//cmdLine.serial().printf(" 0x"));
whismanoid	1:77f1ee332e4a	205	//Serial.print( (mosiData16_00FF00 & 0xFF), HEX);
whismanoid	1:77f1ee332e4a	206	//cmdLine.serial().printf(" 0x"));
whismanoid	1:77f1ee332e4a	207	//Serial.print( (mosiData16_0000FF & 0xFF), HEX);
whismanoid	1:77f1ee332e4a	208	// hex dump mosiData[0..byteCount-1]
whismanoid	1:77f1ee332e4a	209	#if 0 // HAS_MICROUSBSERIAL
whismanoid	1:77f1ee332e4a	210	cmdLine_microUSBserial.serial().printf("\r\nSPI");
whismanoid	1:77f1ee332e4a	211	if (byteCount > 7) {
whismanoid	1:77f1ee332e4a	212	cmdLine_microUSBserial.serial().printf(" byteCount:%d", byteCount);
whismanoid	1:77f1ee332e4a	213	}
whismanoid	1:77f1ee332e4a	214	cmdLine_microUSBserial.serial().printf(" MOSI->");
whismanoid	1:77f1ee332e4a	215	for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid	1:77f1ee332e4a	216	{
whismanoid	1:77f1ee332e4a	217	cmdLine_microUSBserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid	1:77f1ee332e4a	218	}
whismanoid	1:77f1ee332e4a	219	// hex dump misoData[0..byteCount-1]
whismanoid	1:77f1ee332e4a	220	cmdLine_microUSBserial.serial().printf(" MISO<-");
whismanoid	1:77f1ee332e4a	221	for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid	1:77f1ee332e4a	222	{
whismanoid	1:77f1ee332e4a	223	cmdLine_microUSBserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid	1:77f1ee332e4a	224	}
whismanoid	1:77f1ee332e4a	225	cmdLine_microUSBserial.serial().printf(" ");
whismanoid	1:77f1ee332e4a	226	#endif
whismanoid	1:77f1ee332e4a	227	#if 0 // HAS_DAPLINK_SERIAL
whismanoid	1:77f1ee332e4a	228	cmdLine_DAPLINKserial.serial().printf("\r\nSPI");
whismanoid	1:77f1ee332e4a	229	if (byteCount > 7) {
whismanoid	1:77f1ee332e4a	230	cmdLine_DAPLINKserial.serial().printf(" byteCount:%d", byteCount);
whismanoid	1:77f1ee332e4a	231	}
whismanoid	1:77f1ee332e4a	232	cmdLine_DAPLINKserial.serial().printf(" MOSI->");
whismanoid	1:77f1ee332e4a	233	for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid	1:77f1ee332e4a	234	{
whismanoid	1:77f1ee332e4a	235	cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid	1:77f1ee332e4a	236	}
whismanoid	1:77f1ee332e4a	237	// hex dump misoData[0..byteCount-1]
whismanoid	1:77f1ee332e4a	238	cmdLine_DAPLINKserial.serial().printf(" MISO<-");
whismanoid	1:77f1ee332e4a	239	for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid	1:77f1ee332e4a	240	{
whismanoid	1:77f1ee332e4a	241	cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid	1:77f1ee332e4a	242	}
whismanoid	1:77f1ee332e4a	243	cmdLine_DAPLINKserial.serial().printf(" ");
whismanoid	1:77f1ee332e4a	244	#endif
whismanoid	1:77f1ee332e4a	245	// VERIFY: DIAGNOSTIC: print MAX5715 device register write
whismanoid	1:77f1ee332e4a	246	// TODO: MAX5715_print_register_verbose(mosiData8_FF0000, mosiData16_00FFFF);
whismanoid	1:77f1ee332e4a	247	// TODO: print_verbose_SPI_diagnostic(mosiData16_FF00, mosiData16_00FF, misoData16_FF00, misoData16_00FF);
whismanoid	1:77f1ee332e4a	248	//
whismanoid	1:77f1ee332e4a	249	// int misoData16 = (misoData16_FF00 << 8) \| misoData16_00FF;
whismanoid	1:77f1ee332e4a	250	// return misoData16;
whismanoid	1:77f1ee332e4a	251	}
whismanoid	1:77f1ee332e4a	252
whismanoid	1:77f1ee332e4a	253	// SPI write 17-24 bits
whismanoid	1:77f1ee332e4a	254	// SPI interface to MAX11131 shift 16 bits mosiData16 into MAX11131 DIN
whismanoid	1:77f1ee332e4a	255	// followed by one additional SCLK byte.
whismanoid	1:77f1ee332e4a	256	// ignoring MAX11131 DOUT
whismanoid	1:77f1ee332e4a	257	//
whismanoid	1:77f1ee332e4a	258	void MAX11131::SPIwrite24bits(int16_t mosiData16_FFFF00, int8_t mosiData8_0000FF)
whismanoid	1:77f1ee332e4a	259	{
whismanoid	1:77f1ee332e4a	260	// TODO: implement SPIwrite24bits(int16_t mosiData16_FFFF00, int8_t mosiData8_0000FF)
whismanoid	1:77f1ee332e4a	261	size_t byteCount = 3;
whismanoid	1:77f1ee332e4a	262	static char mosiData[3];
whismanoid	1:77f1ee332e4a	263	static char misoData[3];
whismanoid	1:77f1ee332e4a	264	mosiData[0] = (char)((mosiData16_FFFF00 >> 8) & 0xFF); // MSByte
whismanoid	1:77f1ee332e4a	265	mosiData[1] = (char)((mosiData16_FFFF00 >> 0) & 0xFF); // LSByte
whismanoid	1:77f1ee332e4a	266	mosiData[2] = mosiData8_0000FF;
whismanoid	1:77f1ee332e4a	267	//
whismanoid	1:77f1ee332e4a	268	// Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid	1:77f1ee332e4a	269	//~ noInterrupts();
whismanoid	1:77f1ee332e4a	270	//
whismanoid	1:77f1ee332e4a	271	//~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid	1:77f1ee332e4a	272	//
whismanoid	1:77f1ee332e4a	273	unsigned int numBytesTransferred = m_spi.write(mosiData, byteCount, misoData, byteCount);
whismanoid	1:77f1ee332e4a	274	//~ m_spi.transfer(mosiData8_FF0000);
whismanoid	1:77f1ee332e4a	275	//~ m_spi.transfer(mosiData16_00FF00);
whismanoid	1:77f1ee332e4a	276	//~ m_spi.transfer(mosiData16_0000FF);
whismanoid	1:77f1ee332e4a	277	//
whismanoid	1:77f1ee332e4a	278	//~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid	1:77f1ee332e4a	279	//
whismanoid	1:77f1ee332e4a	280	// Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid	1:77f1ee332e4a	281	//~ interrupts();
whismanoid	6:cb7bdeb185d0	282	// Optional Diagnostic function to print SPI transactions
whismanoid	6:cb7bdeb185d0	283	if (onSPIprint)
whismanoid	6:cb7bdeb185d0	284	{
whismanoid	6:cb7bdeb185d0	285	onSPIprint(byteCount, (uint8_t)mosiData, (uint8_t)misoData);
whismanoid	6:cb7bdeb185d0	286	}
whismanoid	1:77f1ee332e4a	287	//
whismanoid	1:77f1ee332e4a	288	// VERIFY: SPIwrite24bits print diagnostic information
whismanoid	1:77f1ee332e4a	289	//cmdLine.serial().printf(" MOSI->"));
whismanoid	1:77f1ee332e4a	290	//cmdLine.serial().printf(" 0x"));
whismanoid	1:77f1ee332e4a	291	//Serial.print( (mosiData8_FF0000 & 0xFF), HEX);
whismanoid	1:77f1ee332e4a	292	//cmdLine.serial().printf(" 0x"));
whismanoid	1:77f1ee332e4a	293	//Serial.print( (mosiData16_00FF00 & 0xFF), HEX);
whismanoid	1:77f1ee332e4a	294	//cmdLine.serial().printf(" 0x"));
whismanoid	1:77f1ee332e4a	295	//Serial.print( (mosiData16_0000FF & 0xFF), HEX);
whismanoid	1:77f1ee332e4a	296	// hex dump mosiData[0..byteCount-1]
whismanoid	1:77f1ee332e4a	297	#if 0 // HAS_MICROUSBSERIAL
whismanoid	1:77f1ee332e4a	298	cmdLine_microUSBserial.serial().printf("\r\nSPI");
whismanoid	1:77f1ee332e4a	299	if (byteCount > 7) {
whismanoid	1:77f1ee332e4a	300	cmdLine_microUSBserial.serial().printf(" byteCount:%d", byteCount);
whismanoid	1:77f1ee332e4a	301	}
whismanoid	1:77f1ee332e4a	302	cmdLine_microUSBserial.serial().printf(" MOSI->");
whismanoid	1:77f1ee332e4a	303	for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid	1:77f1ee332e4a	304	{
whismanoid	1:77f1ee332e4a	305	cmdLine_microUSBserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid	1:77f1ee332e4a	306	}
whismanoid	1:77f1ee332e4a	307	// hex dump misoData[0..byteCount-1]
whismanoid	1:77f1ee332e4a	308	cmdLine_microUSBserial.serial().printf(" MISO<-");
whismanoid	1:77f1ee332e4a	309	for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid	1:77f1ee332e4a	310	{
whismanoid	1:77f1ee332e4a	311	cmdLine_microUSBserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid	1:77f1ee332e4a	312	}
whismanoid	1:77f1ee332e4a	313	cmdLine_microUSBserial.serial().printf(" ");
whismanoid	1:77f1ee332e4a	314	#endif
whismanoid	1:77f1ee332e4a	315	#if 0 // HAS_DAPLINK_SERIAL
whismanoid	1:77f1ee332e4a	316	cmdLine_DAPLINKserial.serial().printf("\r\nSPI");
whismanoid	1:77f1ee332e4a	317	if (byteCount > 7) {
whismanoid	1:77f1ee332e4a	318	cmdLine_DAPLINKserial.serial().printf(" byteCount:%d", byteCount);
whismanoid	1:77f1ee332e4a	319	}
whismanoid	1:77f1ee332e4a	320	cmdLine_DAPLINKserial.serial().printf(" MOSI->");
whismanoid	1:77f1ee332e4a	321	for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid	1:77f1ee332e4a	322	{
whismanoid	1:77f1ee332e4a	323	cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid	1:77f1ee332e4a	324	}
whismanoid	1:77f1ee332e4a	325	// hex dump misoData[0..byteCount-1]
whismanoid	1:77f1ee332e4a	326	cmdLine_DAPLINKserial.serial().printf(" MISO<-");
whismanoid	1:77f1ee332e4a	327	for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid	1:77f1ee332e4a	328	{
whismanoid	1:77f1ee332e4a	329	cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid	1:77f1ee332e4a	330	}
whismanoid	1:77f1ee332e4a	331	cmdLine_DAPLINKserial.serial().printf(" ");
whismanoid	1:77f1ee332e4a	332	#endif
whismanoid	1:77f1ee332e4a	333	// VERIFY: DIAGNOSTIC: print MAX5715 device register write
whismanoid	1:77f1ee332e4a	334	// TODO: MAX5715_print_register_verbose(mosiData8_FF0000, mosiData16_00FFFF);
whismanoid	1:77f1ee332e4a	335	//
whismanoid	1:77f1ee332e4a	336	// int misoData16 = (misoData16_FF00 << 8) \| misoData16_00FF;
whismanoid	1:77f1ee332e4a	337	// return misoData16;
whismanoid	1:77f1ee332e4a	338	}
whismanoid	1:77f1ee332e4a	339
whismanoid	1:77f1ee332e4a	340	// SPI read 16 bits while MOSI (MAX11131 DIN) is 0
whismanoid	1:77f1ee332e4a	341	// SPI interface to capture 16 bits miso data from MAX11131 DOUT
whismanoid	1:77f1ee332e4a	342	//
whismanoid	1:77f1ee332e4a	343	int16_t MAX11131::SPIread16bits()
whismanoid	1:77f1ee332e4a	344	{
whismanoid	1:77f1ee332e4a	345	int mosiData16 = 0;
whismanoid	1:77f1ee332e4a	346	size_t byteCount = 2;
whismanoid	1:77f1ee332e4a	347	static char mosiData[2];
whismanoid	1:77f1ee332e4a	348	static char misoData[2];
whismanoid	1:77f1ee332e4a	349	mosiData[0] = (char)((mosiData16 >> 8) & 0xFF); // MSByte
whismanoid	1:77f1ee332e4a	350	mosiData[1] = (char)((mosiData16 >> 0) & 0xFF); // LSByte
whismanoid	1:77f1ee332e4a	351	//
whismanoid	1:77f1ee332e4a	352	// Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid	1:77f1ee332e4a	353	//~ noInterrupts();
whismanoid	1:77f1ee332e4a	354	//
whismanoid	1:77f1ee332e4a	355	//~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid	1:77f1ee332e4a	356	//
whismanoid	1:77f1ee332e4a	357	unsigned int numBytesTransferred = m_spi.write(mosiData, byteCount, misoData, byteCount);
whismanoid	1:77f1ee332e4a	358	//~ m_spi.transfer(mosiData8_FF0000);
whismanoid	1:77f1ee332e4a	359	//~ m_spi.transfer(mosiData16_00FF00);
whismanoid	1:77f1ee332e4a	360	//~ m_spi.transfer(mosiData16_0000FF);
whismanoid	1:77f1ee332e4a	361	//
whismanoid	1:77f1ee332e4a	362	//~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid	1:77f1ee332e4a	363	//
whismanoid	1:77f1ee332e4a	364	// Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid	1:77f1ee332e4a	365	//~ interrupts();
whismanoid	6:cb7bdeb185d0	366	// Optional Diagnostic function to print SPI transactions
whismanoid	6:cb7bdeb185d0	367	if (onSPIprint)
whismanoid	6:cb7bdeb185d0	368	{
whismanoid	6:cb7bdeb185d0	369	onSPIprint(byteCount, (uint8_t)mosiData, (uint8_t)misoData);
whismanoid	6:cb7bdeb185d0	370	}
whismanoid	1:77f1ee332e4a	371	//
whismanoid	1:77f1ee332e4a	372	// VERIFY: SPIwrite24bits print diagnostic information
whismanoid	1:77f1ee332e4a	373	//cmdLine.serial().printf(" MOSI->"));
whismanoid	1:77f1ee332e4a	374	//cmdLine.serial().printf(" 0x"));
whismanoid	1:77f1ee332e4a	375	//Serial.print( (mosiData8_FF0000 & 0xFF), HEX);
whismanoid	1:77f1ee332e4a	376	//cmdLine.serial().printf(" 0x"));
whismanoid	1:77f1ee332e4a	377	//Serial.print( (mosiData16_00FF00 & 0xFF), HEX);
whismanoid	1:77f1ee332e4a	378	//cmdLine.serial().printf(" 0x"));
whismanoid	1:77f1ee332e4a	379	//Serial.print( (mosiData16_0000FF & 0xFF), HEX);
whismanoid	1:77f1ee332e4a	380	// hex dump mosiData[0..byteCount-1]
whismanoid	1:77f1ee332e4a	381	#if 0 // HAS_MICROUSBSERIAL
whismanoid	1:77f1ee332e4a	382	cmdLine_microUSBserial.serial().printf("\r\nSPI");
whismanoid	1:77f1ee332e4a	383	if (byteCount > 7) {
whismanoid	1:77f1ee332e4a	384	cmdLine_microUSBserial.serial().printf(" byteCount:%d", byteCount);
whismanoid	1:77f1ee332e4a	385	}
whismanoid	1:77f1ee332e4a	386	cmdLine_microUSBserial.serial().printf(" MOSI->");
whismanoid	1:77f1ee332e4a	387	for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid	1:77f1ee332e4a	388	{
whismanoid	1:77f1ee332e4a	389	cmdLine_microUSBserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid	1:77f1ee332e4a	390	}
whismanoid	1:77f1ee332e4a	391	// hex dump misoData[0..byteCount-1]
whismanoid	1:77f1ee332e4a	392	cmdLine_microUSBserial.serial().printf(" MISO<-");
whismanoid	1:77f1ee332e4a	393	for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid	1:77f1ee332e4a	394	{
whismanoid	1:77f1ee332e4a	395	cmdLine_microUSBserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid	1:77f1ee332e4a	396	}
whismanoid	1:77f1ee332e4a	397	cmdLine_microUSBserial.serial().printf(" ");
whismanoid	1:77f1ee332e4a	398	#endif
whismanoid	1:77f1ee332e4a	399	#if 0 // HAS_DAPLINK_SERIAL
whismanoid	1:77f1ee332e4a	400	cmdLine_DAPLINKserial.serial().printf("\r\nSPI");
whismanoid	1:77f1ee332e4a	401	if (byteCount > 7) {
whismanoid	1:77f1ee332e4a	402	cmdLine_DAPLINKserial.serial().printf(" byteCount:%d", byteCount);
whismanoid	1:77f1ee332e4a	403	}
whismanoid	1:77f1ee332e4a	404	cmdLine_DAPLINKserial.serial().printf(" MOSI->");
whismanoid	1:77f1ee332e4a	405	for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid	1:77f1ee332e4a	406	{
whismanoid	1:77f1ee332e4a	407	cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid	1:77f1ee332e4a	408	}
whismanoid	1:77f1ee332e4a	409	// hex dump misoData[0..byteCount-1]
whismanoid	1:77f1ee332e4a	410	cmdLine_DAPLINKserial.serial().printf(" MISO<-");
whismanoid	1:77f1ee332e4a	411	for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid	1:77f1ee332e4a	412	{
whismanoid	1:77f1ee332e4a	413	cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid	1:77f1ee332e4a	414	}
whismanoid	1:77f1ee332e4a	415	cmdLine_DAPLINKserial.serial().printf(" ");
whismanoid	1:77f1ee332e4a	416	#endif
whismanoid	1:77f1ee332e4a	417	// VERIFY: DIAGNOSTIC: print MAX5715 device register write
whismanoid	1:77f1ee332e4a	418	// TODO: MAX5715_print_register_verbose(mosiData8_FF0000, mosiData16_00FFFF);
whismanoid	1:77f1ee332e4a	419	// TODO: print_verbose_SPI_diagnostic(mosiData16_FF00, mosiData16_00FF, misoData16_FF00, misoData16_00FF);
whismanoid	1:77f1ee332e4a	420	//
whismanoid	1:77f1ee332e4a	421	int misoData16 = (misoData[0] << 8) \| misoData[1];
whismanoid	1:77f1ee332e4a	422	return misoData16;
whismanoid	1:77f1ee332e4a	423	}
whismanoid	1:77f1ee332e4a	424
whismanoid	1:77f1ee332e4a	425	// Assert MAX11131 CNVST convert start.
whismanoid	1:77f1ee332e4a	426	// Required when using any of the InternalClock modes with SWCNV 0.
whismanoid	1:77f1ee332e4a	427	// Trigger measurement by driving CNVST/AIN14 pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	1:77f1ee332e4a	428	//
whismanoid	1:77f1ee332e4a	429	void MAX11131::CNVSToutputPulseLow()
whismanoid	1:77f1ee332e4a	430	{
whismanoid	1:77f1ee332e4a	431	// m_CNVST_pin.output(); // only applicable to DigitalInOut
whismanoid	1:77f1ee332e4a	432	m_CNVST_pin = 0; // output logic low
whismanoid	1:77f1ee332e4a	433	wait(0.01); // pulse low delay time
whismanoid	1:77f1ee332e4a	434	m_CNVST_pin = 1; // output logic high
whismanoid	1:77f1ee332e4a	435	}
whismanoid	1:77f1ee332e4a	436
whismanoid	1:77f1ee332e4a	437	// Wait for MAX11131 EOC pin low, indicating end of conversion.
whismanoid	1:77f1ee332e4a	438	// Required when using any of the InternalClock modes.
whismanoid	1:77f1ee332e4a	439	//
whismanoid	1:77f1ee332e4a	440	void MAX11131::EOCinputWaitUntilLow()
whismanoid	1:77f1ee332e4a	441	{
whismanoid	1:77f1ee332e4a	442	// m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid	1:77f1ee332e4a	443	while (m_EOC_pin != 0)
whismanoid	1:77f1ee332e4a	444	{
whismanoid	1:77f1ee332e4a	445	// spinlock waiting for logic low pin state
whismanoid	1:77f1ee332e4a	446	}
whismanoid	1:77f1ee332e4a	447	}
whismanoid	1:77f1ee332e4a	448
whismanoid	1:77f1ee332e4a	449	// Return the status of the MAX11131 EOC pin.
whismanoid	1:77f1ee332e4a	450	//
whismanoid	1:77f1ee332e4a	451	int MAX11131::EOCinputValue()
whismanoid	1:77f1ee332e4a	452	{
whismanoid	1:77f1ee332e4a	453	// m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid	1:77f1ee332e4a	454	return m_EOC_pin.read();
whismanoid	1:77f1ee332e4a	455	}
whismanoid	1:77f1ee332e4a	456
whismanoid	1:77f1ee332e4a	457	//----------------------------------------
whismanoid	6:cb7bdeb185d0	458	// Menu item '!'
whismanoid	1:77f1ee332e4a	459	// Initialize device
whismanoid	1:77f1ee332e4a	460	void MAX11131::Init(void)
whismanoid	1:77f1ee332e4a	461	{
whismanoid	1:77f1ee332e4a	462
whismanoid	1:77f1ee332e4a	463	//----------------------------------------
whismanoid	1:77f1ee332e4a	464	// Nominal Full-Scale Voltage Reference
whismanoid	1:77f1ee332e4a	465	VRef = 2.500;
whismanoid	1:77f1ee332e4a	466
whismanoid	1:77f1ee332e4a	467	//----------------------------------------
whismanoid	1:77f1ee332e4a	468	// define write-only register ADC_MODE_CONTROL
whismanoid	1:77f1ee332e4a	469	ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid	1:77f1ee332e4a	470	const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid	1:77f1ee332e4a	471	const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid	1:77f1ee332e4a	472	const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	1:77f1ee332e4a	473	const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	1:77f1ee332e4a	474	const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid	1:77f1ee332e4a	475	const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid	1:77f1ee332e4a	476
whismanoid	1:77f1ee332e4a	477	//----------------------------------------
whismanoid	1:77f1ee332e4a	478	// define write-only register ADC_CONFIGURATION
whismanoid	1:77f1ee332e4a	479	ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid	1:77f1ee332e4a	480	const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid	1:77f1ee332e4a	481	const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid	1:77f1ee332e4a	482	const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid	1:77f1ee332e4a	483	const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid	1:77f1ee332e4a	484	const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid	1:77f1ee332e4a	485	const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid	1:77f1ee332e4a	486
whismanoid	1:77f1ee332e4a	487	//----------------------------------------
whismanoid	1:77f1ee332e4a	488	// define write-only registers UNIPOLAR,BIPOLAR,RANGE
whismanoid	1:77f1ee332e4a	489	UNIPOLAR = 0x8800; //!< mosiData16 0x8800..0x8FFF format: 1 0 0 0 1 UCH0/1 UCH2/3 UCH4/5 UCH6/7 UCH8/9 UCH10/11 UCH12/13 UCH14/15 PDIFF_COM x x
whismanoid	1:77f1ee332e4a	490	BIPOLAR = 0x9000; //!< mosiData16 0x9000..0x97FF format: 1 0 0 1 0 BCH0/1 BCH2/3 BCH4/5 BCH6/7 BCH8/9 BCH10/11 BCH12/13 BCH14/15 x x x
whismanoid	1:77f1ee332e4a	491	RANGE = 0x9800; //!< mosiData16 0x9800..0x9FFF format: 1 0 0 1 1 RANGE0/1 RANGE2/3 RANGE4/5 RANGE6/7 RANGE8/9 RANGE10/11 RANGE12/13 RANGE14/15 x x x
whismanoid	1:77f1ee332e4a	492	const int AIN_0_1_LSB = 10; // UNIPOLAR.UCH0/1 BIPOLAR.BCH0/1 RANGE.RANGE0/1
whismanoid	1:77f1ee332e4a	493	const int AIN_2_3_LSB = 9; // UNIPOLAR.UCH2/3 BIPOLAR.BCH2/3 RANGE.RANGE2/3
whismanoid	1:77f1ee332e4a	494	const int AIN_4_5_LSB = 8; // UNIPOLAR.UCH4/5 BIPOLAR.BCH4/5 RANGE.RANGE4/5
whismanoid	1:77f1ee332e4a	495	const int AIN_6_7_LSB = 7; // UNIPOLAR.UCH6/7 BIPOLAR.BCH6/7 RANGE.RANGE6/7
whismanoid	1:77f1ee332e4a	496	const int AIN_8_9_LSB = 6; // UNIPOLAR.UCH8/9 BIPOLAR.BCH8/9 RANGE.RANGE8/9
whismanoid	1:77f1ee332e4a	497	const int AIN_10_11_LSB = 5; // UNIPOLAR.UCH10/11 BIPOLAR.BCH10/11 RANGE.RANGE10/11
whismanoid	1:77f1ee332e4a	498	const int AIN_12_13_LSB = 4; // UNIPOLAR.UCH12/13 BIPOLAR.BCH12/13 RANGE.RANGE12/13
whismanoid	1:77f1ee332e4a	499	const int AIN_14_15_LSB = 3; // UNIPOLAR.UCH14/15 BIPOLAR.BCH14/15 RANGE.RANGE14/15
whismanoid	1:77f1ee332e4a	500	const int PDIFF_COMM_LSB = 2; const int PDIFF_COMM_BITS = 0x01; // UNIPOLAR.PDIFF_COM
whismanoid	1:77f1ee332e4a	501	// Summary of Table 8:
whismanoid	1:77f1ee332e4a	502	// UCH0/1=0, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	503	// UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	4:8a0ae95546fa	504	// UCH0/1=0, BCH0/1=1, RANGE0/1=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	505	// UCH0/1=1, BCH0/1=1, RANGE0/1=0: reserved do not use
whismanoid	1:77f1ee332e4a	506	// UCH0/1=0, BCH0/1=0, RANGE0/1=1: reserved do not use
whismanoid	1:77f1ee332e4a	507	// UCH0/1=1, BCH0/1=0, RANGE0/1=1: reserved do not use
whismanoid	4:8a0ae95546fa	508	// UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	1:77f1ee332e4a	509	// UCH0/1=1, BCH0/1=1, RANGE0/1=1: reserved do not use
whismanoid	1:77f1ee332e4a	510	// Both channels of a differential pair must be within Input Voltage Range (dynamic signal range) 0..VREF.
whismanoid	1:77f1ee332e4a	511
whismanoid	1:77f1ee332e4a	512	//----------------------------------------
whismanoid	1:77f1ee332e4a	513	// define write-only registers CSCAN0,CSCAN1
whismanoid	1:77f1ee332e4a	514	CSCAN0 = 0xA000; //!< mosiData16 0xA000..0xA7FF format: 1 0 1 0 0 CHSCAN15 CHSCAN14 CHSCAN13 CHSCAN12 CHSCAN11 CHSCAN10 CHSCAN9 CHSCAN8 x x x
whismanoid	1:77f1ee332e4a	515	const int CHSCAN15_LSB = 10; // CSCAN0.CHSCAN15
whismanoid	1:77f1ee332e4a	516	const int CHSCAN14_LSB = 9; // CSCAN0.CHSCAN14
whismanoid	1:77f1ee332e4a	517	const int CHSCAN13_LSB = 8; // CSCAN0.CHSCAN13
whismanoid	1:77f1ee332e4a	518	const int CHSCAN12_LSB = 7; // CSCAN0.CHSCAN12
whismanoid	1:77f1ee332e4a	519	const int CHSCAN11_LSB = 6; // CSCAN0.CHSCAN11
whismanoid	1:77f1ee332e4a	520	const int CHSCAN10_LSB = 5; // CSCAN0.CHSCAN10
whismanoid	1:77f1ee332e4a	521	const int CHSCAN9_LSB = 4; // CSCAN0.CHSCAN9
whismanoid	1:77f1ee332e4a	522	const int CHSCAN8_LSB = 3; // CSCAN0.CHSCAN8
whismanoid	1:77f1ee332e4a	523	CSCAN1 = 0xA800; //!< mosiData16 0xA800..0xAFFF format: 1 0 1 0 1 CHSCAN7 CHSCAN6 CHSCAN5 CHSCAN4 CHSCAN3 CHSCAN2 CHSCAN1 CHSCAN0 x x x
whismanoid	1:77f1ee332e4a	524	const int CHSCAN7_LSB = 10; // CSCAN1.CHSCAN7
whismanoid	1:77f1ee332e4a	525	const int CHSCAN6_LSB = 9; // CSCAN1.CHSCAN6
whismanoid	1:77f1ee332e4a	526	const int CHSCAN5_LSB = 8; // CSCAN1.CHSCAN5
whismanoid	1:77f1ee332e4a	527	const int CHSCAN4_LSB = 7; // CSCAN1.CHSCAN4
whismanoid	1:77f1ee332e4a	528	const int CHSCAN3_LSB = 6; // CSCAN1.CHSCAN3
whismanoid	1:77f1ee332e4a	529	const int CHSCAN2_LSB = 5; // CSCAN1.CHSCAN2
whismanoid	1:77f1ee332e4a	530	const int CHSCAN1_LSB = 4; // CSCAN1.CHSCAN1
whismanoid	1:77f1ee332e4a	531	const int CHSCAN0_LSB = 3; // CSCAN1.CHSCAN0
whismanoid	1:77f1ee332e4a	532
whismanoid	1:77f1ee332e4a	533	//----------------------------------------
whismanoid	1:77f1ee332e4a	534	// Initialize shadow of write-only register SAMPLESET.
whismanoid	1:77f1ee332e4a	535	// Do not write to SAMPLESET at this time.
whismanoid	1:77f1ee332e4a	536	// A write to SAMPLESET must be followed by specified number of pattern entry words.
whismanoid	1:77f1ee332e4a	537	// See ScanSampleSetExternalClock function for details.
whismanoid	1:77f1ee332e4a	538	SAMPLESET = 0xB000; //!< mosiData16 0xB000..0xB7FF format: 1 0 1 1 0 SEQ_LENGTH[7:0] x x x
whismanoid	1:77f1ee332e4a	539	const int SAMPLESET_LSB = 3; const int SAMPLESET_BITS = 0xFF; // SAMPLESET.SEQ_LENGTH[7:0]
whismanoid	1:77f1ee332e4a	540
whismanoid	1:77f1ee332e4a	541	//----------------------------------------
whismanoid	1:77f1ee332e4a	542	// Reset all registers: ADC_MODE_CONTROL.RESET[1:0] = 2
whismanoid	1:77f1ee332e4a	543	ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	1:77f1ee332e4a	544	ADC_MODE_CONTROL \|= ((2 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	1:77f1ee332e4a	545
whismanoid	1:77f1ee332e4a	546	//----------------------------------------
whismanoid	1:77f1ee332e4a	547	// SPI write ADC MODE CONTROL register
whismanoid	1:77f1ee332e4a	548	// Send SPI configuration to device
whismanoid	1:77f1ee332e4a	549	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	550	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	551	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	1:77f1ee332e4a	552	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	553
whismanoid	1:77f1ee332e4a	554	#if REFSEL_0
whismanoid	1:77f1ee332e4a	555
whismanoid	1:77f1ee332e4a	556	//----------------------------------------
whismanoid	1:77f1ee332e4a	557	// Global setting for all channels: ADC_CONFIGURATION.REFSEL=0: external single-ended reference
whismanoid	1:77f1ee332e4a	558	// SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL
whismanoid	1:77f1ee332e4a	559	// SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL: EXTERNAL SINGLE-ENDED
whismanoid	1:77f1ee332e4a	560	// SELECT ADC CONFIGURATION register set REFSEL BIT TO 0
whismanoid	1:77f1ee332e4a	561	ADC_CONFIGURATION &= ~ (( REFSEL_BITS) << REFSEL_LSB); // ADC_CONFIGURATION.REFSEL=0: external single-ended reference. (For the 16-channel chips: channel AIN15 is available.)
whismanoid	1:77f1ee332e4a	562	#endif // REFSEL_0
whismanoid	1:77f1ee332e4a	563
whismanoid	1:77f1ee332e4a	564	#if REFSEL_1
whismanoid	1:77f1ee332e4a	565
whismanoid	1:77f1ee332e4a	566	//----------------------------------------
whismanoid	1:77f1ee332e4a	567	// Global setting for all channels: ADC_CONFIGURATION.REFSEL=1: external differential reference (For the 16-channel chips: channel AIN15 is unavailable, the pin is assigned to REF-.)
whismanoid	1:77f1ee332e4a	568	// SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL
whismanoid	1:77f1ee332e4a	569	// SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL: EXTERNAL DIFFERENTIAL
whismanoid	1:77f1ee332e4a	570	// SELECT ADC CONFIGURATION register set REFSEL BIT TO 1
whismanoid	1:77f1ee332e4a	571	ADC_CONFIGURATION \|= ((1 & REFSEL_BITS) << REFSEL_LSB); // ADC_CONFIGURATION.REFSEL=1: external differential reference. (For the 16-channel chips: channel AIN15 is unavailable, the pin is assigned to REF-.)
whismanoid	1:77f1ee332e4a	572	#endif // REFSEL_1
whismanoid	1:77f1ee332e4a	573
whismanoid	1:77f1ee332e4a	574	#if PDIFF_COMM_0
whismanoid	1:77f1ee332e4a	575
whismanoid	1:77f1ee332e4a	576	//----------------------------------------
whismanoid	1:77f1ee332e4a	577	// Global setting for all channels: PDIFF_COMM
whismanoid	1:77f1ee332e4a	578	UNIPOLAR &= ~ (( PDIFF_COMM_BITS) << PDIFF_COMM_LSB); // UNIPOLAR.PDIFF_COMM=0: all single-ended channels use GND as common
whismanoid	1:77f1ee332e4a	579	#endif // PDIFF_COMM_0
whismanoid	1:77f1ee332e4a	580
whismanoid	1:77f1ee332e4a	581	#if PDIFF_COMM_1
whismanoid	1:77f1ee332e4a	582
whismanoid	1:77f1ee332e4a	583	//----------------------------------------
whismanoid	1:77f1ee332e4a	584	// Global setting for all channels: PDIFF_COMM
whismanoid	1:77f1ee332e4a	585	// SELECT UNIPOLAR AND register set BIT PDIFF_COM TO 1 FOR PSEUDODIFFERENTIAL SELECTION
whismanoid	1:77f1ee332e4a	586	UNIPOLAR \|= ((1 & PDIFF_COMM_BITS) << PDIFF_COMM_LSB); // UNIPOLAR.PDIFF_COMM=1: all single-ended channels are pseudo-differential with REF- as common
whismanoid	1:77f1ee332e4a	587	#endif // PDIFF_COMM_1
whismanoid	1:77f1ee332e4a	588
whismanoid	1:77f1ee332e4a	589	#if AIN_0_1_SingleEnded
whismanoid	1:77f1ee332e4a	590
whismanoid	1:77f1ee332e4a	591	//----------------------------------------
whismanoid	1:77f1ee332e4a	592	// ADC Channels AIN0, AIN1 = Both Single-Ended, Unipolar
whismanoid	1:77f1ee332e4a	593	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	594	// Voltage per LSB count = VREF/4096
whismanoid	1:77f1ee332e4a	595	// AIN0 is a Single-Ended input using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	596	// AIN1 is a Single-Ended input using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	597	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	1:77f1ee332e4a	598	// AIN0 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	599	// AIN1 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	600	//
whismanoid	1:77f1ee332e4a	601	// SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid	1:77f1ee332e4a	602	UNIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid	1:77f1ee332e4a	603	BIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid	1:77f1ee332e4a	604	RANGE &= ~ (1 << AIN_0_1_LSB);
whismanoid	1:77f1ee332e4a	605	// UCH0/1=0, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	606	#endif // AIN_0_1_SingleEnded
whismanoid	1:77f1ee332e4a	607
whismanoid	1:77f1ee332e4a	608	#if AIN_0_1_DifferentialUnipolar
whismanoid	1:77f1ee332e4a	609
whismanoid	1:77f1ee332e4a	610	//----------------------------------------
whismanoid	1:77f1ee332e4a	611	// ADC Channels AIN0, AIN1 = Differential Unipolar (AIN0 > AIN1)
whismanoid	1:77f1ee332e4a	612	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	613	// Voltage per LSB count = VREF/4096
whismanoid	1:77f1ee332e4a	614	// AIN0, AIN1 are a Differential pair using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	615	// AIN0 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	616	// AIN1 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	617	//
whismanoid	1:77f1ee332e4a	618	// SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid	1:77f1ee332e4a	619	UNIPOLAR \|= (1 << AIN_0_1_LSB);
whismanoid	1:77f1ee332e4a	620	BIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid	1:77f1ee332e4a	621	RANGE &= ~ (1 << AIN_0_1_LSB);
whismanoid	1:77f1ee332e4a	622	// UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	623	#endif // AIN_0_1_DifferentialUnipolar
whismanoid	1:77f1ee332e4a	624
whismanoid	1:77f1ee332e4a	625	#if AIN_0_1_DifferentialBipolarFSVref
whismanoid	1:77f1ee332e4a	626
whismanoid	1:77f1ee332e4a	627	//----------------------------------------
whismanoid	1:77f1ee332e4a	628	// ADC Channels AIN0, AIN1 = Differential Bipolar
whismanoid	1:77f1ee332e4a	629	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	630	// Voltage per LSB count = VREF/4096
whismanoid	4:8a0ae95546fa	631	// AIN0, AIN1 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid	1:77f1ee332e4a	632	// AIN0 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	633	// AIN1 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	634	//
whismanoid	1:77f1ee332e4a	635	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	1:77f1ee332e4a	636	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid	1:77f1ee332e4a	637	UNIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid	1:77f1ee332e4a	638	BIPOLAR \|= (1 << AIN_0_1_LSB);
whismanoid	1:77f1ee332e4a	639	RANGE &= ~ (1 << AIN_0_1_LSB);
whismanoid	4:8a0ae95546fa	640	// UCH0/1=0, BCH0/1=1, RANGE0/1=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	641	#endif // AIN_0_1_DifferentialBipolarFSVref
whismanoid	1:77f1ee332e4a	642
whismanoid	1:77f1ee332e4a	643	#if AIN_0_1_DifferentialBipolarFS2Vref
whismanoid	1:77f1ee332e4a	644
whismanoid	1:77f1ee332e4a	645	//----------------------------------------
whismanoid	1:77f1ee332e4a	646	// ADC Channels AIN0, AIN1 = Differential Bipolar
whismanoid	1:77f1ee332e4a	647	// Full Scale = 2 * VREF
whismanoid	1:77f1ee332e4a	648	// Voltage per LSB count = VREF/2048
whismanoid	4:8a0ae95546fa	649	// AIN0, AIN1 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid	1:77f1ee332e4a	650	// AIN0 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	651	// AIN1 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	652	//
whismanoid	1:77f1ee332e4a	653	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	1:77f1ee332e4a	654	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid	1:77f1ee332e4a	655	UNIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid	1:77f1ee332e4a	656	BIPOLAR \|= (1 << AIN_0_1_LSB);
whismanoid	1:77f1ee332e4a	657	RANGE \|= (1 << AIN_0_1_LSB);
whismanoid	4:8a0ae95546fa	658	// UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	1:77f1ee332e4a	659	#endif // AIN_0_1_DifferentialBipolarFS2Vref
whismanoid	1:77f1ee332e4a	660
whismanoid	1:77f1ee332e4a	661	#if AIN_2_3_SingleEnded
whismanoid	1:77f1ee332e4a	662
whismanoid	1:77f1ee332e4a	663	//----------------------------------------
whismanoid	1:77f1ee332e4a	664	// ADC Channels AIN2, AIN3 = Both Single-Ended, Unipolar
whismanoid	1:77f1ee332e4a	665	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	666	// Voltage per LSB count = VREF/4096
whismanoid	1:77f1ee332e4a	667	// AIN2 is a Single-Ended input using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	668	// AIN3 is a Single-Ended input using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	669	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	1:77f1ee332e4a	670	// AIN2 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	671	// AIN3 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	672	//
whismanoid	1:77f1ee332e4a	673	// SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid	1:77f1ee332e4a	674	UNIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid	1:77f1ee332e4a	675	BIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid	1:77f1ee332e4a	676	RANGE &= ~ (1 << AIN_2_3_LSB);
whismanoid	1:77f1ee332e4a	677	// UCH2/3=0, BCH2/3=0, RANGE2/3=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	678	#endif // AIN_2_3_SingleEnded
whismanoid	1:77f1ee332e4a	679
whismanoid	1:77f1ee332e4a	680	#if AIN_2_3_DifferentialUnipolar
whismanoid	1:77f1ee332e4a	681
whismanoid	1:77f1ee332e4a	682	//----------------------------------------
whismanoid	1:77f1ee332e4a	683	// ADC Channels AIN2, AIN3 = Differential Unipolar (AIN2 > AIN3)
whismanoid	1:77f1ee332e4a	684	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	685	// Voltage per LSB count = VREF/4096
whismanoid	1:77f1ee332e4a	686	// AIN2, AIN3 are a Differential pair using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	687	// AIN2 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	688	// AIN3 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	689	//
whismanoid	1:77f1ee332e4a	690	// SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid	1:77f1ee332e4a	691	UNIPOLAR \|= (1 << AIN_2_3_LSB);
whismanoid	1:77f1ee332e4a	692	BIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid	1:77f1ee332e4a	693	RANGE &= ~ (1 << AIN_2_3_LSB);
whismanoid	1:77f1ee332e4a	694	// UCH2/3=1, BCH2/3=0, RANGE2/3=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	695	#endif // AIN_2_3_DifferentialUnipolar
whismanoid	1:77f1ee332e4a	696
whismanoid	1:77f1ee332e4a	697	#if AIN_2_3_DifferentialBipolarFSVref
whismanoid	1:77f1ee332e4a	698
whismanoid	1:77f1ee332e4a	699	//----------------------------------------
whismanoid	1:77f1ee332e4a	700	// ADC Channels AIN2, AIN3 = Differential Bipolar
whismanoid	1:77f1ee332e4a	701	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	702	// Voltage per LSB count = VREF/4096
whismanoid	4:8a0ae95546fa	703	// AIN2, AIN3 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid	1:77f1ee332e4a	704	// AIN2 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	705	// AIN3 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	706	//
whismanoid	1:77f1ee332e4a	707	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	1:77f1ee332e4a	708	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid	1:77f1ee332e4a	709	UNIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid	1:77f1ee332e4a	710	BIPOLAR \|= (1 << AIN_2_3_LSB);
whismanoid	1:77f1ee332e4a	711	RANGE &= ~ (1 << AIN_2_3_LSB);
whismanoid	4:8a0ae95546fa	712	// UCH2/3=0, BCH2/3=1, RANGE2/3=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	713	#endif // AIN_2_3_DifferentialBipolarFSVref
whismanoid	1:77f1ee332e4a	714
whismanoid	1:77f1ee332e4a	715	#if AIN_2_3_DifferentialBipolarFS2Vref
whismanoid	1:77f1ee332e4a	716
whismanoid	1:77f1ee332e4a	717	//----------------------------------------
whismanoid	1:77f1ee332e4a	718	// ADC Channels AIN2, AIN3 = Differential Bipolar
whismanoid	1:77f1ee332e4a	719	// Full Scale = 2 * VREF
whismanoid	1:77f1ee332e4a	720	// Voltage per LSB count = VREF/2048
whismanoid	4:8a0ae95546fa	721	// AIN2, AIN3 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid	1:77f1ee332e4a	722	// AIN2 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	723	// AIN3 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	724	//
whismanoid	1:77f1ee332e4a	725	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	1:77f1ee332e4a	726	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid	1:77f1ee332e4a	727	UNIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid	1:77f1ee332e4a	728	BIPOLAR \|= (1 << AIN_2_3_LSB);
whismanoid	1:77f1ee332e4a	729	RANGE \|= (1 << AIN_2_3_LSB);
whismanoid	4:8a0ae95546fa	730	// UCH2/3=0, BCH2/3=1, RANGE2/3=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	1:77f1ee332e4a	731	#endif // AIN_2_3_DifferentialBipolarFS2Vref
whismanoid	1:77f1ee332e4a	732
whismanoid	1:77f1ee332e4a	733	#if AIN_4_5_SingleEnded
whismanoid	1:77f1ee332e4a	734
whismanoid	1:77f1ee332e4a	735	//----------------------------------------
whismanoid	1:77f1ee332e4a	736	// ADC Channels AIN4, AIN5 = Both Single-Ended, Unipolar
whismanoid	1:77f1ee332e4a	737	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	738	// Voltage per LSB count = VREF/4096
whismanoid	1:77f1ee332e4a	739	// AIN4 is a Single-Ended input using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	740	// AIN5 is a Single-Ended input using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	741	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	1:77f1ee332e4a	742	// AIN4 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	743	// AIN5 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	744	//
whismanoid	1:77f1ee332e4a	745	// SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid	1:77f1ee332e4a	746	UNIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid	1:77f1ee332e4a	747	BIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid	1:77f1ee332e4a	748	RANGE &= ~ (1 << AIN_4_5_LSB);
whismanoid	1:77f1ee332e4a	749	// UCH4/5=0, BCH4/5=0, RANGE4/5=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	750	#endif // AIN_4_5_SingleEnded
whismanoid	1:77f1ee332e4a	751
whismanoid	1:77f1ee332e4a	752	#if AIN_4_5_DifferentialUnipolar
whismanoid	1:77f1ee332e4a	753
whismanoid	1:77f1ee332e4a	754	//----------------------------------------
whismanoid	1:77f1ee332e4a	755	// ADC Channels AIN4, AIN5 = Differential Unipolar (AIN4 > AIN5)
whismanoid	1:77f1ee332e4a	756	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	757	// Voltage per LSB count = VREF/4096
whismanoid	1:77f1ee332e4a	758	// AIN4, AIN5 are a Differential pair using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	759	// AIN4 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	760	// AIN5 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	761	//
whismanoid	1:77f1ee332e4a	762	// SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid	1:77f1ee332e4a	763	UNIPOLAR \|= (1 << AIN_4_5_LSB);
whismanoid	1:77f1ee332e4a	764	BIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid	1:77f1ee332e4a	765	RANGE &= ~ (1 << AIN_4_5_LSB);
whismanoid	1:77f1ee332e4a	766	// UCH4/5=1, BCH4/5=0, RANGE4/5=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	767	#endif // AIN_4_5_DifferentialUnipolar
whismanoid	1:77f1ee332e4a	768
whismanoid	1:77f1ee332e4a	769	#if AIN_4_5_DifferentialBipolarFSVref
whismanoid	1:77f1ee332e4a	770
whismanoid	1:77f1ee332e4a	771	//----------------------------------------
whismanoid	1:77f1ee332e4a	772	// ADC Channels AIN4, AIN5 = Differential Bipolar
whismanoid	1:77f1ee332e4a	773	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	774	// Voltage per LSB count = VREF/4096
whismanoid	4:8a0ae95546fa	775	// AIN4, AIN5 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid	1:77f1ee332e4a	776	// AIN4 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	777	// AIN5 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	778	//
whismanoid	1:77f1ee332e4a	779	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	1:77f1ee332e4a	780	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid	1:77f1ee332e4a	781	UNIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid	1:77f1ee332e4a	782	BIPOLAR \|= (1 << AIN_4_5_LSB);
whismanoid	1:77f1ee332e4a	783	RANGE &= ~ (1 << AIN_4_5_LSB);
whismanoid	4:8a0ae95546fa	784	// UCH4/5=0, BCH4/5=1, RANGE4/5=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	785	#endif // AIN_4_5_DifferentialBipolarFSVref
whismanoid	1:77f1ee332e4a	786
whismanoid	1:77f1ee332e4a	787	#if AIN_4_5_DifferentialBipolarFS2Vref
whismanoid	1:77f1ee332e4a	788
whismanoid	1:77f1ee332e4a	789	//----------------------------------------
whismanoid	1:77f1ee332e4a	790	// ADC Channels AIN4, AIN5 = Differential Bipolar
whismanoid	1:77f1ee332e4a	791	// Full Scale = 2 * VREF
whismanoid	1:77f1ee332e4a	792	// Voltage per LSB count = VREF/2048
whismanoid	4:8a0ae95546fa	793	// AIN4, AIN5 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid	1:77f1ee332e4a	794	// AIN4 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	795	// AIN5 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	796	//
whismanoid	1:77f1ee332e4a	797	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	1:77f1ee332e4a	798	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid	1:77f1ee332e4a	799	UNIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid	1:77f1ee332e4a	800	BIPOLAR \|= (1 << AIN_4_5_LSB);
whismanoid	1:77f1ee332e4a	801	RANGE \|= (1 << AIN_4_5_LSB);
whismanoid	4:8a0ae95546fa	802	// UCH4/5=0, BCH4/5=1, RANGE4/5=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	1:77f1ee332e4a	803	#endif // AIN_4_5_DifferentialBipolarFS2Vref
whismanoid	1:77f1ee332e4a	804
whismanoid	1:77f1ee332e4a	805	#if AIN_6_7_SingleEnded
whismanoid	1:77f1ee332e4a	806
whismanoid	1:77f1ee332e4a	807	//----------------------------------------
whismanoid	1:77f1ee332e4a	808	// ADC Channels AIN6, AIN7 = Both Single-Ended, Unipolar
whismanoid	1:77f1ee332e4a	809	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	810	// Voltage per LSB count = VREF/4096
whismanoid	1:77f1ee332e4a	811	// AIN6 is a Single-Ended input using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	812	// AIN7 is a Single-Ended input using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	813	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	1:77f1ee332e4a	814	// AIN6 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	815	// AIN7 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	816	//
whismanoid	1:77f1ee332e4a	817	// SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid	1:77f1ee332e4a	818	UNIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid	1:77f1ee332e4a	819	BIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid	1:77f1ee332e4a	820	RANGE &= ~ (1 << AIN_6_7_LSB);
whismanoid	1:77f1ee332e4a	821	// UCH6/7=0, BCH6/7=0, RANGE6/7=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	822	#endif // AIN_6_7_SingleEnded
whismanoid	1:77f1ee332e4a	823
whismanoid	1:77f1ee332e4a	824	#if AIN_6_7_DifferentialUnipolar
whismanoid	1:77f1ee332e4a	825
whismanoid	1:77f1ee332e4a	826	//----------------------------------------
whismanoid	1:77f1ee332e4a	827	// ADC Channels AIN6, AIN7 = Differential Unipolar (AIN6 > AIN7)
whismanoid	1:77f1ee332e4a	828	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	829	// Voltage per LSB count = VREF/4096
whismanoid	1:77f1ee332e4a	830	// AIN6, AIN7 are a Differential pair using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	831	// AIN6 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	832	// AIN7 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	833	//
whismanoid	1:77f1ee332e4a	834	// SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid	1:77f1ee332e4a	835	UNIPOLAR \|= (1 << AIN_6_7_LSB);
whismanoid	1:77f1ee332e4a	836	BIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid	1:77f1ee332e4a	837	RANGE &= ~ (1 << AIN_6_7_LSB);
whismanoid	1:77f1ee332e4a	838	// UCH6/7=1, BCH6/7=0, RANGE6/7=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	839	#endif // AIN_6_7_DifferentialUnipolar
whismanoid	1:77f1ee332e4a	840
whismanoid	1:77f1ee332e4a	841	#if AIN_6_7_DifferentialBipolarFSVref
whismanoid	1:77f1ee332e4a	842
whismanoid	1:77f1ee332e4a	843	//----------------------------------------
whismanoid	1:77f1ee332e4a	844	// ADC Channels AIN6, AIN7 = Differential Bipolar
whismanoid	1:77f1ee332e4a	845	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	846	// Voltage per LSB count = VREF/4096
whismanoid	4:8a0ae95546fa	847	// AIN6, AIN7 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid	1:77f1ee332e4a	848	// AIN6 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	849	// AIN7 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	850	//
whismanoid	1:77f1ee332e4a	851	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	1:77f1ee332e4a	852	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid	1:77f1ee332e4a	853	UNIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid	1:77f1ee332e4a	854	BIPOLAR \|= (1 << AIN_6_7_LSB);
whismanoid	1:77f1ee332e4a	855	RANGE &= ~ (1 << AIN_6_7_LSB);
whismanoid	4:8a0ae95546fa	856	// UCH6/7=0, BCH6/7=1, RANGE6/7=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	857	#endif // AIN_6_7_DifferentialBipolarFSVref
whismanoid	1:77f1ee332e4a	858
whismanoid	1:77f1ee332e4a	859	#if AIN_6_7_DifferentialBipolarFS2Vref
whismanoid	1:77f1ee332e4a	860
whismanoid	1:77f1ee332e4a	861	//----------------------------------------
whismanoid	1:77f1ee332e4a	862	// ADC Channels AIN6, AIN7 = Differential Bipolar
whismanoid	1:77f1ee332e4a	863	// Full Scale = 2 * VREF
whismanoid	1:77f1ee332e4a	864	// Voltage per LSB count = VREF/2048
whismanoid	4:8a0ae95546fa	865	// AIN6, AIN7 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid	1:77f1ee332e4a	866	// AIN6 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	867	// AIN7 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	868	//
whismanoid	1:77f1ee332e4a	869	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	1:77f1ee332e4a	870	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid	1:77f1ee332e4a	871	UNIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid	1:77f1ee332e4a	872	BIPOLAR \|= (1 << AIN_6_7_LSB);
whismanoid	1:77f1ee332e4a	873	RANGE \|= (1 << AIN_6_7_LSB);
whismanoid	4:8a0ae95546fa	874	// UCH6/7=0, BCH6/7=1, RANGE6/7=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	1:77f1ee332e4a	875	#endif // AIN_6_7_DifferentialBipolarFS2Vref
whismanoid	1:77f1ee332e4a	876
whismanoid	1:77f1ee332e4a	877	#if AIN_8_9_SingleEnded
whismanoid	1:77f1ee332e4a	878
whismanoid	1:77f1ee332e4a	879	//----------------------------------------
whismanoid	1:77f1ee332e4a	880	// ADC Channels AIN8, AIN9 = Both Single-Ended, Unipolar
whismanoid	1:77f1ee332e4a	881	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	882	// Voltage per LSB count = VREF/4096
whismanoid	1:77f1ee332e4a	883	// AIN8 is a Single-Ended input using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	884	// AIN9 is a Single-Ended input using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	885	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	1:77f1ee332e4a	886	// AIN8 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	887	// AIN9 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	888	//
whismanoid	1:77f1ee332e4a	889	// SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid	1:77f1ee332e4a	890	UNIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid	1:77f1ee332e4a	891	BIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid	1:77f1ee332e4a	892	RANGE &= ~ (1 << AIN_8_9_LSB);
whismanoid	1:77f1ee332e4a	893	// UCH8/9=0, BCH8/9=0, RANGE8/9=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	894	#endif // AIN_8_9_SingleEnded
whismanoid	1:77f1ee332e4a	895
whismanoid	1:77f1ee332e4a	896	#if AIN_8_9_DifferentialUnipolar
whismanoid	1:77f1ee332e4a	897
whismanoid	1:77f1ee332e4a	898	//----------------------------------------
whismanoid	1:77f1ee332e4a	899	// ADC Channels AIN8, AIN9 = Differential Unipolar (AIN8 > AIN9)
whismanoid	1:77f1ee332e4a	900	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	901	// Voltage per LSB count = VREF/4096
whismanoid	1:77f1ee332e4a	902	// AIN8, AIN9 are a Differential pair using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	903	// AIN8 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	904	// AIN9 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	905	//
whismanoid	1:77f1ee332e4a	906	// SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid	1:77f1ee332e4a	907	UNIPOLAR \|= (1 << AIN_8_9_LSB);
whismanoid	1:77f1ee332e4a	908	BIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid	1:77f1ee332e4a	909	RANGE &= ~ (1 << AIN_8_9_LSB);
whismanoid	1:77f1ee332e4a	910	// UCH8/9=1, BCH8/9=0, RANGE8/9=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	911	#endif // AIN_8_9_DifferentialUnipolar
whismanoid	1:77f1ee332e4a	912
whismanoid	1:77f1ee332e4a	913	#if AIN_8_9_DifferentialBipolarFSVref
whismanoid	1:77f1ee332e4a	914
whismanoid	1:77f1ee332e4a	915	//----------------------------------------
whismanoid	1:77f1ee332e4a	916	// ADC Channels AIN8, AIN9 = Differential Bipolar
whismanoid	1:77f1ee332e4a	917	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	918	// Voltage per LSB count = VREF/4096
whismanoid	4:8a0ae95546fa	919	// AIN8, AIN9 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid	1:77f1ee332e4a	920	// AIN8 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	921	// AIN9 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	922	//
whismanoid	1:77f1ee332e4a	923	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	1:77f1ee332e4a	924	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid	1:77f1ee332e4a	925	UNIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid	1:77f1ee332e4a	926	BIPOLAR \|= (1 << AIN_8_9_LSB);
whismanoid	1:77f1ee332e4a	927	RANGE &= ~ (1 << AIN_8_9_LSB);
whismanoid	4:8a0ae95546fa	928	// UCH8/9=0, BCH8/9=1, RANGE8/9=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	929	#endif // AIN_8_9_DifferentialBipolarFSVref
whismanoid	1:77f1ee332e4a	930
whismanoid	1:77f1ee332e4a	931	#if AIN_8_9_DifferentialBipolarFS2Vref
whismanoid	1:77f1ee332e4a	932
whismanoid	1:77f1ee332e4a	933	//----------------------------------------
whismanoid	1:77f1ee332e4a	934	// ADC Channels AIN8, AIN9 = Differential Bipolar
whismanoid	1:77f1ee332e4a	935	// Full Scale = 2 * VREF
whismanoid	1:77f1ee332e4a	936	// Voltage per LSB count = VREF/2048
whismanoid	4:8a0ae95546fa	937	// AIN8, AIN9 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid	1:77f1ee332e4a	938	// AIN8 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	939	// AIN9 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	940	//
whismanoid	1:77f1ee332e4a	941	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	1:77f1ee332e4a	942	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid	1:77f1ee332e4a	943	UNIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid	1:77f1ee332e4a	944	BIPOLAR \|= (1 << AIN_8_9_LSB);
whismanoid	1:77f1ee332e4a	945	RANGE \|= (1 << AIN_8_9_LSB);
whismanoid	4:8a0ae95546fa	946	// UCH8/9=0, BCH8/9=1, RANGE8/9=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	1:77f1ee332e4a	947	#endif // AIN_8_9_DifferentialBipolarFS2Vref
whismanoid	1:77f1ee332e4a	948
whismanoid	1:77f1ee332e4a	949	#if AIN_10_11_SingleEnded
whismanoid	1:77f1ee332e4a	950
whismanoid	1:77f1ee332e4a	951	//----------------------------------------
whismanoid	1:77f1ee332e4a	952	// ADC Channels AIN10, AIN11 = Both Single-Ended, Unipolar
whismanoid	1:77f1ee332e4a	953	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	954	// Voltage per LSB count = VREF/4096
whismanoid	1:77f1ee332e4a	955	// AIN10 is a Single-Ended input using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	956	// AIN11 is a Single-Ended input using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	957	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	1:77f1ee332e4a	958	// AIN10 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	959	// AIN11 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	960	//
whismanoid	1:77f1ee332e4a	961	// SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid	1:77f1ee332e4a	962	UNIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid	1:77f1ee332e4a	963	BIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid	1:77f1ee332e4a	964	RANGE &= ~ (1 << AIN_10_11_LSB);
whismanoid	1:77f1ee332e4a	965	// UCH10/11=0, BCH10/11=0, RANGE10/11=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	966	#endif // AIN_10_11_SingleEnded
whismanoid	1:77f1ee332e4a	967
whismanoid	1:77f1ee332e4a	968	#if AIN_10_11_DifferentialUnipolar
whismanoid	1:77f1ee332e4a	969
whismanoid	1:77f1ee332e4a	970	//----------------------------------------
whismanoid	1:77f1ee332e4a	971	// ADC Channels AIN10, AIN11 = Differential Unipolar (AIN10 > AIN11)
whismanoid	1:77f1ee332e4a	972	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	973	// Voltage per LSB count = VREF/4096
whismanoid	1:77f1ee332e4a	974	// AIN10, AIN11 are a Differential pair using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	975	// AIN10 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	976	// AIN11 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	977	//
whismanoid	1:77f1ee332e4a	978	// SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid	1:77f1ee332e4a	979	UNIPOLAR \|= (1 << AIN_10_11_LSB);
whismanoid	1:77f1ee332e4a	980	BIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid	1:77f1ee332e4a	981	RANGE &= ~ (1 << AIN_10_11_LSB);
whismanoid	1:77f1ee332e4a	982	// UCH10/11=1, BCH10/11=0, RANGE10/11=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	983	#endif // AIN_10_11_DifferentialUnipolar
whismanoid	1:77f1ee332e4a	984
whismanoid	1:77f1ee332e4a	985	#if AIN_10_11_DifferentialBipolarFSVref
whismanoid	1:77f1ee332e4a	986
whismanoid	1:77f1ee332e4a	987	//----------------------------------------
whismanoid	1:77f1ee332e4a	988	// ADC Channels AIN10, AIN11 = Differential Bipolar
whismanoid	1:77f1ee332e4a	989	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	990	// Voltage per LSB count = VREF/4096
whismanoid	4:8a0ae95546fa	991	// AIN10, AIN11 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid	1:77f1ee332e4a	992	// AIN10 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	993	// AIN11 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	994	//
whismanoid	1:77f1ee332e4a	995	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	1:77f1ee332e4a	996	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid	1:77f1ee332e4a	997	UNIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid	1:77f1ee332e4a	998	BIPOLAR \|= (1 << AIN_10_11_LSB);
whismanoid	1:77f1ee332e4a	999	RANGE &= ~ (1 << AIN_10_11_LSB);
whismanoid	4:8a0ae95546fa	1000	// UCH10/11=0, BCH10/11=1, RANGE10/11=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	1001	#endif // AIN_10_11_DifferentialBipolarFSVref
whismanoid	1:77f1ee332e4a	1002
whismanoid	1:77f1ee332e4a	1003	#if AIN_10_11_DifferentialBipolarFS2Vref
whismanoid	1:77f1ee332e4a	1004
whismanoid	1:77f1ee332e4a	1005	//----------------------------------------
whismanoid	1:77f1ee332e4a	1006	// ADC Channels AIN10, AIN11 = Differential Bipolar
whismanoid	1:77f1ee332e4a	1007	// Full Scale = 2 * VREF
whismanoid	1:77f1ee332e4a	1008	// Voltage per LSB count = VREF/2048
whismanoid	4:8a0ae95546fa	1009	// AIN10, AIN11 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid	1:77f1ee332e4a	1010	// AIN10 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1011	// AIN11 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1012	//
whismanoid	1:77f1ee332e4a	1013	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	1:77f1ee332e4a	1014	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid	1:77f1ee332e4a	1015	UNIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid	1:77f1ee332e4a	1016	BIPOLAR \|= (1 << AIN_10_11_LSB);
whismanoid	1:77f1ee332e4a	1017	RANGE \|= (1 << AIN_10_11_LSB);
whismanoid	4:8a0ae95546fa	1018	// UCH10/11=0, BCH10/11=1, RANGE10/11=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	1:77f1ee332e4a	1019	#endif // AIN_10_11_DifferentialBipolarFS2Vref
whismanoid	1:77f1ee332e4a	1020
whismanoid	1:77f1ee332e4a	1021	#if AIN_12_13_SingleEnded
whismanoid	1:77f1ee332e4a	1022
whismanoid	1:77f1ee332e4a	1023	//----------------------------------------
whismanoid	1:77f1ee332e4a	1024	// ADC Channels AIN12, AIN13 = Both Single-Ended, Unipolar
whismanoid	1:77f1ee332e4a	1025	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	1026	// Voltage per LSB count = VREF/4096
whismanoid	1:77f1ee332e4a	1027	// AIN12 is a Single-Ended input using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	1028	// AIN13 is a Single-Ended input using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	1029	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	1:77f1ee332e4a	1030	// AIN12 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1031	// AIN13 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1032	//
whismanoid	1:77f1ee332e4a	1033	// SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid	1:77f1ee332e4a	1034	UNIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid	1:77f1ee332e4a	1035	BIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid	1:77f1ee332e4a	1036	RANGE &= ~ (1 << AIN_12_13_LSB);
whismanoid	1:77f1ee332e4a	1037	// UCH12/13=0, BCH12/13=0, RANGE12/13=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	1038	#endif // AIN_12_13_SingleEnded
whismanoid	1:77f1ee332e4a	1039
whismanoid	1:77f1ee332e4a	1040	#if AIN_12_13_DifferentialUnipolar
whismanoid	1:77f1ee332e4a	1041
whismanoid	1:77f1ee332e4a	1042	//----------------------------------------
whismanoid	1:77f1ee332e4a	1043	// ADC Channels AIN12, AIN13 = Differential Unipolar (AIN12 > AIN13)
whismanoid	1:77f1ee332e4a	1044	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	1045	// Voltage per LSB count = VREF/4096
whismanoid	1:77f1ee332e4a	1046	// AIN12, AIN13 are a Differential pair using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	1047	// AIN12 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1048	// AIN13 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1049	//
whismanoid	1:77f1ee332e4a	1050	// SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid	1:77f1ee332e4a	1051	UNIPOLAR \|= (1 << AIN_12_13_LSB);
whismanoid	1:77f1ee332e4a	1052	BIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid	1:77f1ee332e4a	1053	RANGE &= ~ (1 << AIN_12_13_LSB);
whismanoid	1:77f1ee332e4a	1054	// UCH12/13=1, BCH12/13=0, RANGE12/13=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	1055	#endif // AIN_12_13_DifferentialUnipolar
whismanoid	1:77f1ee332e4a	1056
whismanoid	1:77f1ee332e4a	1057	#if AIN_12_13_DifferentialBipolarFSVref
whismanoid	1:77f1ee332e4a	1058
whismanoid	1:77f1ee332e4a	1059	//----------------------------------------
whismanoid	1:77f1ee332e4a	1060	// ADC Channels AIN12, AIN13 = Differential Bipolar
whismanoid	1:77f1ee332e4a	1061	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	1062	// Voltage per LSB count = VREF/4096
whismanoid	4:8a0ae95546fa	1063	// AIN12, AIN13 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid	1:77f1ee332e4a	1064	// AIN12 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1065	// AIN13 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1066	//
whismanoid	1:77f1ee332e4a	1067	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	1:77f1ee332e4a	1068	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid	1:77f1ee332e4a	1069	UNIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid	1:77f1ee332e4a	1070	BIPOLAR \|= (1 << AIN_12_13_LSB);
whismanoid	1:77f1ee332e4a	1071	RANGE &= ~ (1 << AIN_12_13_LSB);
whismanoid	4:8a0ae95546fa	1072	// UCH12/13=0, BCH12/13=1, RANGE12/13=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	1073	#endif // AIN_12_13_DifferentialBipolarFSVref
whismanoid	1:77f1ee332e4a	1074
whismanoid	1:77f1ee332e4a	1075	#if AIN_12_13_DifferentialBipolarFS2Vref
whismanoid	1:77f1ee332e4a	1076
whismanoid	1:77f1ee332e4a	1077	//----------------------------------------
whismanoid	1:77f1ee332e4a	1078	// ADC Channels AIN12, AIN13 = Differential Bipolar
whismanoid	1:77f1ee332e4a	1079	// Full Scale = 2 * VREF
whismanoid	1:77f1ee332e4a	1080	// Voltage per LSB count = VREF/2048
whismanoid	4:8a0ae95546fa	1081	// AIN12, AIN13 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid	1:77f1ee332e4a	1082	// AIN12 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1083	// AIN13 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1084	//
whismanoid	1:77f1ee332e4a	1085	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	1:77f1ee332e4a	1086	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid	1:77f1ee332e4a	1087	UNIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid	1:77f1ee332e4a	1088	BIPOLAR \|= (1 << AIN_12_13_LSB);
whismanoid	1:77f1ee332e4a	1089	RANGE \|= (1 << AIN_12_13_LSB);
whismanoid	4:8a0ae95546fa	1090	// UCH12/13=0, BCH12/13=1, RANGE12/13=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	1:77f1ee332e4a	1091	#endif // AIN_12_13_DifferentialBipolarFS2Vref
whismanoid	1:77f1ee332e4a	1092
whismanoid	1:77f1ee332e4a	1093	#if AIN_14_15_SingleEnded
whismanoid	1:77f1ee332e4a	1094
whismanoid	1:77f1ee332e4a	1095	//----------------------------------------
whismanoid	1:77f1ee332e4a	1096	// ADC Channels AIN14, AIN15 = Both Single-Ended, Unipolar
whismanoid	1:77f1ee332e4a	1097	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	1098	// Voltage per LSB count = VREF/4096
whismanoid	1:77f1ee332e4a	1099	// AIN14 is a Single-Ended input using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	1100	// AIN15 is a Single-Ended input using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	1101	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	1:77f1ee332e4a	1102	// AIN14 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1103	// AIN15 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1104	//
whismanoid	1:77f1ee332e4a	1105	// SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid	1:77f1ee332e4a	1106	UNIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid	1:77f1ee332e4a	1107	BIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid	1:77f1ee332e4a	1108	RANGE &= ~ (1 << AIN_14_15_LSB);
whismanoid	1:77f1ee332e4a	1109	// UCH14/15=0, BCH14/15=0, RANGE14/15=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	1110	#endif // AIN_14_15_SingleEnded
whismanoid	1:77f1ee332e4a	1111
whismanoid	1:77f1ee332e4a	1112	#if AIN_14_15_DifferentialUnipolar
whismanoid	1:77f1ee332e4a	1113
whismanoid	1:77f1ee332e4a	1114	//----------------------------------------
whismanoid	1:77f1ee332e4a	1115	// ADC Channels AIN14, AIN15 = Differential Unipolar (AIN14 > AIN15)
whismanoid	1:77f1ee332e4a	1116	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	1117	// Voltage per LSB count = VREF/4096
whismanoid	1:77f1ee332e4a	1118	// AIN14, AIN15 are a Differential pair using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	1119	// AIN14 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1120	// AIN15 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1121	//
whismanoid	1:77f1ee332e4a	1122	// SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid	1:77f1ee332e4a	1123	UNIPOLAR \|= (1 << AIN_14_15_LSB);
whismanoid	1:77f1ee332e4a	1124	BIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid	1:77f1ee332e4a	1125	RANGE &= ~ (1 << AIN_14_15_LSB);
whismanoid	1:77f1ee332e4a	1126	// UCH14/15=1, BCH14/15=0, RANGE14/15=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	1127	#endif // AIN_14_15_DifferentialUnipolar
whismanoid	1:77f1ee332e4a	1128
whismanoid	1:77f1ee332e4a	1129	#if AIN_14_15_DifferentialBipolarFSVref
whismanoid	1:77f1ee332e4a	1130
whismanoid	1:77f1ee332e4a	1131	//----------------------------------------
whismanoid	1:77f1ee332e4a	1132	// ADC Channels AIN14, AIN15 = Differential Bipolar
whismanoid	1:77f1ee332e4a	1133	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	1134	// Voltage per LSB count = VREF/4096
whismanoid	4:8a0ae95546fa	1135	// AIN14, AIN15 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid	1:77f1ee332e4a	1136	// AIN14 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1137	// AIN15 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1138	//
whismanoid	1:77f1ee332e4a	1139	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	1:77f1ee332e4a	1140	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid	1:77f1ee332e4a	1141	UNIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid	1:77f1ee332e4a	1142	BIPOLAR \|= (1 << AIN_14_15_LSB);
whismanoid	1:77f1ee332e4a	1143	RANGE &= ~ (1 << AIN_14_15_LSB);
whismanoid	4:8a0ae95546fa	1144	// UCH14/15=0, BCH14/15=1, RANGE14/15=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	1145	#endif // AIN_14_15_DifferentialBipolarFSVref
whismanoid	1:77f1ee332e4a	1146
whismanoid	1:77f1ee332e4a	1147	#if AIN_14_15_DifferentialBipolarFS2Vref
whismanoid	1:77f1ee332e4a	1148
whismanoid	1:77f1ee332e4a	1149	//----------------------------------------
whismanoid	1:77f1ee332e4a	1150	// ADC Channels AIN14, AIN15 = Differential Bipolar
whismanoid	1:77f1ee332e4a	1151	// Full Scale = 2 * VREF
whismanoid	1:77f1ee332e4a	1152	// Voltage per LSB count = VREF/2048
whismanoid	4:8a0ae95546fa	1153	// AIN14, AIN15 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid	1:77f1ee332e4a	1154	// AIN14 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1155	// AIN15 voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1156	//
whismanoid	1:77f1ee332e4a	1157	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	1:77f1ee332e4a	1158	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid	1:77f1ee332e4a	1159	UNIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid	1:77f1ee332e4a	1160	BIPOLAR \|= (1 << AIN_14_15_LSB);
whismanoid	1:77f1ee332e4a	1161	RANGE \|= (1 << AIN_14_15_LSB);
whismanoid	4:8a0ae95546fa	1162	// UCH14/15=0, BCH14/15=1, RANGE14/15=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	1:77f1ee332e4a	1163	#endif // AIN_14_15_DifferentialBipolarFS2Vref
whismanoid	1:77f1ee332e4a	1164
whismanoid	1:77f1ee332e4a	1165	//----------------------------------------
whismanoid	1:77f1ee332e4a	1166	// SPI write ADC CONFIGURATION register
whismanoid	1:77f1ee332e4a	1167	// Send SPI configuration to device
whismanoid	1:77f1ee332e4a	1168	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	1169	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1170	SPIwrite16bits(ADC_CONFIGURATION);
whismanoid	1:77f1ee332e4a	1171	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1172
whismanoid	1:77f1ee332e4a	1173	//----------------------------------------
whismanoid	1:77f1ee332e4a	1174	// SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid	1:77f1ee332e4a	1175	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	1176	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1177	SPIwrite16bits(UNIPOLAR);
whismanoid	1:77f1ee332e4a	1178	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1179	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1180	SPIwrite16bits(BIPOLAR);
whismanoid	1:77f1ee332e4a	1181	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1182	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1183	SPIwrite16bits(RANGE);
whismanoid	1:77f1ee332e4a	1184	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1185
whismanoid	1:77f1ee332e4a	1186	//----------------------------------------
whismanoid	1:77f1ee332e4a	1187	// SPI write CSCAN0 CSCAN1 registers
whismanoid	1:77f1ee332e4a	1188	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	1189	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1190	SPIwrite16bits(CSCAN0);
whismanoid	1:77f1ee332e4a	1191	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1192	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1193	SPIwrite16bits(CSCAN1);
whismanoid	1:77f1ee332e4a	1194	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1195	}
whismanoid	1:77f1ee332e4a	1196
whismanoid	1:77f1ee332e4a	1197	//----------------------------------------
whismanoid	6:cb7bdeb185d0	1198	// Menu item 'IS'
whismanoid	1:77f1ee332e4a	1199	// ADC Channels AIN(channelId), AIN(channelId+1) = Both Single-Ended, Unipolar
whismanoid	1:77f1ee332e4a	1200	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	1201	// Voltage per LSB count = VREF/4096
whismanoid	1:77f1ee332e4a	1202	// AIN(channelId) is a Single-Ended input using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	1203	// AIN(channelId+1) is a Single-Ended input using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	1204	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	1:77f1ee332e4a	1205	// AIN(channelId) voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1206	// AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1207	//
whismanoid	6:cb7bdeb185d0	1208	void MAX11131::Reconfigure_SingleEnded(int channel_0_15)
whismanoid	1:77f1ee332e4a	1209	{
whismanoid	1:77f1ee332e4a	1210
whismanoid	1:77f1ee332e4a	1211	//----------------------------------------
whismanoid	1:77f1ee332e4a	1212	// UCH(ch)/(ch+1)=0, BCH(ch)/(ch+1)=0, RANGE(ch)/(ch+1)=0:
whismanoid	1:77f1ee332e4a	1213	// AIN(ch)/AIN(ch+1) two independent single-ended inputs,
whismanoid	1:77f1ee332e4a	1214	// unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	1215	//
whismanoid	6:cb7bdeb185d0	1216	const int channelPairIndex = channel_0_15 / 2;
whismanoid	1:77f1ee332e4a	1217	const int bitmask = (1 << (10 - channelPairIndex));
whismanoid	1:77f1ee332e4a	1218	UNIPOLAR &= ~ bitmask;
whismanoid	1:77f1ee332e4a	1219	BIPOLAR &= ~ bitmask;
whismanoid	1:77f1ee332e4a	1220	RANGE &= ~ bitmask;
whismanoid	1:77f1ee332e4a	1221
whismanoid	1:77f1ee332e4a	1222	//----------------------------------------
whismanoid	1:77f1ee332e4a	1223	// SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid	1:77f1ee332e4a	1224	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	1225	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1226	SPIwrite16bits(UNIPOLAR);
whismanoid	1:77f1ee332e4a	1227	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1228	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1229	SPIwrite16bits(BIPOLAR);
whismanoid	1:77f1ee332e4a	1230	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1231	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1232	SPIwrite16bits(RANGE);
whismanoid	1:77f1ee332e4a	1233	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1234	}
whismanoid	1:77f1ee332e4a	1235
whismanoid	1:77f1ee332e4a	1236	//----------------------------------------
whismanoid	6:cb7bdeb185d0	1237	// Menu item 'IU'
whismanoid	1:77f1ee332e4a	1238	// ADC Channels AIN(channelId), AIN(channelId+1) = Differential Unipolar (AIN(channelId) > AIN(channelId+1))
whismanoid	1:77f1ee332e4a	1239	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	1240	// Voltage per LSB count = VREF/4096
whismanoid	1:77f1ee332e4a	1241	// AIN(channelId), AIN(channelId+1) are a Differential pair using Unipolar transfer function.
whismanoid	1:77f1ee332e4a	1242	// AIN(channelId) voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1243	// AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1244	//
whismanoid	6:cb7bdeb185d0	1245	void MAX11131::Reconfigure_DifferentialUnipolar(int channel_0_15)
whismanoid	1:77f1ee332e4a	1246	{
whismanoid	1:77f1ee332e4a	1247
whismanoid	1:77f1ee332e4a	1248	//----------------------------------------
whismanoid	1:77f1ee332e4a	1249	// UCH(ch)/(ch+1)=1, BCH(ch)/(ch+1)=0, RANGE(ch)/(ch+1)=0:
whismanoid	1:77f1ee332e4a	1250	// AIN(ch)/AIN(ch+1) differential input pair,
whismanoid	1:77f1ee332e4a	1251	// unipolar code (AIN(ch)>AIN(ch+1)) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	1252	//
whismanoid	6:cb7bdeb185d0	1253	const int channelPairIndex = channel_0_15 / 2;
whismanoid	1:77f1ee332e4a	1254	const int bitmask = (1 << (10 - channelPairIndex));
whismanoid	1:77f1ee332e4a	1255	UNIPOLAR \|= bitmask;
whismanoid	1:77f1ee332e4a	1256	BIPOLAR &= ~ bitmask;
whismanoid	1:77f1ee332e4a	1257	RANGE &= ~ bitmask;
whismanoid	1:77f1ee332e4a	1258	// UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	1259
whismanoid	1:77f1ee332e4a	1260	//----------------------------------------
whismanoid	1:77f1ee332e4a	1261	// SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid	1:77f1ee332e4a	1262	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	1263	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1264	SPIwrite16bits(UNIPOLAR);
whismanoid	1:77f1ee332e4a	1265	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1266	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1267	SPIwrite16bits(BIPOLAR);
whismanoid	1:77f1ee332e4a	1268	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1269	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1270	SPIwrite16bits(RANGE);
whismanoid	1:77f1ee332e4a	1271	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1272	}
whismanoid	1:77f1ee332e4a	1273
whismanoid	1:77f1ee332e4a	1274	//----------------------------------------
whismanoid	6:cb7bdeb185d0	1275	// Menu item 'IB'
whismanoid	1:77f1ee332e4a	1276	// ADC Channels AIN(channelId), AIN(channelId+1) = Differential Bipolar
whismanoid	1:77f1ee332e4a	1277	// Full Scale = VREF
whismanoid	1:77f1ee332e4a	1278	// Voltage per LSB count = VREF/4096
whismanoid	4:8a0ae95546fa	1279	// AIN(channelId), AIN(channelId+1) are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid	1:77f1ee332e4a	1280	// AIN(channelId) voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1281	// AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1282	//
whismanoid	6:cb7bdeb185d0	1283	void MAX11131::Reconfigure_DifferentialBipolarFSVref(int channel_0_15)
whismanoid	1:77f1ee332e4a	1284	{
whismanoid	1:77f1ee332e4a	1285
whismanoid	1:77f1ee332e4a	1286	//----------------------------------------
whismanoid	1:77f1ee332e4a	1287	// UCH(ch)/(ch+1)=0, BCH(ch)/(ch+1)=1, RANGE(ch)/(ch+1)=0:
whismanoid	4:8a0ae95546fa	1288	// AIN(ch)/AIN(ch+1) differential input pair (+/-)(1/2)Vref,
whismanoid	1:77f1ee332e4a	1289	// bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	1290	//
whismanoid	6:cb7bdeb185d0	1291	const int channelPairIndex = channel_0_15 / 2;
whismanoid	1:77f1ee332e4a	1292	const int bitmask = (1 << (10 - channelPairIndex));
whismanoid	1:77f1ee332e4a	1293	UNIPOLAR &= ~ bitmask;
whismanoid	1:77f1ee332e4a	1294	BIPOLAR \|= bitmask;
whismanoid	1:77f1ee332e4a	1295	RANGE &= ~ bitmask;
whismanoid	1:77f1ee332e4a	1296
whismanoid	1:77f1ee332e4a	1297	//----------------------------------------
whismanoid	1:77f1ee332e4a	1298	// SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid	1:77f1ee332e4a	1299	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	1300	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1301	SPIwrite16bits(UNIPOLAR);
whismanoid	1:77f1ee332e4a	1302	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1303	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1304	SPIwrite16bits(BIPOLAR);
whismanoid	1:77f1ee332e4a	1305	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1306	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1307	SPIwrite16bits(RANGE);
whismanoid	1:77f1ee332e4a	1308	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1309	}
whismanoid	1:77f1ee332e4a	1310
whismanoid	1:77f1ee332e4a	1311	//----------------------------------------
whismanoid	6:cb7bdeb185d0	1312	// Menu item 'IR'
whismanoid	1:77f1ee332e4a	1313	// ADC Channels AIN(channelId), AIN(channelId+1) = Differential Bipolar
whismanoid	1:77f1ee332e4a	1314	// Full Scale = 2 * VREF
whismanoid	1:77f1ee332e4a	1315	// Voltage per LSB count = VREF/2048
whismanoid	4:8a0ae95546fa	1316	// AIN(channelId), AIN(channelId+1) are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid	1:77f1ee332e4a	1317	// AIN(channelId) voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1318	// AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid	1:77f1ee332e4a	1319	//
whismanoid	6:cb7bdeb185d0	1320	void MAX11131::Reconfigure_DifferentialBipolarFS2Vref(int channel_0_15)
whismanoid	1:77f1ee332e4a	1321	{
whismanoid	1:77f1ee332e4a	1322
whismanoid	1:77f1ee332e4a	1323	//----------------------------------------
whismanoid	1:77f1ee332e4a	1324	// UCH(ch)/(ch+1)=0, BCH(ch)/(ch+1)=1, RANGE(ch)/(ch+1)=1:
whismanoid	4:8a0ae95546fa	1325	// AIN(ch)/AIN(ch+1) differential input pair (+/-)Vref,
whismanoid	1:77f1ee332e4a	1326	// bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	1:77f1ee332e4a	1327	//
whismanoid	6:cb7bdeb185d0	1328	const int channelPairIndex = channel_0_15 / 2;
whismanoid	1:77f1ee332e4a	1329	const int bitmask = (1 << (10 - channelPairIndex));
whismanoid	1:77f1ee332e4a	1330	UNIPOLAR &= ~ bitmask;
whismanoid	1:77f1ee332e4a	1331	BIPOLAR \|= bitmask;
whismanoid	1:77f1ee332e4a	1332	RANGE \|= bitmask;
whismanoid	4:8a0ae95546fa	1333	// UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	1:77f1ee332e4a	1334
whismanoid	1:77f1ee332e4a	1335	//----------------------------------------
whismanoid	1:77f1ee332e4a	1336	// SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid	1:77f1ee332e4a	1337	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	1338	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1339	SPIwrite16bits(UNIPOLAR);
whismanoid	1:77f1ee332e4a	1340	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1341	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1342	SPIwrite16bits(BIPOLAR);
whismanoid	1:77f1ee332e4a	1343	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1344	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1345	SPIwrite16bits(RANGE);
whismanoid	1:77f1ee332e4a	1346	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1347	}
whismanoid	1:77f1ee332e4a	1348
whismanoid	1:77f1ee332e4a	1349	//----------------------------------------
whismanoid	1:77f1ee332e4a	1350	// SCAN_0000_NOP
whismanoid	1:77f1ee332e4a	1351	//
whismanoid	1:77f1ee332e4a	1352	// Shift 16 bits out of ADC, without changing configuration.
whismanoid	1:77f1ee332e4a	1353	// Note: @return data format depends on CHAN_ID bit:
whismanoid	1:77f1ee332e4a	1354	// "CH[3:0] DATA[11:0]" when CHAN_ID = 1, or
whismanoid	1:77f1ee332e4a	1355	// "0 DATA[11:0] x x x" when CHAN_ID = 0.
whismanoid	1:77f1ee332e4a	1356	int16_t MAX11131::ScanRead(void)
whismanoid	1:77f1ee332e4a	1357	{
whismanoid	1:77f1ee332e4a	1358
whismanoid	1:77f1ee332e4a	1359	//----------------------------------------
whismanoid	1:77f1ee332e4a	1360	// Read SPI data from device while MOSI (Maxim DIN) is 0. Effectively ADC_MODE_CONTROL SCAN[3:0] = SCAN_0000_NOP = 0
whismanoid	1:77f1ee332e4a	1361	SPI_MOSI_Semantic = 0; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	1362	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1363	int16_t misoData16 = SPIread16bits();
whismanoid	1:77f1ee332e4a	1364	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1365	// For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid	1:77f1ee332e4a	1366	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	1:77f1ee332e4a	1367	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	1368	// For internal clock modes, the data format always includes the channel address.
whismanoid	1:77f1ee332e4a	1369	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	1370	return misoData16;
whismanoid	1:77f1ee332e4a	1371	}
whismanoid	0:f7d706d2904d	1372
whismanoid	1:77f1ee332e4a	1373	//----------------------------------------
whismanoid	1:77f1ee332e4a	1374	// SCAN_0000_NOP
whismanoid	1:77f1ee332e4a	1375	//
whismanoid	1:77f1ee332e4a	1376	// Read raw ADC codes from device into AINcode[] and RAW_misoData16[].
whismanoid	1:77f1ee332e4a	1377	// If internal clock mode with SWCNV=0, measurements will be triggered using CNVST pin.
whismanoid	1:77f1ee332e4a	1378	//
whismanoid	1:77f1ee332e4a	1379	// @pre one of the Scan functions was called, setting NumWords
whismanoid	6:cb7bdeb185d0	1380	// @param[in] NumWords: number of words to be read from the FIFO
whismanoid	1:77f1ee332e4a	1381	// @post RAW_misoData16[index] contains the raw SPI Master-In,Slave-Out data
whismanoid	1:77f1ee332e4a	1382	// @post AINcode[NUM_CHANNELS] contains the latest readings in LSBs
whismanoid	1:77f1ee332e4a	1383	//
whismanoid	1:77f1ee332e4a	1384	void MAX11131::ReadAINcode(void)
whismanoid	1:77f1ee332e4a	1385	{
whismanoid	1:77f1ee332e4a	1386
whismanoid	1:77f1ee332e4a	1387	//----------------------------------------
whismanoid	1:77f1ee332e4a	1388	// loop index for RAW_misoData16[SAMPLESET_MAX_ENTRIES];
whismanoid	1:77f1ee332e4a	1389	int index;
whismanoid	1:77f1ee332e4a	1390
whismanoid	1:77f1ee332e4a	1391	//----------------------------------------
whismanoid	1:77f1ee332e4a	1392	// If internal clock mode with SWCNV=0, trigger measurement using CNVST pin and wait for EOC pin.
whismanoid	1:77f1ee332e4a	1393	if (isExternalClock == 0)
whismanoid	1:77f1ee332e4a	1394	{
whismanoid	1:77f1ee332e4a	1395	if (swcnv_0_1 == 0)
whismanoid	1:77f1ee332e4a	1396	{
whismanoid	1:77f1ee332e4a	1397	// SWCNV=0: trigger measurement by driving CNVST/AIN14 pin low
whismanoid	1:77f1ee332e4a	1398	// for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	1:77f1ee332e4a	1399	// One CNVST pulse scans all requested channels and stores the results in the FIFO.
whismanoid	1:77f1ee332e4a	1400	CNVSToutputPulseLow();
whismanoid	1:77f1ee332e4a	1401	}
whismanoid	1:77f1ee332e4a	1402	// wait for EOC low (internal clock mode end of conversion)
whismanoid	1:77f1ee332e4a	1403	EOCinputWaitUntilLow();
whismanoid	1:77f1ee332e4a	1404	}
whismanoid	1:77f1ee332e4a	1405
whismanoid	1:77f1ee332e4a	1406	//----------------------------------------
whismanoid	1:77f1ee332e4a	1407	// Read raw ADC codes from device into AINcode[] and RAW_misoData16[].
whismanoid	1:77f1ee332e4a	1408	// For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid	1:77f1ee332e4a	1409	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	1:77f1ee332e4a	1410	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	1411	// For internal clock modes, the data format always includes the channel address.
whismanoid	1:77f1ee332e4a	1412	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	1413	switch(ScanMode)
whismanoid	1:77f1ee332e4a	1414	{
whismanoid	1:77f1ee332e4a	1415	//----------------------------------------
whismanoid	1:77f1ee332e4a	1416	// read data words
whismanoid	1:77f1ee332e4a	1417	// For internal clock modes, the data format always includes the channel address.
whismanoid	1:77f1ee332e4a	1418	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	1419	case SCAN_0000_NOP:
whismanoid	1:77f1ee332e4a	1420	case SCAN_0011_StandardInternalClock:
whismanoid	1:77f1ee332e4a	1421	case SCAN_0101_UpperInternalClock:
whismanoid	1:77f1ee332e4a	1422	case SCAN_0111_CustomInternalClock:
whismanoid	1:77f1ee332e4a	1423	default:
whismanoid	1:77f1ee332e4a	1424	for (index = 0; index < NumWords; index++) {
whismanoid	1:77f1ee332e4a	1425	RAW_misoData16[index] = ScanRead();
whismanoid	1:77f1ee332e4a	1426	// For internal clock modes, the data format always includes the channel address.
whismanoid	1:77f1ee332e4a	1427	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	1428	int16_t value_u12 = (RAW_misoData16[index] & 0x0FFF);
whismanoid	1:77f1ee332e4a	1429	int channelId = ((RAW_misoData16[index] >> 12) & 0x000F);
whismanoid	1:77f1ee332e4a	1430	AINcode[channelId] = value_u12;
whismanoid	1:77f1ee332e4a	1431	}
whismanoid	1:77f1ee332e4a	1432	break;
whismanoid	1:77f1ee332e4a	1433	//----------------------------------------
whismanoid	1:77f1ee332e4a	1434	// read data words
whismanoid	1:77f1ee332e4a	1435	// For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid	1:77f1ee332e4a	1436	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	1:77f1ee332e4a	1437	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	1438	// For internal clock modes, the data format always includes the channel address.
whismanoid	1:77f1ee332e4a	1439	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	1440	case SCAN_0001_Manual:
whismanoid	1:77f1ee332e4a	1441	case SCAN_0100_StandardExternalClock:
whismanoid	1:77f1ee332e4a	1442	case SCAN_0110_UpperExternalClock:
whismanoid	1:77f1ee332e4a	1443	case SCAN_1000_CustomExternalClock:
whismanoid	1:77f1ee332e4a	1444	case SCAN_1001_SampleSetExternalClock:
whismanoid	1:77f1ee332e4a	1445	if (chan_id_0_1 != 0) {
whismanoid	1:77f1ee332e4a	1446	for (index = 0; index < NumWords; index++) {
whismanoid	1:77f1ee332e4a	1447	RAW_misoData16[index] = ScanRead();
whismanoid	1:77f1ee332e4a	1448	// For internal clock modes, the data format always includes the channel address.
whismanoid	1:77f1ee332e4a	1449	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	1450	int16_t value_u12 = (RAW_misoData16[index] & 0x0FFF);
whismanoid	1:77f1ee332e4a	1451	int channelId = ((RAW_misoData16[index] >> 12) & 0x000F);
whismanoid	1:77f1ee332e4a	1452	AINcode[channelId] = value_u12;
whismanoid	1:77f1ee332e4a	1453	}
whismanoid	1:77f1ee332e4a	1454	} else {
whismanoid	1:77f1ee332e4a	1455	for (index = 0; index < NumWords; index++) {
whismanoid	1:77f1ee332e4a	1456	RAW_misoData16[index] = ScanRead();
whismanoid	1:77f1ee332e4a	1457	int16_t value_u12 = ((RAW_misoData16[index] >> 3) & 0x0FFF);
whismanoid	1:77f1ee332e4a	1458	int channelId = channelNumber_0_15;
whismanoid	1:77f1ee332e4a	1459	AINcode[channelId] = value_u12;
whismanoid	1:77f1ee332e4a	1460	}
whismanoid	1:77f1ee332e4a	1461	}
whismanoid	1:77f1ee332e4a	1462	break;
whismanoid	1:77f1ee332e4a	1463	//----------------------------------------
whismanoid	1:77f1ee332e4a	1464	// read data words and calculate mean, stddev
whismanoid	1:77f1ee332e4a	1465	case SCAN_0010_Repeat:
whismanoid	1:77f1ee332e4a	1466	// ScanRead_nWords_chanID_mean(NumWords); // TODO1: missing function
whismanoid	1:77f1ee332e4a	1467	// was this function AINcode_print_value_chanID_mean(int nWords) in main?
whismanoid	1:77f1ee332e4a	1468	// But this function prints to standard output so can't be inside the driver.
whismanoid	1:77f1ee332e4a	1469	for (index = 0; index < NumWords; index++) {
whismanoid	1:77f1ee332e4a	1470	RAW_misoData16[index] = ScanRead();
whismanoid	1:77f1ee332e4a	1471	}
whismanoid	1:77f1ee332e4a	1472	break;
whismanoid	1:77f1ee332e4a	1473	}
whismanoid	1:77f1ee332e4a	1474	}
whismanoid	1:77f1ee332e4a	1475
whismanoid	1:77f1ee332e4a	1476	//----------------------------------------
whismanoid	1:77f1ee332e4a	1477	// Sign-Extend a right-aligned MAX11131 code into a signed 2's complement value.
whismanoid	1:77f1ee332e4a	1478	// Supports the bipolar transfer functions.
whismanoid	1:77f1ee332e4a	1479	// @param[in] value_u12: raw 12-bit MAX11131 code (right justified).
whismanoid	1:77f1ee332e4a	1480	// @return sign-extended 2's complement value.
whismanoid	1:77f1ee332e4a	1481	//
whismanoid	1:77f1ee332e4a	1482	int32_t MAX11131::TwosComplementValue(uint32_t regValue)
whismanoid	1:77f1ee332e4a	1483	{
whismanoid	1:77f1ee332e4a	1484	const uint16_t SIGN_BIT_12BIT = 0x0800;
whismanoid	1:77f1ee332e4a	1485	const uint16_t FULL_SCALE_CODE_12BIT = 0x0fff;
whismanoid	1:77f1ee332e4a	1486	if (((regValue & SIGN_BIT_12BIT) != 0) && !((regValue & (SIGN_BIT_12BIT << 1)) != 0))
whismanoid	1:77f1ee332e4a	1487	{
whismanoid	1:77f1ee332e4a	1488	// (bSignBitNegative && !bExtendedSignBitNegative)
whismanoid	1:77f1ee332e4a	1489	// Twos_Complement negative value
whismanoid	1:77f1ee332e4a	1490	int32_t Offset_regValue = (int32_t)(regValue - (FULL_SCALE_CODE_12BIT + 1));
whismanoid	1:77f1ee332e4a	1491	return Offset_regValue;
whismanoid	1:77f1ee332e4a	1492	}
whismanoid	1:77f1ee332e4a	1493	// Twos_Complement positive value or zero
whismanoid	1:77f1ee332e4a	1494	return (int32_t)regValue;
whismanoid	1:77f1ee332e4a	1495	}
whismanoid	1:77f1ee332e4a	1496
whismanoid	1:77f1ee332e4a	1497	//----------------------------------------
whismanoid	1:77f1ee332e4a	1498	// Return the physical voltage corresponding to MAX11131 code.
whismanoid	1:77f1ee332e4a	1499	// Does not perform any offset or gain correction.
whismanoid	1:77f1ee332e4a	1500	// @pre VRef = Voltage of REF input, in Volts
whismanoid	1:77f1ee332e4a	1501	// @param[in] value_u12: raw 12-bit MAX11131 code (right justified).
whismanoid	1:77f1ee332e4a	1502	// @param[in] channelId: AIN channel number.
whismanoid	1:77f1ee332e4a	1503	// @return physical voltage corresponding to MAX11131 code.
whismanoid	1:77f1ee332e4a	1504	//
whismanoid	1:77f1ee332e4a	1505	double MAX11131::VoltageOfCode(int16_t value_u12, int channelId)
whismanoid	1:77f1ee332e4a	1506	{
whismanoid	1:77f1ee332e4a	1507	int channelPairIndex = channelId / 2;
whismanoid	1:77f1ee332e4a	1508	// format: 1 0 0 0 1 UCH0/1 UCH2/3 UCH4/5 UCH6/7 UCH8/9 UCH10/11 UCH12/13 UCH14/15 PDIFF_COM x x
whismanoid	1:77f1ee332e4a	1509	int UCHn = (UNIPOLAR >> (10 - channelPairIndex)) & 0x01;
whismanoid	1:77f1ee332e4a	1510	int BCHn = (BIPOLAR >> (10 - channelPairIndex)) & 0x01;
whismanoid	1:77f1ee332e4a	1511	int RANGEn = (RANGE >> (10 - channelPairIndex)) & 0x01;
whismanoid	1:77f1ee332e4a	1512	if (UCHn)
whismanoid	1:77f1ee332e4a	1513	{
whismanoid	1:77f1ee332e4a	1514	// UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	1515	return (value_u12 * VRef / 4096);
whismanoid	1:77f1ee332e4a	1516	}
whismanoid	1:77f1ee332e4a	1517	else
whismanoid	1:77f1ee332e4a	1518	{
whismanoid	1:77f1ee332e4a	1519	if (BCHn)
whismanoid	1:77f1ee332e4a	1520	{
whismanoid	1:77f1ee332e4a	1521	if (RANGEn)
whismanoid	1:77f1ee332e4a	1522	{
whismanoid	4:8a0ae95546fa	1523	// UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	1:77f1ee332e4a	1524	return (TwosComplementValue(value_u12) * VRef / 2048);
whismanoid	1:77f1ee332e4a	1525	}
whismanoid	1:77f1ee332e4a	1526	else
whismanoid	1:77f1ee332e4a	1527	{
whismanoid	4:8a0ae95546fa	1528	// UCH0/1=0, BCH0/1=1, RANGE0/1=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	1529	return (TwosComplementValue(value_u12) * VRef / 4096);
whismanoid	1:77f1ee332e4a	1530	}
whismanoid	1:77f1ee332e4a	1531	}
whismanoid	1:77f1ee332e4a	1532	else
whismanoid	1:77f1ee332e4a	1533	{
whismanoid	1:77f1ee332e4a	1534	// UCH0/1=0, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	1:77f1ee332e4a	1535	return (value_u12 * VRef / 4096);
whismanoid	1:77f1ee332e4a	1536	}
whismanoid	1:77f1ee332e4a	1537	}
whismanoid	1:77f1ee332e4a	1538	}
whismanoid	1:77f1ee332e4a	1539
whismanoid	1:77f1ee332e4a	1540	//----------------------------------------
whismanoid	1:77f1ee332e4a	1541	// SCAN_0001_Manual
whismanoid	1:77f1ee332e4a	1542	//
whismanoid	1:77f1ee332e4a	1543	// Measure ADC channel channelNumber_0_15 once.
whismanoid	1:77f1ee332e4a	1544	// External clock mode.
whismanoid	1:77f1ee332e4a	1545	// @param[in] channelNumber_0_15: AIN Channel Number
whismanoid	1:77f1ee332e4a	1546	// @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	1:77f1ee332e4a	1547	// @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid	1:77f1ee332e4a	1548	// @return number of ScanRead() words needed to retrieve the data.
whismanoid	6:cb7bdeb185d0	1549	// @post NumWords = number of words to be read from the FIFO
whismanoid	1:77f1ee332e4a	1550	// For external clock modes, the data format depends on CHAN_ID.
whismanoid	1:77f1ee332e4a	1551	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	1:77f1ee332e4a	1552	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	1553	//
whismanoid	1:77f1ee332e4a	1554	int MAX11131::ScanManual(void)
whismanoid	1:77f1ee332e4a	1555	{
whismanoid	1:77f1ee332e4a	1556
whismanoid	1:77f1ee332e4a	1557	//----------------------------------------
whismanoid	2:50a0cf017492	1558	// define write-only register ADC_MODE_CONTROL
whismanoid	2:50a0cf017492	1559	ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid	2:50a0cf017492	1560	const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid	2:50a0cf017492	1561	const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid	2:50a0cf017492	1562	const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	2:50a0cf017492	1563	const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	2:50a0cf017492	1564	const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid	2:50a0cf017492	1565	const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid	2:50a0cf017492	1566
whismanoid	2:50a0cf017492	1567	//----------------------------------------
whismanoid	2:50a0cf017492	1568	// Apply a soft reset when changing from internal to external clock mode.
whismanoid	2:50a0cf017492	1569	int needFIFOreset = (isExternalClock != 1);
whismanoid	2:50a0cf017492	1570	if (needFIFOreset) {
whismanoid	2:50a0cf017492	1571	// Apply a soft reset when changing from internal to external clock mode.
whismanoid	2:50a0cf017492	1572	ADC_MODE_CONTROL = ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	2:50a0cf017492	1573	// Send SPI configuration to device
whismanoid	2:50a0cf017492	1574	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	2:50a0cf017492	1575	SPIoutputCS(0); // drive CS low
whismanoid	2:50a0cf017492	1576	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	2:50a0cf017492	1577	SPIoutputCS(1); // drive CS high
whismanoid	2:50a0cf017492	1578	ADC_MODE_CONTROL = 0;
whismanoid	2:50a0cf017492	1579	}
whismanoid	2:50a0cf017492	1580
whismanoid	2:50a0cf017492	1581	//----------------------------------------
whismanoid	1:77f1ee332e4a	1582	// number of words to read
whismanoid	1:77f1ee332e4a	1583	NumWords = 1;
whismanoid	1:77f1ee332e4a	1584
whismanoid	1:77f1ee332e4a	1585	//----------------------------------------
whismanoid	1:77f1ee332e4a	1586	// External Clock Mode
whismanoid	1:77f1ee332e4a	1587	isExternalClock = 1;
whismanoid	1:77f1ee332e4a	1588
whismanoid	1:77f1ee332e4a	1589	//----------------------------------------
whismanoid	1:77f1ee332e4a	1590	// update device driver global variable
whismanoid	1:77f1ee332e4a	1591	ScanMode = SCAN_0001_Manual;
whismanoid	1:77f1ee332e4a	1592
whismanoid	1:77f1ee332e4a	1593	//----------------------------------------
whismanoid	1:77f1ee332e4a	1594	// ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0001_Manual = 1
whismanoid	1:77f1ee332e4a	1595	//~ const int SCAN_0001_Manual = 1; // replaced local const with enum
whismanoid	1:77f1ee332e4a	1596	ADC_MODE_CONTROL \|= ((SCAN_0001_Manual & SCAN_BITS) << SCAN_LSB);
whismanoid	1:77f1ee332e4a	1597
whismanoid	1:77f1ee332e4a	1598	//----------------------------------------
whismanoid	1:77f1ee332e4a	1599	// ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid	1:77f1ee332e4a	1600	ADC_MODE_CONTROL \|= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid	1:77f1ee332e4a	1601
whismanoid	1:77f1ee332e4a	1602	//----------------------------------------
whismanoid	1:77f1ee332e4a	1603	// ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid	1:77f1ee332e4a	1604	ADC_MODE_CONTROL \|= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid	1:77f1ee332e4a	1605
whismanoid	1:77f1ee332e4a	1606	//----------------------------------------
whismanoid	1:77f1ee332e4a	1607	// ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid	1:77f1ee332e4a	1608	// (applicable to external clock mode only)
whismanoid	1:77f1ee332e4a	1609	// For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid	1:77f1ee332e4a	1610	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	1:77f1ee332e4a	1611	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	1612	// For internal clock modes, the data format always includes the channel address.
whismanoid	1:77f1ee332e4a	1613	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	1614	ADC_MODE_CONTROL \|= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid	1:77f1ee332e4a	1615
whismanoid	1:77f1ee332e4a	1616	//----------------------------------------
whismanoid	1:77f1ee332e4a	1617	// SPI write ADC MODE CONTROL register
whismanoid	1:77f1ee332e4a	1618	// Send SPI configuration to device
whismanoid	1:77f1ee332e4a	1619	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	1620	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1621	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	1:77f1ee332e4a	1622	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1623
whismanoid	1:77f1ee332e4a	1624	//----------------------------------------
whismanoid	1:77f1ee332e4a	1625	// return number of words to read
whismanoid	1:77f1ee332e4a	1626	return NumWords;
whismanoid	1:77f1ee332e4a	1627	}
whismanoid	1:77f1ee332e4a	1628
whismanoid	1:77f1ee332e4a	1629	//----------------------------------------
whismanoid	1:77f1ee332e4a	1630	// SCAN_0010_Repeat
whismanoid	1:77f1ee332e4a	1631	//
whismanoid	1:77f1ee332e4a	1632	// Measure ADC channel channelNumber_0_15 repeatedly with averaging.
whismanoid	1:77f1ee332e4a	1633	// Internal clock mode.
whismanoid	1:77f1ee332e4a	1634	// @param[in] channelNumber_0_15: AIN Channel Number
whismanoid	1:77f1ee332e4a	1635	// @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid	1:77f1ee332e4a	1636	// average_0_4_8_16_32=0 to disable averaging.
whismanoid	1:77f1ee332e4a	1637	// @param[in] nscan_4_8_12_16: Number of ScanRead() words to report.
whismanoid	1:77f1ee332e4a	1638	// @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid	1:77f1ee332e4a	1639	// SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid	1:77f1ee332e4a	1640	// Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	1:77f1ee332e4a	1641	// SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid	1:77f1ee332e4a	1642	// CS must be held low for minimum of 17 SCLK cycles.
whismanoid	1:77f1ee332e4a	1643	// CNVST pin is not used. (AIN14 is available)
whismanoid	1:77f1ee332e4a	1644	// @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	1:77f1ee332e4a	1645	// @return number of ScanRead() words needed to retrieve the data.
whismanoid	6:cb7bdeb185d0	1646	// @post NumWords = number of words to be read from the FIFO
whismanoid	1:77f1ee332e4a	1647	// For internal clock modes, the data format always includes the channel address.
whismanoid	1:77f1ee332e4a	1648	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	1649	//
whismanoid	1:77f1ee332e4a	1650	int MAX11131::ScanRepeat(void)
whismanoid	1:77f1ee332e4a	1651	{
whismanoid	1:77f1ee332e4a	1652
whismanoid	1:77f1ee332e4a	1653	//----------------------------------------
whismanoid	1:77f1ee332e4a	1654	// number of words to read
whismanoid	1:77f1ee332e4a	1655	NumWords = (nscan_4_8_12_16);
whismanoid	1:77f1ee332e4a	1656
whismanoid	1:77f1ee332e4a	1657	//----------------------------------------
whismanoid	1:77f1ee332e4a	1658	// Internal Clock Mode
whismanoid	1:77f1ee332e4a	1659	isExternalClock = 0;
whismanoid	1:77f1ee332e4a	1660
whismanoid	1:77f1ee332e4a	1661	//----------------------------------------
whismanoid	1:77f1ee332e4a	1662	// update device driver global variable
whismanoid	1:77f1ee332e4a	1663	ScanMode = SCAN_0010_Repeat;
whismanoid	1:77f1ee332e4a	1664
whismanoid	1:77f1ee332e4a	1665	//----------------------------------------
whismanoid	1:77f1ee332e4a	1666	// define write-only register ADC_MODE_CONTROL
whismanoid	1:77f1ee332e4a	1667	ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid	1:77f1ee332e4a	1668	const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid	1:77f1ee332e4a	1669	const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid	1:77f1ee332e4a	1670	const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	1:77f1ee332e4a	1671	const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	1:77f1ee332e4a	1672	const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid	1:77f1ee332e4a	1673	const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid	1:77f1ee332e4a	1674
whismanoid	1:77f1ee332e4a	1675	//----------------------------------------
whismanoid	1:77f1ee332e4a	1676	// define write-only register ADC_CONFIGURATION
whismanoid	1:77f1ee332e4a	1677	ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid	1:77f1ee332e4a	1678	const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid	1:77f1ee332e4a	1679	const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid	1:77f1ee332e4a	1680	const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid	1:77f1ee332e4a	1681	const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid	1:77f1ee332e4a	1682	const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid	1:77f1ee332e4a	1683	const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid	1:77f1ee332e4a	1684
whismanoid	1:77f1ee332e4a	1685	//----------------------------------------
whismanoid	1:77f1ee332e4a	1686	// if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid	1:77f1ee332e4a	1687	// (applicable to internal clock mode only)
whismanoid	1:77f1ee332e4a	1688	// if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid	1:77f1ee332e4a	1689	// if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid	1:77f1ee332e4a	1690	if (average_0_4_8_16_32 == 4) {
whismanoid	1:77f1ee332e4a	1691	// Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid	1:77f1ee332e4a	1692	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	1:77f1ee332e4a	1693	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	1694	ADC_CONFIGURATION \|= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	1695	} else if (average_0_4_8_16_32 == 8) {
whismanoid	1:77f1ee332e4a	1696	// Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid	1:77f1ee332e4a	1697	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	1:77f1ee332e4a	1698	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	1699	ADC_CONFIGURATION \|= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	1700	} else if (average_0_4_8_16_32 == 16) {
whismanoid	1:77f1ee332e4a	1701	// Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid	1:77f1ee332e4a	1702	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	1:77f1ee332e4a	1703	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	1704	ADC_CONFIGURATION \|= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	1705	} else if (average_0_4_8_16_32 == 32) {
whismanoid	1:77f1ee332e4a	1706	// Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid	1:77f1ee332e4a	1707	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	1:77f1ee332e4a	1708	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	1709	ADC_CONFIGURATION \|= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	1710	} else {
whismanoid	1:77f1ee332e4a	1711	// Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid	1:77f1ee332e4a	1712	ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid	1:77f1ee332e4a	1713	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	1714	}
whismanoid	1:77f1ee332e4a	1715
whismanoid	1:77f1ee332e4a	1716	//----------------------------------------
whismanoid	1:77f1ee332e4a	1717	// ADC CONFIGURATION register set NSCAN[1:0] for scan count
whismanoid	1:77f1ee332e4a	1718	// (applicable to SCAN_0010_Repeat only)
whismanoid	1:77f1ee332e4a	1719	if (nscan_4_8_12_16 == 4) {
whismanoid	1:77f1ee332e4a	1720	// Set scan count 4
whismanoid	1:77f1ee332e4a	1721	ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid	1:77f1ee332e4a	1722	ADC_CONFIGURATION \|= ((0 & NSCAN_BITS) << NSCAN_LSB);
whismanoid	1:77f1ee332e4a	1723	} else if (nscan_4_8_12_16 == 8) {
whismanoid	1:77f1ee332e4a	1724	// Set scan count 8
whismanoid	1:77f1ee332e4a	1725	ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid	1:77f1ee332e4a	1726	ADC_CONFIGURATION \|= ((1 & NSCAN_BITS) << NSCAN_LSB);
whismanoid	1:77f1ee332e4a	1727	} else if (nscan_4_8_12_16 == 12) {
whismanoid	1:77f1ee332e4a	1728	// Set scan count 12
whismanoid	1:77f1ee332e4a	1729	ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid	1:77f1ee332e4a	1730	ADC_CONFIGURATION \|= ((2 & NSCAN_BITS) << NSCAN_LSB);
whismanoid	1:77f1ee332e4a	1731	} else if (nscan_4_8_12_16 == 16) {
whismanoid	1:77f1ee332e4a	1732	// Set scan count 16
whismanoid	1:77f1ee332e4a	1733	ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid	1:77f1ee332e4a	1734	ADC_CONFIGURATION \|= ((3 & NSCAN_BITS) << NSCAN_LSB);
whismanoid	1:77f1ee332e4a	1735	}
whismanoid	1:77f1ee332e4a	1736
whismanoid	1:77f1ee332e4a	1737	//----------------------------------------
whismanoid	1:77f1ee332e4a	1738	// SPI write ADC CONFIGURATION register
whismanoid	1:77f1ee332e4a	1739	// Send SPI configuration to device
whismanoid	1:77f1ee332e4a	1740	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	1741	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1742	SPIwrite16bits(ADC_CONFIGURATION);
whismanoid	1:77f1ee332e4a	1743	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1744
whismanoid	1:77f1ee332e4a	1745	//----------------------------------------
whismanoid	1:77f1ee332e4a	1746	// Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid	1:77f1ee332e4a	1747	ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	1:77f1ee332e4a	1748	ADC_MODE_CONTROL \|= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	1:77f1ee332e4a	1749
whismanoid	1:77f1ee332e4a	1750	//----------------------------------------
whismanoid	1:77f1ee332e4a	1751	// ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0010_Repeat = 2
whismanoid	1:77f1ee332e4a	1752	//~ const int SCAN_0010_Repeat = 2; // replaced local const with enum
whismanoid	1:77f1ee332e4a	1753	ADC_MODE_CONTROL \|= ((SCAN_0010_Repeat & SCAN_BITS) << SCAN_LSB);
whismanoid	1:77f1ee332e4a	1754
whismanoid	1:77f1ee332e4a	1755	//----------------------------------------
whismanoid	1:77f1ee332e4a	1756	// ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid	1:77f1ee332e4a	1757	ADC_MODE_CONTROL \|= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid	1:77f1ee332e4a	1758
whismanoid	1:77f1ee332e4a	1759	//----------------------------------------
whismanoid	1:77f1ee332e4a	1760	// ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid	1:77f1ee332e4a	1761	ADC_MODE_CONTROL \|= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid	1:77f1ee332e4a	1762
whismanoid	1:77f1ee332e4a	1763	//----------------------------------------
whismanoid	1:77f1ee332e4a	1764	// ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid	1:77f1ee332e4a	1765	// ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid	1:77f1ee332e4a	1766	// (applicable to internal clock mode only)
whismanoid	1:77f1ee332e4a	1767	// SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid	1:77f1ee332e4a	1768	// SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	1:77f1ee332e4a	1769	if (swcnv_0_1) {
whismanoid	1:77f1ee332e4a	1770	ADC_MODE_CONTROL \|= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid	1:77f1ee332e4a	1771	} else {
whismanoid	1:77f1ee332e4a	1772	ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid	1:77f1ee332e4a	1773	}
whismanoid	1:77f1ee332e4a	1774
whismanoid	1:77f1ee332e4a	1775	//----------------------------------------
whismanoid	1:77f1ee332e4a	1776	// SPI write ADC MODE CONTROL register
whismanoid	1:77f1ee332e4a	1777	// If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid	1:77f1ee332e4a	1778	// Send SPI configuration to device
whismanoid	1:77f1ee332e4a	1779	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	1780	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1781	if (swcnv_0_1) {
whismanoid	1:77f1ee332e4a	1782	// If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid	1:77f1ee332e4a	1783	// NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid	1:77f1ee332e4a	1784	SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid	1:77f1ee332e4a	1785	} else {
whismanoid	1:77f1ee332e4a	1786	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	1:77f1ee332e4a	1787	}
whismanoid	1:77f1ee332e4a	1788	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1789
whismanoid	1:77f1ee332e4a	1790	//----------------------------------------
whismanoid	1:77f1ee332e4a	1791	// return number of words to read
whismanoid	1:77f1ee332e4a	1792	return NumWords;
whismanoid	1:77f1ee332e4a	1793	}
whismanoid	1:77f1ee332e4a	1794
whismanoid	1:77f1ee332e4a	1795	//----------------------------------------
whismanoid	1:77f1ee332e4a	1796	// SCAN_0011_StandardInternalClock
whismanoid	1:77f1ee332e4a	1797	//
whismanoid	1:77f1ee332e4a	1798	// Measure ADC channels in sequence from AIN0 to channelNumber_0_15.
whismanoid	1:77f1ee332e4a	1799	// Internal clock mode.
whismanoid	1:77f1ee332e4a	1800	// @param[in] channelNumber_0_15: AIN Channel Number
whismanoid	1:77f1ee332e4a	1801	// @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid	1:77f1ee332e4a	1802	// average_0_4_8_16_32=0 to disable averaging.
whismanoid	1:77f1ee332e4a	1803	// @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	1:77f1ee332e4a	1804	// @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid	1:77f1ee332e4a	1805	// SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid	1:77f1ee332e4a	1806	// Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	1:77f1ee332e4a	1807	// SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid	1:77f1ee332e4a	1808	// CS must be held low for minimum of 17 SCLK cycles.
whismanoid	1:77f1ee332e4a	1809	// CNVST pin is not used. (AIN14 is available)
whismanoid	1:77f1ee332e4a	1810	// @return number of ScanRead() words needed to retrieve the data.
whismanoid	6:cb7bdeb185d0	1811	// @post NumWords = number of words to be read from the FIFO
whismanoid	1:77f1ee332e4a	1812	// For internal clock modes, the data format always includes the channel address.
whismanoid	1:77f1ee332e4a	1813	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	1814	//
whismanoid	1:77f1ee332e4a	1815	int MAX11131::ScanStandardInternalClock(void)
whismanoid	1:77f1ee332e4a	1816	{
whismanoid	1:77f1ee332e4a	1817
whismanoid	1:77f1ee332e4a	1818	//----------------------------------------
whismanoid	1:77f1ee332e4a	1819	// number of words to read
whismanoid	1:77f1ee332e4a	1820	NumWords = (1 + channelNumber_0_15);
whismanoid	1:77f1ee332e4a	1821
whismanoid	1:77f1ee332e4a	1822	//----------------------------------------
whismanoid	1:77f1ee332e4a	1823	// Internal Clock Mode
whismanoid	1:77f1ee332e4a	1824	isExternalClock = 0;
whismanoid	1:77f1ee332e4a	1825
whismanoid	1:77f1ee332e4a	1826	//----------------------------------------
whismanoid	1:77f1ee332e4a	1827	// update device driver global variable
whismanoid	1:77f1ee332e4a	1828	ScanMode = SCAN_0011_StandardInternalClock;
whismanoid	1:77f1ee332e4a	1829
whismanoid	1:77f1ee332e4a	1830	//----------------------------------------
whismanoid	1:77f1ee332e4a	1831	// define write-only register ADC_MODE_CONTROL
whismanoid	1:77f1ee332e4a	1832	ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid	1:77f1ee332e4a	1833	const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid	1:77f1ee332e4a	1834	const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid	1:77f1ee332e4a	1835	const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	1:77f1ee332e4a	1836	const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	1:77f1ee332e4a	1837	const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid	1:77f1ee332e4a	1838	const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid	1:77f1ee332e4a	1839
whismanoid	1:77f1ee332e4a	1840	//----------------------------------------
whismanoid	1:77f1ee332e4a	1841	// define write-only register ADC_CONFIGURATION
whismanoid	1:77f1ee332e4a	1842	ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid	1:77f1ee332e4a	1843	const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid	1:77f1ee332e4a	1844	const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid	1:77f1ee332e4a	1845	const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid	1:77f1ee332e4a	1846	const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid	1:77f1ee332e4a	1847	const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid	1:77f1ee332e4a	1848	const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid	1:77f1ee332e4a	1849
whismanoid	1:77f1ee332e4a	1850	//----------------------------------------
whismanoid	1:77f1ee332e4a	1851	// if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid	1:77f1ee332e4a	1852	// (applicable to internal clock mode only)
whismanoid	1:77f1ee332e4a	1853	// if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid	1:77f1ee332e4a	1854	// if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid	1:77f1ee332e4a	1855	if (average_0_4_8_16_32 == 4) {
whismanoid	1:77f1ee332e4a	1856	// Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid	1:77f1ee332e4a	1857	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	1:77f1ee332e4a	1858	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	1859	ADC_CONFIGURATION \|= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	1860	} else if (average_0_4_8_16_32 == 8) {
whismanoid	1:77f1ee332e4a	1861	// Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid	1:77f1ee332e4a	1862	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	1:77f1ee332e4a	1863	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	1864	ADC_CONFIGURATION \|= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	1865	} else if (average_0_4_8_16_32 == 16) {
whismanoid	1:77f1ee332e4a	1866	// Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid	1:77f1ee332e4a	1867	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	1:77f1ee332e4a	1868	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	1869	ADC_CONFIGURATION \|= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	1870	} else if (average_0_4_8_16_32 == 32) {
whismanoid	1:77f1ee332e4a	1871	// Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid	1:77f1ee332e4a	1872	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	1:77f1ee332e4a	1873	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	1874	ADC_CONFIGURATION \|= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	1875	} else {
whismanoid	1:77f1ee332e4a	1876	// Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid	1:77f1ee332e4a	1877	ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid	1:77f1ee332e4a	1878	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	1879	}
whismanoid	1:77f1ee332e4a	1880
whismanoid	1:77f1ee332e4a	1881	//----------------------------------------
whismanoid	1:77f1ee332e4a	1882	// SPI write ADC CONFIGURATION register
whismanoid	1:77f1ee332e4a	1883	// Send SPI configuration to device
whismanoid	1:77f1ee332e4a	1884	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	1885	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1886	SPIwrite16bits(ADC_CONFIGURATION);
whismanoid	1:77f1ee332e4a	1887	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1888
whismanoid	1:77f1ee332e4a	1889	//----------------------------------------
whismanoid	1:77f1ee332e4a	1890	// Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid	1:77f1ee332e4a	1891	ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	1:77f1ee332e4a	1892	ADC_MODE_CONTROL \|= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	1:77f1ee332e4a	1893
whismanoid	1:77f1ee332e4a	1894	//----------------------------------------
whismanoid	1:77f1ee332e4a	1895	// ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0011_StandardInternalClock = 3
whismanoid	1:77f1ee332e4a	1896	//~ const int SCAN_0011_StandardInternalClock = 3; // replaced local const with enum
whismanoid	1:77f1ee332e4a	1897	ADC_MODE_CONTROL \|= ((SCAN_0011_StandardInternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid	1:77f1ee332e4a	1898
whismanoid	1:77f1ee332e4a	1899	//----------------------------------------
whismanoid	1:77f1ee332e4a	1900	// ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid	1:77f1ee332e4a	1901	ADC_MODE_CONTROL \|= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid	1:77f1ee332e4a	1902
whismanoid	1:77f1ee332e4a	1903	//----------------------------------------
whismanoid	1:77f1ee332e4a	1904	// ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid	1:77f1ee332e4a	1905	ADC_MODE_CONTROL \|= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid	1:77f1ee332e4a	1906
whismanoid	1:77f1ee332e4a	1907	//----------------------------------------
whismanoid	1:77f1ee332e4a	1908	// ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid	1:77f1ee332e4a	1909	// ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid	1:77f1ee332e4a	1910	// (applicable to internal clock mode only)
whismanoid	1:77f1ee332e4a	1911	// SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid	1:77f1ee332e4a	1912	// SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	1:77f1ee332e4a	1913	if (swcnv_0_1) {
whismanoid	1:77f1ee332e4a	1914	ADC_MODE_CONTROL \|= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid	1:77f1ee332e4a	1915	} else {
whismanoid	1:77f1ee332e4a	1916	ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid	1:77f1ee332e4a	1917	}
whismanoid	1:77f1ee332e4a	1918
whismanoid	1:77f1ee332e4a	1919	//----------------------------------------
whismanoid	1:77f1ee332e4a	1920	// SPI write ADC MODE CONTROL register
whismanoid	1:77f1ee332e4a	1921	// If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid	1:77f1ee332e4a	1922	// Send SPI configuration to device
whismanoid	1:77f1ee332e4a	1923	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	1924	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	1925	if (swcnv_0_1) {
whismanoid	1:77f1ee332e4a	1926	// If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid	1:77f1ee332e4a	1927	// NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid	1:77f1ee332e4a	1928	SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid	1:77f1ee332e4a	1929	} else {
whismanoid	1:77f1ee332e4a	1930	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	1:77f1ee332e4a	1931	}
whismanoid	1:77f1ee332e4a	1932	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	1933
whismanoid	1:77f1ee332e4a	1934	//----------------------------------------
whismanoid	1:77f1ee332e4a	1935	// return number of words to read
whismanoid	1:77f1ee332e4a	1936	return NumWords;
whismanoid	1:77f1ee332e4a	1937	}
whismanoid	1:77f1ee332e4a	1938
whismanoid	1:77f1ee332e4a	1939	//----------------------------------------
whismanoid	1:77f1ee332e4a	1940	// SCAN_0100_StandardExternalClock
whismanoid	1:77f1ee332e4a	1941	//
whismanoid	1:77f1ee332e4a	1942	// Measure ADC channels in sequence from AIN0 to channelNumber_0_15.
whismanoid	1:77f1ee332e4a	1943	// External clock mode.
whismanoid	1:77f1ee332e4a	1944	// @param[in] channelNumber_0_15: AIN Channel Number
whismanoid	1:77f1ee332e4a	1945	// @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	1:77f1ee332e4a	1946	// @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid	1:77f1ee332e4a	1947	// @return number of ScanRead() words needed to retrieve the data.
whismanoid	6:cb7bdeb185d0	1948	// @post NumWords = number of words to be read from the FIFO
whismanoid	1:77f1ee332e4a	1949	// For external clock modes, the data format depends on CHAN_ID.
whismanoid	1:77f1ee332e4a	1950	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	1:77f1ee332e4a	1951	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	1952	//
whismanoid	1:77f1ee332e4a	1953	int MAX11131::ScanStandardExternalClock(void)
whismanoid	1:77f1ee332e4a	1954	{
whismanoid	1:77f1ee332e4a	1955
whismanoid	1:77f1ee332e4a	1956	//----------------------------------------
whismanoid	2:50a0cf017492	1957	// define write-only register ADC_MODE_CONTROL
whismanoid	2:50a0cf017492	1958	ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid	2:50a0cf017492	1959	const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid	2:50a0cf017492	1960	const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid	2:50a0cf017492	1961	const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	2:50a0cf017492	1962	const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	2:50a0cf017492	1963	const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid	2:50a0cf017492	1964	const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid	2:50a0cf017492	1965
whismanoid	2:50a0cf017492	1966	//----------------------------------------
whismanoid	2:50a0cf017492	1967	// Apply a soft reset when changing from internal to external clock mode.
whismanoid	2:50a0cf017492	1968	int needFIFOreset = (isExternalClock != 1);
whismanoid	2:50a0cf017492	1969	if (needFIFOreset) {
whismanoid	2:50a0cf017492	1970	// Apply a soft reset when changing from internal to external clock mode.
whismanoid	2:50a0cf017492	1971	ADC_MODE_CONTROL = ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	2:50a0cf017492	1972	// Send SPI configuration to device
whismanoid	2:50a0cf017492	1973	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	2:50a0cf017492	1974	SPIoutputCS(0); // drive CS low
whismanoid	2:50a0cf017492	1975	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	2:50a0cf017492	1976	SPIoutputCS(1); // drive CS high
whismanoid	2:50a0cf017492	1977	ADC_MODE_CONTROL = 0;
whismanoid	2:50a0cf017492	1978	}
whismanoid	2:50a0cf017492	1979
whismanoid	2:50a0cf017492	1980	//----------------------------------------
whismanoid	1:77f1ee332e4a	1981	// number of words to read
whismanoid	1:77f1ee332e4a	1982	NumWords = (1 + channelNumber_0_15);
whismanoid	1:77f1ee332e4a	1983
whismanoid	1:77f1ee332e4a	1984	//----------------------------------------
whismanoid	1:77f1ee332e4a	1985	// External Clock Mode
whismanoid	1:77f1ee332e4a	1986	isExternalClock = 1;
whismanoid	1:77f1ee332e4a	1987
whismanoid	1:77f1ee332e4a	1988	//----------------------------------------
whismanoid	1:77f1ee332e4a	1989	// update device driver global variable
whismanoid	1:77f1ee332e4a	1990	ScanMode = SCAN_0100_StandardExternalClock;
whismanoid	1:77f1ee332e4a	1991
whismanoid	1:77f1ee332e4a	1992	//----------------------------------------
whismanoid	1:77f1ee332e4a	1993	// ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0100_StandardExternalClock = 4
whismanoid	1:77f1ee332e4a	1994	//~ const int SCAN_0100_StandardExternalClock = 4; // replaced local const with enum
whismanoid	1:77f1ee332e4a	1995	ADC_MODE_CONTROL \|= ((SCAN_0100_StandardExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid	1:77f1ee332e4a	1996
whismanoid	1:77f1ee332e4a	1997	//----------------------------------------
whismanoid	1:77f1ee332e4a	1998	// ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid	1:77f1ee332e4a	1999	ADC_MODE_CONTROL \|= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid	1:77f1ee332e4a	2000
whismanoid	1:77f1ee332e4a	2001	//----------------------------------------
whismanoid	1:77f1ee332e4a	2002	// ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid	1:77f1ee332e4a	2003	ADC_MODE_CONTROL \|= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid	1:77f1ee332e4a	2004
whismanoid	1:77f1ee332e4a	2005	//----------------------------------------
whismanoid	1:77f1ee332e4a	2006	// ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid	1:77f1ee332e4a	2007	// (applicable to external clock mode only)
whismanoid	1:77f1ee332e4a	2008	// For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid	1:77f1ee332e4a	2009	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	1:77f1ee332e4a	2010	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	2011	// For internal clock modes, the data format always includes the channel address.
whismanoid	1:77f1ee332e4a	2012	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	2013	ADC_MODE_CONTROL \|= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid	1:77f1ee332e4a	2014
whismanoid	1:77f1ee332e4a	2015	//----------------------------------------
whismanoid	1:77f1ee332e4a	2016	// SPI write ADC MODE CONTROL register
whismanoid	1:77f1ee332e4a	2017	// Send SPI configuration to device
whismanoid	1:77f1ee332e4a	2018	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	2019	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	2020	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	1:77f1ee332e4a	2021	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	2022
whismanoid	1:77f1ee332e4a	2023	//----------------------------------------
whismanoid	1:77f1ee332e4a	2024	// return number of words to read
whismanoid	1:77f1ee332e4a	2025	return NumWords;
whismanoid	1:77f1ee332e4a	2026	}
whismanoid	1:77f1ee332e4a	2027
whismanoid	1:77f1ee332e4a	2028	//----------------------------------------
whismanoid	1:77f1ee332e4a	2029	// SCAN_0101_UpperInternalClock
whismanoid	1:77f1ee332e4a	2030	//
whismanoid	1:77f1ee332e4a	2031	// Measure ADC channels in sequence from channelNumber_0_15 to AIN15.
whismanoid	1:77f1ee332e4a	2032	// Internal clock mode.
whismanoid	1:77f1ee332e4a	2033	// @param[in] channelNumber_0_15: AIN Channel Number
whismanoid	1:77f1ee332e4a	2034	// @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid	1:77f1ee332e4a	2035	// average_0_4_8_16_32=0 to disable averaging.
whismanoid	1:77f1ee332e4a	2036	// @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	1:77f1ee332e4a	2037	// @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid	1:77f1ee332e4a	2038	// SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid	1:77f1ee332e4a	2039	// Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	1:77f1ee332e4a	2040	// SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid	1:77f1ee332e4a	2041	// CS must be held low for minimum of 17 SCLK cycles.
whismanoid	1:77f1ee332e4a	2042	// CNVST pin is not used. (AIN14 is available)
whismanoid	1:77f1ee332e4a	2043	// @return number of ScanRead() words needed to retrieve the data.
whismanoid	6:cb7bdeb185d0	2044	// @post NumWords = number of words to be read from the FIFO
whismanoid	1:77f1ee332e4a	2045	// For internal clock modes, the data format always includes the channel address.
whismanoid	1:77f1ee332e4a	2046	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	2047	//
whismanoid	1:77f1ee332e4a	2048	int MAX11131::ScanUpperInternalClock(void)
whismanoid	1:77f1ee332e4a	2049	{
whismanoid	1:77f1ee332e4a	2050
whismanoid	1:77f1ee332e4a	2051	//----------------------------------------
whismanoid	1:77f1ee332e4a	2052	// number of words to read
whismanoid	1:77f1ee332e4a	2053	NumWords = (16 - channelNumber_0_15);
whismanoid	1:77f1ee332e4a	2054
whismanoid	1:77f1ee332e4a	2055	//----------------------------------------
whismanoid	1:77f1ee332e4a	2056	// Internal Clock Mode
whismanoid	1:77f1ee332e4a	2057	isExternalClock = 0;
whismanoid	1:77f1ee332e4a	2058
whismanoid	1:77f1ee332e4a	2059	//----------------------------------------
whismanoid	1:77f1ee332e4a	2060	// update device driver global variable
whismanoid	1:77f1ee332e4a	2061	ScanMode = SCAN_0101_UpperInternalClock;
whismanoid	1:77f1ee332e4a	2062
whismanoid	1:77f1ee332e4a	2063	//----------------------------------------
whismanoid	1:77f1ee332e4a	2064	// define write-only register ADC_MODE_CONTROL
whismanoid	1:77f1ee332e4a	2065	ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid	1:77f1ee332e4a	2066	const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid	1:77f1ee332e4a	2067	const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid	1:77f1ee332e4a	2068	const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	1:77f1ee332e4a	2069	const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	1:77f1ee332e4a	2070	const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid	1:77f1ee332e4a	2071	const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid	1:77f1ee332e4a	2072
whismanoid	1:77f1ee332e4a	2073	//----------------------------------------
whismanoid	1:77f1ee332e4a	2074	// define write-only register ADC_CONFIGURATION
whismanoid	1:77f1ee332e4a	2075	ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid	1:77f1ee332e4a	2076	const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid	1:77f1ee332e4a	2077	const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid	1:77f1ee332e4a	2078	const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid	1:77f1ee332e4a	2079	const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid	1:77f1ee332e4a	2080	const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid	1:77f1ee332e4a	2081	const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid	1:77f1ee332e4a	2082
whismanoid	1:77f1ee332e4a	2083	//----------------------------------------
whismanoid	1:77f1ee332e4a	2084	// if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid	1:77f1ee332e4a	2085	// (applicable to internal clock mode only)
whismanoid	1:77f1ee332e4a	2086	// if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid	1:77f1ee332e4a	2087	// if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid	1:77f1ee332e4a	2088	if (average_0_4_8_16_32 == 4) {
whismanoid	1:77f1ee332e4a	2089	// Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid	1:77f1ee332e4a	2090	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	1:77f1ee332e4a	2091	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	2092	ADC_CONFIGURATION \|= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	2093	} else if (average_0_4_8_16_32 == 8) {
whismanoid	1:77f1ee332e4a	2094	// Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid	1:77f1ee332e4a	2095	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	1:77f1ee332e4a	2096	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	2097	ADC_CONFIGURATION \|= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	2098	} else if (average_0_4_8_16_32 == 16) {
whismanoid	1:77f1ee332e4a	2099	// Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid	1:77f1ee332e4a	2100	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	1:77f1ee332e4a	2101	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	2102	ADC_CONFIGURATION \|= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	2103	} else if (average_0_4_8_16_32 == 32) {
whismanoid	1:77f1ee332e4a	2104	// Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid	1:77f1ee332e4a	2105	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	1:77f1ee332e4a	2106	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	2107	ADC_CONFIGURATION \|= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	2108	} else {
whismanoid	1:77f1ee332e4a	2109	// Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid	1:77f1ee332e4a	2110	ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid	1:77f1ee332e4a	2111	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	2112	}
whismanoid	1:77f1ee332e4a	2113
whismanoid	1:77f1ee332e4a	2114	//----------------------------------------
whismanoid	1:77f1ee332e4a	2115	// SPI write ADC CONFIGURATION register
whismanoid	1:77f1ee332e4a	2116	// Send SPI configuration to device
whismanoid	1:77f1ee332e4a	2117	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	2118	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	2119	SPIwrite16bits(ADC_CONFIGURATION);
whismanoid	1:77f1ee332e4a	2120	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	2121
whismanoid	1:77f1ee332e4a	2122	//----------------------------------------
whismanoid	1:77f1ee332e4a	2123	// Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid	1:77f1ee332e4a	2124	ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	1:77f1ee332e4a	2125	ADC_MODE_CONTROL \|= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	1:77f1ee332e4a	2126
whismanoid	1:77f1ee332e4a	2127	//----------------------------------------
whismanoid	1:77f1ee332e4a	2128	// ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0101_UpperInternalClock = 5
whismanoid	1:77f1ee332e4a	2129	//~ const int SCAN_0101_UpperInternalClock = 5; // replaced local const with enum
whismanoid	1:77f1ee332e4a	2130	ADC_MODE_CONTROL \|= ((SCAN_0101_UpperInternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid	1:77f1ee332e4a	2131
whismanoid	1:77f1ee332e4a	2132	//----------------------------------------
whismanoid	1:77f1ee332e4a	2133	// ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid	1:77f1ee332e4a	2134	ADC_MODE_CONTROL \|= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid	1:77f1ee332e4a	2135
whismanoid	1:77f1ee332e4a	2136	//----------------------------------------
whismanoid	1:77f1ee332e4a	2137	// ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid	1:77f1ee332e4a	2138	ADC_MODE_CONTROL \|= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid	1:77f1ee332e4a	2139
whismanoid	1:77f1ee332e4a	2140	//----------------------------------------
whismanoid	1:77f1ee332e4a	2141	// ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid	1:77f1ee332e4a	2142	// ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid	1:77f1ee332e4a	2143	// (applicable to internal clock mode only)
whismanoid	1:77f1ee332e4a	2144	// SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid	1:77f1ee332e4a	2145	// SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	1:77f1ee332e4a	2146	if (swcnv_0_1) {
whismanoid	1:77f1ee332e4a	2147	ADC_MODE_CONTROL \|= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid	1:77f1ee332e4a	2148	} else {
whismanoid	1:77f1ee332e4a	2149	ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid	1:77f1ee332e4a	2150	}
whismanoid	1:77f1ee332e4a	2151
whismanoid	1:77f1ee332e4a	2152	//----------------------------------------
whismanoid	1:77f1ee332e4a	2153	// SPI write ADC MODE CONTROL register
whismanoid	1:77f1ee332e4a	2154	// If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid	1:77f1ee332e4a	2155	// Send SPI configuration to device
whismanoid	1:77f1ee332e4a	2156	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	2157	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	2158	if (swcnv_0_1) {
whismanoid	1:77f1ee332e4a	2159	// If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid	1:77f1ee332e4a	2160	// NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid	1:77f1ee332e4a	2161	SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid	1:77f1ee332e4a	2162	} else {
whismanoid	1:77f1ee332e4a	2163	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	1:77f1ee332e4a	2164	}
whismanoid	1:77f1ee332e4a	2165	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	2166
whismanoid	1:77f1ee332e4a	2167	//----------------------------------------
whismanoid	1:77f1ee332e4a	2168	// return number of words to read
whismanoid	1:77f1ee332e4a	2169	return NumWords;
whismanoid	1:77f1ee332e4a	2170	}
whismanoid	1:77f1ee332e4a	2171
whismanoid	1:77f1ee332e4a	2172	//----------------------------------------
whismanoid	1:77f1ee332e4a	2173	// SCAN_0110_UpperExternalClock
whismanoid	1:77f1ee332e4a	2174	//
whismanoid	1:77f1ee332e4a	2175	// Measure ADC channels in sequence from channelNumber_0_15 to AIN15.
whismanoid	1:77f1ee332e4a	2176	// External clock mode.
whismanoid	1:77f1ee332e4a	2177	// @param[in] channelNumber_0_15: AIN Channel Number
whismanoid	1:77f1ee332e4a	2178	// @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	1:77f1ee332e4a	2179	// @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid	1:77f1ee332e4a	2180	// @return number of ScanRead() words needed to retrieve the data.
whismanoid	6:cb7bdeb185d0	2181	// @post NumWords = number of words to be read from the FIFO
whismanoid	1:77f1ee332e4a	2182	// For external clock modes, the data format depends on CHAN_ID.
whismanoid	1:77f1ee332e4a	2183	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	1:77f1ee332e4a	2184	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	2185	//
whismanoid	1:77f1ee332e4a	2186	int MAX11131::ScanUpperExternalClock(void)
whismanoid	1:77f1ee332e4a	2187	{
whismanoid	1:77f1ee332e4a	2188
whismanoid	1:77f1ee332e4a	2189	//----------------------------------------
whismanoid	2:50a0cf017492	2190	// define write-only register ADC_MODE_CONTROL
whismanoid	2:50a0cf017492	2191	ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid	2:50a0cf017492	2192	const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid	2:50a0cf017492	2193	const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid	2:50a0cf017492	2194	const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	2:50a0cf017492	2195	const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	2:50a0cf017492	2196	const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid	2:50a0cf017492	2197	const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid	2:50a0cf017492	2198
whismanoid	2:50a0cf017492	2199	//----------------------------------------
whismanoid	2:50a0cf017492	2200	// Apply a soft reset when changing from internal to external clock mode.
whismanoid	2:50a0cf017492	2201	int needFIFOreset = (isExternalClock != 1);
whismanoid	2:50a0cf017492	2202	if (needFIFOreset) {
whismanoid	2:50a0cf017492	2203	// Apply a soft reset when changing from internal to external clock mode.
whismanoid	2:50a0cf017492	2204	ADC_MODE_CONTROL = ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	2:50a0cf017492	2205	// Send SPI configuration to device
whismanoid	2:50a0cf017492	2206	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	2:50a0cf017492	2207	SPIoutputCS(0); // drive CS low
whismanoid	2:50a0cf017492	2208	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	2:50a0cf017492	2209	SPIoutputCS(1); // drive CS high
whismanoid	2:50a0cf017492	2210	ADC_MODE_CONTROL = 0;
whismanoid	2:50a0cf017492	2211	}
whismanoid	2:50a0cf017492	2212
whismanoid	2:50a0cf017492	2213	//----------------------------------------
whismanoid	1:77f1ee332e4a	2214	// number of words to read
whismanoid	1:77f1ee332e4a	2215	NumWords = (16 - channelNumber_0_15);
whismanoid	1:77f1ee332e4a	2216
whismanoid	1:77f1ee332e4a	2217	//----------------------------------------
whismanoid	1:77f1ee332e4a	2218	// External Clock Mode
whismanoid	1:77f1ee332e4a	2219	isExternalClock = 1;
whismanoid	1:77f1ee332e4a	2220
whismanoid	1:77f1ee332e4a	2221	//----------------------------------------
whismanoid	1:77f1ee332e4a	2222	// update device driver global variable
whismanoid	1:77f1ee332e4a	2223	ScanMode = SCAN_0110_UpperExternalClock;
whismanoid	1:77f1ee332e4a	2224
whismanoid	1:77f1ee332e4a	2225	//----------------------------------------
whismanoid	1:77f1ee332e4a	2226	// ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0110_UpperExternalClock = 6
whismanoid	1:77f1ee332e4a	2227	//~ const int SCAN_0110_UpperExternalClock = 6; // replaced local const with enum
whismanoid	1:77f1ee332e4a	2228	ADC_MODE_CONTROL \|= ((SCAN_0110_UpperExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid	1:77f1ee332e4a	2229
whismanoid	1:77f1ee332e4a	2230	//----------------------------------------
whismanoid	1:77f1ee332e4a	2231	// ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid	1:77f1ee332e4a	2232	ADC_MODE_CONTROL \|= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid	1:77f1ee332e4a	2233
whismanoid	1:77f1ee332e4a	2234	//----------------------------------------
whismanoid	1:77f1ee332e4a	2235	// ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid	1:77f1ee332e4a	2236	ADC_MODE_CONTROL \|= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid	1:77f1ee332e4a	2237
whismanoid	1:77f1ee332e4a	2238	//----------------------------------------
whismanoid	1:77f1ee332e4a	2239	// ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid	1:77f1ee332e4a	2240	// (applicable to external clock mode only)
whismanoid	1:77f1ee332e4a	2241	// For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid	1:77f1ee332e4a	2242	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	1:77f1ee332e4a	2243	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	2244	// For internal clock modes, the data format always includes the channel address.
whismanoid	1:77f1ee332e4a	2245	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	2246	ADC_MODE_CONTROL \|= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid	1:77f1ee332e4a	2247
whismanoid	1:77f1ee332e4a	2248	//----------------------------------------
whismanoid	1:77f1ee332e4a	2249	// SPI write ADC MODE CONTROL register
whismanoid	1:77f1ee332e4a	2250	// Send SPI configuration to device
whismanoid	1:77f1ee332e4a	2251	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	2252	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	2253	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	1:77f1ee332e4a	2254	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	2255
whismanoid	1:77f1ee332e4a	2256	//----------------------------------------
whismanoid	1:77f1ee332e4a	2257	// return number of words to read
whismanoid	1:77f1ee332e4a	2258	return NumWords;
whismanoid	1:77f1ee332e4a	2259	}
whismanoid	1:77f1ee332e4a	2260
whismanoid	1:77f1ee332e4a	2261	//----------------------------------------
whismanoid	1:77f1ee332e4a	2262	// SCAN_0111_CustomInternalClock
whismanoid	1:77f1ee332e4a	2263	//
whismanoid	1:77f1ee332e4a	2264	// Measure selected ADC channels in sequence from AIN0 to AIN15,
whismanoid	1:77f1ee332e4a	2265	// using only the channels enabled by enabledChannelsMask.
whismanoid	1:77f1ee332e4a	2266	// Bit 0x0001 enables AIN0.
whismanoid	1:77f1ee332e4a	2267	// Bit 0x0002 enables AIN1.
whismanoid	1:77f1ee332e4a	2268	// Bit 0x0004 enables AIN2.
whismanoid	1:77f1ee332e4a	2269	// Bit 0x0008 enables AIN3.
whismanoid	1:77f1ee332e4a	2270	// Bit 0x0010 enables AIN4.
whismanoid	1:77f1ee332e4a	2271	// Bit 0x0020 enables AIN5.
whismanoid	1:77f1ee332e4a	2272	// Bit 0x0040 enables AIN6.
whismanoid	1:77f1ee332e4a	2273	// Bit 0x0080 enables AIN7.
whismanoid	1:77f1ee332e4a	2274	// Bit 0x0100 enables AIN8.
whismanoid	1:77f1ee332e4a	2275	// Bit 0x0200 enables AIN9.
whismanoid	1:77f1ee332e4a	2276	// Bit 0x0400 enables AIN10.
whismanoid	1:77f1ee332e4a	2277	// Bit 0x0800 enables AIN11.
whismanoid	1:77f1ee332e4a	2278	// Bit 0x1000 enables AIN12.
whismanoid	1:77f1ee332e4a	2279	// Bit 0x2000 enables AIN13.
whismanoid	1:77f1ee332e4a	2280	// Bit 0x4000 enables AIN14.
whismanoid	1:77f1ee332e4a	2281	// Bit 0x8000 enables AIN15.
whismanoid	1:77f1ee332e4a	2282	// Internal clock mode.
whismanoid	1:77f1ee332e4a	2283	// @param[in] enabledChannelsMask: Bitmap of AIN Channels to scan.
whismanoid	1:77f1ee332e4a	2284	// @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid	1:77f1ee332e4a	2285	// average_0_4_8_16_32=0 to disable averaging.
whismanoid	1:77f1ee332e4a	2286	// @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	1:77f1ee332e4a	2287	// @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid	1:77f1ee332e4a	2288	// SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid	1:77f1ee332e4a	2289	// Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	1:77f1ee332e4a	2290	// SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid	1:77f1ee332e4a	2291	// CS must be held low for minimum of 17 SCLK cycles.
whismanoid	1:77f1ee332e4a	2292	// CNVST pin is not used. (AIN14 is available)
whismanoid	1:77f1ee332e4a	2293	// @return number of ScanRead() words needed to retrieve the data.
whismanoid	6:cb7bdeb185d0	2294	// @post NumWords = number of words to be read from the FIFO
whismanoid	1:77f1ee332e4a	2295	// For internal clock modes, the data format always includes the channel address.
whismanoid	1:77f1ee332e4a	2296	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	2297	//
whismanoid	1:77f1ee332e4a	2298	int MAX11131::ScanCustomInternalClock(void)
whismanoid	1:77f1ee332e4a	2299	{
whismanoid	1:77f1ee332e4a	2300
whismanoid	1:77f1ee332e4a	2301	//----------------------------------------
whismanoid	1:77f1ee332e4a	2302	// count nWords = number of set bits in enabledChannelsMask
whismanoid	1:77f1ee332e4a	2303	uint16_t bitMask;
whismanoid	1:77f1ee332e4a	2304	int nWords = 0;
whismanoid	1:77f1ee332e4a	2305	for (bitMask = 0x8000; bitMask != 0; bitMask = bitMask / 2)
whismanoid	1:77f1ee332e4a	2306	{
whismanoid	1:77f1ee332e4a	2307	if (enabledChannelsMask & bitMask)
whismanoid	1:77f1ee332e4a	2308	{
whismanoid	1:77f1ee332e4a	2309	nWords++;
whismanoid	1:77f1ee332e4a	2310	}
whismanoid	1:77f1ee332e4a	2311	}
whismanoid	1:77f1ee332e4a	2312
whismanoid	1:77f1ee332e4a	2313	//----------------------------------------
whismanoid	1:77f1ee332e4a	2314	// number of words to read
whismanoid	1:77f1ee332e4a	2315	NumWords = nWords;
whismanoid	1:77f1ee332e4a	2316
whismanoid	1:77f1ee332e4a	2317	//----------------------------------------
whismanoid	1:77f1ee332e4a	2318	// Internal Clock Mode
whismanoid	1:77f1ee332e4a	2319	isExternalClock = 0;
whismanoid	1:77f1ee332e4a	2320
whismanoid	1:77f1ee332e4a	2321	//----------------------------------------
whismanoid	1:77f1ee332e4a	2322	// update device driver global variable
whismanoid	1:77f1ee332e4a	2323	ScanMode = SCAN_0111_CustomInternalClock;
whismanoid	1:77f1ee332e4a	2324
whismanoid	1:77f1ee332e4a	2325	//----------------------------------------
whismanoid	1:77f1ee332e4a	2326	// define write-only register ADC_MODE_CONTROL
whismanoid	1:77f1ee332e4a	2327	ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid	1:77f1ee332e4a	2328	const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid	1:77f1ee332e4a	2329	const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid	1:77f1ee332e4a	2330	const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	1:77f1ee332e4a	2331	const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	1:77f1ee332e4a	2332	const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid	1:77f1ee332e4a	2333	const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid	1:77f1ee332e4a	2334
whismanoid	1:77f1ee332e4a	2335	//----------------------------------------
whismanoid	1:77f1ee332e4a	2336	// define write-only register ADC_CONFIGURATION
whismanoid	1:77f1ee332e4a	2337	ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid	1:77f1ee332e4a	2338	const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid	1:77f1ee332e4a	2339	const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid	1:77f1ee332e4a	2340	const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid	1:77f1ee332e4a	2341	const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid	1:77f1ee332e4a	2342	const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid	1:77f1ee332e4a	2343	const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid	1:77f1ee332e4a	2344
whismanoid	1:77f1ee332e4a	2345	//----------------------------------------
whismanoid	1:77f1ee332e4a	2346	// define write-only registers CSCAN0,CSCAN1
whismanoid	1:77f1ee332e4a	2347	CSCAN0 = 0xA000; //!< mosiData16 0xA000..0xA7FF format: 1 0 1 0 0 CHSCAN15 CHSCAN14 CHSCAN13 CHSCAN12 CHSCAN11 CHSCAN10 CHSCAN9 CHSCAN8 x x x
whismanoid	1:77f1ee332e4a	2348	const int CHSCAN15_LSB = 10; // CSCAN0.CHSCAN15
whismanoid	1:77f1ee332e4a	2349	const int CHSCAN14_LSB = 9; // CSCAN0.CHSCAN14
whismanoid	1:77f1ee332e4a	2350	const int CHSCAN13_LSB = 8; // CSCAN0.CHSCAN13
whismanoid	1:77f1ee332e4a	2351	const int CHSCAN12_LSB = 7; // CSCAN0.CHSCAN12
whismanoid	1:77f1ee332e4a	2352	const int CHSCAN11_LSB = 6; // CSCAN0.CHSCAN11
whismanoid	1:77f1ee332e4a	2353	const int CHSCAN10_LSB = 5; // CSCAN0.CHSCAN10
whismanoid	1:77f1ee332e4a	2354	const int CHSCAN9_LSB = 4; // CSCAN0.CHSCAN9
whismanoid	1:77f1ee332e4a	2355	const int CHSCAN8_LSB = 3; // CSCAN0.CHSCAN8
whismanoid	1:77f1ee332e4a	2356	CSCAN1 = 0xA800; //!< mosiData16 0xA800..0xAFFF format: 1 0 1 0 1 CHSCAN7 CHSCAN6 CHSCAN5 CHSCAN4 CHSCAN3 CHSCAN2 CHSCAN1 CHSCAN0 x x x
whismanoid	1:77f1ee332e4a	2357	const int CHSCAN7_LSB = 10; // CSCAN1.CHSCAN7
whismanoid	1:77f1ee332e4a	2358	const int CHSCAN6_LSB = 9; // CSCAN1.CHSCAN6
whismanoid	1:77f1ee332e4a	2359	const int CHSCAN5_LSB = 8; // CSCAN1.CHSCAN5
whismanoid	1:77f1ee332e4a	2360	const int CHSCAN4_LSB = 7; // CSCAN1.CHSCAN4
whismanoid	1:77f1ee332e4a	2361	const int CHSCAN3_LSB = 6; // CSCAN1.CHSCAN3
whismanoid	1:77f1ee332e4a	2362	const int CHSCAN2_LSB = 5; // CSCAN1.CHSCAN2
whismanoid	1:77f1ee332e4a	2363	const int CHSCAN1_LSB = 4; // CSCAN1.CHSCAN1
whismanoid	1:77f1ee332e4a	2364	const int CHSCAN0_LSB = 3; // CSCAN1.CHSCAN0
whismanoid	1:77f1ee332e4a	2365
whismanoid	1:77f1ee332e4a	2366	//----------------------------------------
whismanoid	1:77f1ee332e4a	2367	// if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid	1:77f1ee332e4a	2368	// (applicable to internal clock mode only)
whismanoid	1:77f1ee332e4a	2369	// if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid	1:77f1ee332e4a	2370	// if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid	1:77f1ee332e4a	2371	if (average_0_4_8_16_32 == 4) {
whismanoid	1:77f1ee332e4a	2372	// Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid	1:77f1ee332e4a	2373	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	1:77f1ee332e4a	2374	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	2375	ADC_CONFIGURATION \|= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	2376	} else if (average_0_4_8_16_32 == 8) {
whismanoid	1:77f1ee332e4a	2377	// Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid	1:77f1ee332e4a	2378	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	1:77f1ee332e4a	2379	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	2380	ADC_CONFIGURATION \|= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	2381	} else if (average_0_4_8_16_32 == 16) {
whismanoid	1:77f1ee332e4a	2382	// Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid	1:77f1ee332e4a	2383	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	1:77f1ee332e4a	2384	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	2385	ADC_CONFIGURATION \|= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	2386	} else if (average_0_4_8_16_32 == 32) {
whismanoid	1:77f1ee332e4a	2387	// Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid	1:77f1ee332e4a	2388	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	1:77f1ee332e4a	2389	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	2390	ADC_CONFIGURATION \|= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	2391	} else {
whismanoid	1:77f1ee332e4a	2392	// Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid	1:77f1ee332e4a	2393	ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid	1:77f1ee332e4a	2394	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	1:77f1ee332e4a	2395	}
whismanoid	1:77f1ee332e4a	2396
whismanoid	1:77f1ee332e4a	2397	//----------------------------------------
whismanoid	1:77f1ee332e4a	2398	// SPI write ADC CONFIGURATION register
whismanoid	1:77f1ee332e4a	2399	// Send SPI configuration to device
whismanoid	1:77f1ee332e4a	2400	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	2401	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	2402	SPIwrite16bits(ADC_CONFIGURATION);
whismanoid	1:77f1ee332e4a	2403	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	2404
whismanoid	1:77f1ee332e4a	2405	//----------------------------------------
whismanoid	1:77f1ee332e4a	2406	// SET CSCAN0 CSCAN1 REGISTERS from enabledChannelsMask
whismanoid	1:77f1ee332e4a	2407	CSCAN0 = 0xA000 \| (((enabledChannelsMask >> 8) & 0xFF) << 3); // CSCAN0.CHSCAN[15:8]
whismanoid	1:77f1ee332e4a	2408	CSCAN1 = 0xA800 \| (((enabledChannelsMask) & 0xFF) << 3); // CSCAN1.CHSCAN[7:0]
whismanoid	1:77f1ee332e4a	2409	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	2410	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	2411	SPIwrite16bits(CSCAN0);
whismanoid	1:77f1ee332e4a	2412	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	2413	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	2414	SPIwrite16bits(CSCAN1);
whismanoid	1:77f1ee332e4a	2415	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	2416
whismanoid	1:77f1ee332e4a	2417	//----------------------------------------
whismanoid	1:77f1ee332e4a	2418	// Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid	1:77f1ee332e4a	2419	ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	1:77f1ee332e4a	2420	ADC_MODE_CONTROL \|= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	1:77f1ee332e4a	2421
whismanoid	1:77f1ee332e4a	2422	//----------------------------------------
whismanoid	1:77f1ee332e4a	2423	// ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0111_CustomInternalClock = 7
whismanoid	1:77f1ee332e4a	2424	//~ const int SCAN_0111_CustomInternalClock = 7; // replaced local const with enum
whismanoid	1:77f1ee332e4a	2425	ADC_MODE_CONTROL \|= ((SCAN_0111_CustomInternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid	1:77f1ee332e4a	2426
whismanoid	1:77f1ee332e4a	2427	//----------------------------------------
whismanoid	1:77f1ee332e4a	2428	// ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid	1:77f1ee332e4a	2429	ADC_MODE_CONTROL \|= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid	1:77f1ee332e4a	2430
whismanoid	1:77f1ee332e4a	2431	//----------------------------------------
whismanoid	1:77f1ee332e4a	2432	// ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid	1:77f1ee332e4a	2433	// ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid	1:77f1ee332e4a	2434	// (applicable to internal clock mode only)
whismanoid	1:77f1ee332e4a	2435	// SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid	1:77f1ee332e4a	2436	// SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	1:77f1ee332e4a	2437	if (swcnv_0_1) {
whismanoid	1:77f1ee332e4a	2438	ADC_MODE_CONTROL \|= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid	1:77f1ee332e4a	2439	} else {
whismanoid	1:77f1ee332e4a	2440	ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid	1:77f1ee332e4a	2441	}
whismanoid	1:77f1ee332e4a	2442
whismanoid	1:77f1ee332e4a	2443	//----------------------------------------
whismanoid	1:77f1ee332e4a	2444	// SPI write ADC MODE CONTROL register
whismanoid	1:77f1ee332e4a	2445	// If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid	1:77f1ee332e4a	2446	// Send SPI configuration to device
whismanoid	1:77f1ee332e4a	2447	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	2448	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	2449	if (swcnv_0_1) {
whismanoid	1:77f1ee332e4a	2450	// If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid	1:77f1ee332e4a	2451	// NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid	1:77f1ee332e4a	2452	SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid	1:77f1ee332e4a	2453	} else {
whismanoid	1:77f1ee332e4a	2454	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	1:77f1ee332e4a	2455	}
whismanoid	1:77f1ee332e4a	2456	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	2457
whismanoid	1:77f1ee332e4a	2458	//----------------------------------------
whismanoid	1:77f1ee332e4a	2459	// return number of words to read
whismanoid	1:77f1ee332e4a	2460	return NumWords;
whismanoid	1:77f1ee332e4a	2461	}
whismanoid	1:77f1ee332e4a	2462
whismanoid	1:77f1ee332e4a	2463	//----------------------------------------
whismanoid	1:77f1ee332e4a	2464	// SCAN_1000_CustomExternalClock
whismanoid	1:77f1ee332e4a	2465	//
whismanoid	1:77f1ee332e4a	2466	// Measure selected ADC channels in sequence from AIN0 to AIN15,
whismanoid	1:77f1ee332e4a	2467	// using only the channels enabled by enabledChannelsMask.
whismanoid	1:77f1ee332e4a	2468	// Bit 0x0001 enables AIN0.
whismanoid	1:77f1ee332e4a	2469	// Bit 0x0002 enables AIN1.
whismanoid	1:77f1ee332e4a	2470	// Bit 0x0004 enables AIN2.
whismanoid	1:77f1ee332e4a	2471	// Bit 0x0008 enables AIN3.
whismanoid	1:77f1ee332e4a	2472	// Bit 0x0010 enables AIN4.
whismanoid	1:77f1ee332e4a	2473	// Bit 0x0020 enables AIN5.
whismanoid	1:77f1ee332e4a	2474	// Bit 0x0040 enables AIN6.
whismanoid	1:77f1ee332e4a	2475	// Bit 0x0080 enables AIN7.
whismanoid	1:77f1ee332e4a	2476	// Bit 0x0100 enables AIN8.
whismanoid	1:77f1ee332e4a	2477	// Bit 0x0200 enables AIN9.
whismanoid	1:77f1ee332e4a	2478	// Bit 0x0400 enables AIN10.
whismanoid	1:77f1ee332e4a	2479	// Bit 0x0800 enables AIN11.
whismanoid	1:77f1ee332e4a	2480	// Bit 0x1000 enables AIN12.
whismanoid	1:77f1ee332e4a	2481	// Bit 0x2000 enables AIN13.
whismanoid	1:77f1ee332e4a	2482	// Bit 0x4000 enables AIN14.
whismanoid	1:77f1ee332e4a	2483	// Bit 0x8000 enables AIN15.
whismanoid	1:77f1ee332e4a	2484	// External clock mode.
whismanoid	1:77f1ee332e4a	2485	// @param[in] enabledChannelsMask: Bitmap of AIN Channels to scan.
whismanoid	1:77f1ee332e4a	2486	// @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	1:77f1ee332e4a	2487	// @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid	1:77f1ee332e4a	2488	// @return number of ScanRead() words needed to retrieve the data.
whismanoid	6:cb7bdeb185d0	2489	// @post NumWords = number of words to be read from the FIFO
whismanoid	1:77f1ee332e4a	2490	// For external clock modes, the data format depends on CHAN_ID.
whismanoid	1:77f1ee332e4a	2491	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	1:77f1ee332e4a	2492	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	2493	//
whismanoid	1:77f1ee332e4a	2494	int MAX11131::ScanCustomExternalClock(void)
whismanoid	1:77f1ee332e4a	2495	{
whismanoid	1:77f1ee332e4a	2496
whismanoid	1:77f1ee332e4a	2497	//----------------------------------------
whismanoid	1:77f1ee332e4a	2498	// count nWords = number of set bits in enabledChannelsMask
whismanoid	1:77f1ee332e4a	2499	uint16_t bitMask;
whismanoid	1:77f1ee332e4a	2500	int nWords = 0;
whismanoid	1:77f1ee332e4a	2501	for (bitMask = 0x8000; bitMask != 0; bitMask = bitMask / 2)
whismanoid	1:77f1ee332e4a	2502	{
whismanoid	1:77f1ee332e4a	2503	if (enabledChannelsMask & bitMask)
whismanoid	1:77f1ee332e4a	2504	{
whismanoid	1:77f1ee332e4a	2505	nWords++;
whismanoid	1:77f1ee332e4a	2506	}
whismanoid	1:77f1ee332e4a	2507	}
whismanoid	1:77f1ee332e4a	2508
whismanoid	1:77f1ee332e4a	2509	//----------------------------------------
whismanoid	2:50a0cf017492	2510	// define write-only register ADC_MODE_CONTROL
whismanoid	2:50a0cf017492	2511	ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid	2:50a0cf017492	2512	const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid	2:50a0cf017492	2513	const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid	2:50a0cf017492	2514	const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	2:50a0cf017492	2515	const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	2:50a0cf017492	2516	const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid	2:50a0cf017492	2517	const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid	2:50a0cf017492	2518
whismanoid	2:50a0cf017492	2519	//----------------------------------------
whismanoid	2:50a0cf017492	2520	// Apply a soft reset when changing from internal to external clock mode.
whismanoid	2:50a0cf017492	2521	int needFIFOreset = (isExternalClock != 1);
whismanoid	2:50a0cf017492	2522	if (needFIFOreset) {
whismanoid	2:50a0cf017492	2523	// Apply a soft reset when changing from internal to external clock mode.
whismanoid	2:50a0cf017492	2524	ADC_MODE_CONTROL = ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	2:50a0cf017492	2525	// Send SPI configuration to device
whismanoid	2:50a0cf017492	2526	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	2:50a0cf017492	2527	SPIoutputCS(0); // drive CS low
whismanoid	2:50a0cf017492	2528	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	2:50a0cf017492	2529	SPIoutputCS(1); // drive CS high
whismanoid	2:50a0cf017492	2530	ADC_MODE_CONTROL = 0;
whismanoid	2:50a0cf017492	2531	}
whismanoid	2:50a0cf017492	2532
whismanoid	2:50a0cf017492	2533	//----------------------------------------
whismanoid	1:77f1ee332e4a	2534	// number of words to read
whismanoid	1:77f1ee332e4a	2535	NumWords = nWords;
whismanoid	1:77f1ee332e4a	2536
whismanoid	1:77f1ee332e4a	2537	//----------------------------------------
whismanoid	1:77f1ee332e4a	2538	// External Clock Mode
whismanoid	1:77f1ee332e4a	2539	isExternalClock = 1;
whismanoid	1:77f1ee332e4a	2540
whismanoid	1:77f1ee332e4a	2541	//----------------------------------------
whismanoid	1:77f1ee332e4a	2542	// update device driver global variable
whismanoid	1:77f1ee332e4a	2543	ScanMode = SCAN_1000_CustomExternalClock;
whismanoid	1:77f1ee332e4a	2544
whismanoid	1:77f1ee332e4a	2545	//----------------------------------------
whismanoid	1:77f1ee332e4a	2546	// define write-only registers CSCAN0,CSCAN1
whismanoid	1:77f1ee332e4a	2547	CSCAN0 = 0xA000; //!< mosiData16 0xA000..0xA7FF format: 1 0 1 0 0 CHSCAN15 CHSCAN14 CHSCAN13 CHSCAN12 CHSCAN11 CHSCAN10 CHSCAN9 CHSCAN8 x x x
whismanoid	1:77f1ee332e4a	2548	const int CHSCAN15_LSB = 10; // CSCAN0.CHSCAN15
whismanoid	1:77f1ee332e4a	2549	const int CHSCAN14_LSB = 9; // CSCAN0.CHSCAN14
whismanoid	1:77f1ee332e4a	2550	const int CHSCAN13_LSB = 8; // CSCAN0.CHSCAN13
whismanoid	1:77f1ee332e4a	2551	const int CHSCAN12_LSB = 7; // CSCAN0.CHSCAN12
whismanoid	1:77f1ee332e4a	2552	const int CHSCAN11_LSB = 6; // CSCAN0.CHSCAN11
whismanoid	1:77f1ee332e4a	2553	const int CHSCAN10_LSB = 5; // CSCAN0.CHSCAN10
whismanoid	1:77f1ee332e4a	2554	const int CHSCAN9_LSB = 4; // CSCAN0.CHSCAN9
whismanoid	1:77f1ee332e4a	2555	const int CHSCAN8_LSB = 3; // CSCAN0.CHSCAN8
whismanoid	1:77f1ee332e4a	2556	CSCAN1 = 0xA800; //!< mosiData16 0xA800..0xAFFF format: 1 0 1 0 1 CHSCAN7 CHSCAN6 CHSCAN5 CHSCAN4 CHSCAN3 CHSCAN2 CHSCAN1 CHSCAN0 x x x
whismanoid	1:77f1ee332e4a	2557	const int CHSCAN7_LSB = 10; // CSCAN1.CHSCAN7
whismanoid	1:77f1ee332e4a	2558	const int CHSCAN6_LSB = 9; // CSCAN1.CHSCAN6
whismanoid	1:77f1ee332e4a	2559	const int CHSCAN5_LSB = 8; // CSCAN1.CHSCAN5
whismanoid	1:77f1ee332e4a	2560	const int CHSCAN4_LSB = 7; // CSCAN1.CHSCAN4
whismanoid	1:77f1ee332e4a	2561	const int CHSCAN3_LSB = 6; // CSCAN1.CHSCAN3
whismanoid	1:77f1ee332e4a	2562	const int CHSCAN2_LSB = 5; // CSCAN1.CHSCAN2
whismanoid	1:77f1ee332e4a	2563	const int CHSCAN1_LSB = 4; // CSCAN1.CHSCAN1
whismanoid	1:77f1ee332e4a	2564	const int CHSCAN0_LSB = 3; // CSCAN1.CHSCAN0
whismanoid	1:77f1ee332e4a	2565
whismanoid	1:77f1ee332e4a	2566	//----------------------------------------
whismanoid	1:77f1ee332e4a	2567	// SET CSCAN0 CSCAN1 REGISTERS from enabledChannelsMask
whismanoid	1:77f1ee332e4a	2568	CSCAN0 = 0xA000 \| (((enabledChannelsMask >> 8) & 0xFF) << 3); // CSCAN0.CHSCAN[15:8]
whismanoid	1:77f1ee332e4a	2569	CSCAN1 = 0xA800 \| (((enabledChannelsMask) & 0xFF) << 3); // CSCAN1.CHSCAN[7:0]
whismanoid	1:77f1ee332e4a	2570	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	2571	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	2572	SPIwrite16bits(CSCAN0);
whismanoid	1:77f1ee332e4a	2573	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	2574	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	2575	SPIwrite16bits(CSCAN1);
whismanoid	1:77f1ee332e4a	2576	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	2577
whismanoid	1:77f1ee332e4a	2578	//----------------------------------------
whismanoid	1:77f1ee332e4a	2579	// ADC MODE CONTROL register set SCAN[3:0] TO SCAN_1000_CustomExternalClock = 8
whismanoid	1:77f1ee332e4a	2580	//~ const int SCAN_1000_CustomExternalClock = 8; // replaced local const with enum
whismanoid	1:77f1ee332e4a	2581	ADC_MODE_CONTROL \|= ((SCAN_1000_CustomExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid	1:77f1ee332e4a	2582
whismanoid	1:77f1ee332e4a	2583	//----------------------------------------
whismanoid	1:77f1ee332e4a	2584	// ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid	1:77f1ee332e4a	2585	ADC_MODE_CONTROL \|= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid	1:77f1ee332e4a	2586
whismanoid	1:77f1ee332e4a	2587	//----------------------------------------
whismanoid	1:77f1ee332e4a	2588	// ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid	1:77f1ee332e4a	2589	// (applicable to external clock mode only)
whismanoid	1:77f1ee332e4a	2590	// For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid	1:77f1ee332e4a	2591	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	1:77f1ee332e4a	2592	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	2593	// For internal clock modes, the data format always includes the channel address.
whismanoid	1:77f1ee332e4a	2594	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	2595	ADC_MODE_CONTROL \|= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid	1:77f1ee332e4a	2596
whismanoid	1:77f1ee332e4a	2597	//----------------------------------------
whismanoid	1:77f1ee332e4a	2598	// SPI write ADC MODE CONTROL register
whismanoid	1:77f1ee332e4a	2599	// Send SPI configuration to device
whismanoid	1:77f1ee332e4a	2600	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	2601	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	2602	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	1:77f1ee332e4a	2603	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	2604
whismanoid	1:77f1ee332e4a	2605	//----------------------------------------
whismanoid	1:77f1ee332e4a	2606	// return number of words to read
whismanoid	1:77f1ee332e4a	2607	return NumWords;
whismanoid	1:77f1ee332e4a	2608	}
whismanoid	1:77f1ee332e4a	2609
whismanoid	1:77f1ee332e4a	2610	//----------------------------------------
whismanoid	1:77f1ee332e4a	2611	// SCAN_1001_SampleSetExternalClock
whismanoid	1:77f1ee332e4a	2612	//
whismanoid	1:77f1ee332e4a	2613	// Measure ADC channels in an arbitrary pattern.
whismanoid	1:77f1ee332e4a	2614	// Channels can be visited in any order, with repetition allowed.
whismanoid	1:77f1ee332e4a	2615	// External clock mode.
whismanoid	1:77f1ee332e4a	2616	// @pre enabledChannelsPatternLength_1_256: number of channel selections
whismanoid	1:77f1ee332e4a	2617	// @pre enabledChannelsPattern: array containing channel selection pattern
whismanoid	1:77f1ee332e4a	2618	// In the array, one channel select per byte.
whismanoid	1:77f1ee332e4a	2619	// In the SPI interface, immediately after SAMPLESET register is written,
whismanoid	1:77f1ee332e4a	2620	// each byte encodes two channelNumber selections.
whismanoid	1:77f1ee332e4a	2621	// The high 4 bits encode the first channelNumber.
whismanoid	1:77f1ee332e4a	2622	// (((enabledChannelsPattern[0]) & 0x0F) << 4) \| ((enabledChannelsPattern[1]) & 0x0F)
whismanoid	1:77f1ee332e4a	2623	// If it is an odd number of channels, additional nybbles will be ignored.
whismanoid	1:77f1ee332e4a	2624	// CS will be asserted low during the entire SAMPLESET pattern selection.
whismanoid	6:cb7bdeb185d0	2625	// @param[in] enabledChannelsPattern: array of channel select, one channel per byte
whismanoid	1:77f1ee332e4a	2626	// @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	1:77f1ee332e4a	2627	// @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid	1:77f1ee332e4a	2628	// @return number of ScanRead() words needed to retrieve the data.
whismanoid	6:cb7bdeb185d0	2629	// @post NumWords = number of words to be read from the FIFO
whismanoid	1:77f1ee332e4a	2630	// For external clock modes, the data format depends on CHAN_ID.
whismanoid	1:77f1ee332e4a	2631	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	1:77f1ee332e4a	2632	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	2633	//
whismanoid	1:77f1ee332e4a	2634	int MAX11131::ScanSampleSetExternalClock(void)
whismanoid	1:77f1ee332e4a	2635	{
whismanoid	1:77f1ee332e4a	2636
whismanoid	1:77f1ee332e4a	2637	//----------------------------------------
whismanoid	2:50a0cf017492	2638	// define write-only register ADC_MODE_CONTROL
whismanoid	2:50a0cf017492	2639	ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid	2:50a0cf017492	2640	const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid	2:50a0cf017492	2641	const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid	2:50a0cf017492	2642	const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	2:50a0cf017492	2643	const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	2:50a0cf017492	2644	const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid	2:50a0cf017492	2645	const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid	2:50a0cf017492	2646
whismanoid	2:50a0cf017492	2647	//----------------------------------------
whismanoid	2:50a0cf017492	2648	// Apply a soft reset when changing from internal to external clock mode.
whismanoid	2:50a0cf017492	2649	int needFIFOreset = (isExternalClock != 1);
whismanoid	2:50a0cf017492	2650	if (needFIFOreset) {
whismanoid	2:50a0cf017492	2651	// Apply a soft reset when changing from internal to external clock mode.
whismanoid	2:50a0cf017492	2652	ADC_MODE_CONTROL = ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	2:50a0cf017492	2653	// Send SPI configuration to device
whismanoid	2:50a0cf017492	2654	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	2:50a0cf017492	2655	SPIoutputCS(0); // drive CS low
whismanoid	2:50a0cf017492	2656	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	2:50a0cf017492	2657	SPIoutputCS(1); // drive CS high
whismanoid	2:50a0cf017492	2658	ADC_MODE_CONTROL = 0;
whismanoid	2:50a0cf017492	2659	}
whismanoid	2:50a0cf017492	2660
whismanoid	2:50a0cf017492	2661	//----------------------------------------
whismanoid	1:77f1ee332e4a	2662	// number of words to read
whismanoid	1:77f1ee332e4a	2663	NumWords = ((enabledChannelsPatternLength_1_256 != 0) ? enabledChannelsPatternLength_1_256 : 256 );
whismanoid	1:77f1ee332e4a	2664
whismanoid	1:77f1ee332e4a	2665	//----------------------------------------
whismanoid	1:77f1ee332e4a	2666	// External Clock Mode
whismanoid	1:77f1ee332e4a	2667	isExternalClock = 1;
whismanoid	1:77f1ee332e4a	2668
whismanoid	1:77f1ee332e4a	2669	//----------------------------------------
whismanoid	1:77f1ee332e4a	2670	// update device driver global variable
whismanoid	1:77f1ee332e4a	2671	ScanMode = SCAN_1001_SampleSetExternalClock;
whismanoid	1:77f1ee332e4a	2672
whismanoid	1:77f1ee332e4a	2673	//----------------------------------------
whismanoid	1:77f1ee332e4a	2674	// Initialize shadow of write-only register SAMPLESET.
whismanoid	1:77f1ee332e4a	2675	// Do not write to SAMPLESET at this time.
whismanoid	1:77f1ee332e4a	2676	// A write to SAMPLESET must be followed by specified number of pattern entry words.
whismanoid	1:77f1ee332e4a	2677	// See ScanSampleSetExternalClock function for details.
whismanoid	1:77f1ee332e4a	2678	SAMPLESET = 0xB000; //!< mosiData16 0xB000..0xB7FF format: 1 0 1 1 0 SEQ_LENGTH[7:0] x x x
whismanoid	1:77f1ee332e4a	2679	const int SAMPLESET_LSB = 3; const int SAMPLESET_BITS = 0xFF; // SAMPLESET.SEQ_LENGTH[7:0]
whismanoid	1:77f1ee332e4a	2680
whismanoid	1:77f1ee332e4a	2681	//----------------------------------------
whismanoid	1:77f1ee332e4a	2682	// SampleSet register set SEQ_DEPTH[7:0] TO SET CHANNEL CAPTURE DEPTH; FOLLOW SampleSet REGISTER WITH CHANNEL PATTERN OF THE SAME SIZE AS SEQUENCE DEPTH
whismanoid	1:77f1ee332e4a	2683	// NOTE: SAMPLESET.SEQ_LENGTH[7:0] is the number of channel entries in the pattern.
whismanoid	1:77f1ee332e4a	2684	// NOTE: Each channel entry is 4 bits. The first 4 bits are the first channel in the sequence.
whismanoid	1:77f1ee332e4a	2685	// NOTE: Channels can be repeated in any arbitrary order.
whismanoid	1:77f1ee332e4a	2686	// NOTE: The channel entry pattern is sent immediately after writing SAMPLESET.
whismanoid	1:77f1ee332e4a	2687	// NOTE: Keep CS low during the entire SAMPLESET pattern entry.
whismanoid	1:77f1ee332e4a	2688	const int seq_length_minus_one_0_255 = enabledChannelsPatternLength_1_256 - 1;
whismanoid	1:77f1ee332e4a	2689	SAMPLESET = 0xB000;
whismanoid	1:77f1ee332e4a	2690	//SAMPLESET &= ~ (( SAMPLESET_BITS) << SAMPLESET_LSB);
whismanoid	1:77f1ee332e4a	2691	SAMPLESET \|= ((seq_length_minus_one_0_255 & SAMPLESET_BITS) << SAMPLESET_LSB);
whismanoid	1:77f1ee332e4a	2692	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	2693	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	2694	SPIwrite16bits(SAMPLESET); // SAMPLESET must be followed by several more bytes, length specified by SEQ_LENGTH[7:0]
whismanoid	1:77f1ee332e4a	2695	// pack enabledChannelsPattern[index] into nybbles
whismanoid	1:77f1ee332e4a	2696	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	2697	// NOTE: Send the sampleset pattern, with 4 entries packed into each 16-bit SPI word. Pad unused entries with 0.
whismanoid	1:77f1ee332e4a	2698	SPI_MOSI_Semantic = 2; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	2699	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	2700	// NOTE: Keep CS low during the entire SAMPLESET pattern entry.
whismanoid	1:77f1ee332e4a	2701	int entryIndex;
whismanoid	1:77f1ee332e4a	2702	for (entryIndex = 0; entryIndex < enabledChannelsPatternLength_1_256; entryIndex += 4)
whismanoid	1:77f1ee332e4a	2703	{
whismanoid	1:77f1ee332e4a	2704	uint16_t pack4channels = 0;
whismanoid	1:77f1ee332e4a	2705	pack4channels \|= (((enabledChannelsPattern[entryIndex + 0]) & 0x0F) << 12);
whismanoid	1:77f1ee332e4a	2706	if ((entryIndex + 1) < enabledChannelsPatternLength_1_256) {
whismanoid	1:77f1ee332e4a	2707	pack4channels \|= (((enabledChannelsPattern[entryIndex + 1]) & 0x0F) << 8);
whismanoid	1:77f1ee332e4a	2708	}
whismanoid	1:77f1ee332e4a	2709	if ((entryIndex + 2) < enabledChannelsPatternLength_1_256) {
whismanoid	1:77f1ee332e4a	2710	pack4channels \|= (((enabledChannelsPattern[entryIndex + 2]) & 0x0F) << 4);
whismanoid	1:77f1ee332e4a	2711	}
whismanoid	1:77f1ee332e4a	2712	if ((entryIndex + 3) < enabledChannelsPatternLength_1_256) {
whismanoid	1:77f1ee332e4a	2713	pack4channels \|= ((enabledChannelsPattern[entryIndex + 3]) & 0x0F);
whismanoid	1:77f1ee332e4a	2714	}
whismanoid	1:77f1ee332e4a	2715	SPIwrite16bits(pack4channels);
whismanoid	1:77f1ee332e4a	2716	}
whismanoid	1:77f1ee332e4a	2717	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	2718
whismanoid	1:77f1ee332e4a	2719	//----------------------------------------
whismanoid	1:77f1ee332e4a	2720	// ADC MODE CONTROL register set SCAN[3:0] TO SCAN_1001_SampleSetExternalClock = 9
whismanoid	1:77f1ee332e4a	2721	//~ const int SCAN_1001_SampleSetExternalClock = 9; // replaced local const with enum
whismanoid	1:77f1ee332e4a	2722	ADC_MODE_CONTROL \|= ((SCAN_1001_SampleSetExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid	1:77f1ee332e4a	2723
whismanoid	1:77f1ee332e4a	2724	//----------------------------------------
whismanoid	1:77f1ee332e4a	2725	// ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid	1:77f1ee332e4a	2726	ADC_MODE_CONTROL \|= ((0 & CHSEL_BITS) << CHSEL_LSB);
whismanoid	1:77f1ee332e4a	2727
whismanoid	1:77f1ee332e4a	2728	//----------------------------------------
whismanoid	1:77f1ee332e4a	2729	// ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid	1:77f1ee332e4a	2730	ADC_MODE_CONTROL \|= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid	1:77f1ee332e4a	2731
whismanoid	1:77f1ee332e4a	2732	//----------------------------------------
whismanoid	1:77f1ee332e4a	2733	// ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid	1:77f1ee332e4a	2734	// (applicable to external clock mode only)
whismanoid	1:77f1ee332e4a	2735	// For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid	1:77f1ee332e4a	2736	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	1:77f1ee332e4a	2737	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	2738	// For internal clock modes, the data format always includes the channel address.
whismanoid	1:77f1ee332e4a	2739	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	2740	ADC_MODE_CONTROL \|= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid	1:77f1ee332e4a	2741
whismanoid	1:77f1ee332e4a	2742	//----------------------------------------
whismanoid	1:77f1ee332e4a	2743	// SPI write ADC MODE CONTROL register
whismanoid	1:77f1ee332e4a	2744	// Send SPI configuration to device
whismanoid	1:77f1ee332e4a	2745	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	1:77f1ee332e4a	2746	SPIoutputCS(0); // drive CS low
whismanoid	1:77f1ee332e4a	2747	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	1:77f1ee332e4a	2748	SPIoutputCS(1); // drive CS high
whismanoid	1:77f1ee332e4a	2749
whismanoid	1:77f1ee332e4a	2750	//----------------------------------------
whismanoid	1:77f1ee332e4a	2751	// return number of words to read
whismanoid	1:77f1ee332e4a	2752	return NumWords;
whismanoid	1:77f1ee332e4a	2753	}
whismanoid	1:77f1ee332e4a	2754
whismanoid	1:77f1ee332e4a	2755	//----------------------------------------
whismanoid	1:77f1ee332e4a	2756	// Example configure and perform some measurements in ScanManual mode.
whismanoid	1:77f1ee332e4a	2757	// @param[out] pd_mean = address for double mean (avearge)
whismanoid	1:77f1ee332e4a	2758	// @param[out] pd_variance = address for double variance (variance)
whismanoid	1:77f1ee332e4a	2759	// @param[out] pd_stddev = address for double stddev (standard deviation)
whismanoid	1:77f1ee332e4a	2760	// @param[out] pd_Sx = address for double Sx (sum of all X)
whismanoid	1:77f1ee332e4a	2761	// @param[out] pd_Sxx = address for double Sxx (sum of squares of each X)
whismanoid	1:77f1ee332e4a	2762	void MAX11131::Example_ScanManual(int channelNumber_0_15, int nWords,
whismanoid	1:77f1ee332e4a	2763	double* pd_mean, double* pd_variance, double* pd_stddev,
whismanoid	1:77f1ee332e4a	2764	double* pd_Sx, double* pd_Sxx)
whismanoid	1:77f1ee332e4a	2765	{
whismanoid	1:77f1ee332e4a	2766
whismanoid	1:77f1ee332e4a	2767	//----------------------------------------
whismanoid	1:77f1ee332e4a	2768	// configure and perform some measurements in ScanManual mode
whismanoid	1:77f1ee332e4a	2769	Init();
whismanoid	1:77f1ee332e4a	2770	channelNumber_0_15 = channelNumber_0_15; // Analog Input Channel Select AIN0..
whismanoid	1:77f1ee332e4a	2771	PowerManagement_0_2 = 0; // Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	1:77f1ee332e4a	2772	chan_id_0_1 = 1; // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	1:77f1ee332e4a	2773	// const int nWords = 100;
whismanoid	1:77f1ee332e4a	2774	double Sx = 0;
whismanoid	1:77f1ee332e4a	2775	double Sxx = 0;
whismanoid	1:77f1ee332e4a	2776	int index;
whismanoid	1:77f1ee332e4a	2777	ScanManual();
whismanoid	1:77f1ee332e4a	2778	for (index = 0; index < nWords; index++)
whismanoid	1:77f1ee332e4a	2779	{
whismanoid	1:77f1ee332e4a	2780	int16_t misoData16 = ScanRead();
whismanoid	1:77f1ee332e4a	2781	// For internal clock modes, the data format always includes the channel address.
whismanoid	1:77f1ee332e4a	2782	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	1:77f1ee332e4a	2783	int16_t value_u12 = (misoData16 & 0x0FFF);
whismanoid	1:77f1ee332e4a	2784	int channelId = ((misoData16 >> 12) & 0x000F);
whismanoid	1:77f1ee332e4a	2785	Sx = Sx + value_u12;
whismanoid	1:77f1ee332e4a	2786	Sxx = Sxx + ((double)value_u12 * value_u12);
whismanoid	1:77f1ee332e4a	2787	}
whismanoid	1:77f1ee332e4a	2788	if (pd_Sx != 0) {
whismanoid	1:77f1ee332e4a	2789	*(pd_Sx) = Sx;
whismanoid	1:77f1ee332e4a	2790	}
whismanoid	1:77f1ee332e4a	2791	if (pd_Sxx != 0) {
whismanoid	1:77f1ee332e4a	2792	*(pd_Sxx) = Sxx;
whismanoid	1:77f1ee332e4a	2793	}
whismanoid	1:77f1ee332e4a	2794	if (pd_mean != 0) {
whismanoid	1:77f1ee332e4a	2795	*(pd_mean) = Sx / nWords;
whismanoid	1:77f1ee332e4a	2796	}
whismanoid	1:77f1ee332e4a	2797	if (nWords >= 2)
whismanoid	1:77f1ee332e4a	2798	{
whismanoid	1:77f1ee332e4a	2799	if (pd_variance != 0) {
whismanoid	1:77f1ee332e4a	2800	// TODO1: is this variance calculation too naive to work reliably?
whismanoid	1:77f1ee332e4a	2801	// see https://en.wikipedia.org/wiki/Algorithms_for_calculating_variance
whismanoid	1:77f1ee332e4a	2802	(pd_variance) = (Sxx - ( Sx Sx / nWords) ) / (nWords - 1);
whismanoid	1:77f1ee332e4a	2803	}
whismanoid	1:77f1ee332e4a	2804	if (pd_stddev != 0) {
whismanoid	1:77f1ee332e4a	2805	(pd_stddev) = sqrt( (pd_variance) );
whismanoid	1:77f1ee332e4a	2806	}
whismanoid	1:77f1ee332e4a	2807	}
whismanoid	1:77f1ee332e4a	2808	}
whismanoid	1:77f1ee332e4a	2809
whismanoid	1:77f1ee332e4a	2810
whismanoid	1:77f1ee332e4a	2811	// End of file

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Type:	Library
Created:	05 Jun 2019
Imports:	7
Forks:	0
Commits:	12
Dependents:	3
Dependencies:	0
Followers:	111

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MAX11131BOB

MAX11131.cpp@8:2171c1889a84, 2019-10-30 (annotated)

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