MH / Mbed OS MAX30003WING_monitorhealth_beta_test1_RTC_RK_69

RTC integrations

Dependencies:   MAX30003 max32630fthr DS1307

main.cpp@10:54aa50490b15, 2020-09-21 (annotated)

Committer:
parthsagar2010
Date:
Mon Sep 21 23:13:36 2020 +0000
Revision:
10:54aa50490b15
Parent:
9:24ecf16eab0f
Child:
11:300afaf2696b
to PK Team

Who changed what in which revision?

UserRevisionLine numberNew contents of line
coreyharris 6:86ac850c718d 1
parthsagar2010 8:6b9359f81cc0 2 #include "MAX30003.h"
coreyharris 0:38c49bc37c7c 3 #include "mbed.h"
coreyharris 0:38c49bc37c7c 4 #include "max32630fthr.h"
parthsagar2010 9:24ecf16eab0f 5 #include "ds1307.h"
parthsagar2010 10:54aa50490b15 6 #include <BufferedSerial.h>
parthsagar2010 10:54aa50490b15 7 #include <string>
parthsagar2010 10:54aa50490b15 8 //#include <Serial.h>
parthsagar2010 9:24ecf16eab0f 9 Timer timer_fast;
parthsagar2010 10:54aa50490b15 10 Timer t;
coreyharris 0:38c49bc37c7c 11 MAX32630FTHR pegasus(MAX32630FTHR::VIO_3V3);
coreyharris 0:38c49bc37c7c 12
parthsagar2010 9:24ecf16eab0f 13 void task_fast(void);
parthsagar2010 9:24ecf16eab0f 14 DigitalOut ledA(LED2);
coreyharris 0:38c49bc37c7c 15 void ecg_config(MAX30003 &ecgAFE);
parthsagar2010 10:54aa50490b15 16 BufferedSerial pc(P3_1,P3_0); // Use USB debug probe for serial link static Unbuffered
parthsagar2010 10:54aa50490b15 17 //Serial uart_1(USBTX, USBRX); // Use USB debug probe for serial link static Unbuffered
parthsagar2010 10:54aa50490b15 18 //
parthsagar2010 10:54aa50490b15 19 //Serial pc(P3_1,P3_0);
coreyharris 0:38c49bc37c7c 20 volatile bool ecgFIFOIntFlag = 0;
parthsagar2010 9:24ecf16eab0f 21 volatile bool timerflag = 0;
parthsagar2010 8:6b9359f81cc0 22 void ecgFIFO_callback_1() { // Triggered when the ECG FIFO is about to be full
coreyharris 0:38c49bc37c7c 23
coreyharris 0:38c49bc37c7c 24 ecgFIFOIntFlag = 1;
coreyharris 0:38c49bc37c7c 25 }
coreyharris 0:38c49bc37c7c 26
coreyharris 0:38c49bc37c7c 27 int main()
coreyharris 3:420d5efbd967 28 {
coreyharris 6:86ac850c718d 29 // Constants
coreyharris 4:06e258ff0b97 30 const int EINT_STATUS_MASK = 1 << 23;
coreyharris 6:86ac850c718d 31 const int FIFO_OVF_MASK = 0x7;
coreyharris 6:86ac850c718d 32 const int FIFO_VALID_SAMPLE_MASK = 0x0;
coreyharris 6:86ac850c718d 33 const int FIFO_FAST_SAMPLE_MASK = 0x1;
coreyharris 6:86ac850c718d 34 const int ETAG_BITS_MASK = 0x7;
parthsagar2010 9:24ecf16eab0f 35 timer_fast.start();
parthsagar2010 8:6b9359f81cc0 36 DigitalOut rLed(LED1, LED_OFF);
parthsagar2010 10:54aa50490b15 37 // pc.baud(9600);
coreyharris 3:420d5efbd967 38
parthsagar2010 10:54aa50490b15 39 pc.set_baud(115200); // Baud rate = 115200
parthsagar2010 10:54aa50490b15 40 pc.set_format(
parthsagar2010 10:54aa50490b15 41 /* bits */ 8,
parthsagar2010 10:54aa50490b15 42 /* parity */ BufferedSerial::None,
parthsagar2010 10:54aa50490b15 43 /* stop bit */ 1 //1
parthsagar2010 10:54aa50490b15 44 );
parthsagar2010 10:54aa50490b15 45 //uart_1.baud(115200);
coreyharris 1:86843c27cc81 46 InterruptIn ecgFIFO_int(P5_4); // Config P5_4 as int. in for the
parthsagar2010 8:6b9359f81cc0 47 ecgFIFO_int.fall(&ecgFIFO_callback_1); // ecg FIFO interrupt at falling edge
coreyharris 0:38c49bc37c7c 48
coreyharris 1:86843c27cc81 49 SPI spiBus(SPI2_MOSI, SPI2_MISO, SPI2_SCK); // SPI bus, P5_1 = MOSI,
coreyharris 1:86843c27cc81 50 // P5_2 = MISO, P5_0 = SCK
parthsagar2010 10:54aa50490b15 51
coreyharris 4:06e258ff0b97 52 MAX30003 ecgAFE(spiBus, P5_3); // New MAX30003 on spiBus, CS = P5_3
parthsagar2010 8:6b9359f81cc0 53
coreyharris 4:06e258ff0b97 54 ecg_config(ecgAFE); // Config ECG
coreyharris 1:86843c27cc81 55
coreyharris 0:38c49bc37c7c 56
coreyharris 4:06e258ff0b97 57 ecgAFE.writeRegister( MAX30003::SYNCH , 0);
coreyharris 0:38c49bc37c7c 58
coreyharris 4:06e258ff0b97 59 uint32_t ecgFIFO, readECGSamples, idx, ETAG[32], status;
coreyharris 1:86843c27cc81 60 int16_t ecgSample[32];
parthsagar2010 9:24ecf16eab0f 61 //bool timerflag = false;
parthsagar2010 10:54aa50490b15 62 int16_t ecgSample_1sec[200];
parthsagar2010 10:54aa50490b15 63 uint8_t ecg_1 = 0;
parthsagar2010 10:54aa50490b15 64 uint8_t ecg_2 = 0;
parthsagar2010 10:54aa50490b15 65 uint16_t onesec_counter = 0;
parthsagar2010 10:54aa50490b15 66 uint16_t onesec_counter_temp = 0;
parthsagar2010 10:54aa50490b15 67
parthsagar2010 9:24ecf16eab0f 68 int16_t sample = 300;
parthsagar2010 10:54aa50490b15 69 uint8_t final[10];
parthsagar2010 10:54aa50490b15 70 uint32_t packet_1 = 1600674360;
parthsagar2010 10:54aa50490b15 71 uint16_t checksum_ = 0;
parthsagar2010 10:54aa50490b15 72 uint16_t mod_checksum = 0;
parthsagar2010 10:54aa50490b15 73
parthsagar2010 10:54aa50490b15 74 uint8_t p_1 = 0;
parthsagar2010 10:54aa50490b15 75 uint8_t p_2 = 0;
parthsagar2010 10:54aa50490b15 76 uint8_t p_3 = 0;
parthsagar2010 10:54aa50490b15 77 uint8_t p_4 = 0;
parthsagar2010 10:54aa50490b15 78
parthsagar2010 10:54aa50490b15 79 uint8_t data_len_1 = 0;
parthsagar2010 10:54aa50490b15 80 uint8_t data_len_2 = 0;
parthsagar2010 10:54aa50490b15 81
parthsagar2010 10:54aa50490b15 82 uint8_t cksm_1 = 0;
parthsagar2010 10:54aa50490b15 83 uint8_t cksm_2 = 0;
parthsagar2010 10:54aa50490b15 84 uint8_t header_device_id[3] = {0,0,210};
parthsagar2010 10:54aa50490b15 85 uint8_t header_packet_type[2] = {0,2};
parthsagar2010 10:54aa50490b15 86
parthsagar2010 10:54aa50490b15 87 uint8_t ending[5] = {'@','#','%','!','7'};
parthsagar2010 10:54aa50490b15 88
parthsagar2010 10:54aa50490b15 89 char buf[5];
coreyharris 2:812d40f1853d 90
parthsagar2010 9:24ecf16eab0f 91 while(1)
parthsagar2010 9:24ecf16eab0f 92 {
parthsagar2010 10:54aa50490b15 93
parthsagar2010 9:24ecf16eab0f 94
parthsagar2010 10:54aa50490b15 95 if (timer_fast.read() > .9)
parthsagar2010 9:24ecf16eab0f 96 {
parthsagar2010 10:54aa50490b15 97 t.start();
parthsagar2010 10:54aa50490b15 98 //ledA = !ledA;
parthsagar2010 10:54aa50490b15 99
parthsagar2010 10:54aa50490b15 100
parthsagar2010 10:54aa50490b15 101 pc.write((uint8_t *)header_device_id, sizeof(header_device_id));
parthsagar2010 10:54aa50490b15 102
parthsagar2010 10:54aa50490b15 103 pc.write((uint8_t *)header_packet_type, sizeof(header_packet_type));
parthsagar2010 10:54aa50490b15 104 packet_1 ++;
parthsagar2010 10:54aa50490b15 105 p_1 = packet_1 & 0xff;
parthsagar2010 10:54aa50490b15 106 p_2 = (packet_1 >> 8) & 0xff;
parthsagar2010 10:54aa50490b15 107 p_3 = (packet_1 >> 16) & 0xff;
parthsagar2010 10:54aa50490b15 108 p_4 = (packet_1 >> 24) & 0xff;
parthsagar2010 10:54aa50490b15 109 // checksum_ = checksum_ + (packet_1 & 0xffff) + ((packet_1 >> 16) & 0xffff) ;
parthsagar2010 10:54aa50490b15 110 checksum_ = checksum_ + p_1 + p_2 + p_3 + p_4 ;
parthsagar2010 10:54aa50490b15 111 uint8_t header_packet_id[4] = {p_4,p_3,p_2,p_1};
parthsagar2010 10:54aa50490b15 112 pc.write((uint8_t *)header_packet_id, sizeof(header_packet_id));
parthsagar2010 10:54aa50490b15 113 onesec_counter_temp = onesec_counter * 2;
parthsagar2010 10:54aa50490b15 114 data_len_1 = onesec_counter_temp & 0xff;
parthsagar2010 10:54aa50490b15 115 data_len_2 = (onesec_counter_temp >> 8) & 0xff;
parthsagar2010 10:54aa50490b15 116 checksum_ = checksum_ + data_len_1 + data_len_2;
parthsagar2010 10:54aa50490b15 117 //pc.write((uint32_t *)packet_1, sizeof(packet_1));
parthsagar2010 10:54aa50490b15 118 uint8_t header_ecg_datalen[2] = {data_len_2,data_len_1};
parthsagar2010 10:54aa50490b15 119 pc.write((uint8_t *)header_ecg_datalen, sizeof(header_ecg_datalen));
parthsagar2010 10:54aa50490b15 120 mod_checksum = checksum_ % 65536 ;
parthsagar2010 10:54aa50490b15 121 cksm_1 = mod_checksum & 0xff;
parthsagar2010 10:54aa50490b15 122 cksm_2 = (mod_checksum >> 8) & 0xff;
parthsagar2010 10:54aa50490b15 123 uint8_t header_ecg_checksum[2] = {cksm_2,cksm_1};
parthsagar2010 10:54aa50490b15 124 pc.write((uint8_t *)header_ecg_checksum, sizeof(header_ecg_checksum));
parthsagar2010 10:54aa50490b15 125
parthsagar2010 10:54aa50490b15 126 pc.write((int16_t *)ecgSample_1sec,onesec_counter * sizeof(int16_t));
parthsagar2010 10:54aa50490b15 127 onesec_counter = 0;
parthsagar2010 10:54aa50490b15 128 // memset(ecgSample_1sec, 0, sizeof(ecgSample_1sec));
parthsagar2010 10:54aa50490b15 129
parthsagar2010 10:54aa50490b15 130 pc.write((uint8_t *)ending, sizeof(ending));
parthsagar2010 10:54aa50490b15 131 checksum_ = 0;
parthsagar2010 10:54aa50490b15 132 t.stop();
parthsagar2010 10:54aa50490b15 133 auto us = t.elapsed_time().count();
parthsagar2010 10:54aa50490b15 134 printf("Timer time: %llu ms \n", us);
parthsagar2010 9:24ecf16eab0f 135 timer_fast.reset();
parthsagar2010 9:24ecf16eab0f 136 }
coreyharris 4:06e258ff0b97 137 // Read back ECG samples from the FIFO
parthsagar2010 9:24ecf16eab0f 138 else if( (ecgFIFOIntFlag==1))// && (timerflag == 0))
parthsagar2010 9:24ecf16eab0f 139 {
coreyharris 2:812d40f1853d 140
coreyharris 5:f8d1f651bef5 141 ecgFIFOIntFlag = 0;
coreyharris 4:06e258ff0b97 142 status = ecgAFE.readRegister( MAX30003::STATUS ); // Read the STATUS register
coreyharris 2:812d40f1853d 143
coreyharris 3:420d5efbd967 144 // Check if EINT interrupt asserted
parthsagar2010 9:24ecf16eab0f 145 if ( ( status & EINT_STATUS_MASK ) == EINT_STATUS_MASK )
parthsagar2010 9:24ecf16eab0f 146 {
coreyharris 3:420d5efbd967 147
coreyharris 4:06e258ff0b97 148 readECGSamples = 0; // Reset sample counter
coreyharris 3:420d5efbd967 149
coreyharris 2:812d40f1853d 150 do {
coreyharris 6:86ac850c718d 151 ecgFIFO = ecgAFE.readRegister( MAX30003::ECG_FIFO ); // Read FIFO
coreyharris 4:06e258ff0b97 152 ecgSample[readECGSamples] = ecgFIFO >> 8; // Isolate voltage data
parthsagar2010 10:54aa50490b15 153 ecgSample[readECGSamples] = ((ecgSample[readECGSamples]<<8)&0xFF00)|((ecgSample[readECGSamples]>>8)&0x00FF);
coreyharris 6:86ac850c718d 154 ETAG[readECGSamples] = ( ecgFIFO >> 3 ) & ETAG_BITS_MASK; // Isolate ETAG
coreyharris 4:06e258ff0b97 155 readECGSamples++; // Increment sample counter
coreyharris 3:420d5efbd967 156
coreyharris 3:420d5efbd967 157 // Check that sample is not last sample in FIFO
coreyharris 6:86ac850c718d 158 } while ( ETAG[readECGSamples-1] == FIFO_VALID_SAMPLE_MASK ||
coreyharris 6:86ac850c718d 159 ETAG[readECGSamples-1] == FIFO_FAST_SAMPLE_MASK );
coreyharris 2:812d40f1853d 160
coreyharris 3:420d5efbd967 161 // Check if FIFO has overflowed
parthsagar2010 9:24ecf16eab0f 162 if( ETAG[readECGSamples - 1] == FIFO_OVF_MASK )
parthsagar2010 9:24ecf16eab0f 163 {
coreyharris 3:420d5efbd967 164 ecgAFE.writeRegister( MAX30003::FIFO_RST , 0); // Reset FIFO
johnGreeneMaxim 7:cf0855a0450a 165 rLed = 1;//notifies the user that an over flow occured
coreyharris 3:420d5efbd967 166 }
parthsagar2010 10:54aa50490b15 167 //uint8_t header_ecg_checksum[2] = {'%','%'};
parthsagar2010 10:54aa50490b15 168 //pc.write((uint8_t *)header_ecg_checksum, sizeof(header_ecg_checksum));
coreyharris 3:420d5efbd967 169
parthsagar2010 10:54aa50490b15 170 //pc.write((int16_t *)ecgSample,readECGSamples * sizeof(int16_t ));
parthsagar2010 10:54aa50490b15 171 //memcpy(ecgSample_1sec , ecgSample, sizeof(ecgSample));
parthsagar2010 10:54aa50490b15 172
parthsagar2010 10:54aa50490b15 173 //memcpy(ecgSample_1sec + (onesec_counter * sizeof(int16_t)), ecgSample, sizeof(ecgSample));
parthsagar2010 10:54aa50490b15 174 for( idx = 0; idx < readECGSamples; idx++ )
parthsagar2010 9:24ecf16eab0f 175 {
parthsagar2010 9:24ecf16eab0f 176 //pc.printf("%6d\r\n", ecgSample[idx]);
parthsagar2010 9:24ecf16eab0f 177 ecgSample_1sec[onesec_counter] = ecgSample[idx];
parthsagar2010 10:54aa50490b15 178
parthsagar2010 10:54aa50490b15 179 cksm_1 = ecgSample[idx] & 0xff;
parthsagar2010 10:54aa50490b15 180 cksm_2 = (ecgSample[idx] >> 8) & 0xff;
parthsagar2010 10:54aa50490b15 181 checksum_ += cksm_1 + cksm_2;
parthsagar2010 9:24ecf16eab0f 182 onesec_counter++;
coreyharris 6:86ac850c718d 183 }
parthsagar2010 10:54aa50490b15 184 //onesec_counter += readECGSamples;
coreyharris 6:86ac850c718d 185
coreyharris 0:38c49bc37c7c 186 }
parthsagar2010 10:54aa50490b15 187
coreyharris 0:38c49bc37c7c 188 }
coreyharris 0:38c49bc37c7c 189 }
coreyharris 0:38c49bc37c7c 190 }
coreyharris 0:38c49bc37c7c 191
coreyharris 0:38c49bc37c7c 192
coreyharris 0:38c49bc37c7c 193
coreyharris 0:38c49bc37c7c 194
coreyharris 0:38c49bc37c7c 195 void ecg_config(MAX30003& ecgAFE) {
coreyharris 0:38c49bc37c7c 196
coreyharris 1:86843c27cc81 197 // Reset ECG to clear registers
coreyharris 1:86843c27cc81 198 ecgAFE.writeRegister( MAX30003::SW_RST , 0);
coreyharris 0:38c49bc37c7c 199
coreyharris 1:86843c27cc81 200 // General config register setting
coreyharris 1:86843c27cc81 201 MAX30003::GeneralConfiguration_u CNFG_GEN_r;
coreyharris 3:420d5efbd967 202 CNFG_GEN_r.bits.en_ecg = 1; // Enable ECG channel
coreyharris 3:420d5efbd967 203 CNFG_GEN_r.bits.rbiasn = 1; // Enable resistive bias on negative input
coreyharris 3:420d5efbd967 204 CNFG_GEN_r.bits.rbiasp = 1; // Enable resistive bias on positive input
coreyharris 3:420d5efbd967 205 CNFG_GEN_r.bits.en_rbias = 1; // Enable resistive bias
coreyharris 3:420d5efbd967 206 CNFG_GEN_r.bits.imag = 2; // Current magnitude = 10nA
coreyharris 3:420d5efbd967 207 CNFG_GEN_r.bits.en_dcloff = 1; // Enable DC lead-off detection
coreyharris 1:86843c27cc81 208 ecgAFE.writeRegister( MAX30003::CNFG_GEN , CNFG_GEN_r.all);
coreyharris 1:86843c27cc81 209
coreyharris 1:86843c27cc81 210
coreyharris 1:86843c27cc81 211 // ECG Config register setting
coreyharris 1:86843c27cc81 212 MAX30003::ECGConfiguration_u CNFG_ECG_r;
coreyharris 3:420d5efbd967 213 CNFG_ECG_r.bits.dlpf = 1; // Digital LPF cutoff = 40Hz
coreyharris 3:420d5efbd967 214 CNFG_ECG_r.bits.dhpf = 1; // Digital HPF cutoff = 0.5Hz
coreyharris 3:420d5efbd967 215 CNFG_ECG_r.bits.gain = 3; // ECG gain = 160V/V
coreyharris 3:420d5efbd967 216 CNFG_ECG_r.bits.rate = 2; // Sample rate = 128 sps
coreyharris 1:86843c27cc81 217 ecgAFE.writeRegister( MAX30003::CNFG_ECG , CNFG_ECG_r.all);
coreyharris 1:86843c27cc81 218
coreyharris 1:86843c27cc81 219
coreyharris 1:86843c27cc81 220 //R-to-R configuration
coreyharris 1:86843c27cc81 221 MAX30003::RtoR1Configuration_u CNFG_RTOR_r;
coreyharris 3:420d5efbd967 222 CNFG_RTOR_r.bits.en_rtor = 1; // Enable R-to-R detection
coreyharris 1:86843c27cc81 223 ecgAFE.writeRegister( MAX30003::CNFG_RTOR1 , CNFG_RTOR_r.all);
coreyharris 1:86843c27cc81 224
coreyharris 1:86843c27cc81 225
coreyharris 1:86843c27cc81 226 //Manage interrupts register setting
coreyharris 1:86843c27cc81 227 MAX30003::ManageInterrupts_u MNG_INT_r;
coreyharris 3:420d5efbd967 228 MNG_INT_r.bits.efit = 0b00011; // Assert EINT w/ 4 unread samples
coreyharris 3:420d5efbd967 229 MNG_INT_r.bits.clr_rrint = 0b01; // Clear R-to-R on RTOR reg. read back
coreyharris 1:86843c27cc81 230 ecgAFE.writeRegister( MAX30003::MNGR_INT , MNG_INT_r.all);
coreyharris 0:38c49bc37c7c 231
coreyharris 0:38c49bc37c7c 232
coreyharris 1:86843c27cc81 233 //Enable interrupts register setting
coreyharris 1:86843c27cc81 234 MAX30003::EnableInterrupts_u EN_INT_r;
coreyharris 5:f8d1f651bef5 235 EN_INT_r.all = 0;
coreyharris 3:420d5efbd967 236 EN_INT_r.bits.en_eint = 1; // Enable EINT interrupt
coreyharris 4:06e258ff0b97 237 EN_INT_r.bits.en_rrint = 0; // Disable R-to-R interrupt
coreyharris 3:420d5efbd967 238 EN_INT_r.bits.intb_type = 3; // Open-drain NMOS with internal pullup
coreyharris 1:86843c27cc81 239 ecgAFE.writeRegister( MAX30003::EN_INT , EN_INT_r.all);
coreyharris 1:86843c27cc81 240
coreyharris 1:86843c27cc81 241
coreyharris 1:86843c27cc81 242 //Dyanmic modes config
coreyharris 1:86843c27cc81 243 MAX30003::ManageDynamicModes_u MNG_DYN_r;
coreyharris 3:420d5efbd967 244 MNG_DYN_r.bits.fast = 0; // Fast recovery mode disabled
coreyharris 1:86843c27cc81 245 ecgAFE.writeRegister( MAX30003::MNGR_DYN , MNG_DYN_r.all);
coreyharris 5:f8d1f651bef5 246
coreyharris 5:f8d1f651bef5 247 // MUX Config
coreyharris 5:f8d1f651bef5 248 MAX30003::MuxConfiguration_u CNFG_MUX_r;
coreyharris 5:f8d1f651bef5 249 CNFG_MUX_r.bits.openn = 0; // Connect ECGN to AFE channel
coreyharris 5:f8d1f651bef5 250 CNFG_MUX_r.bits.openp = 0; // Connect ECGP to AFE channel
coreyharris 5:f8d1f651bef5 251 ecgAFE.writeRegister( MAX30003::CNFG_EMUX , CNFG_MUX_r.all);
coreyharris 1:86843c27cc81 252
coreyharris 1:86843c27cc81 253 return;
coreyharris 0:38c49bc37c7c 254 }
coreyharris 0:38c49bc37c7c 255