MH / Mbed OS MAX30003WING_monitorhealth_beta_test1_RTC_RK_69

RTC integrations

Dependencies:   MAX30003 max32630fthr DS1307

main.cpp@0:38c49bc37c7c, 2017-08-16 (annotated)

Committer:
coreyharris
Date:
Wed Aug 16 22:59:59 2017 +0000
Revision:
0:38c49bc37c7c
Child:
1:86843c27cc81
Stable demo for MAX30003, need to add ETAG monitoring if possible

Who changed what in which revision?

UserRevisionLine numberNew contents of line
coreyharris 0:38c49bc37c7c 1 #include "mbed.h"
coreyharris 0:38c49bc37c7c 2 #include "max32630fthr.h"
coreyharris 0:38c49bc37c7c 3 #include "MAX30003.h"
coreyharris 0:38c49bc37c7c 4
coreyharris 0:38c49bc37c7c 5 MAX32630FTHR pegasus(MAX32630FTHR::VIO_3V3);
coreyharris 0:38c49bc37c7c 6
coreyharris 0:38c49bc37c7c 7 void ecg_config(MAX30003 &ecgAFE);
coreyharris 0:38c49bc37c7c 8
coreyharris 0:38c49bc37c7c 9 /* ECG FIFO nearly full callback */
coreyharris 0:38c49bc37c7c 10 volatile bool ecgFIFOIntFlag = 0;
coreyharris 0:38c49bc37c7c 11 void ecgFIFO_callback() {
coreyharris 0:38c49bc37c7c 12
coreyharris 0:38c49bc37c7c 13 ecgFIFOIntFlag = 1;
coreyharris 0:38c49bc37c7c 14
coreyharris 0:38c49bc37c7c 15 }
coreyharris 0:38c49bc37c7c 16
coreyharris 0:38c49bc37c7c 17 int main()
coreyharris 0:38c49bc37c7c 18 {
coreyharris 0:38c49bc37c7c 19 DigitalOut rLed(LED1, LED_OFF);
coreyharris 0:38c49bc37c7c 20 DigitalOut gLed(LED2, LED_OFF);
coreyharris 0:38c49bc37c7c 21 DigitalOut bLed(LED3, LED_OFF);
coreyharris 0:38c49bc37c7c 22
coreyharris 0:38c49bc37c7c 23 Serial pc(USBTX, USBRX);
coreyharris 0:38c49bc37c7c 24 pc.baud(115200);
coreyharris 0:38c49bc37c7c 25
coreyharris 0:38c49bc37c7c 26 pc.printf("Running.... \r\n\r\n");
coreyharris 0:38c49bc37c7c 27 wait(0.5);
coreyharris 0:38c49bc37c7c 28
coreyharris 0:38c49bc37c7c 29 SPI spiBus(SPI2_MOSI, SPI2_MISO, SPI2_SCK);
coreyharris 0:38c49bc37c7c 30
coreyharris 0:38c49bc37c7c 31 MAX30003 *ecgAFE;
coreyharris 0:38c49bc37c7c 32 ecgAFE = new MAX30003(spiBus, P5_3);
coreyharris 0:38c49bc37c7c 33 ecg_config(*ecgAFE);
coreyharris 0:38c49bc37c7c 34
coreyharris 0:38c49bc37c7c 35 /* Peripehral configuration */
coreyharris 0:38c49bc37c7c 36 InterruptIn ecgFIFO_int(P5_4); // Config P5_4 as int. in for the ecg FIFO almost full interrupt
coreyharris 0:38c49bc37c7c 37 ecgFIFO_int.fall(&ecgFIFO_callback); //
coreyharris 0:38c49bc37c7c 38
coreyharris 0:38c49bc37c7c 39 pc.printf("Config. complete.... \r\n\r\n");
coreyharris 0:38c49bc37c7c 40 wait(0.5);
coreyharris 0:38c49bc37c7c 41
coreyharris 0:38c49bc37c7c 42 uint32_t ecgFIFO[32];
coreyharris 0:38c49bc37c7c 43 int16_t ecgSample, ETAG;
coreyharris 0:38c49bc37c7c 44 while(1)
coreyharris 0:38c49bc37c7c 45 {
coreyharris 0:38c49bc37c7c 46 /* Read back ECG samples from the FIFO */
coreyharris 0:38c49bc37c7c 47 if( ecgFIFOIntFlag ) {
coreyharris 0:38c49bc37c7c 48
coreyharris 0:38c49bc37c7c 49 for( int i = 0; i < 16; i++ ){
coreyharris 0:38c49bc37c7c 50 ecgFIFO[i] = ecgAFE->readRegister( MAX30003::ECG_FIFO );
coreyharris 0:38c49bc37c7c 51 ecgSample = ecgFIFO[i] >> 8;
coreyharris 0:38c49bc37c7c 52 ETAG = ( ecgFIFO[i] >> 3 ) && 0x07;
coreyharris 0:38c49bc37c7c 53
coreyharris 0:38c49bc37c7c 54 pc.printf("Sample : %5d, \t ETAG : 0x%x \r\n", ecgSample, ETAG);
coreyharris 0:38c49bc37c7c 55 }
coreyharris 0:38c49bc37c7c 56
coreyharris 0:38c49bc37c7c 57 bLed = !bLed;
coreyharris 0:38c49bc37c7c 58 ecgFIFOIntFlag = 0;
coreyharris 0:38c49bc37c7c 59
coreyharris 0:38c49bc37c7c 60 }
coreyharris 0:38c49bc37c7c 61 }
coreyharris 0:38c49bc37c7c 62 }
coreyharris 0:38c49bc37c7c 63
coreyharris 0:38c49bc37c7c 64
coreyharris 0:38c49bc37c7c 65
coreyharris 0:38c49bc37c7c 66
coreyharris 0:38c49bc37c7c 67 void ecg_config(MAX30003& ecgAFE) {
coreyharris 0:38c49bc37c7c 68
coreyharris 0:38c49bc37c7c 69 // Reset ECG to clear registers
coreyharris 0:38c49bc37c7c 70 ecgAFE.writeRegister( MAX30003::SW_RST , 0);
coreyharris 0:38c49bc37c7c 71
coreyharris 0:38c49bc37c7c 72
coreyharris 0:38c49bc37c7c 73
coreyharris 0:38c49bc37c7c 74 // General config register setting
coreyharris 0:38c49bc37c7c 75 MAX30003::GeneralConfiguration_u CNFG_GEN_r;
coreyharris 0:38c49bc37c7c 76 CNFG_GEN_r.bits.en_ecg = 1;
coreyharris 0:38c49bc37c7c 77 CNFG_GEN_r.bits.rbiasn = 1;
coreyharris 0:38c49bc37c7c 78 CNFG_GEN_r.bits.rbiasp = 1;
coreyharris 0:38c49bc37c7c 79 CNFG_GEN_r.bits.en_rbias = 1;
coreyharris 0:38c49bc37c7c 80 CNFG_GEN_r.bits.imag = 2;
coreyharris 0:38c49bc37c7c 81 CNFG_GEN_r.bits.en_dcloff = 1;
coreyharris 0:38c49bc37c7c 82 ecgAFE.writeRegister( MAX30003::CNFG_GEN , CNFG_GEN_r.all);
coreyharris 0:38c49bc37c7c 83
coreyharris 0:38c49bc37c7c 84
coreyharris 0:38c49bc37c7c 85
coreyharris 0:38c49bc37c7c 86 // ECG Config register setting
coreyharris 0:38c49bc37c7c 87 MAX30003::ECGConfiguration_u CNFG_ECG_r;
coreyharris 0:38c49bc37c7c 88 CNFG_ECG_r.bits.dlpf = 1;
coreyharris 0:38c49bc37c7c 89 CNFG_ECG_r.bits.dhpf = 1;
coreyharris 0:38c49bc37c7c 90 CNFG_ECG_r.bits.gain = 3;
coreyharris 0:38c49bc37c7c 91 CNFG_ECG_r.bits.rate = 3;
coreyharris 0:38c49bc37c7c 92 ecgAFE.writeRegister( MAX30003::CNFG_ECG , CNFG_ECG_r.all);
coreyharris 0:38c49bc37c7c 93
coreyharris 0:38c49bc37c7c 94
coreyharris 0:38c49bc37c7c 95
coreyharris 0:38c49bc37c7c 96 //R-to-R configuration
coreyharris 0:38c49bc37c7c 97 MAX30003::RtoR1Configuration_u CNFG_RTOR_r;
coreyharris 0:38c49bc37c7c 98 CNFG_RTOR_r.bits.en_rtor = 1;
coreyharris 0:38c49bc37c7c 99 ecgAFE.writeRegister( MAX30003::CNFG_RTOR1 , CNFG_RTOR_r.all);
coreyharris 0:38c49bc37c7c 100
coreyharris 0:38c49bc37c7c 101
coreyharris 0:38c49bc37c7c 102
coreyharris 0:38c49bc37c7c 103 // Manage interrupts register setting
coreyharris 0:38c49bc37c7c 104 MAX30003::ManageInterrupts_u MNG_INT_r;
coreyharris 0:38c49bc37c7c 105 MNG_INT_r.bits.efit = 0b01111;
coreyharris 0:38c49bc37c7c 106 ecgAFE.writeRegister( MAX30003::MNGR_INT , MNG_INT_r.all);
coreyharris 0:38c49bc37c7c 107
coreyharris 0:38c49bc37c7c 108
coreyharris 0:38c49bc37c7c 109
coreyharris 0:38c49bc37c7c 110 // Enable interrupts register setting
coreyharris 0:38c49bc37c7c 111 MAX30003::EnableInterrupts_u EN_INT_r;
coreyharris 0:38c49bc37c7c 112 EN_INT_r.all = 0;
coreyharris 0:38c49bc37c7c 113 EN_INT_r.bits.en_eint = 1;
coreyharris 0:38c49bc37c7c 114 EN_INT_r.bits.intb_type = 0b11;
coreyharris 0:38c49bc37c7c 115 ecgAFE.writeRegister( MAX30003::EN_INT , EN_INT_r.all);
coreyharris 0:38c49bc37c7c 116
coreyharris 0:38c49bc37c7c 117
coreyharris 0:38c49bc37c7c 118
coreyharris 0:38c49bc37c7c 119 // Dyanmic modes config
coreyharris 0:38c49bc37c7c 120 MAX30003::ManageDynamicModes_u MNG_DYN_r;
coreyharris 0:38c49bc37c7c 121 MNG_DYN_r.bits.fast = 0;
coreyharris 0:38c49bc37c7c 122 ecgAFE.writeRegister( MAX30003::MNGR_DYN , MNG_DYN_r.all);
coreyharris 0:38c49bc37c7c 123
coreyharris 0:38c49bc37c7c 124
coreyharris 0:38c49bc37c7c 125
coreyharris 0:38c49bc37c7c 126 // MUX Config
coreyharris 0:38c49bc37c7c 127 MAX30003::MuxConfiguration_u CNFG_MUX_r;
coreyharris 0:38c49bc37c7c 128 CNFG_MUX_r.bits.pol = 0;
coreyharris 0:38c49bc37c7c 129 ecgAFE.writeRegister( MAX30003::CNFG_EMUX , CNFG_MUX_r.all);
coreyharris 0:38c49bc37c7c 130
coreyharris 0:38c49bc37c7c 131
coreyharris 0:38c49bc37c7c 132 ecgAFE.writeRegister( MAX30003::SYNCH , 0);
coreyharris 0:38c49bc37c7c 133
coreyharris 0:38c49bc37c7c 134 }
coreyharris 0:38c49bc37c7c 135