Lancaster University / mbed-dev-bin

Binary version of Lancaster University's mbed branch, soon to be merged. The source lives here:https://developer.mbed.org/teams/Lancaster-University/code/mbed-src/

Dependents:   microbit-dal microbit-ble-open microbit-dal-eddystone microbit-dal ... more

Fork of mbed-lite-test by Lancaster University

TARGET_NRF51_MICROBIT/nrf51.h@3:768173a57492, 2016-07-13 (annotated)

Committer:
jamesadevine
Date:
Wed Jul 13 15:12:06 2016 +0100
Revision:
3:768173a57492
Parent:
2:e32c8485c88f 
further updates to mbed-dev-bin

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jamesadevine 2:e32c8485c88f 1 /*
jamesadevine 2:e32c8485c88f 2 * Copyright (c) Nordic Semiconductor ASA
jamesadevine 2:e32c8485c88f 3 * All rights reserved.
jamesadevine 2:e32c8485c88f 4 *
jamesadevine 2:e32c8485c88f 5 * Redistribution and use in source and binary forms, with or without modification,
jamesadevine 2:e32c8485c88f 6 * are permitted provided that the following conditions are met:
jamesadevine 2:e32c8485c88f 7 *
jamesadevine 2:e32c8485c88f 8 * 1. Redistributions of source code must retain the above copyright notice, this
jamesadevine 2:e32c8485c88f 9 * list of conditions and the following disclaimer.
jamesadevine 2:e32c8485c88f 10 *
jamesadevine 2:e32c8485c88f 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this
jamesadevine 2:e32c8485c88f 12 * list of conditions and the following disclaimer in the documentation and/or
jamesadevine 2:e32c8485c88f 13 * other materials provided with the distribution.
jamesadevine 2:e32c8485c88f 14 *
jamesadevine 2:e32c8485c88f 15 * 3. Neither the name of Nordic Semiconductor ASA nor the names of other
jamesadevine 2:e32c8485c88f 16 * contributors to this software may be used to endorse or promote products
jamesadevine 2:e32c8485c88f 17 * derived from this software without specific prior written permission.
jamesadevine 2:e32c8485c88f 18 *
jamesadevine 2:e32c8485c88f 19 *
jamesadevine 2:e32c8485c88f 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
jamesadevine 2:e32c8485c88f 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
jamesadevine 2:e32c8485c88f 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
jamesadevine 2:e32c8485c88f 23 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
jamesadevine 2:e32c8485c88f 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
jamesadevine 2:e32c8485c88f 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
jamesadevine 2:e32c8485c88f 26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
jamesadevine 2:e32c8485c88f 27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
jamesadevine 2:e32c8485c88f 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
jamesadevine 2:e32c8485c88f 29 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
jamesadevine 2:e32c8485c88f 30 *
jamesadevine 2:e32c8485c88f 31 */
jamesadevine 2:e32c8485c88f 32
jamesadevine 0:e1a608bb55e8 33 #ifndef NRF51_H
jamesadevine 0:e1a608bb55e8 34 #define NRF51_H
jamesadevine 0:e1a608bb55e8 35
jamesadevine 0:e1a608bb55e8 36 #ifdef __cplusplus
jamesadevine 0:e1a608bb55e8 37 extern "C" {
jamesadevine 0:e1a608bb55e8 38 #endif
jamesadevine 0:e1a608bb55e8 39
jamesadevine 0:e1a608bb55e8 40
jamesadevine 0:e1a608bb55e8 41 /* ------------------------- Interrupt Number Definition ------------------------ */
jamesadevine 0:e1a608bb55e8 42
jamesadevine 0:e1a608bb55e8 43 typedef enum {
jamesadevine 0:e1a608bb55e8 44 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
jamesadevine 0:e1a608bb55e8 45 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
jamesadevine 0:e1a608bb55e8 46 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
jamesadevine 0:e1a608bb55e8 47 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
jamesadevine 0:e1a608bb55e8 48 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
jamesadevine 0:e1a608bb55e8 49 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
jamesadevine 0:e1a608bb55e8 50 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
jamesadevine 0:e1a608bb55e8 51 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
jamesadevine 1:a7c51b5e0534 52 /* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
jamesadevine 0:e1a608bb55e8 53 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
jamesadevine 0:e1a608bb55e8 54 RADIO_IRQn = 1, /*!< 1 RADIO */
jamesadevine 0:e1a608bb55e8 55 UART0_IRQn = 2, /*!< 2 UART0 */
jamesadevine 0:e1a608bb55e8 56 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
jamesadevine 0:e1a608bb55e8 57 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
jamesadevine 0:e1a608bb55e8 58 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
jamesadevine 0:e1a608bb55e8 59 ADC_IRQn = 7, /*!< 7 ADC */
jamesadevine 0:e1a608bb55e8 60 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
jamesadevine 0:e1a608bb55e8 61 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
jamesadevine 0:e1a608bb55e8 62 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
jamesadevine 0:e1a608bb55e8 63 RTC0_IRQn = 11, /*!< 11 RTC0 */
jamesadevine 0:e1a608bb55e8 64 TEMP_IRQn = 12, /*!< 12 TEMP */
jamesadevine 0:e1a608bb55e8 65 RNG_IRQn = 13, /*!< 13 RNG */
jamesadevine 0:e1a608bb55e8 66 ECB_IRQn = 14, /*!< 14 ECB */
jamesadevine 0:e1a608bb55e8 67 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
jamesadevine 0:e1a608bb55e8 68 WDT_IRQn = 16, /*!< 16 WDT */
jamesadevine 0:e1a608bb55e8 69 RTC1_IRQn = 17, /*!< 17 RTC1 */
jamesadevine 0:e1a608bb55e8 70 QDEC_IRQn = 18, /*!< 18 QDEC */
jamesadevine 0:e1a608bb55e8 71 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
jamesadevine 0:e1a608bb55e8 72 SWI0_IRQn = 20, /*!< 20 SWI0 */
jamesadevine 0:e1a608bb55e8 73 SWI1_IRQn = 21, /*!< 21 SWI1 */
jamesadevine 0:e1a608bb55e8 74 SWI2_IRQn = 22, /*!< 22 SWI2 */
jamesadevine 0:e1a608bb55e8 75 SWI3_IRQn = 23, /*!< 23 SWI3 */
jamesadevine 0:e1a608bb55e8 76 SWI4_IRQn = 24, /*!< 24 SWI4 */
jamesadevine 0:e1a608bb55e8 77 SWI5_IRQn = 25 /*!< 25 SWI5 */
jamesadevine 0:e1a608bb55e8 78 } IRQn_Type;
jamesadevine 0:e1a608bb55e8 79
jamesadevine 0:e1a608bb55e8 80
jamesadevine 0:e1a608bb55e8 81 /** @addtogroup Configuration_of_CMSIS
jamesadevine 0:e1a608bb55e8 82 * @{
jamesadevine 0:e1a608bb55e8 83 */
jamesadevine 0:e1a608bb55e8 84
jamesadevine 0:e1a608bb55e8 85
jamesadevine 0:e1a608bb55e8 86 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 87 /* ================ Processor and Core Peripheral Section ================ */
jamesadevine 0:e1a608bb55e8 88 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 89
jamesadevine 0:e1a608bb55e8 90 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
jamesadevine 0:e1a608bb55e8 91 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
jamesadevine 0:e1a608bb55e8 92 #define __MPU_PRESENT 0 /*!< MPU present or not */
jamesadevine 0:e1a608bb55e8 93 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
jamesadevine 0:e1a608bb55e8 94 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
jamesadevine 0:e1a608bb55e8 95 /** @} */ /* End of group Configuration_of_CMSIS */
jamesadevine 0:e1a608bb55e8 96
jamesadevine 0:e1a608bb55e8 97 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
jamesadevine 1:a7c51b5e0534 98 #include "system_nrf51.h" /*!< nrf51 System */
jamesadevine 1:a7c51b5e0534 99
jamesadevine 0:e1a608bb55e8 100
jamesadevine 0:e1a608bb55e8 101 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 102 /* ================ Device Specific Peripheral Section ================ */
jamesadevine 0:e1a608bb55e8 103 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 104
jamesadevine 0:e1a608bb55e8 105
jamesadevine 0:e1a608bb55e8 106 /** @addtogroup Device_Peripheral_Registers
jamesadevine 0:e1a608bb55e8 107 * @{
jamesadevine 0:e1a608bb55e8 108 */
jamesadevine 0:e1a608bb55e8 109
jamesadevine 0:e1a608bb55e8 110
jamesadevine 0:e1a608bb55e8 111 /* ------------------- Start of section using anonymous unions ------------------ */
jamesadevine 0:e1a608bb55e8 112 #if defined(__CC_ARM)
jamesadevine 0:e1a608bb55e8 113 #pragma push
jamesadevine 0:e1a608bb55e8 114 #pragma anon_unions
jamesadevine 0:e1a608bb55e8 115 #elif defined(__ICCARM__)
jamesadevine 0:e1a608bb55e8 116 #pragma language=extended
jamesadevine 0:e1a608bb55e8 117 #elif defined(__GNUC__)
jamesadevine 0:e1a608bb55e8 118 /* anonymous unions are enabled by default */
jamesadevine 0:e1a608bb55e8 119 #elif defined(__TMS470__)
jamesadevine 0:e1a608bb55e8 120 /* anonymous unions are enabled by default */
jamesadevine 0:e1a608bb55e8 121 #elif defined(__TASKING__)
jamesadevine 0:e1a608bb55e8 122 #pragma warning 586
jamesadevine 0:e1a608bb55e8 123 #else
jamesadevine 0:e1a608bb55e8 124 #warning Not supported compiler type
jamesadevine 0:e1a608bb55e8 125 #endif
jamesadevine 0:e1a608bb55e8 126
jamesadevine 0:e1a608bb55e8 127
jamesadevine 0:e1a608bb55e8 128 typedef struct {
jamesadevine 0:e1a608bb55e8 129 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
jamesadevine 0:e1a608bb55e8 130 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
jamesadevine 0:e1a608bb55e8 131 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
jamesadevine 0:e1a608bb55e8 132 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
jamesadevine 0:e1a608bb55e8 133 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
jamesadevine 0:e1a608bb55e8 134 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
jamesadevine 0:e1a608bb55e8 135 } AMLI_RAMPRI_Type;
jamesadevine 0:e1a608bb55e8 136
jamesadevine 0:e1a608bb55e8 137 typedef struct {
jamesadevine 0:e1a608bb55e8 138 __IO uint32_t SCK; /*!< Pin select for SCK. */
jamesadevine 0:e1a608bb55e8 139 __IO uint32_t MOSI; /*!< Pin select for MOSI. */
jamesadevine 0:e1a608bb55e8 140 __IO uint32_t MISO; /*!< Pin select for MISO. */
jamesadevine 0:e1a608bb55e8 141 } SPIM_PSEL_Type;
jamesadevine 0:e1a608bb55e8 142
jamesadevine 0:e1a608bb55e8 143 typedef struct {
jamesadevine 0:e1a608bb55e8 144 __IO uint32_t PTR; /*!< Data pointer. */
jamesadevine 0:e1a608bb55e8 145 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
jamesadevine 0:e1a608bb55e8 146 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
jamesadevine 0:e1a608bb55e8 147 } SPIM_RXD_Type;
jamesadevine 0:e1a608bb55e8 148
jamesadevine 0:e1a608bb55e8 149 typedef struct {
jamesadevine 0:e1a608bb55e8 150 __IO uint32_t PTR; /*!< Data pointer. */
jamesadevine 0:e1a608bb55e8 151 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
jamesadevine 0:e1a608bb55e8 152 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
jamesadevine 0:e1a608bb55e8 153 } SPIM_TXD_Type;
jamesadevine 0:e1a608bb55e8 154
jamesadevine 0:e1a608bb55e8 155 typedef struct {
jamesadevine 0:e1a608bb55e8 156 __O uint32_t EN; /*!< Enable channel group. */
jamesadevine 0:e1a608bb55e8 157 __O uint32_t DIS; /*!< Disable channel group. */
jamesadevine 0:e1a608bb55e8 158 } PPI_TASKS_CHG_Type;
jamesadevine 0:e1a608bb55e8 159
jamesadevine 0:e1a608bb55e8 160 typedef struct {
jamesadevine 0:e1a608bb55e8 161 __IO uint32_t EEP; /*!< Channel event end-point. */
jamesadevine 0:e1a608bb55e8 162 __IO uint32_t TEP; /*!< Channel task end-point. */
jamesadevine 0:e1a608bb55e8 163 } PPI_CH_Type;
jamesadevine 0:e1a608bb55e8 164
jamesadevine 0:e1a608bb55e8 165
jamesadevine 0:e1a608bb55e8 166 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 167 /* ================ POWER ================ */
jamesadevine 0:e1a608bb55e8 168 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 169
jamesadevine 0:e1a608bb55e8 170
jamesadevine 0:e1a608bb55e8 171 /**
jamesadevine 0:e1a608bb55e8 172 * @brief Power Control. (POWER)
jamesadevine 0:e1a608bb55e8 173 */
jamesadevine 0:e1a608bb55e8 174
jamesadevine 0:e1a608bb55e8 175 typedef struct { /*!< POWER Structure */
jamesadevine 0:e1a608bb55e8 176 __I uint32_t RESERVED0[30];
jamesadevine 0:e1a608bb55e8 177 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
jamesadevine 0:e1a608bb55e8 178 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
jamesadevine 0:e1a608bb55e8 179 __I uint32_t RESERVED1[34];
jamesadevine 0:e1a608bb55e8 180 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
jamesadevine 0:e1a608bb55e8 181 __I uint32_t RESERVED2[126];
jamesadevine 0:e1a608bb55e8 182 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
jamesadevine 0:e1a608bb55e8 183 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
jamesadevine 0:e1a608bb55e8 184 __I uint32_t RESERVED3[61];
jamesadevine 0:e1a608bb55e8 185 __IO uint32_t RESETREAS; /*!< Reset reason. */
jamesadevine 0:e1a608bb55e8 186 __I uint32_t RESERVED4[9];
jamesadevine 0:e1a608bb55e8 187 __I uint32_t RAMSTATUS; /*!< Ram status register. */
jamesadevine 0:e1a608bb55e8 188 __I uint32_t RESERVED5[53];
jamesadevine 0:e1a608bb55e8 189 __O uint32_t SYSTEMOFF; /*!< System off register. */
jamesadevine 0:e1a608bb55e8 190 __I uint32_t RESERVED6[3];
jamesadevine 0:e1a608bb55e8 191 __IO uint32_t POFCON; /*!< Power failure configuration. */
jamesadevine 0:e1a608bb55e8 192 __I uint32_t RESERVED7[2];
jamesadevine 0:e1a608bb55e8 193 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
jamesadevine 0:e1a608bb55e8 194 register. */
jamesadevine 0:e1a608bb55e8 195 __I uint32_t RESERVED8;
jamesadevine 0:e1a608bb55e8 196 __IO uint32_t RAMON; /*!< Ram on/off. */
jamesadevine 0:e1a608bb55e8 197 __I uint32_t RESERVED9[7];
jamesadevine 0:e1a608bb55e8 198 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
jamesadevine 0:e1a608bb55e8 199 is a retained register. */
jamesadevine 0:e1a608bb55e8 200 __I uint32_t RESERVED10[3];
jamesadevine 0:e1a608bb55e8 201 __IO uint32_t RAMONB; /*!< Ram on/off. */
jamesadevine 0:e1a608bb55e8 202 __I uint32_t RESERVED11[8];
jamesadevine 0:e1a608bb55e8 203 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
jamesadevine 0:e1a608bb55e8 204 __I uint32_t RESERVED12[291];
jamesadevine 0:e1a608bb55e8 205 __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
jamesadevine 0:e1a608bb55e8 206 } NRF_POWER_Type;
jamesadevine 0:e1a608bb55e8 207
jamesadevine 0:e1a608bb55e8 208
jamesadevine 0:e1a608bb55e8 209 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 210 /* ================ CLOCK ================ */
jamesadevine 0:e1a608bb55e8 211 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 212
jamesadevine 0:e1a608bb55e8 213
jamesadevine 0:e1a608bb55e8 214 /**
jamesadevine 0:e1a608bb55e8 215 * @brief Clock control. (CLOCK)
jamesadevine 0:e1a608bb55e8 216 */
jamesadevine 0:e1a608bb55e8 217
jamesadevine 0:e1a608bb55e8 218 typedef struct { /*!< CLOCK Structure */
jamesadevine 0:e1a608bb55e8 219 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
jamesadevine 0:e1a608bb55e8 220 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
jamesadevine 0:e1a608bb55e8 221 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
jamesadevine 0:e1a608bb55e8 222 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
jamesadevine 0:e1a608bb55e8 223 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
jamesadevine 0:e1a608bb55e8 224 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
jamesadevine 0:e1a608bb55e8 225 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
jamesadevine 0:e1a608bb55e8 226 __I uint32_t RESERVED0[57];
jamesadevine 0:e1a608bb55e8 227 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
jamesadevine 0:e1a608bb55e8 228 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
jamesadevine 0:e1a608bb55e8 229 __I uint32_t RESERVED1;
jamesadevine 0:e1a608bb55e8 230 __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
jamesadevine 0:e1a608bb55e8 231 __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
jamesadevine 0:e1a608bb55e8 232 __I uint32_t RESERVED2[124];
jamesadevine 0:e1a608bb55e8 233 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
jamesadevine 0:e1a608bb55e8 234 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
jamesadevine 0:e1a608bb55e8 235 __I uint32_t RESERVED3[63];
jamesadevine 0:e1a608bb55e8 236 __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
jamesadevine 0:e1a608bb55e8 237 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
jamesadevine 0:e1a608bb55e8 238 __I uint32_t RESERVED4;
jamesadevine 0:e1a608bb55e8 239 __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
jamesadevine 0:e1a608bb55e8 240 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
jamesadevine 0:e1a608bb55e8 241 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
jamesadevine 0:e1a608bb55e8 242 triggered. */
jamesadevine 0:e1a608bb55e8 243 __I uint32_t RESERVED5[62];
jamesadevine 0:e1a608bb55e8 244 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
jamesadevine 0:e1a608bb55e8 245 __I uint32_t RESERVED6[7];
jamesadevine 0:e1a608bb55e8 246 __IO uint32_t CTIV; /*!< Calibration timer interval. */
jamesadevine 0:e1a608bb55e8 247 __I uint32_t RESERVED7[5];
jamesadevine 0:e1a608bb55e8 248 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
jamesadevine 0:e1a608bb55e8 249 } NRF_CLOCK_Type;
jamesadevine 0:e1a608bb55e8 250
jamesadevine 0:e1a608bb55e8 251
jamesadevine 0:e1a608bb55e8 252 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 253 /* ================ MPU ================ */
jamesadevine 0:e1a608bb55e8 254 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 255
jamesadevine 0:e1a608bb55e8 256
jamesadevine 0:e1a608bb55e8 257 /**
jamesadevine 0:e1a608bb55e8 258 * @brief Memory Protection Unit. (MPU)
jamesadevine 0:e1a608bb55e8 259 */
jamesadevine 0:e1a608bb55e8 260
jamesadevine 0:e1a608bb55e8 261 typedef struct { /*!< MPU Structure */
jamesadevine 0:e1a608bb55e8 262 __I uint32_t RESERVED0[330];
jamesadevine 0:e1a608bb55e8 263 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
jamesadevine 0:e1a608bb55e8 264 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
jamesadevine 0:e1a608bb55e8 265 __I uint32_t RESERVED1[52];
jamesadevine 0:e1a608bb55e8 266 __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
jamesadevine 0:e1a608bb55e8 267 __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
jamesadevine 0:e1a608bb55e8 268 __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
jamesadevine 0:e1a608bb55e8 269 __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
jamesadevine 0:e1a608bb55e8 270 } NRF_MPU_Type;
jamesadevine 0:e1a608bb55e8 271
jamesadevine 0:e1a608bb55e8 272
jamesadevine 0:e1a608bb55e8 273 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 274 /* ================ AMLI ================ */
jamesadevine 0:e1a608bb55e8 275 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 276
jamesadevine 0:e1a608bb55e8 277
jamesadevine 0:e1a608bb55e8 278 /**
jamesadevine 0:e1a608bb55e8 279 * @brief AHB Multi-Layer Interface. (AMLI)
jamesadevine 0:e1a608bb55e8 280 */
jamesadevine 0:e1a608bb55e8 281
jamesadevine 0:e1a608bb55e8 282 typedef struct { /*!< AMLI Structure */
jamesadevine 0:e1a608bb55e8 283 __I uint32_t RESERVED0[896];
jamesadevine 0:e1a608bb55e8 284 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
jamesadevine 0:e1a608bb55e8 285 } NRF_AMLI_Type;
jamesadevine 0:e1a608bb55e8 286
jamesadevine 0:e1a608bb55e8 287
jamesadevine 0:e1a608bb55e8 288 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 289 /* ================ RADIO ================ */
jamesadevine 0:e1a608bb55e8 290 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 291
jamesadevine 0:e1a608bb55e8 292
jamesadevine 0:e1a608bb55e8 293 /**
jamesadevine 0:e1a608bb55e8 294 * @brief The radio. (RADIO)
jamesadevine 0:e1a608bb55e8 295 */
jamesadevine 0:e1a608bb55e8 296
jamesadevine 0:e1a608bb55e8 297 typedef struct { /*!< RADIO Structure */
jamesadevine 0:e1a608bb55e8 298 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
jamesadevine 0:e1a608bb55e8 299 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
jamesadevine 0:e1a608bb55e8 300 __O uint32_t TASKS_START; /*!< Start radio. */
jamesadevine 0:e1a608bb55e8 301 __O uint32_t TASKS_STOP; /*!< Stop radio. */
jamesadevine 0:e1a608bb55e8 302 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
jamesadevine 0:e1a608bb55e8 303 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
jamesadevine 0:e1a608bb55e8 304 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
jamesadevine 0:e1a608bb55e8 305 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
jamesadevine 0:e1a608bb55e8 306 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
jamesadevine 0:e1a608bb55e8 307 __I uint32_t RESERVED0[55];
jamesadevine 0:e1a608bb55e8 308 __IO uint32_t EVENTS_READY; /*!< Ready event. */
jamesadevine 0:e1a608bb55e8 309 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
jamesadevine 0:e1a608bb55e8 310 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
jamesadevine 0:e1a608bb55e8 311 __IO uint32_t EVENTS_END; /*!< End event. */
jamesadevine 0:e1a608bb55e8 312 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
jamesadevine 0:e1a608bb55e8 313 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
jamesadevine 0:e1a608bb55e8 314 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
jamesadevine 0:e1a608bb55e8 315 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
jamesadevine 0:e1a608bb55e8 316 sample is ready for readout at the RSSISAMPLE register. */
jamesadevine 0:e1a608bb55e8 317 __I uint32_t RESERVED1[2];
jamesadevine 1:a7c51b5e0534 318 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */
jamesadevine 0:e1a608bb55e8 319 __I uint32_t RESERVED2[53];
jamesadevine 0:e1a608bb55e8 320 __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
jamesadevine 0:e1a608bb55e8 321 __I uint32_t RESERVED3[64];
jamesadevine 0:e1a608bb55e8 322 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
jamesadevine 0:e1a608bb55e8 323 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
jamesadevine 0:e1a608bb55e8 324 __I uint32_t RESERVED4[61];
jamesadevine 0:e1a608bb55e8 325 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
jamesadevine 1:a7c51b5e0534 326 __I uint32_t RESERVED5;
jamesadevine 0:e1a608bb55e8 327 __I uint32_t RXMATCH; /*!< Received address. */
jamesadevine 0:e1a608bb55e8 328 __I uint32_t RXCRC; /*!< Received CRC. */
jamesadevine 0:e1a608bb55e8 329 __I uint32_t DAI; /*!< Device address match index. */
jamesadevine 1:a7c51b5e0534 330 __I uint32_t RESERVED6[60];
jamesadevine 0:e1a608bb55e8 331 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
jamesadevine 0:e1a608bb55e8 332 __IO uint32_t FREQUENCY; /*!< Frequency. */
jamesadevine 0:e1a608bb55e8 333 __IO uint32_t TXPOWER; /*!< Output power. */
jamesadevine 0:e1a608bb55e8 334 __IO uint32_t MODE; /*!< Data rate and modulation. */
jamesadevine 0:e1a608bb55e8 335 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
jamesadevine 0:e1a608bb55e8 336 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
jamesadevine 0:e1a608bb55e8 337 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
jamesadevine 0:e1a608bb55e8 338 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
jamesadevine 0:e1a608bb55e8 339 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
jamesadevine 0:e1a608bb55e8 340 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
jamesadevine 0:e1a608bb55e8 341 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
jamesadevine 0:e1a608bb55e8 342 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
jamesadevine 0:e1a608bb55e8 343 __IO uint32_t CRCCNF; /*!< CRC configuration. */
jamesadevine 0:e1a608bb55e8 344 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
jamesadevine 0:e1a608bb55e8 345 __IO uint32_t CRCINIT; /*!< CRC initial value. */
jamesadevine 0:e1a608bb55e8 346 __IO uint32_t TEST; /*!< Test features enable register. */
jamesadevine 0:e1a608bb55e8 347 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
jamesadevine 0:e1a608bb55e8 348 __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
jamesadevine 1:a7c51b5e0534 349 __I uint32_t RESERVED7;
jamesadevine 0:e1a608bb55e8 350 __I uint32_t STATE; /*!< Current radio state. */
jamesadevine 0:e1a608bb55e8 351 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
jamesadevine 1:a7c51b5e0534 352 __I uint32_t RESERVED8[2];
jamesadevine 0:e1a608bb55e8 353 __IO uint32_t BCC; /*!< Bit counter compare. */
jamesadevine 1:a7c51b5e0534 354 __I uint32_t RESERVED9[39];
jamesadevine 0:e1a608bb55e8 355 __IO uint32_t DAB[8]; /*!< Device address base segment. */
jamesadevine 0:e1a608bb55e8 356 __IO uint32_t DAP[8]; /*!< Device address prefix. */
jamesadevine 0:e1a608bb55e8 357 __IO uint32_t DACNF; /*!< Device address match configuration. */
jamesadevine 1:a7c51b5e0534 358 __I uint32_t RESERVED10[56];
jamesadevine 0:e1a608bb55e8 359 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
jamesadevine 0:e1a608bb55e8 360 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
jamesadevine 0:e1a608bb55e8 361 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
jamesadevine 0:e1a608bb55e8 362 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
jamesadevine 0:e1a608bb55e8 363 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
jamesadevine 1:a7c51b5e0534 364 __I uint32_t RESERVED11[561];
jamesadevine 0:e1a608bb55e8 365 __IO uint32_t POWER; /*!< Peripheral power control. */
jamesadevine 0:e1a608bb55e8 366 } NRF_RADIO_Type;
jamesadevine 0:e1a608bb55e8 367
jamesadevine 0:e1a608bb55e8 368
jamesadevine 0:e1a608bb55e8 369 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 370 /* ================ UART ================ */
jamesadevine 0:e1a608bb55e8 371 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 372
jamesadevine 0:e1a608bb55e8 373
jamesadevine 0:e1a608bb55e8 374 /**
jamesadevine 0:e1a608bb55e8 375 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
jamesadevine 0:e1a608bb55e8 376 */
jamesadevine 0:e1a608bb55e8 377
jamesadevine 0:e1a608bb55e8 378 typedef struct { /*!< UART Structure */
jamesadevine 0:e1a608bb55e8 379 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
jamesadevine 0:e1a608bb55e8 380 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
jamesadevine 0:e1a608bb55e8 381 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
jamesadevine 0:e1a608bb55e8 382 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
jamesadevine 0:e1a608bb55e8 383 __I uint32_t RESERVED0[3];
jamesadevine 0:e1a608bb55e8 384 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
jamesadevine 0:e1a608bb55e8 385 __I uint32_t RESERVED1[56];
jamesadevine 0:e1a608bb55e8 386 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
jamesadevine 0:e1a608bb55e8 387 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
jamesadevine 0:e1a608bb55e8 388 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
jamesadevine 0:e1a608bb55e8 389 __I uint32_t RESERVED2[4];
jamesadevine 0:e1a608bb55e8 390 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
jamesadevine 0:e1a608bb55e8 391 __I uint32_t RESERVED3;
jamesadevine 0:e1a608bb55e8 392 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
jamesadevine 0:e1a608bb55e8 393 __I uint32_t RESERVED4[7];
jamesadevine 0:e1a608bb55e8 394 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
jamesadevine 0:e1a608bb55e8 395 __I uint32_t RESERVED5[46];
jamesadevine 0:e1a608bb55e8 396 __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
jamesadevine 0:e1a608bb55e8 397 __I uint32_t RESERVED6[64];
jamesadevine 0:e1a608bb55e8 398 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
jamesadevine 0:e1a608bb55e8 399 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
jamesadevine 0:e1a608bb55e8 400 __I uint32_t RESERVED7[93];
jamesadevine 0:e1a608bb55e8 401 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
jamesadevine 0:e1a608bb55e8 402 __I uint32_t RESERVED8[31];
jamesadevine 0:e1a608bb55e8 403 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
jamesadevine 0:e1a608bb55e8 404 __I uint32_t RESERVED9;
jamesadevine 0:e1a608bb55e8 405 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
jamesadevine 0:e1a608bb55e8 406 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
jamesadevine 0:e1a608bb55e8 407 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
jamesadevine 0:e1a608bb55e8 408 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
jamesadevine 0:e1a608bb55e8 409 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
jamesadevine 0:e1a608bb55e8 410 Once read the character is consumed. If read when no character
jamesadevine 0:e1a608bb55e8 411 available, the UART will stop working. */
jamesadevine 0:e1a608bb55e8 412 __O uint32_t TXD; /*!< TXD register. */
jamesadevine 0:e1a608bb55e8 413 __I uint32_t RESERVED10;
jamesadevine 0:e1a608bb55e8 414 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
jamesadevine 0:e1a608bb55e8 415 __I uint32_t RESERVED11[17];
jamesadevine 0:e1a608bb55e8 416 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
jamesadevine 0:e1a608bb55e8 417 __I uint32_t RESERVED12[675];
jamesadevine 0:e1a608bb55e8 418 __IO uint32_t POWER; /*!< Peripheral power control. */
jamesadevine 0:e1a608bb55e8 419 } NRF_UART_Type;
jamesadevine 0:e1a608bb55e8 420
jamesadevine 0:e1a608bb55e8 421
jamesadevine 0:e1a608bb55e8 422 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 423 /* ================ SPI ================ */
jamesadevine 0:e1a608bb55e8 424 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 425
jamesadevine 0:e1a608bb55e8 426
jamesadevine 0:e1a608bb55e8 427 /**
jamesadevine 0:e1a608bb55e8 428 * @brief SPI master 0. (SPI)
jamesadevine 0:e1a608bb55e8 429 */
jamesadevine 0:e1a608bb55e8 430
jamesadevine 0:e1a608bb55e8 431 typedef struct { /*!< SPI Structure */
jamesadevine 0:e1a608bb55e8 432 __I uint32_t RESERVED0[66];
jamesadevine 0:e1a608bb55e8 433 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
jamesadevine 0:e1a608bb55e8 434 __I uint32_t RESERVED1[126];
jamesadevine 0:e1a608bb55e8 435 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
jamesadevine 0:e1a608bb55e8 436 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
jamesadevine 0:e1a608bb55e8 437 __I uint32_t RESERVED2[125];
jamesadevine 0:e1a608bb55e8 438 __IO uint32_t ENABLE; /*!< Enable SPI. */
jamesadevine 0:e1a608bb55e8 439 __I uint32_t RESERVED3;
jamesadevine 0:e1a608bb55e8 440 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
jamesadevine 0:e1a608bb55e8 441 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
jamesadevine 0:e1a608bb55e8 442 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
jamesadevine 0:e1a608bb55e8 443 __I uint32_t RESERVED4;
jamesadevine 0:e1a608bb55e8 444 __I uint32_t RXD; /*!< RX data. */
jamesadevine 0:e1a608bb55e8 445 __IO uint32_t TXD; /*!< TX data. */
jamesadevine 0:e1a608bb55e8 446 __I uint32_t RESERVED5;
jamesadevine 0:e1a608bb55e8 447 __IO uint32_t FREQUENCY; /*!< SPI frequency */
jamesadevine 0:e1a608bb55e8 448 __I uint32_t RESERVED6[11];
jamesadevine 0:e1a608bb55e8 449 __IO uint32_t CONFIG; /*!< Configuration register. */
jamesadevine 0:e1a608bb55e8 450 __I uint32_t RESERVED7[681];
jamesadevine 0:e1a608bb55e8 451 __IO uint32_t POWER; /*!< Peripheral power control. */
jamesadevine 0:e1a608bb55e8 452 } NRF_SPI_Type;
jamesadevine 0:e1a608bb55e8 453
jamesadevine 0:e1a608bb55e8 454
jamesadevine 0:e1a608bb55e8 455 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 456 /* ================ TWI ================ */
jamesadevine 0:e1a608bb55e8 457 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 458
jamesadevine 0:e1a608bb55e8 459
jamesadevine 0:e1a608bb55e8 460 /**
jamesadevine 0:e1a608bb55e8 461 * @brief Two-wire interface master 0. (TWI)
jamesadevine 0:e1a608bb55e8 462 */
jamesadevine 0:e1a608bb55e8 463
jamesadevine 0:e1a608bb55e8 464 typedef struct { /*!< TWI Structure */
jamesadevine 0:e1a608bb55e8 465 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
jamesadevine 0:e1a608bb55e8 466 __I uint32_t RESERVED0;
jamesadevine 0:e1a608bb55e8 467 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
jamesadevine 0:e1a608bb55e8 468 __I uint32_t RESERVED1[2];
jamesadevine 0:e1a608bb55e8 469 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
jamesadevine 0:e1a608bb55e8 470 __I uint32_t RESERVED2;
jamesadevine 0:e1a608bb55e8 471 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
jamesadevine 0:e1a608bb55e8 472 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
jamesadevine 0:e1a608bb55e8 473 __I uint32_t RESERVED3[56];
jamesadevine 0:e1a608bb55e8 474 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
jamesadevine 0:e1a608bb55e8 475 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
jamesadevine 0:e1a608bb55e8 476 __I uint32_t RESERVED4[4];
jamesadevine 0:e1a608bb55e8 477 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
jamesadevine 0:e1a608bb55e8 478 __I uint32_t RESERVED5;
jamesadevine 0:e1a608bb55e8 479 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
jamesadevine 0:e1a608bb55e8 480 __I uint32_t RESERVED6[4];
jamesadevine 0:e1a608bb55e8 481 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
jamesadevine 0:e1a608bb55e8 482 __I uint32_t RESERVED7[3];
jamesadevine 0:e1a608bb55e8 483 __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
jamesadevine 0:e1a608bb55e8 484 __I uint32_t RESERVED8[45];
jamesadevine 0:e1a608bb55e8 485 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
jamesadevine 0:e1a608bb55e8 486 __I uint32_t RESERVED9[64];
jamesadevine 0:e1a608bb55e8 487 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
jamesadevine 0:e1a608bb55e8 488 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
jamesadevine 0:e1a608bb55e8 489 __I uint32_t RESERVED10[110];
jamesadevine 0:e1a608bb55e8 490 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
jamesadevine 0:e1a608bb55e8 491 __I uint32_t RESERVED11[14];
jamesadevine 0:e1a608bb55e8 492 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
jamesadevine 0:e1a608bb55e8 493 __I uint32_t RESERVED12;
jamesadevine 0:e1a608bb55e8 494 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
jamesadevine 0:e1a608bb55e8 495 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
jamesadevine 0:e1a608bb55e8 496 __I uint32_t RESERVED13[2];
jamesadevine 0:e1a608bb55e8 497 __I uint32_t RXD; /*!< RX data register. */
jamesadevine 0:e1a608bb55e8 498 __IO uint32_t TXD; /*!< TX data register. */
jamesadevine 0:e1a608bb55e8 499 __I uint32_t RESERVED14;
jamesadevine 0:e1a608bb55e8 500 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
jamesadevine 0:e1a608bb55e8 501 __I uint32_t RESERVED15[24];
jamesadevine 0:e1a608bb55e8 502 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
jamesadevine 0:e1a608bb55e8 503 __I uint32_t RESERVED16[668];
jamesadevine 0:e1a608bb55e8 504 __IO uint32_t POWER; /*!< Peripheral power control. */
jamesadevine 0:e1a608bb55e8 505 } NRF_TWI_Type;
jamesadevine 0:e1a608bb55e8 506
jamesadevine 0:e1a608bb55e8 507
jamesadevine 0:e1a608bb55e8 508 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 509 /* ================ SPIS ================ */
jamesadevine 0:e1a608bb55e8 510 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 511
jamesadevine 0:e1a608bb55e8 512
jamesadevine 0:e1a608bb55e8 513 /**
jamesadevine 0:e1a608bb55e8 514 * @brief SPI slave 1. (SPIS)
jamesadevine 0:e1a608bb55e8 515 */
jamesadevine 0:e1a608bb55e8 516
jamesadevine 0:e1a608bb55e8 517 typedef struct { /*!< SPIS Structure */
jamesadevine 0:e1a608bb55e8 518 __I uint32_t RESERVED0[9];
jamesadevine 0:e1a608bb55e8 519 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
jamesadevine 0:e1a608bb55e8 520 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
jamesadevine 0:e1a608bb55e8 521 __I uint32_t RESERVED1[54];
jamesadevine 0:e1a608bb55e8 522 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
jamesadevine 1:a7c51b5e0534 523 __I uint32_t RESERVED2[2];
jamesadevine 1:a7c51b5e0534 524 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
jamesadevine 1:a7c51b5e0534 525 __I uint32_t RESERVED3[5];
jamesadevine 0:e1a608bb55e8 526 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
jamesadevine 1:a7c51b5e0534 527 __I uint32_t RESERVED4[53];
jamesadevine 0:e1a608bb55e8 528 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
jamesadevine 1:a7c51b5e0534 529 __I uint32_t RESERVED5[64];
jamesadevine 0:e1a608bb55e8 530 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
jamesadevine 0:e1a608bb55e8 531 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
jamesadevine 1:a7c51b5e0534 532 __I uint32_t RESERVED6[61];
jamesadevine 0:e1a608bb55e8 533 __I uint32_t SEMSTAT; /*!< Semaphore status. */
jamesadevine 1:a7c51b5e0534 534 __I uint32_t RESERVED7[15];
jamesadevine 0:e1a608bb55e8 535 __IO uint32_t STATUS; /*!< Status from last transaction. */
jamesadevine 1:a7c51b5e0534 536 __I uint32_t RESERVED8[47];
jamesadevine 0:e1a608bb55e8 537 __IO uint32_t ENABLE; /*!< Enable SPIS. */
jamesadevine 1:a7c51b5e0534 538 __I uint32_t RESERVED9;
jamesadevine 0:e1a608bb55e8 539 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
jamesadevine 0:e1a608bb55e8 540 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
jamesadevine 0:e1a608bb55e8 541 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
jamesadevine 0:e1a608bb55e8 542 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
jamesadevine 1:a7c51b5e0534 543 __I uint32_t RESERVED10[7];
jamesadevine 0:e1a608bb55e8 544 __IO uint32_t RXDPTR; /*!< RX data pointer. */
jamesadevine 0:e1a608bb55e8 545 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
jamesadevine 0:e1a608bb55e8 546 __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
jamesadevine 1:a7c51b5e0534 547 __I uint32_t RESERVED11;
jamesadevine 0:e1a608bb55e8 548 __IO uint32_t TXDPTR; /*!< TX data pointer. */
jamesadevine 0:e1a608bb55e8 549 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
jamesadevine 0:e1a608bb55e8 550 __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
jamesadevine 1:a7c51b5e0534 551 __I uint32_t RESERVED12;
jamesadevine 0:e1a608bb55e8 552 __IO uint32_t CONFIG; /*!< Configuration register. */
jamesadevine 1:a7c51b5e0534 553 __I uint32_t RESERVED13;
jamesadevine 0:e1a608bb55e8 554 __IO uint32_t DEF; /*!< Default character. */
jamesadevine 1:a7c51b5e0534 555 __I uint32_t RESERVED14[24];
jamesadevine 0:e1a608bb55e8 556 __IO uint32_t ORC; /*!< Over-read character. */
jamesadevine 1:a7c51b5e0534 557 __I uint32_t RESERVED15[654];
jamesadevine 0:e1a608bb55e8 558 __IO uint32_t POWER; /*!< Peripheral power control. */
jamesadevine 0:e1a608bb55e8 559 } NRF_SPIS_Type;
jamesadevine 0:e1a608bb55e8 560
jamesadevine 0:e1a608bb55e8 561
jamesadevine 0:e1a608bb55e8 562 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 563 /* ================ SPIM ================ */
jamesadevine 0:e1a608bb55e8 564 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 565
jamesadevine 0:e1a608bb55e8 566
jamesadevine 0:e1a608bb55e8 567 /**
jamesadevine 0:e1a608bb55e8 568 * @brief SPI master with easyDMA 1. (SPIM)
jamesadevine 0:e1a608bb55e8 569 */
jamesadevine 0:e1a608bb55e8 570
jamesadevine 0:e1a608bb55e8 571 typedef struct { /*!< SPIM Structure */
jamesadevine 0:e1a608bb55e8 572 __I uint32_t RESERVED0[4];
jamesadevine 0:e1a608bb55e8 573 __O uint32_t TASKS_START; /*!< Start SPI transaction. */
jamesadevine 0:e1a608bb55e8 574 __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
jamesadevine 0:e1a608bb55e8 575 __I uint32_t RESERVED1;
jamesadevine 0:e1a608bb55e8 576 __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
jamesadevine 0:e1a608bb55e8 577 __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
jamesadevine 0:e1a608bb55e8 578 __I uint32_t RESERVED2[56];
jamesadevine 0:e1a608bb55e8 579 __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
jamesadevine 0:e1a608bb55e8 580 __I uint32_t RESERVED3[2];
jamesadevine 0:e1a608bb55e8 581 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
jamesadevine 1:a7c51b5e0534 582 __I uint32_t RESERVED4[3];
jamesadevine 0:e1a608bb55e8 583 __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
jamesadevine 1:a7c51b5e0534 584 __I uint32_t RESERVED5[10];
jamesadevine 0:e1a608bb55e8 585 __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
jamesadevine 1:a7c51b5e0534 586 __I uint32_t RESERVED6[109];
jamesadevine 0:e1a608bb55e8 587 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
jamesadevine 0:e1a608bb55e8 588 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
jamesadevine 1:a7c51b5e0534 589 __I uint32_t RESERVED7[125];
jamesadevine 0:e1a608bb55e8 590 __IO uint32_t ENABLE; /*!< Enable SPIM. */
jamesadevine 1:a7c51b5e0534 591 __I uint32_t RESERVED8;
jamesadevine 0:e1a608bb55e8 592 SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
jamesadevine 1:a7c51b5e0534 593 __I uint32_t RESERVED9[4];
jamesadevine 0:e1a608bb55e8 594 __IO uint32_t FREQUENCY; /*!< SPI frequency. */
jamesadevine 1:a7c51b5e0534 595 __I uint32_t RESERVED10[3];
jamesadevine 0:e1a608bb55e8 596 SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
jamesadevine 1:a7c51b5e0534 597 __I uint32_t RESERVED11;
jamesadevine 0:e1a608bb55e8 598 SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
jamesadevine 1:a7c51b5e0534 599 __I uint32_t RESERVED12;
jamesadevine 0:e1a608bb55e8 600 __IO uint32_t CONFIG; /*!< Configuration register. */
jamesadevine 1:a7c51b5e0534 601 __I uint32_t RESERVED13[26];
jamesadevine 0:e1a608bb55e8 602 __IO uint32_t ORC; /*!< Over-read character. */
jamesadevine 1:a7c51b5e0534 603 __I uint32_t RESERVED14[654];
jamesadevine 0:e1a608bb55e8 604 __IO uint32_t POWER; /*!< Peripheral power control. */
jamesadevine 0:e1a608bb55e8 605 } NRF_SPIM_Type;
jamesadevine 0:e1a608bb55e8 606
jamesadevine 0:e1a608bb55e8 607
jamesadevine 0:e1a608bb55e8 608 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 609 /* ================ GPIOTE ================ */
jamesadevine 0:e1a608bb55e8 610 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 611
jamesadevine 0:e1a608bb55e8 612
jamesadevine 0:e1a608bb55e8 613 /**
jamesadevine 0:e1a608bb55e8 614 * @brief GPIO tasks and events. (GPIOTE)
jamesadevine 0:e1a608bb55e8 615 */
jamesadevine 0:e1a608bb55e8 616
jamesadevine 0:e1a608bb55e8 617 typedef struct { /*!< GPIOTE Structure */
jamesadevine 0:e1a608bb55e8 618 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
jamesadevine 0:e1a608bb55e8 619 __I uint32_t RESERVED0[60];
jamesadevine 0:e1a608bb55e8 620 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
jamesadevine 0:e1a608bb55e8 621 __I uint32_t RESERVED1[27];
jamesadevine 0:e1a608bb55e8 622 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
jamesadevine 0:e1a608bb55e8 623 __I uint32_t RESERVED2[97];
jamesadevine 0:e1a608bb55e8 624 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
jamesadevine 0:e1a608bb55e8 625 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
jamesadevine 0:e1a608bb55e8 626 __I uint32_t RESERVED3[129];
jamesadevine 0:e1a608bb55e8 627 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
jamesadevine 0:e1a608bb55e8 628 __I uint32_t RESERVED4[695];
jamesadevine 0:e1a608bb55e8 629 __IO uint32_t POWER; /*!< Peripheral power control. */
jamesadevine 0:e1a608bb55e8 630 } NRF_GPIOTE_Type;
jamesadevine 0:e1a608bb55e8 631
jamesadevine 0:e1a608bb55e8 632
jamesadevine 0:e1a608bb55e8 633 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 634 /* ================ ADC ================ */
jamesadevine 0:e1a608bb55e8 635 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 636
jamesadevine 0:e1a608bb55e8 637
jamesadevine 0:e1a608bb55e8 638 /**
jamesadevine 0:e1a608bb55e8 639 * @brief Analog to digital converter. (ADC)
jamesadevine 0:e1a608bb55e8 640 */
jamesadevine 0:e1a608bb55e8 641
jamesadevine 0:e1a608bb55e8 642 typedef struct { /*!< ADC Structure */
jamesadevine 0:e1a608bb55e8 643 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
jamesadevine 0:e1a608bb55e8 644 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
jamesadevine 0:e1a608bb55e8 645 __I uint32_t RESERVED0[62];
jamesadevine 0:e1a608bb55e8 646 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
jamesadevine 0:e1a608bb55e8 647 __I uint32_t RESERVED1[128];
jamesadevine 0:e1a608bb55e8 648 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
jamesadevine 0:e1a608bb55e8 649 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
jamesadevine 0:e1a608bb55e8 650 __I uint32_t RESERVED2[61];
jamesadevine 0:e1a608bb55e8 651 __I uint32_t BUSY; /*!< ADC busy register. */
jamesadevine 0:e1a608bb55e8 652 __I uint32_t RESERVED3[63];
jamesadevine 0:e1a608bb55e8 653 __IO uint32_t ENABLE; /*!< ADC enable. */
jamesadevine 0:e1a608bb55e8 654 __IO uint32_t CONFIG; /*!< ADC configuration register. */
jamesadevine 0:e1a608bb55e8 655 __I uint32_t RESULT; /*!< Result of ADC conversion. */
jamesadevine 0:e1a608bb55e8 656 __I uint32_t RESERVED4[700];
jamesadevine 0:e1a608bb55e8 657 __IO uint32_t POWER; /*!< Peripheral power control. */
jamesadevine 0:e1a608bb55e8 658 } NRF_ADC_Type;
jamesadevine 0:e1a608bb55e8 659
jamesadevine 0:e1a608bb55e8 660
jamesadevine 0:e1a608bb55e8 661 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 662 /* ================ TIMER ================ */
jamesadevine 0:e1a608bb55e8 663 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 664
jamesadevine 0:e1a608bb55e8 665
jamesadevine 0:e1a608bb55e8 666 /**
jamesadevine 0:e1a608bb55e8 667 * @brief Timer 0. (TIMER)
jamesadevine 0:e1a608bb55e8 668 */
jamesadevine 0:e1a608bb55e8 669
jamesadevine 0:e1a608bb55e8 670 typedef struct { /*!< TIMER Structure */
jamesadevine 0:e1a608bb55e8 671 __O uint32_t TASKS_START; /*!< Start Timer. */
jamesadevine 0:e1a608bb55e8 672 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
jamesadevine 0:e1a608bb55e8 673 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
jamesadevine 0:e1a608bb55e8 674 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
jamesadevine 0:e1a608bb55e8 675 __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
jamesadevine 0:e1a608bb55e8 676 __I uint32_t RESERVED0[11];
jamesadevine 0:e1a608bb55e8 677 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
jamesadevine 0:e1a608bb55e8 678 __I uint32_t RESERVED1[60];
jamesadevine 0:e1a608bb55e8 679 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
jamesadevine 0:e1a608bb55e8 680 __I uint32_t RESERVED2[44];
jamesadevine 0:e1a608bb55e8 681 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
jamesadevine 0:e1a608bb55e8 682 __I uint32_t RESERVED3[64];
jamesadevine 0:e1a608bb55e8 683 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
jamesadevine 0:e1a608bb55e8 684 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
jamesadevine 0:e1a608bb55e8 685 __I uint32_t RESERVED4[126];
jamesadevine 0:e1a608bb55e8 686 __IO uint32_t MODE; /*!< Timer Mode selection. */
jamesadevine 0:e1a608bb55e8 687 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
jamesadevine 0:e1a608bb55e8 688 __I uint32_t RESERVED5;
jamesadevine 0:e1a608bb55e8 689 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
jamesadevine 0:e1a608bb55e8 690 clock frequency is divided by 2^SCALE. */
jamesadevine 0:e1a608bb55e8 691 __I uint32_t RESERVED6[11];
jamesadevine 0:e1a608bb55e8 692 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
jamesadevine 0:e1a608bb55e8 693 __I uint32_t RESERVED7[683];
jamesadevine 0:e1a608bb55e8 694 __IO uint32_t POWER; /*!< Peripheral power control. */
jamesadevine 0:e1a608bb55e8 695 } NRF_TIMER_Type;
jamesadevine 0:e1a608bb55e8 696
jamesadevine 0:e1a608bb55e8 697
jamesadevine 0:e1a608bb55e8 698 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 699 /* ================ RTC ================ */
jamesadevine 0:e1a608bb55e8 700 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 701
jamesadevine 0:e1a608bb55e8 702
jamesadevine 0:e1a608bb55e8 703 /**
jamesadevine 0:e1a608bb55e8 704 * @brief Real time counter 0. (RTC)
jamesadevine 0:e1a608bb55e8 705 */
jamesadevine 0:e1a608bb55e8 706
jamesadevine 0:e1a608bb55e8 707 typedef struct { /*!< RTC Structure */
jamesadevine 0:e1a608bb55e8 708 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
jamesadevine 0:e1a608bb55e8 709 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
jamesadevine 0:e1a608bb55e8 710 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
jamesadevine 0:e1a608bb55e8 711 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
jamesadevine 0:e1a608bb55e8 712 __I uint32_t RESERVED0[60];
jamesadevine 0:e1a608bb55e8 713 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
jamesadevine 0:e1a608bb55e8 714 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
jamesadevine 0:e1a608bb55e8 715 __I uint32_t RESERVED1[14];
jamesadevine 0:e1a608bb55e8 716 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
jamesadevine 0:e1a608bb55e8 717 __I uint32_t RESERVED2[109];
jamesadevine 0:e1a608bb55e8 718 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
jamesadevine 0:e1a608bb55e8 719 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
jamesadevine 0:e1a608bb55e8 720 __I uint32_t RESERVED3[13];
jamesadevine 0:e1a608bb55e8 721 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
jamesadevine 0:e1a608bb55e8 722 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
jamesadevine 0:e1a608bb55e8 723 the value of EVTEN. */
jamesadevine 0:e1a608bb55e8 724 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
jamesadevine 0:e1a608bb55e8 725 gives the value of EVTEN. */
jamesadevine 0:e1a608bb55e8 726 __I uint32_t RESERVED4[110];
jamesadevine 0:e1a608bb55e8 727 __I uint32_t COUNTER; /*!< Current COUNTER value. */
jamesadevine 0:e1a608bb55e8 728 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
jamesadevine 0:e1a608bb55e8 729 Must be written when RTC is STOPed. */
jamesadevine 0:e1a608bb55e8 730 __I uint32_t RESERVED5[13];
jamesadevine 0:e1a608bb55e8 731 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
jamesadevine 0:e1a608bb55e8 732 __I uint32_t RESERVED6[683];
jamesadevine 0:e1a608bb55e8 733 __IO uint32_t POWER; /*!< Peripheral power control. */
jamesadevine 0:e1a608bb55e8 734 } NRF_RTC_Type;
jamesadevine 0:e1a608bb55e8 735
jamesadevine 0:e1a608bb55e8 736
jamesadevine 0:e1a608bb55e8 737 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 738 /* ================ TEMP ================ */
jamesadevine 0:e1a608bb55e8 739 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 740
jamesadevine 0:e1a608bb55e8 741
jamesadevine 0:e1a608bb55e8 742 /**
jamesadevine 0:e1a608bb55e8 743 * @brief Temperature Sensor. (TEMP)
jamesadevine 0:e1a608bb55e8 744 */
jamesadevine 0:e1a608bb55e8 745
jamesadevine 0:e1a608bb55e8 746 typedef struct { /*!< TEMP Structure */
jamesadevine 0:e1a608bb55e8 747 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
jamesadevine 0:e1a608bb55e8 748 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
jamesadevine 0:e1a608bb55e8 749 __I uint32_t RESERVED0[62];
jamesadevine 0:e1a608bb55e8 750 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
jamesadevine 0:e1a608bb55e8 751 __I uint32_t RESERVED1[128];
jamesadevine 0:e1a608bb55e8 752 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
jamesadevine 0:e1a608bb55e8 753 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
jamesadevine 0:e1a608bb55e8 754 __I uint32_t RESERVED2[127];
jamesadevine 0:e1a608bb55e8 755 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
jamesadevine 0:e1a608bb55e8 756 __I uint32_t RESERVED3[700];
jamesadevine 0:e1a608bb55e8 757 __IO uint32_t POWER; /*!< Peripheral power control. */
jamesadevine 0:e1a608bb55e8 758 } NRF_TEMP_Type;
jamesadevine 0:e1a608bb55e8 759
jamesadevine 0:e1a608bb55e8 760
jamesadevine 0:e1a608bb55e8 761 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 762 /* ================ RNG ================ */
jamesadevine 0:e1a608bb55e8 763 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 764
jamesadevine 0:e1a608bb55e8 765
jamesadevine 0:e1a608bb55e8 766 /**
jamesadevine 0:e1a608bb55e8 767 * @brief Random Number Generator. (RNG)
jamesadevine 0:e1a608bb55e8 768 */
jamesadevine 0:e1a608bb55e8 769
jamesadevine 0:e1a608bb55e8 770 typedef struct { /*!< RNG Structure */
jamesadevine 0:e1a608bb55e8 771 __O uint32_t TASKS_START; /*!< Start the random number generator. */
jamesadevine 0:e1a608bb55e8 772 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
jamesadevine 0:e1a608bb55e8 773 __I uint32_t RESERVED0[62];
jamesadevine 0:e1a608bb55e8 774 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
jamesadevine 0:e1a608bb55e8 775 __I uint32_t RESERVED1[63];
jamesadevine 0:e1a608bb55e8 776 __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
jamesadevine 0:e1a608bb55e8 777 __I uint32_t RESERVED2[64];
jamesadevine 0:e1a608bb55e8 778 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
jamesadevine 0:e1a608bb55e8 779 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
jamesadevine 0:e1a608bb55e8 780 __I uint32_t RESERVED3[126];
jamesadevine 0:e1a608bb55e8 781 __IO uint32_t CONFIG; /*!< Configuration register. */
jamesadevine 0:e1a608bb55e8 782 __I uint32_t VALUE; /*!< RNG random number. */
jamesadevine 0:e1a608bb55e8 783 __I uint32_t RESERVED4[700];
jamesadevine 0:e1a608bb55e8 784 __IO uint32_t POWER; /*!< Peripheral power control. */
jamesadevine 0:e1a608bb55e8 785 } NRF_RNG_Type;
jamesadevine 0:e1a608bb55e8 786
jamesadevine 0:e1a608bb55e8 787
jamesadevine 0:e1a608bb55e8 788 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 789 /* ================ ECB ================ */
jamesadevine 0:e1a608bb55e8 790 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 791
jamesadevine 0:e1a608bb55e8 792
jamesadevine 0:e1a608bb55e8 793 /**
jamesadevine 0:e1a608bb55e8 794 * @brief AES ECB Mode Encryption. (ECB)
jamesadevine 0:e1a608bb55e8 795 */
jamesadevine 0:e1a608bb55e8 796
jamesadevine 0:e1a608bb55e8 797 typedef struct { /*!< ECB Structure */
jamesadevine 0:e1a608bb55e8 798 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
jamesadevine 0:e1a608bb55e8 799 will not initiate a new encryption and the ERRORECB event will
jamesadevine 0:e1a608bb55e8 800 be triggered. */
jamesadevine 0:e1a608bb55e8 801 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
jamesadevine 0:e1a608bb55e8 802 this will will trigger the ERRORECB event. */
jamesadevine 0:e1a608bb55e8 803 __I uint32_t RESERVED0[62];
jamesadevine 0:e1a608bb55e8 804 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
jamesadevine 0:e1a608bb55e8 805 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
jamesadevine 0:e1a608bb55e8 806 error. */
jamesadevine 0:e1a608bb55e8 807 __I uint32_t RESERVED1[127];
jamesadevine 0:e1a608bb55e8 808 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
jamesadevine 0:e1a608bb55e8 809 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
jamesadevine 0:e1a608bb55e8 810 __I uint32_t RESERVED2[126];
jamesadevine 0:e1a608bb55e8 811 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
jamesadevine 0:e1a608bb55e8 812 __I uint32_t RESERVED3[701];
jamesadevine 0:e1a608bb55e8 813 __IO uint32_t POWER; /*!< Peripheral power control. */
jamesadevine 0:e1a608bb55e8 814 } NRF_ECB_Type;
jamesadevine 0:e1a608bb55e8 815
jamesadevine 0:e1a608bb55e8 816
jamesadevine 0:e1a608bb55e8 817 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 818 /* ================ AAR ================ */
jamesadevine 0:e1a608bb55e8 819 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 820
jamesadevine 0:e1a608bb55e8 821
jamesadevine 0:e1a608bb55e8 822 /**
jamesadevine 0:e1a608bb55e8 823 * @brief Accelerated Address Resolver. (AAR)
jamesadevine 0:e1a608bb55e8 824 */
jamesadevine 0:e1a608bb55e8 825
jamesadevine 0:e1a608bb55e8 826 typedef struct { /*!< AAR Structure */
jamesadevine 0:e1a608bb55e8 827 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
jamesadevine 0:e1a608bb55e8 828 data structure. */
jamesadevine 0:e1a608bb55e8 829 __I uint32_t RESERVED0;
jamesadevine 0:e1a608bb55e8 830 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
jamesadevine 0:e1a608bb55e8 831 __I uint32_t RESERVED1[61];
jamesadevine 0:e1a608bb55e8 832 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
jamesadevine 0:e1a608bb55e8 833 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
jamesadevine 0:e1a608bb55e8 834 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
jamesadevine 0:e1a608bb55e8 835 __I uint32_t RESERVED2[126];
jamesadevine 0:e1a608bb55e8 836 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
jamesadevine 0:e1a608bb55e8 837 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
jamesadevine 0:e1a608bb55e8 838 __I uint32_t RESERVED3[61];
jamesadevine 0:e1a608bb55e8 839 __I uint32_t STATUS; /*!< Resolution status. */
jamesadevine 0:e1a608bb55e8 840 __I uint32_t RESERVED4[63];
jamesadevine 0:e1a608bb55e8 841 __IO uint32_t ENABLE; /*!< Enable AAR. */
jamesadevine 0:e1a608bb55e8 842 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
jamesadevine 0:e1a608bb55e8 843 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
jamesadevine 0:e1a608bb55e8 844 __I uint32_t RESERVED5;
jamesadevine 0:e1a608bb55e8 845 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
jamesadevine 0:e1a608bb55e8 846 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
jamesadevine 0:e1a608bb55e8 847 during resolution. A minimum of 3 bytes must be reserved. */
jamesadevine 0:e1a608bb55e8 848 __I uint32_t RESERVED6[697];
jamesadevine 0:e1a608bb55e8 849 __IO uint32_t POWER; /*!< Peripheral power control. */
jamesadevine 0:e1a608bb55e8 850 } NRF_AAR_Type;
jamesadevine 0:e1a608bb55e8 851
jamesadevine 0:e1a608bb55e8 852
jamesadevine 0:e1a608bb55e8 853 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 854 /* ================ CCM ================ */
jamesadevine 0:e1a608bb55e8 855 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 856
jamesadevine 0:e1a608bb55e8 857
jamesadevine 0:e1a608bb55e8 858 /**
jamesadevine 0:e1a608bb55e8 859 * @brief AES CCM Mode Encryption. (CCM)
jamesadevine 0:e1a608bb55e8 860 */
jamesadevine 0:e1a608bb55e8 861
jamesadevine 0:e1a608bb55e8 862 typedef struct { /*!< CCM Structure */
jamesadevine 0:e1a608bb55e8 863 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
jamesadevine 0:e1a608bb55e8 864 itself when completed. */
jamesadevine 0:e1a608bb55e8 865 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
jamesadevine 0:e1a608bb55e8 866 completed. */
jamesadevine 0:e1a608bb55e8 867 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
jamesadevine 0:e1a608bb55e8 868 __I uint32_t RESERVED0[61];
jamesadevine 0:e1a608bb55e8 869 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
jamesadevine 0:e1a608bb55e8 870 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
jamesadevine 0:e1a608bb55e8 871 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
jamesadevine 0:e1a608bb55e8 872 __I uint32_t RESERVED1[61];
jamesadevine 0:e1a608bb55e8 873 __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
jamesadevine 0:e1a608bb55e8 874 __I uint32_t RESERVED2[64];
jamesadevine 0:e1a608bb55e8 875 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
jamesadevine 0:e1a608bb55e8 876 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
jamesadevine 0:e1a608bb55e8 877 __I uint32_t RESERVED3[61];
jamesadevine 0:e1a608bb55e8 878 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
jamesadevine 0:e1a608bb55e8 879 __I uint32_t RESERVED4[63];
jamesadevine 0:e1a608bb55e8 880 __IO uint32_t ENABLE; /*!< CCM enable. */
jamesadevine 0:e1a608bb55e8 881 __IO uint32_t MODE; /*!< Operation mode. */
jamesadevine 0:e1a608bb55e8 882 __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
jamesadevine 0:e1a608bb55e8 883 __IO uint32_t INPTR; /*!< Pointer to the input packet. */
jamesadevine 0:e1a608bb55e8 884 __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
jamesadevine 0:e1a608bb55e8 885 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
jamesadevine 0:e1a608bb55e8 886 during resolution. A minimum of 43 bytes must be reserved. */
jamesadevine 0:e1a608bb55e8 887 __I uint32_t RESERVED5[697];
jamesadevine 0:e1a608bb55e8 888 __IO uint32_t POWER; /*!< Peripheral power control. */
jamesadevine 0:e1a608bb55e8 889 } NRF_CCM_Type;
jamesadevine 0:e1a608bb55e8 890
jamesadevine 0:e1a608bb55e8 891
jamesadevine 0:e1a608bb55e8 892 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 893 /* ================ WDT ================ */
jamesadevine 0:e1a608bb55e8 894 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 895
jamesadevine 0:e1a608bb55e8 896
jamesadevine 0:e1a608bb55e8 897 /**
jamesadevine 0:e1a608bb55e8 898 * @brief Watchdog Timer. (WDT)
jamesadevine 0:e1a608bb55e8 899 */
jamesadevine 0:e1a608bb55e8 900
jamesadevine 0:e1a608bb55e8 901 typedef struct { /*!< WDT Structure */
jamesadevine 0:e1a608bb55e8 902 __O uint32_t TASKS_START; /*!< Start the watchdog. */
jamesadevine 0:e1a608bb55e8 903 __I uint32_t RESERVED0[63];
jamesadevine 0:e1a608bb55e8 904 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
jamesadevine 0:e1a608bb55e8 905 __I uint32_t RESERVED1[128];
jamesadevine 0:e1a608bb55e8 906 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
jamesadevine 0:e1a608bb55e8 907 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
jamesadevine 0:e1a608bb55e8 908 __I uint32_t RESERVED2[61];
jamesadevine 0:e1a608bb55e8 909 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
jamesadevine 0:e1a608bb55e8 910 __I uint32_t REQSTATUS; /*!< Request status. */
jamesadevine 0:e1a608bb55e8 911 __I uint32_t RESERVED3[63];
jamesadevine 0:e1a608bb55e8 912 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
jamesadevine 0:e1a608bb55e8 913 __IO uint32_t RREN; /*!< Reload request enable. */
jamesadevine 0:e1a608bb55e8 914 __IO uint32_t CONFIG; /*!< Configuration register. */
jamesadevine 0:e1a608bb55e8 915 __I uint32_t RESERVED4[60];
jamesadevine 0:e1a608bb55e8 916 __O uint32_t RR[8]; /*!< Reload requests registers. */
jamesadevine 0:e1a608bb55e8 917 __I uint32_t RESERVED5[631];
jamesadevine 0:e1a608bb55e8 918 __IO uint32_t POWER; /*!< Peripheral power control. */
jamesadevine 0:e1a608bb55e8 919 } NRF_WDT_Type;
jamesadevine 0:e1a608bb55e8 920
jamesadevine 0:e1a608bb55e8 921
jamesadevine 0:e1a608bb55e8 922 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 923 /* ================ QDEC ================ */
jamesadevine 0:e1a608bb55e8 924 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 925
jamesadevine 0:e1a608bb55e8 926
jamesadevine 0:e1a608bb55e8 927 /**
jamesadevine 0:e1a608bb55e8 928 * @brief Rotary decoder. (QDEC)
jamesadevine 0:e1a608bb55e8 929 */
jamesadevine 0:e1a608bb55e8 930
jamesadevine 0:e1a608bb55e8 931 typedef struct { /*!< QDEC Structure */
jamesadevine 0:e1a608bb55e8 932 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
jamesadevine 0:e1a608bb55e8 933 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
jamesadevine 0:e1a608bb55e8 934 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
jamesadevine 0:e1a608bb55e8 935 and clears the ACC registers. */
jamesadevine 0:e1a608bb55e8 936 __I uint32_t RESERVED0[61];
jamesadevine 0:e1a608bb55e8 937 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
jamesadevine 0:e1a608bb55e8 938 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
jamesadevine 0:e1a608bb55e8 939 ACC register different than zero. */
jamesadevine 0:e1a608bb55e8 940 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
jamesadevine 0:e1a608bb55e8 941 __I uint32_t RESERVED1[61];
jamesadevine 0:e1a608bb55e8 942 __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
jamesadevine 0:e1a608bb55e8 943 __I uint32_t RESERVED2[64];
jamesadevine 0:e1a608bb55e8 944 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
jamesadevine 0:e1a608bb55e8 945 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
jamesadevine 0:e1a608bb55e8 946 __I uint32_t RESERVED3[125];
jamesadevine 0:e1a608bb55e8 947 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
jamesadevine 0:e1a608bb55e8 948 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
jamesadevine 0:e1a608bb55e8 949 __IO uint32_t SAMPLEPER; /*!< Sample period. */
jamesadevine 0:e1a608bb55e8 950 __I int32_t SAMPLE; /*!< Motion sample value. */
jamesadevine 0:e1a608bb55e8 951 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
jamesadevine 0:e1a608bb55e8 952 __I int32_t ACC; /*!< Accumulated valid transitions register. */
jamesadevine 0:e1a608bb55e8 953 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
jamesadevine 0:e1a608bb55e8 954 task. */
jamesadevine 0:e1a608bb55e8 955 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
jamesadevine 0:e1a608bb55e8 956 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
jamesadevine 0:e1a608bb55e8 957 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
jamesadevine 0:e1a608bb55e8 958 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
jamesadevine 0:e1a608bb55e8 959 __I uint32_t RESERVED4[5];
jamesadevine 0:e1a608bb55e8 960 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
jamesadevine 0:e1a608bb55e8 961 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
jamesadevine 0:e1a608bb55e8 962 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
jamesadevine 0:e1a608bb55e8 963 task. */
jamesadevine 0:e1a608bb55e8 964 __I uint32_t RESERVED5[684];
jamesadevine 0:e1a608bb55e8 965 __IO uint32_t POWER; /*!< Peripheral power control. */
jamesadevine 0:e1a608bb55e8 966 } NRF_QDEC_Type;
jamesadevine 0:e1a608bb55e8 967
jamesadevine 0:e1a608bb55e8 968
jamesadevine 0:e1a608bb55e8 969 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 970 /* ================ LPCOMP ================ */
jamesadevine 0:e1a608bb55e8 971 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 972
jamesadevine 0:e1a608bb55e8 973
jamesadevine 0:e1a608bb55e8 974 /**
jamesadevine 0:e1a608bb55e8 975 * @brief Low power comparator. (LPCOMP)
jamesadevine 0:e1a608bb55e8 976 */
jamesadevine 0:e1a608bb55e8 977
jamesadevine 0:e1a608bb55e8 978 typedef struct { /*!< LPCOMP Structure */
jamesadevine 0:e1a608bb55e8 979 __O uint32_t TASKS_START; /*!< Start the comparator. */
jamesadevine 0:e1a608bb55e8 980 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
jamesadevine 0:e1a608bb55e8 981 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
jamesadevine 0:e1a608bb55e8 982 __I uint32_t RESERVED0[61];
jamesadevine 0:e1a608bb55e8 983 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
jamesadevine 0:e1a608bb55e8 984 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
jamesadevine 0:e1a608bb55e8 985 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
jamesadevine 0:e1a608bb55e8 986 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
jamesadevine 0:e1a608bb55e8 987 __I uint32_t RESERVED1[60];
jamesadevine 0:e1a608bb55e8 988 __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
jamesadevine 0:e1a608bb55e8 989 __I uint32_t RESERVED2[64];
jamesadevine 0:e1a608bb55e8 990 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
jamesadevine 0:e1a608bb55e8 991 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
jamesadevine 0:e1a608bb55e8 992 __I uint32_t RESERVED3[61];
jamesadevine 0:e1a608bb55e8 993 __I uint32_t RESULT; /*!< Result of last compare. */
jamesadevine 0:e1a608bb55e8 994 __I uint32_t RESERVED4[63];
jamesadevine 0:e1a608bb55e8 995 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
jamesadevine 0:e1a608bb55e8 996 __IO uint32_t PSEL; /*!< Input pin select. */
jamesadevine 0:e1a608bb55e8 997 __IO uint32_t REFSEL; /*!< Reference select. */
jamesadevine 0:e1a608bb55e8 998 __IO uint32_t EXTREFSEL; /*!< External reference select. */
jamesadevine 0:e1a608bb55e8 999 __I uint32_t RESERVED5[4];
jamesadevine 0:e1a608bb55e8 1000 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
jamesadevine 0:e1a608bb55e8 1001 __I uint32_t RESERVED6[694];
jamesadevine 0:e1a608bb55e8 1002 __IO uint32_t POWER; /*!< Peripheral power control. */
jamesadevine 0:e1a608bb55e8 1003 } NRF_LPCOMP_Type;
jamesadevine 0:e1a608bb55e8 1004
jamesadevine 0:e1a608bb55e8 1005
jamesadevine 0:e1a608bb55e8 1006 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 1007 /* ================ SWI ================ */
jamesadevine 0:e1a608bb55e8 1008 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 1009
jamesadevine 0:e1a608bb55e8 1010
jamesadevine 0:e1a608bb55e8 1011 /**
jamesadevine 0:e1a608bb55e8 1012 * @brief SW Interrupts. (SWI)
jamesadevine 0:e1a608bb55e8 1013 */
jamesadevine 0:e1a608bb55e8 1014
jamesadevine 0:e1a608bb55e8 1015 typedef struct { /*!< SWI Structure */
jamesadevine 0:e1a608bb55e8 1016 __I uint32_t UNUSED; /*!< Unused. */
jamesadevine 0:e1a608bb55e8 1017 } NRF_SWI_Type;
jamesadevine 0:e1a608bb55e8 1018
jamesadevine 0:e1a608bb55e8 1019
jamesadevine 0:e1a608bb55e8 1020 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 1021 /* ================ NVMC ================ */
jamesadevine 0:e1a608bb55e8 1022 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 1023
jamesadevine 0:e1a608bb55e8 1024
jamesadevine 0:e1a608bb55e8 1025 /**
jamesadevine 0:e1a608bb55e8 1026 * @brief Non Volatile Memory Controller. (NVMC)
jamesadevine 0:e1a608bb55e8 1027 */
jamesadevine 0:e1a608bb55e8 1028
jamesadevine 0:e1a608bb55e8 1029 typedef struct { /*!< NVMC Structure */
jamesadevine 0:e1a608bb55e8 1030 __I uint32_t RESERVED0[256];
jamesadevine 0:e1a608bb55e8 1031 __I uint32_t READY; /*!< Ready flag. */
jamesadevine 0:e1a608bb55e8 1032 __I uint32_t RESERVED1[64];
jamesadevine 0:e1a608bb55e8 1033 __IO uint32_t CONFIG; /*!< Configuration register. */
jamesadevine 1:a7c51b5e0534 1034
jamesadevine 1:a7c51b5e0534 1035 union {
jamesadevine 1:a7c51b5e0534 1036 __IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */
jamesadevine 1:a7c51b5e0534 1037 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
jamesadevine 1:a7c51b5e0534 1038 };
jamesadevine 0:e1a608bb55e8 1039 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
jamesadevine 1:a7c51b5e0534 1040 __IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */
jamesadevine 0:e1a608bb55e8 1041 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
jamesadevine 0:e1a608bb55e8 1042 } NRF_NVMC_Type;
jamesadevine 0:e1a608bb55e8 1043
jamesadevine 0:e1a608bb55e8 1044
jamesadevine 0:e1a608bb55e8 1045 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 1046 /* ================ PPI ================ */
jamesadevine 0:e1a608bb55e8 1047 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 1048
jamesadevine 0:e1a608bb55e8 1049
jamesadevine 0:e1a608bb55e8 1050 /**
jamesadevine 0:e1a608bb55e8 1051 * @brief PPI controller. (PPI)
jamesadevine 0:e1a608bb55e8 1052 */
jamesadevine 0:e1a608bb55e8 1053
jamesadevine 0:e1a608bb55e8 1054 typedef struct { /*!< PPI Structure */
jamesadevine 0:e1a608bb55e8 1055 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
jamesadevine 0:e1a608bb55e8 1056 __I uint32_t RESERVED0[312];
jamesadevine 0:e1a608bb55e8 1057 __IO uint32_t CHEN; /*!< Channel enable. */
jamesadevine 0:e1a608bb55e8 1058 __IO uint32_t CHENSET; /*!< Channel enable set. */
jamesadevine 0:e1a608bb55e8 1059 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
jamesadevine 0:e1a608bb55e8 1060 __I uint32_t RESERVED1;
jamesadevine 0:e1a608bb55e8 1061 PPI_CH_Type CH[16]; /*!< PPI Channel. */
jamesadevine 0:e1a608bb55e8 1062 __I uint32_t RESERVED2[156];
jamesadevine 0:e1a608bb55e8 1063 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
jamesadevine 0:e1a608bb55e8 1064 } NRF_PPI_Type;
jamesadevine 0:e1a608bb55e8 1065
jamesadevine 0:e1a608bb55e8 1066
jamesadevine 0:e1a608bb55e8 1067 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 1068 /* ================ FICR ================ */
jamesadevine 0:e1a608bb55e8 1069 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 1070
jamesadevine 0:e1a608bb55e8 1071
jamesadevine 0:e1a608bb55e8 1072 /**
jamesadevine 0:e1a608bb55e8 1073 * @brief Factory Information Configuration. (FICR)
jamesadevine 0:e1a608bb55e8 1074 */
jamesadevine 0:e1a608bb55e8 1075
jamesadevine 0:e1a608bb55e8 1076 typedef struct { /*!< FICR Structure */
jamesadevine 0:e1a608bb55e8 1077 __I uint32_t RESERVED0[4];
jamesadevine 0:e1a608bb55e8 1078 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
jamesadevine 0:e1a608bb55e8 1079 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
jamesadevine 0:e1a608bb55e8 1080 __I uint32_t RESERVED1[4];
jamesadevine 0:e1a608bb55e8 1081 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
jamesadevine 0:e1a608bb55e8 1082 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
jamesadevine 0:e1a608bb55e8 1083 __I uint32_t RESERVED2;
jamesadevine 0:e1a608bb55e8 1084 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
jamesadevine 1:a7c51b5e0534 1085
jamesadevine 0:e1a608bb55e8 1086 union {
jamesadevine 0:e1a608bb55e8 1087 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
jamesadevine 0:e1a608bb55e8 1088 kept for backward compatinility purposes. Use SIZERAMBLOCKS
jamesadevine 0:e1a608bb55e8 1089 instead. */
jamesadevine 0:e1a608bb55e8 1090 __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
jamesadevine 0:e1a608bb55e8 1091 };
jamesadevine 0:e1a608bb55e8 1092 __I uint32_t RESERVED3[5];
jamesadevine 0:e1a608bb55e8 1093 __I uint32_t CONFIGID; /*!< Configuration identifier. */
jamesadevine 0:e1a608bb55e8 1094 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
jamesadevine 0:e1a608bb55e8 1095 __I uint32_t RESERVED4[6];
jamesadevine 0:e1a608bb55e8 1096 __I uint32_t ER[4]; /*!< Encryption root. */
jamesadevine 0:e1a608bb55e8 1097 __I uint32_t IR[4]; /*!< Identity root. */
jamesadevine 0:e1a608bb55e8 1098 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
jamesadevine 0:e1a608bb55e8 1099 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
jamesadevine 0:e1a608bb55e8 1100 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
jamesadevine 0:e1a608bb55e8 1101 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
jamesadevine 0:e1a608bb55e8 1102 mode. */
jamesadevine 0:e1a608bb55e8 1103 __I uint32_t RESERVED5[10];
jamesadevine 0:e1a608bb55e8 1104 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
jamesadevine 0:e1a608bb55e8 1105 mode. */
jamesadevine 0:e1a608bb55e8 1106 } NRF_FICR_Type;
jamesadevine 0:e1a608bb55e8 1107
jamesadevine 0:e1a608bb55e8 1108
jamesadevine 0:e1a608bb55e8 1109 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 1110 /* ================ UICR ================ */
jamesadevine 0:e1a608bb55e8 1111 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 1112
jamesadevine 0:e1a608bb55e8 1113
jamesadevine 0:e1a608bb55e8 1114 /**
jamesadevine 0:e1a608bb55e8 1115 * @brief User Information Configuration. (UICR)
jamesadevine 0:e1a608bb55e8 1116 */
jamesadevine 0:e1a608bb55e8 1117
jamesadevine 0:e1a608bb55e8 1118 typedef struct { /*!< UICR Structure */
jamesadevine 0:e1a608bb55e8 1119 __IO uint32_t CLENR0; /*!< Length of code region 0. */
jamesadevine 0:e1a608bb55e8 1120 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
jamesadevine 0:e1a608bb55e8 1121 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
jamesadevine 0:e1a608bb55e8 1122 __I uint32_t RESERVED0;
jamesadevine 0:e1a608bb55e8 1123 __I uint32_t FWID; /*!< Firmware ID. */
jamesadevine 1:a7c51b5e0534 1124
jamesadevine 1:a7c51b5e0534 1125 union {
jamesadevine 1:a7c51b5e0534 1126 __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */
jamesadevine 1:a7c51b5e0534 1127 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
jamesadevine 1:a7c51b5e0534 1128 };
jamesadevine 1:a7c51b5e0534 1129 __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */
jamesadevine 1:a7c51b5e0534 1130 __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */
jamesadevine 0:e1a608bb55e8 1131 } NRF_UICR_Type;
jamesadevine 0:e1a608bb55e8 1132
jamesadevine 0:e1a608bb55e8 1133
jamesadevine 0:e1a608bb55e8 1134 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 1135 /* ================ GPIO ================ */
jamesadevine 0:e1a608bb55e8 1136 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 1137
jamesadevine 0:e1a608bb55e8 1138
jamesadevine 0:e1a608bb55e8 1139 /**
jamesadevine 0:e1a608bb55e8 1140 * @brief General purpose input and output. (GPIO)
jamesadevine 0:e1a608bb55e8 1141 */
jamesadevine 0:e1a608bb55e8 1142
jamesadevine 0:e1a608bb55e8 1143 typedef struct { /*!< GPIO Structure */
jamesadevine 0:e1a608bb55e8 1144 __I uint32_t RESERVED0[321];
jamesadevine 0:e1a608bb55e8 1145 __IO uint32_t OUT; /*!< Write GPIO port. */
jamesadevine 0:e1a608bb55e8 1146 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
jamesadevine 0:e1a608bb55e8 1147 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
jamesadevine 0:e1a608bb55e8 1148 __I uint32_t IN; /*!< Read GPIO port. */
jamesadevine 0:e1a608bb55e8 1149 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
jamesadevine 0:e1a608bb55e8 1150 __IO uint32_t DIRSET; /*!< DIR set register. */
jamesadevine 0:e1a608bb55e8 1151 __IO uint32_t DIRCLR; /*!< DIR clear register. */
jamesadevine 0:e1a608bb55e8 1152 __I uint32_t RESERVED1[120];
jamesadevine 0:e1a608bb55e8 1153 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
jamesadevine 0:e1a608bb55e8 1154 } NRF_GPIO_Type;
jamesadevine 0:e1a608bb55e8 1155
jamesadevine 0:e1a608bb55e8 1156
jamesadevine 0:e1a608bb55e8 1157 /* -------------------- End of section using anonymous unions ------------------- */
jamesadevine 0:e1a608bb55e8 1158 #if defined(__CC_ARM)
jamesadevine 0:e1a608bb55e8 1159 #pragma pop
jamesadevine 0:e1a608bb55e8 1160 #elif defined(__ICCARM__)
jamesadevine 0:e1a608bb55e8 1161 /* leave anonymous unions enabled */
jamesadevine 0:e1a608bb55e8 1162 #elif defined(__GNUC__)
jamesadevine 0:e1a608bb55e8 1163 /* anonymous unions are enabled by default */
jamesadevine 0:e1a608bb55e8 1164 #elif defined(__TMS470__)
jamesadevine 0:e1a608bb55e8 1165 /* anonymous unions are enabled by default */
jamesadevine 0:e1a608bb55e8 1166 #elif defined(__TASKING__)
jamesadevine 0:e1a608bb55e8 1167 #pragma warning restore
jamesadevine 0:e1a608bb55e8 1168 #else
jamesadevine 0:e1a608bb55e8 1169 #warning Not supported compiler type
jamesadevine 0:e1a608bb55e8 1170 #endif
jamesadevine 0:e1a608bb55e8 1171
jamesadevine 0:e1a608bb55e8 1172
jamesadevine 0:e1a608bb55e8 1173
jamesadevine 0:e1a608bb55e8 1174
jamesadevine 0:e1a608bb55e8 1175 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 1176 /* ================ Peripheral memory map ================ */
jamesadevine 0:e1a608bb55e8 1177 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 1178
jamesadevine 0:e1a608bb55e8 1179 #define NRF_POWER_BASE 0x40000000UL
jamesadevine 0:e1a608bb55e8 1180 #define NRF_CLOCK_BASE 0x40000000UL
jamesadevine 0:e1a608bb55e8 1181 #define NRF_MPU_BASE 0x40000000UL
jamesadevine 0:e1a608bb55e8 1182 #define NRF_AMLI_BASE 0x40000000UL
jamesadevine 0:e1a608bb55e8 1183 #define NRF_RADIO_BASE 0x40001000UL
jamesadevine 0:e1a608bb55e8 1184 #define NRF_UART0_BASE 0x40002000UL
jamesadevine 0:e1a608bb55e8 1185 #define NRF_SPI0_BASE 0x40003000UL
jamesadevine 0:e1a608bb55e8 1186 #define NRF_TWI0_BASE 0x40003000UL
jamesadevine 0:e1a608bb55e8 1187 #define NRF_SPI1_BASE 0x40004000UL
jamesadevine 0:e1a608bb55e8 1188 #define NRF_TWI1_BASE 0x40004000UL
jamesadevine 0:e1a608bb55e8 1189 #define NRF_SPIS1_BASE 0x40004000UL
jamesadevine 0:e1a608bb55e8 1190 #define NRF_SPIM1_BASE 0x40004000UL
jamesadevine 0:e1a608bb55e8 1191 #define NRF_GPIOTE_BASE 0x40006000UL
jamesadevine 0:e1a608bb55e8 1192 #define NRF_ADC_BASE 0x40007000UL
jamesadevine 0:e1a608bb55e8 1193 #define NRF_TIMER0_BASE 0x40008000UL
jamesadevine 0:e1a608bb55e8 1194 #define NRF_TIMER1_BASE 0x40009000UL
jamesadevine 0:e1a608bb55e8 1195 #define NRF_TIMER2_BASE 0x4000A000UL
jamesadevine 0:e1a608bb55e8 1196 #define NRF_RTC0_BASE 0x4000B000UL
jamesadevine 0:e1a608bb55e8 1197 #define NRF_TEMP_BASE 0x4000C000UL
jamesadevine 0:e1a608bb55e8 1198 #define NRF_RNG_BASE 0x4000D000UL
jamesadevine 0:e1a608bb55e8 1199 #define NRF_ECB_BASE 0x4000E000UL
jamesadevine 0:e1a608bb55e8 1200 #define NRF_AAR_BASE 0x4000F000UL
jamesadevine 0:e1a608bb55e8 1201 #define NRF_CCM_BASE 0x4000F000UL
jamesadevine 0:e1a608bb55e8 1202 #define NRF_WDT_BASE 0x40010000UL
jamesadevine 0:e1a608bb55e8 1203 #define NRF_RTC1_BASE 0x40011000UL
jamesadevine 0:e1a608bb55e8 1204 #define NRF_QDEC_BASE 0x40012000UL
jamesadevine 0:e1a608bb55e8 1205 #define NRF_LPCOMP_BASE 0x40013000UL
jamesadevine 0:e1a608bb55e8 1206 #define NRF_SWI_BASE 0x40014000UL
jamesadevine 0:e1a608bb55e8 1207 #define NRF_NVMC_BASE 0x4001E000UL
jamesadevine 0:e1a608bb55e8 1208 #define NRF_PPI_BASE 0x4001F000UL
jamesadevine 0:e1a608bb55e8 1209 #define NRF_FICR_BASE 0x10000000UL
jamesadevine 0:e1a608bb55e8 1210 #define NRF_UICR_BASE 0x10001000UL
jamesadevine 0:e1a608bb55e8 1211 #define NRF_GPIO_BASE 0x50000000UL
jamesadevine 0:e1a608bb55e8 1212
jamesadevine 0:e1a608bb55e8 1213
jamesadevine 0:e1a608bb55e8 1214 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 1215 /* ================ Peripheral declaration ================ */
jamesadevine 0:e1a608bb55e8 1216 /* ================================================================================ */
jamesadevine 0:e1a608bb55e8 1217
jamesadevine 0:e1a608bb55e8 1218 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
jamesadevine 0:e1a608bb55e8 1219 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
jamesadevine 0:e1a608bb55e8 1220 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
jamesadevine 0:e1a608bb55e8 1221 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
jamesadevine 0:e1a608bb55e8 1222 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
jamesadevine 0:e1a608bb55e8 1223 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
jamesadevine 0:e1a608bb55e8 1224 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
jamesadevine 0:e1a608bb55e8 1225 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
jamesadevine 0:e1a608bb55e8 1226 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
jamesadevine 0:e1a608bb55e8 1227 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
jamesadevine 0:e1a608bb55e8 1228 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
jamesadevine 0:e1a608bb55e8 1229 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
jamesadevine 0:e1a608bb55e8 1230 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
jamesadevine 0:e1a608bb55e8 1231 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
jamesadevine 0:e1a608bb55e8 1232 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
jamesadevine 0:e1a608bb55e8 1233 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
jamesadevine 0:e1a608bb55e8 1234 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
jamesadevine 0:e1a608bb55e8 1235 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
jamesadevine 0:e1a608bb55e8 1236 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
jamesadevine 0:e1a608bb55e8 1237 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
jamesadevine 0:e1a608bb55e8 1238 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
jamesadevine 0:e1a608bb55e8 1239 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
jamesadevine 0:e1a608bb55e8 1240 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
jamesadevine 0:e1a608bb55e8 1241 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
jamesadevine 0:e1a608bb55e8 1242 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
jamesadevine 0:e1a608bb55e8 1243 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
jamesadevine 0:e1a608bb55e8 1244 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
jamesadevine 0:e1a608bb55e8 1245 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
jamesadevine 0:e1a608bb55e8 1246 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
jamesadevine 0:e1a608bb55e8 1247 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
jamesadevine 0:e1a608bb55e8 1248 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
jamesadevine 0:e1a608bb55e8 1249 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
jamesadevine 0:e1a608bb55e8 1250 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
jamesadevine 0:e1a608bb55e8 1251
jamesadevine 0:e1a608bb55e8 1252
jamesadevine 0:e1a608bb55e8 1253 /** @} */ /* End of group Device_Peripheral_Registers */
jamesadevine 1:a7c51b5e0534 1254 /** @} */ /* End of group nrf51 */
jamesadevine 0:e1a608bb55e8 1255 /** @} */ /* End of group Nordic Semiconductor */
jamesadevine 0:e1a608bb55e8 1256
jamesadevine 0:e1a608bb55e8 1257 #ifdef __cplusplus
jamesadevine 0:e1a608bb55e8 1258 }
jamesadevine 0:e1a608bb55e8 1259 #endif
jamesadevine 0:e1a608bb55e8 1260
jamesadevine 0:e1a608bb55e8 1261
jamesadevine 1:a7c51b5e0534 1262 #endif /* nrf51_H */
jamesadevine 0:e1a608bb55e8 1263