Lancaster University / mbed-dev-bin

Binary version of Lancaster University's mbed branch, soon to be merged. The source lives here:https://developer.mbed.org/teams/Lancaster-University/code/mbed-src/

Dependents:   microbit-dal microbit-ble-open microbit-dal-eddystone microbit-dal ... more

Fork of mbed-lite-test by Lancaster University

TARGET_NRF51_MICROBIT/core_cmInstr.h@3:768173a57492, 2016-07-13 (annotated)

Committer:
jamesadevine
Date:
Wed Jul 13 15:12:06 2016 +0100
Revision:
3:768173a57492
Parent:
0:e1a608bb55e8 
further updates to mbed-dev-bin

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jamesadevine 0:e1a608bb55e8 1 /**************************************************************************//**
jamesadevine 0:e1a608bb55e8 2 * @file core_cmInstr.h
jamesadevine 0:e1a608bb55e8 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
jamesadevine 0:e1a608bb55e8 4 * @version V3.20
jamesadevine 0:e1a608bb55e8 5 * @date 05. March 2013
jamesadevine 0:e1a608bb55e8 6 *
jamesadevine 0:e1a608bb55e8 7 * @note
jamesadevine 0:e1a608bb55e8 8 *
jamesadevine 0:e1a608bb55e8 9 ******************************************************************************/
jamesadevine 0:e1a608bb55e8 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
jamesadevine 0:e1a608bb55e8 11
jamesadevine 0:e1a608bb55e8 12 All rights reserved.
jamesadevine 0:e1a608bb55e8 13 Redistribution and use in source and binary forms, with or without
jamesadevine 0:e1a608bb55e8 14 modification, are permitted provided that the following conditions are met:
jamesadevine 0:e1a608bb55e8 15 - Redistributions of source code must retain the above copyright
jamesadevine 0:e1a608bb55e8 16 notice, this list of conditions and the following disclaimer.
jamesadevine 0:e1a608bb55e8 17 - Redistributions in binary form must reproduce the above copyright
jamesadevine 0:e1a608bb55e8 18 notice, this list of conditions and the following disclaimer in the
jamesadevine 0:e1a608bb55e8 19 documentation and/or other materials provided with the distribution.
jamesadevine 0:e1a608bb55e8 20 - Neither the name of ARM nor the names of its contributors may be used
jamesadevine 0:e1a608bb55e8 21 to endorse or promote products derived from this software without
jamesadevine 0:e1a608bb55e8 22 specific prior written permission.
jamesadevine 0:e1a608bb55e8 23 *
jamesadevine 0:e1a608bb55e8 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jamesadevine 0:e1a608bb55e8 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jamesadevine 0:e1a608bb55e8 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
jamesadevine 0:e1a608bb55e8 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
jamesadevine 0:e1a608bb55e8 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
jamesadevine 0:e1a608bb55e8 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
jamesadevine 0:e1a608bb55e8 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
jamesadevine 0:e1a608bb55e8 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
jamesadevine 0:e1a608bb55e8 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
jamesadevine 0:e1a608bb55e8 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
jamesadevine 0:e1a608bb55e8 34 POSSIBILITY OF SUCH DAMAGE.
jamesadevine 0:e1a608bb55e8 35 ---------------------------------------------------------------------------*/
jamesadevine 0:e1a608bb55e8 36
jamesadevine 0:e1a608bb55e8 37
jamesadevine 0:e1a608bb55e8 38 #ifndef __CORE_CMINSTR_H
jamesadevine 0:e1a608bb55e8 39 #define __CORE_CMINSTR_H
jamesadevine 0:e1a608bb55e8 40
jamesadevine 0:e1a608bb55e8 41
jamesadevine 0:e1a608bb55e8 42 /* ########################## Core Instruction Access ######################### */
jamesadevine 0:e1a608bb55e8 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
jamesadevine 0:e1a608bb55e8 44 Access to dedicated instructions
jamesadevine 0:e1a608bb55e8 45 @{
jamesadevine 0:e1a608bb55e8 46 */
jamesadevine 0:e1a608bb55e8 47
jamesadevine 0:e1a608bb55e8 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
jamesadevine 0:e1a608bb55e8 49 /* ARM armcc specific functions */
jamesadevine 0:e1a608bb55e8 50
jamesadevine 0:e1a608bb55e8 51 #if (__ARMCC_VERSION < 400677)
jamesadevine 0:e1a608bb55e8 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
jamesadevine 0:e1a608bb55e8 53 #endif
jamesadevine 0:e1a608bb55e8 54
jamesadevine 0:e1a608bb55e8 55
jamesadevine 0:e1a608bb55e8 56 /** \brief No Operation
jamesadevine 0:e1a608bb55e8 57
jamesadevine 0:e1a608bb55e8 58 No Operation does nothing. This instruction can be used for code alignment purposes.
jamesadevine 0:e1a608bb55e8 59 */
jamesadevine 0:e1a608bb55e8 60 #define __NOP __nop
jamesadevine 0:e1a608bb55e8 61
jamesadevine 0:e1a608bb55e8 62
jamesadevine 0:e1a608bb55e8 63 /** \brief Wait For Interrupt
jamesadevine 0:e1a608bb55e8 64
jamesadevine 0:e1a608bb55e8 65 Wait For Interrupt is a hint instruction that suspends execution
jamesadevine 0:e1a608bb55e8 66 until one of a number of events occurs.
jamesadevine 0:e1a608bb55e8 67 */
jamesadevine 0:e1a608bb55e8 68 #define __WFI __wfi
jamesadevine 0:e1a608bb55e8 69
jamesadevine 0:e1a608bb55e8 70
jamesadevine 0:e1a608bb55e8 71 /** \brief Wait For Event
jamesadevine 0:e1a608bb55e8 72
jamesadevine 0:e1a608bb55e8 73 Wait For Event is a hint instruction that permits the processor to enter
jamesadevine 0:e1a608bb55e8 74 a low-power state until one of a number of events occurs.
jamesadevine 0:e1a608bb55e8 75 */
jamesadevine 0:e1a608bb55e8 76 #define __WFE __wfe
jamesadevine 0:e1a608bb55e8 77
jamesadevine 0:e1a608bb55e8 78
jamesadevine 0:e1a608bb55e8 79 /** \brief Send Event
jamesadevine 0:e1a608bb55e8 80
jamesadevine 0:e1a608bb55e8 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
jamesadevine 0:e1a608bb55e8 82 */
jamesadevine 0:e1a608bb55e8 83 #define __SEV __sev
jamesadevine 0:e1a608bb55e8 84
jamesadevine 0:e1a608bb55e8 85
jamesadevine 0:e1a608bb55e8 86 /** \brief Instruction Synchronization Barrier
jamesadevine 0:e1a608bb55e8 87
jamesadevine 0:e1a608bb55e8 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
jamesadevine 0:e1a608bb55e8 89 so that all instructions following the ISB are fetched from cache or
jamesadevine 0:e1a608bb55e8 90 memory, after the instruction has been completed.
jamesadevine 0:e1a608bb55e8 91 */
jamesadevine 0:e1a608bb55e8 92 #define __ISB() __isb(0xF)
jamesadevine 0:e1a608bb55e8 93
jamesadevine 0:e1a608bb55e8 94
jamesadevine 0:e1a608bb55e8 95 /** \brief Data Synchronization Barrier
jamesadevine 0:e1a608bb55e8 96
jamesadevine 0:e1a608bb55e8 97 This function acts as a special kind of Data Memory Barrier.
jamesadevine 0:e1a608bb55e8 98 It completes when all explicit memory accesses before this instruction complete.
jamesadevine 0:e1a608bb55e8 99 */
jamesadevine 0:e1a608bb55e8 100 #define __DSB() __dsb(0xF)
jamesadevine 0:e1a608bb55e8 101
jamesadevine 0:e1a608bb55e8 102
jamesadevine 0:e1a608bb55e8 103 /** \brief Data Memory Barrier
jamesadevine 0:e1a608bb55e8 104
jamesadevine 0:e1a608bb55e8 105 This function ensures the apparent order of the explicit memory operations before
jamesadevine 0:e1a608bb55e8 106 and after the instruction, without ensuring their completion.
jamesadevine 0:e1a608bb55e8 107 */
jamesadevine 0:e1a608bb55e8 108 #define __DMB() __dmb(0xF)
jamesadevine 0:e1a608bb55e8 109
jamesadevine 0:e1a608bb55e8 110
jamesadevine 0:e1a608bb55e8 111 /** \brief Reverse byte order (32 bit)
jamesadevine 0:e1a608bb55e8 112
jamesadevine 0:e1a608bb55e8 113 This function reverses the byte order in integer value.
jamesadevine 0:e1a608bb55e8 114
jamesadevine 0:e1a608bb55e8 115 \param [in] value Value to reverse
jamesadevine 0:e1a608bb55e8 116 \return Reversed value
jamesadevine 0:e1a608bb55e8 117 */
jamesadevine 0:e1a608bb55e8 118 #define __REV __rev
jamesadevine 0:e1a608bb55e8 119
jamesadevine 0:e1a608bb55e8 120
jamesadevine 0:e1a608bb55e8 121 /** \brief Reverse byte order (16 bit)
jamesadevine 0:e1a608bb55e8 122
jamesadevine 0:e1a608bb55e8 123 This function reverses the byte order in two unsigned short values.
jamesadevine 0:e1a608bb55e8 124
jamesadevine 0:e1a608bb55e8 125 \param [in] value Value to reverse
jamesadevine 0:e1a608bb55e8 126 \return Reversed value
jamesadevine 0:e1a608bb55e8 127 */
jamesadevine 0:e1a608bb55e8 128 #ifndef __NO_EMBEDDED_ASM
jamesadevine 0:e1a608bb55e8 129 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
jamesadevine 0:e1a608bb55e8 130 {
jamesadevine 0:e1a608bb55e8 131 rev16 r0, r0
jamesadevine 0:e1a608bb55e8 132 bx lr
jamesadevine 0:e1a608bb55e8 133 }
jamesadevine 0:e1a608bb55e8 134 #endif
jamesadevine 0:e1a608bb55e8 135
jamesadevine 0:e1a608bb55e8 136 /** \brief Reverse byte order in signed short value
jamesadevine 0:e1a608bb55e8 137
jamesadevine 0:e1a608bb55e8 138 This function reverses the byte order in a signed short value with sign extension to integer.
jamesadevine 0:e1a608bb55e8 139
jamesadevine 0:e1a608bb55e8 140 \param [in] value Value to reverse
jamesadevine 0:e1a608bb55e8 141 \return Reversed value
jamesadevine 0:e1a608bb55e8 142 */
jamesadevine 0:e1a608bb55e8 143 #ifndef __NO_EMBEDDED_ASM
jamesadevine 0:e1a608bb55e8 144 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
jamesadevine 0:e1a608bb55e8 145 {
jamesadevine 0:e1a608bb55e8 146 revsh r0, r0
jamesadevine 0:e1a608bb55e8 147 bx lr
jamesadevine 0:e1a608bb55e8 148 }
jamesadevine 0:e1a608bb55e8 149 #endif
jamesadevine 0:e1a608bb55e8 150
jamesadevine 0:e1a608bb55e8 151
jamesadevine 0:e1a608bb55e8 152 /** \brief Rotate Right in unsigned value (32 bit)
jamesadevine 0:e1a608bb55e8 153
jamesadevine 0:e1a608bb55e8 154 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
jamesadevine 0:e1a608bb55e8 155
jamesadevine 0:e1a608bb55e8 156 \param [in] value Value to rotate
jamesadevine 0:e1a608bb55e8 157 \param [in] value Number of Bits to rotate
jamesadevine 0:e1a608bb55e8 158 \return Rotated value
jamesadevine 0:e1a608bb55e8 159 */
jamesadevine 0:e1a608bb55e8 160 #define __ROR __ror
jamesadevine 0:e1a608bb55e8 161
jamesadevine 0:e1a608bb55e8 162
jamesadevine 0:e1a608bb55e8 163 /** \brief Breakpoint
jamesadevine 0:e1a608bb55e8 164
jamesadevine 0:e1a608bb55e8 165 This function causes the processor to enter Debug state.
jamesadevine 0:e1a608bb55e8 166 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
jamesadevine 0:e1a608bb55e8 167
jamesadevine 0:e1a608bb55e8 168 \param [in] value is ignored by the processor.
jamesadevine 0:e1a608bb55e8 169 If required, a debugger can use it to store additional information about the breakpoint.
jamesadevine 0:e1a608bb55e8 170 */
jamesadevine 0:e1a608bb55e8 171 #define __BKPT(value) __breakpoint(value)
jamesadevine 0:e1a608bb55e8 172
jamesadevine 0:e1a608bb55e8 173
jamesadevine 0:e1a608bb55e8 174 #if (__CORTEX_M >= 0x03)
jamesadevine 0:e1a608bb55e8 175
jamesadevine 0:e1a608bb55e8 176 /** \brief Reverse bit order of value
jamesadevine 0:e1a608bb55e8 177
jamesadevine 0:e1a608bb55e8 178 This function reverses the bit order of the given value.
jamesadevine 0:e1a608bb55e8 179
jamesadevine 0:e1a608bb55e8 180 \param [in] value Value to reverse
jamesadevine 0:e1a608bb55e8 181 \return Reversed value
jamesadevine 0:e1a608bb55e8 182 */
jamesadevine 0:e1a608bb55e8 183 #define __RBIT __rbit
jamesadevine 0:e1a608bb55e8 184
jamesadevine 0:e1a608bb55e8 185
jamesadevine 0:e1a608bb55e8 186 /** \brief LDR Exclusive (8 bit)
jamesadevine 0:e1a608bb55e8 187
jamesadevine 0:e1a608bb55e8 188 This function performs a exclusive LDR command for 8 bit value.
jamesadevine 0:e1a608bb55e8 189
jamesadevine 0:e1a608bb55e8 190 \param [in] ptr Pointer to data
jamesadevine 0:e1a608bb55e8 191 \return value of type uint8_t at (*ptr)
jamesadevine 0:e1a608bb55e8 192 */
jamesadevine 0:e1a608bb55e8 193 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
jamesadevine 0:e1a608bb55e8 194
jamesadevine 0:e1a608bb55e8 195
jamesadevine 0:e1a608bb55e8 196 /** \brief LDR Exclusive (16 bit)
jamesadevine 0:e1a608bb55e8 197
jamesadevine 0:e1a608bb55e8 198 This function performs a exclusive LDR command for 16 bit values.
jamesadevine 0:e1a608bb55e8 199
jamesadevine 0:e1a608bb55e8 200 \param [in] ptr Pointer to data
jamesadevine 0:e1a608bb55e8 201 \return value of type uint16_t at (*ptr)
jamesadevine 0:e1a608bb55e8 202 */
jamesadevine 0:e1a608bb55e8 203 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
jamesadevine 0:e1a608bb55e8 204
jamesadevine 0:e1a608bb55e8 205
jamesadevine 0:e1a608bb55e8 206 /** \brief LDR Exclusive (32 bit)
jamesadevine 0:e1a608bb55e8 207
jamesadevine 0:e1a608bb55e8 208 This function performs a exclusive LDR command for 32 bit values.
jamesadevine 0:e1a608bb55e8 209
jamesadevine 0:e1a608bb55e8 210 \param [in] ptr Pointer to data
jamesadevine 0:e1a608bb55e8 211 \return value of type uint32_t at (*ptr)
jamesadevine 0:e1a608bb55e8 212 */
jamesadevine 0:e1a608bb55e8 213 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
jamesadevine 0:e1a608bb55e8 214
jamesadevine 0:e1a608bb55e8 215
jamesadevine 0:e1a608bb55e8 216 /** \brief STR Exclusive (8 bit)
jamesadevine 0:e1a608bb55e8 217
jamesadevine 0:e1a608bb55e8 218 This function performs a exclusive STR command for 8 bit values.
jamesadevine 0:e1a608bb55e8 219
jamesadevine 0:e1a608bb55e8 220 \param [in] value Value to store
jamesadevine 0:e1a608bb55e8 221 \param [in] ptr Pointer to location
jamesadevine 0:e1a608bb55e8 222 \return 0 Function succeeded
jamesadevine 0:e1a608bb55e8 223 \return 1 Function failed
jamesadevine 0:e1a608bb55e8 224 */
jamesadevine 0:e1a608bb55e8 225 #define __STREXB(value, ptr) __strex(value, ptr)
jamesadevine 0:e1a608bb55e8 226
jamesadevine 0:e1a608bb55e8 227
jamesadevine 0:e1a608bb55e8 228 /** \brief STR Exclusive (16 bit)
jamesadevine 0:e1a608bb55e8 229
jamesadevine 0:e1a608bb55e8 230 This function performs a exclusive STR command for 16 bit values.
jamesadevine 0:e1a608bb55e8 231
jamesadevine 0:e1a608bb55e8 232 \param [in] value Value to store
jamesadevine 0:e1a608bb55e8 233 \param [in] ptr Pointer to location
jamesadevine 0:e1a608bb55e8 234 \return 0 Function succeeded
jamesadevine 0:e1a608bb55e8 235 \return 1 Function failed
jamesadevine 0:e1a608bb55e8 236 */
jamesadevine 0:e1a608bb55e8 237 #define __STREXH(value, ptr) __strex(value, ptr)
jamesadevine 0:e1a608bb55e8 238
jamesadevine 0:e1a608bb55e8 239
jamesadevine 0:e1a608bb55e8 240 /** \brief STR Exclusive (32 bit)
jamesadevine 0:e1a608bb55e8 241
jamesadevine 0:e1a608bb55e8 242 This function performs a exclusive STR command for 32 bit values.
jamesadevine 0:e1a608bb55e8 243
jamesadevine 0:e1a608bb55e8 244 \param [in] value Value to store
jamesadevine 0:e1a608bb55e8 245 \param [in] ptr Pointer to location
jamesadevine 0:e1a608bb55e8 246 \return 0 Function succeeded
jamesadevine 0:e1a608bb55e8 247 \return 1 Function failed
jamesadevine 0:e1a608bb55e8 248 */
jamesadevine 0:e1a608bb55e8 249 #define __STREXW(value, ptr) __strex(value, ptr)
jamesadevine 0:e1a608bb55e8 250
jamesadevine 0:e1a608bb55e8 251
jamesadevine 0:e1a608bb55e8 252 /** \brief Remove the exclusive lock
jamesadevine 0:e1a608bb55e8 253
jamesadevine 0:e1a608bb55e8 254 This function removes the exclusive lock which is created by LDREX.
jamesadevine 0:e1a608bb55e8 255
jamesadevine 0:e1a608bb55e8 256 */
jamesadevine 0:e1a608bb55e8 257 #define __CLREX __clrex
jamesadevine 0:e1a608bb55e8 258
jamesadevine 0:e1a608bb55e8 259
jamesadevine 0:e1a608bb55e8 260 /** \brief Signed Saturate
jamesadevine 0:e1a608bb55e8 261
jamesadevine 0:e1a608bb55e8 262 This function saturates a signed value.
jamesadevine 0:e1a608bb55e8 263
jamesadevine 0:e1a608bb55e8 264 \param [in] value Value to be saturated
jamesadevine 0:e1a608bb55e8 265 \param [in] sat Bit position to saturate to (1..32)
jamesadevine 0:e1a608bb55e8 266 \return Saturated value
jamesadevine 0:e1a608bb55e8 267 */
jamesadevine 0:e1a608bb55e8 268 #define __SSAT __ssat
jamesadevine 0:e1a608bb55e8 269
jamesadevine 0:e1a608bb55e8 270
jamesadevine 0:e1a608bb55e8 271 /** \brief Unsigned Saturate
jamesadevine 0:e1a608bb55e8 272
jamesadevine 0:e1a608bb55e8 273 This function saturates an unsigned value.
jamesadevine 0:e1a608bb55e8 274
jamesadevine 0:e1a608bb55e8 275 \param [in] value Value to be saturated
jamesadevine 0:e1a608bb55e8 276 \param [in] sat Bit position to saturate to (0..31)
jamesadevine 0:e1a608bb55e8 277 \return Saturated value
jamesadevine 0:e1a608bb55e8 278 */
jamesadevine 0:e1a608bb55e8 279 #define __USAT __usat
jamesadevine 0:e1a608bb55e8 280
jamesadevine 0:e1a608bb55e8 281
jamesadevine 0:e1a608bb55e8 282 /** \brief Count leading zeros
jamesadevine 0:e1a608bb55e8 283
jamesadevine 0:e1a608bb55e8 284 This function counts the number of leading zeros of a data value.
jamesadevine 0:e1a608bb55e8 285
jamesadevine 0:e1a608bb55e8 286 \param [in] value Value to count the leading zeros
jamesadevine 0:e1a608bb55e8 287 \return number of leading zeros in value
jamesadevine 0:e1a608bb55e8 288 */
jamesadevine 0:e1a608bb55e8 289 #define __CLZ __clz
jamesadevine 0:e1a608bb55e8 290
jamesadevine 0:e1a608bb55e8 291 #endif /* (__CORTEX_M >= 0x03) */
jamesadevine 0:e1a608bb55e8 292
jamesadevine 0:e1a608bb55e8 293
jamesadevine 0:e1a608bb55e8 294
jamesadevine 0:e1a608bb55e8 295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
jamesadevine 0:e1a608bb55e8 296 /* IAR iccarm specific functions */
jamesadevine 0:e1a608bb55e8 297
jamesadevine 0:e1a608bb55e8 298 #include <cmsis_iar.h>
jamesadevine 0:e1a608bb55e8 299
jamesadevine 0:e1a608bb55e8 300
jamesadevine 0:e1a608bb55e8 301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
jamesadevine 0:e1a608bb55e8 302 /* TI CCS specific functions */
jamesadevine 0:e1a608bb55e8 303
jamesadevine 0:e1a608bb55e8 304 #include <cmsis_ccs.h>
jamesadevine 0:e1a608bb55e8 305
jamesadevine 0:e1a608bb55e8 306
jamesadevine 0:e1a608bb55e8 307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
jamesadevine 0:e1a608bb55e8 308 /* GNU gcc specific functions */
jamesadevine 0:e1a608bb55e8 309
jamesadevine 0:e1a608bb55e8 310 /* Define macros for porting to both thumb1 and thumb2.
jamesadevine 0:e1a608bb55e8 311 * For thumb1, use low register (r0-r7), specified by constrant "l"
jamesadevine 0:e1a608bb55e8 312 * Otherwise, use general registers, specified by constrant "r" */
jamesadevine 0:e1a608bb55e8 313 #if defined (__thumb__) && !defined (__thumb2__)
jamesadevine 0:e1a608bb55e8 314 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
jamesadevine 0:e1a608bb55e8 315 #define __CMSIS_GCC_USE_REG(r) "l" (r)
jamesadevine 0:e1a608bb55e8 316 #else
jamesadevine 0:e1a608bb55e8 317 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
jamesadevine 0:e1a608bb55e8 318 #define __CMSIS_GCC_USE_REG(r) "r" (r)
jamesadevine 0:e1a608bb55e8 319 #endif
jamesadevine 0:e1a608bb55e8 320
jamesadevine 0:e1a608bb55e8 321 /** \brief No Operation
jamesadevine 0:e1a608bb55e8 322
jamesadevine 0:e1a608bb55e8 323 No Operation does nothing. This instruction can be used for code alignment purposes.
jamesadevine 0:e1a608bb55e8 324 */
jamesadevine 0:e1a608bb55e8 325 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
jamesadevine 0:e1a608bb55e8 326 {
jamesadevine 0:e1a608bb55e8 327 __ASM volatile ("nop");
jamesadevine 0:e1a608bb55e8 328 }
jamesadevine 0:e1a608bb55e8 329
jamesadevine 0:e1a608bb55e8 330
jamesadevine 0:e1a608bb55e8 331 /** \brief Wait For Interrupt
jamesadevine 0:e1a608bb55e8 332
jamesadevine 0:e1a608bb55e8 333 Wait For Interrupt is a hint instruction that suspends execution
jamesadevine 0:e1a608bb55e8 334 until one of a number of events occurs.
jamesadevine 0:e1a608bb55e8 335 */
jamesadevine 0:e1a608bb55e8 336 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
jamesadevine 0:e1a608bb55e8 337 {
jamesadevine 0:e1a608bb55e8 338 __ASM volatile ("wfi");
jamesadevine 0:e1a608bb55e8 339 }
jamesadevine 0:e1a608bb55e8 340
jamesadevine 0:e1a608bb55e8 341
jamesadevine 0:e1a608bb55e8 342 /** \brief Wait For Event
jamesadevine 0:e1a608bb55e8 343
jamesadevine 0:e1a608bb55e8 344 Wait For Event is a hint instruction that permits the processor to enter
jamesadevine 0:e1a608bb55e8 345 a low-power state until one of a number of events occurs.
jamesadevine 0:e1a608bb55e8 346 */
jamesadevine 0:e1a608bb55e8 347 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
jamesadevine 0:e1a608bb55e8 348 {
jamesadevine 0:e1a608bb55e8 349 __ASM volatile ("wfe");
jamesadevine 0:e1a608bb55e8 350 }
jamesadevine 0:e1a608bb55e8 351
jamesadevine 0:e1a608bb55e8 352
jamesadevine 0:e1a608bb55e8 353 /** \brief Send Event
jamesadevine 0:e1a608bb55e8 354
jamesadevine 0:e1a608bb55e8 355 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
jamesadevine 0:e1a608bb55e8 356 */
jamesadevine 0:e1a608bb55e8 357 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
jamesadevine 0:e1a608bb55e8 358 {
jamesadevine 0:e1a608bb55e8 359 __ASM volatile ("sev");
jamesadevine 0:e1a608bb55e8 360 }
jamesadevine 0:e1a608bb55e8 361
jamesadevine 0:e1a608bb55e8 362
jamesadevine 0:e1a608bb55e8 363 /** \brief Instruction Synchronization Barrier
jamesadevine 0:e1a608bb55e8 364
jamesadevine 0:e1a608bb55e8 365 Instruction Synchronization Barrier flushes the pipeline in the processor,
jamesadevine 0:e1a608bb55e8 366 so that all instructions following the ISB are fetched from cache or
jamesadevine 0:e1a608bb55e8 367 memory, after the instruction has been completed.
jamesadevine 0:e1a608bb55e8 368 */
jamesadevine 0:e1a608bb55e8 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
jamesadevine 0:e1a608bb55e8 370 {
jamesadevine 0:e1a608bb55e8 371 __ASM volatile ("isb");
jamesadevine 0:e1a608bb55e8 372 }
jamesadevine 0:e1a608bb55e8 373
jamesadevine 0:e1a608bb55e8 374
jamesadevine 0:e1a608bb55e8 375 /** \brief Data Synchronization Barrier
jamesadevine 0:e1a608bb55e8 376
jamesadevine 0:e1a608bb55e8 377 This function acts as a special kind of Data Memory Barrier.
jamesadevine 0:e1a608bb55e8 378 It completes when all explicit memory accesses before this instruction complete.
jamesadevine 0:e1a608bb55e8 379 */
jamesadevine 0:e1a608bb55e8 380 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
jamesadevine 0:e1a608bb55e8 381 {
jamesadevine 0:e1a608bb55e8 382 __ASM volatile ("dsb");
jamesadevine 0:e1a608bb55e8 383 }
jamesadevine 0:e1a608bb55e8 384
jamesadevine 0:e1a608bb55e8 385
jamesadevine 0:e1a608bb55e8 386 /** \brief Data Memory Barrier
jamesadevine 0:e1a608bb55e8 387
jamesadevine 0:e1a608bb55e8 388 This function ensures the apparent order of the explicit memory operations before
jamesadevine 0:e1a608bb55e8 389 and after the instruction, without ensuring their completion.
jamesadevine 0:e1a608bb55e8 390 */
jamesadevine 0:e1a608bb55e8 391 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
jamesadevine 0:e1a608bb55e8 392 {
jamesadevine 0:e1a608bb55e8 393 __ASM volatile ("dmb");
jamesadevine 0:e1a608bb55e8 394 }
jamesadevine 0:e1a608bb55e8 395
jamesadevine 0:e1a608bb55e8 396
jamesadevine 0:e1a608bb55e8 397 /** \brief Reverse byte order (32 bit)
jamesadevine 0:e1a608bb55e8 398
jamesadevine 0:e1a608bb55e8 399 This function reverses the byte order in integer value.
jamesadevine 0:e1a608bb55e8 400
jamesadevine 0:e1a608bb55e8 401 \param [in] value Value to reverse
jamesadevine 0:e1a608bb55e8 402 \return Reversed value
jamesadevine 0:e1a608bb55e8 403 */
jamesadevine 0:e1a608bb55e8 404 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
jamesadevine 0:e1a608bb55e8 405 {
jamesadevine 0:e1a608bb55e8 406 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
jamesadevine 0:e1a608bb55e8 407 return __builtin_bswap32(value);
jamesadevine 0:e1a608bb55e8 408 #else
jamesadevine 0:e1a608bb55e8 409 uint32_t result;
jamesadevine 0:e1a608bb55e8 410
jamesadevine 0:e1a608bb55e8 411 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
jamesadevine 0:e1a608bb55e8 412 return(result);
jamesadevine 0:e1a608bb55e8 413 #endif
jamesadevine 0:e1a608bb55e8 414 }
jamesadevine 0:e1a608bb55e8 415
jamesadevine 0:e1a608bb55e8 416
jamesadevine 0:e1a608bb55e8 417 /** \brief Reverse byte order (16 bit)
jamesadevine 0:e1a608bb55e8 418
jamesadevine 0:e1a608bb55e8 419 This function reverses the byte order in two unsigned short values.
jamesadevine 0:e1a608bb55e8 420
jamesadevine 0:e1a608bb55e8 421 \param [in] value Value to reverse
jamesadevine 0:e1a608bb55e8 422 \return Reversed value
jamesadevine 0:e1a608bb55e8 423 */
jamesadevine 0:e1a608bb55e8 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
jamesadevine 0:e1a608bb55e8 425 {
jamesadevine 0:e1a608bb55e8 426 uint32_t result;
jamesadevine 0:e1a608bb55e8 427
jamesadevine 0:e1a608bb55e8 428 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
jamesadevine 0:e1a608bb55e8 429 return(result);
jamesadevine 0:e1a608bb55e8 430 }
jamesadevine 0:e1a608bb55e8 431
jamesadevine 0:e1a608bb55e8 432
jamesadevine 0:e1a608bb55e8 433 /** \brief Reverse byte order in signed short value
jamesadevine 0:e1a608bb55e8 434
jamesadevine 0:e1a608bb55e8 435 This function reverses the byte order in a signed short value with sign extension to integer.
jamesadevine 0:e1a608bb55e8 436
jamesadevine 0:e1a608bb55e8 437 \param [in] value Value to reverse
jamesadevine 0:e1a608bb55e8 438 \return Reversed value
jamesadevine 0:e1a608bb55e8 439 */
jamesadevine 0:e1a608bb55e8 440 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
jamesadevine 0:e1a608bb55e8 441 {
jamesadevine 0:e1a608bb55e8 442 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
jamesadevine 0:e1a608bb55e8 443 return (short)__builtin_bswap16(value);
jamesadevine 0:e1a608bb55e8 444 #else
jamesadevine 0:e1a608bb55e8 445 uint32_t result;
jamesadevine 0:e1a608bb55e8 446
jamesadevine 0:e1a608bb55e8 447 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
jamesadevine 0:e1a608bb55e8 448 return(result);
jamesadevine 0:e1a608bb55e8 449 #endif
jamesadevine 0:e1a608bb55e8 450 }
jamesadevine 0:e1a608bb55e8 451
jamesadevine 0:e1a608bb55e8 452
jamesadevine 0:e1a608bb55e8 453 /** \brief Rotate Right in unsigned value (32 bit)
jamesadevine 0:e1a608bb55e8 454
jamesadevine 0:e1a608bb55e8 455 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
jamesadevine 0:e1a608bb55e8 456
jamesadevine 0:e1a608bb55e8 457 \param [in] value Value to rotate
jamesadevine 0:e1a608bb55e8 458 \param [in] value Number of Bits to rotate
jamesadevine 0:e1a608bb55e8 459 \return Rotated value
jamesadevine 0:e1a608bb55e8 460 */
jamesadevine 0:e1a608bb55e8 461 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
jamesadevine 0:e1a608bb55e8 462 {
jamesadevine 0:e1a608bb55e8 463 return (op1 >> op2) | (op1 << (32 - op2));
jamesadevine 0:e1a608bb55e8 464 }
jamesadevine 0:e1a608bb55e8 465
jamesadevine 0:e1a608bb55e8 466
jamesadevine 0:e1a608bb55e8 467 /** \brief Breakpoint
jamesadevine 0:e1a608bb55e8 468
jamesadevine 0:e1a608bb55e8 469 This function causes the processor to enter Debug state.
jamesadevine 0:e1a608bb55e8 470 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
jamesadevine 0:e1a608bb55e8 471
jamesadevine 0:e1a608bb55e8 472 \param [in] value is ignored by the processor.
jamesadevine 0:e1a608bb55e8 473 If required, a debugger can use it to store additional information about the breakpoint.
jamesadevine 0:e1a608bb55e8 474 */
jamesadevine 0:e1a608bb55e8 475 #define __BKPT(value) __ASM volatile ("bkpt "#value)
jamesadevine 0:e1a608bb55e8 476
jamesadevine 0:e1a608bb55e8 477
jamesadevine 0:e1a608bb55e8 478 #if (__CORTEX_M >= 0x03)
jamesadevine 0:e1a608bb55e8 479
jamesadevine 0:e1a608bb55e8 480 /** \brief Reverse bit order of value
jamesadevine 0:e1a608bb55e8 481
jamesadevine 0:e1a608bb55e8 482 This function reverses the bit order of the given value.
jamesadevine 0:e1a608bb55e8 483
jamesadevine 0:e1a608bb55e8 484 \param [in] value Value to reverse
jamesadevine 0:e1a608bb55e8 485 \return Reversed value
jamesadevine 0:e1a608bb55e8 486 */
jamesadevine 0:e1a608bb55e8 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
jamesadevine 0:e1a608bb55e8 488 {
jamesadevine 0:e1a608bb55e8 489 uint32_t result;
jamesadevine 0:e1a608bb55e8 490
jamesadevine 0:e1a608bb55e8 491 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
jamesadevine 0:e1a608bb55e8 492 return(result);
jamesadevine 0:e1a608bb55e8 493 }
jamesadevine 0:e1a608bb55e8 494
jamesadevine 0:e1a608bb55e8 495
jamesadevine 0:e1a608bb55e8 496 /** \brief LDR Exclusive (8 bit)
jamesadevine 0:e1a608bb55e8 497
jamesadevine 0:e1a608bb55e8 498 This function performs a exclusive LDR command for 8 bit value.
jamesadevine 0:e1a608bb55e8 499
jamesadevine 0:e1a608bb55e8 500 \param [in] ptr Pointer to data
jamesadevine 0:e1a608bb55e8 501 \return value of type uint8_t at (*ptr)
jamesadevine 0:e1a608bb55e8 502 */
jamesadevine 0:e1a608bb55e8 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
jamesadevine 0:e1a608bb55e8 504 {
jamesadevine 0:e1a608bb55e8 505 uint32_t result;
jamesadevine 0:e1a608bb55e8 506
jamesadevine 0:e1a608bb55e8 507 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
jamesadevine 0:e1a608bb55e8 508 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
jamesadevine 0:e1a608bb55e8 509 #else
jamesadevine 0:e1a608bb55e8 510 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
jamesadevine 0:e1a608bb55e8 511 accepted by assembler. So has to use following less efficient pattern.
jamesadevine 0:e1a608bb55e8 512 */
jamesadevine 0:e1a608bb55e8 513 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
jamesadevine 0:e1a608bb55e8 514 #endif
jamesadevine 0:e1a608bb55e8 515 return(result);
jamesadevine 0:e1a608bb55e8 516 }
jamesadevine 0:e1a608bb55e8 517
jamesadevine 0:e1a608bb55e8 518
jamesadevine 0:e1a608bb55e8 519 /** \brief LDR Exclusive (16 bit)
jamesadevine 0:e1a608bb55e8 520
jamesadevine 0:e1a608bb55e8 521 This function performs a exclusive LDR command for 16 bit values.
jamesadevine 0:e1a608bb55e8 522
jamesadevine 0:e1a608bb55e8 523 \param [in] ptr Pointer to data
jamesadevine 0:e1a608bb55e8 524 \return value of type uint16_t at (*ptr)
jamesadevine 0:e1a608bb55e8 525 */
jamesadevine 0:e1a608bb55e8 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
jamesadevine 0:e1a608bb55e8 527 {
jamesadevine 0:e1a608bb55e8 528 uint32_t result;
jamesadevine 0:e1a608bb55e8 529
jamesadevine 0:e1a608bb55e8 530 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
jamesadevine 0:e1a608bb55e8 531 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
jamesadevine 0:e1a608bb55e8 532 #else
jamesadevine 0:e1a608bb55e8 533 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
jamesadevine 0:e1a608bb55e8 534 accepted by assembler. So has to use following less efficient pattern.
jamesadevine 0:e1a608bb55e8 535 */
jamesadevine 0:e1a608bb55e8 536 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
jamesadevine 0:e1a608bb55e8 537 #endif
jamesadevine 0:e1a608bb55e8 538 return(result);
jamesadevine 0:e1a608bb55e8 539 }
jamesadevine 0:e1a608bb55e8 540
jamesadevine 0:e1a608bb55e8 541
jamesadevine 0:e1a608bb55e8 542 /** \brief LDR Exclusive (32 bit)
jamesadevine 0:e1a608bb55e8 543
jamesadevine 0:e1a608bb55e8 544 This function performs a exclusive LDR command for 32 bit values.
jamesadevine 0:e1a608bb55e8 545
jamesadevine 0:e1a608bb55e8 546 \param [in] ptr Pointer to data
jamesadevine 0:e1a608bb55e8 547 \return value of type uint32_t at (*ptr)
jamesadevine 0:e1a608bb55e8 548 */
jamesadevine 0:e1a608bb55e8 549 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
jamesadevine 0:e1a608bb55e8 550 {
jamesadevine 0:e1a608bb55e8 551 uint32_t result;
jamesadevine 0:e1a608bb55e8 552
jamesadevine 0:e1a608bb55e8 553 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
jamesadevine 0:e1a608bb55e8 554 return(result);
jamesadevine 0:e1a608bb55e8 555 }
jamesadevine 0:e1a608bb55e8 556
jamesadevine 0:e1a608bb55e8 557
jamesadevine 0:e1a608bb55e8 558 /** \brief STR Exclusive (8 bit)
jamesadevine 0:e1a608bb55e8 559
jamesadevine 0:e1a608bb55e8 560 This function performs a exclusive STR command for 8 bit values.
jamesadevine 0:e1a608bb55e8 561
jamesadevine 0:e1a608bb55e8 562 \param [in] value Value to store
jamesadevine 0:e1a608bb55e8 563 \param [in] ptr Pointer to location
jamesadevine 0:e1a608bb55e8 564 \return 0 Function succeeded
jamesadevine 0:e1a608bb55e8 565 \return 1 Function failed
jamesadevine 0:e1a608bb55e8 566 */
jamesadevine 0:e1a608bb55e8 567 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
jamesadevine 0:e1a608bb55e8 568 {
jamesadevine 0:e1a608bb55e8 569 uint32_t result;
jamesadevine 0:e1a608bb55e8 570
jamesadevine 0:e1a608bb55e8 571 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
jamesadevine 0:e1a608bb55e8 572 return(result);
jamesadevine 0:e1a608bb55e8 573 }
jamesadevine 0:e1a608bb55e8 574
jamesadevine 0:e1a608bb55e8 575
jamesadevine 0:e1a608bb55e8 576 /** \brief STR Exclusive (16 bit)
jamesadevine 0:e1a608bb55e8 577
jamesadevine 0:e1a608bb55e8 578 This function performs a exclusive STR command for 16 bit values.
jamesadevine 0:e1a608bb55e8 579
jamesadevine 0:e1a608bb55e8 580 \param [in] value Value to store
jamesadevine 0:e1a608bb55e8 581 \param [in] ptr Pointer to location
jamesadevine 0:e1a608bb55e8 582 \return 0 Function succeeded
jamesadevine 0:e1a608bb55e8 583 \return 1 Function failed
jamesadevine 0:e1a608bb55e8 584 */
jamesadevine 0:e1a608bb55e8 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
jamesadevine 0:e1a608bb55e8 586 {
jamesadevine 0:e1a608bb55e8 587 uint32_t result;
jamesadevine 0:e1a608bb55e8 588
jamesadevine 0:e1a608bb55e8 589 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
jamesadevine 0:e1a608bb55e8 590 return(result);
jamesadevine 0:e1a608bb55e8 591 }
jamesadevine 0:e1a608bb55e8 592
jamesadevine 0:e1a608bb55e8 593
jamesadevine 0:e1a608bb55e8 594 /** \brief STR Exclusive (32 bit)
jamesadevine 0:e1a608bb55e8 595
jamesadevine 0:e1a608bb55e8 596 This function performs a exclusive STR command for 32 bit values.
jamesadevine 0:e1a608bb55e8 597
jamesadevine 0:e1a608bb55e8 598 \param [in] value Value to store
jamesadevine 0:e1a608bb55e8 599 \param [in] ptr Pointer to location
jamesadevine 0:e1a608bb55e8 600 \return 0 Function succeeded
jamesadevine 0:e1a608bb55e8 601 \return 1 Function failed
jamesadevine 0:e1a608bb55e8 602 */
jamesadevine 0:e1a608bb55e8 603 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
jamesadevine 0:e1a608bb55e8 604 {
jamesadevine 0:e1a608bb55e8 605 uint32_t result;
jamesadevine 0:e1a608bb55e8 606
jamesadevine 0:e1a608bb55e8 607 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
jamesadevine 0:e1a608bb55e8 608 return(result);
jamesadevine 0:e1a608bb55e8 609 }
jamesadevine 0:e1a608bb55e8 610
jamesadevine 0:e1a608bb55e8 611
jamesadevine 0:e1a608bb55e8 612 /** \brief Remove the exclusive lock
jamesadevine 0:e1a608bb55e8 613
jamesadevine 0:e1a608bb55e8 614 This function removes the exclusive lock which is created by LDREX.
jamesadevine 0:e1a608bb55e8 615
jamesadevine 0:e1a608bb55e8 616 */
jamesadevine 0:e1a608bb55e8 617 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
jamesadevine 0:e1a608bb55e8 618 {
jamesadevine 0:e1a608bb55e8 619 __ASM volatile ("clrex" ::: "memory");
jamesadevine 0:e1a608bb55e8 620 }
jamesadevine 0:e1a608bb55e8 621
jamesadevine 0:e1a608bb55e8 622
jamesadevine 0:e1a608bb55e8 623 /** \brief Signed Saturate
jamesadevine 0:e1a608bb55e8 624
jamesadevine 0:e1a608bb55e8 625 This function saturates a signed value.
jamesadevine 0:e1a608bb55e8 626
jamesadevine 0:e1a608bb55e8 627 \param [in] value Value to be saturated
jamesadevine 0:e1a608bb55e8 628 \param [in] sat Bit position to saturate to (1..32)
jamesadevine 0:e1a608bb55e8 629 \return Saturated value
jamesadevine 0:e1a608bb55e8 630 */
jamesadevine 0:e1a608bb55e8 631 #define __SSAT(ARG1,ARG2) \
jamesadevine 0:e1a608bb55e8 632 ({ \
jamesadevine 0:e1a608bb55e8 633 uint32_t __RES, __ARG1 = (ARG1); \
jamesadevine 0:e1a608bb55e8 634 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
jamesadevine 0:e1a608bb55e8 635 __RES; \
jamesadevine 0:e1a608bb55e8 636 })
jamesadevine 0:e1a608bb55e8 637
jamesadevine 0:e1a608bb55e8 638
jamesadevine 0:e1a608bb55e8 639 /** \brief Unsigned Saturate
jamesadevine 0:e1a608bb55e8 640
jamesadevine 0:e1a608bb55e8 641 This function saturates an unsigned value.
jamesadevine 0:e1a608bb55e8 642
jamesadevine 0:e1a608bb55e8 643 \param [in] value Value to be saturated
jamesadevine 0:e1a608bb55e8 644 \param [in] sat Bit position to saturate to (0..31)
jamesadevine 0:e1a608bb55e8 645 \return Saturated value
jamesadevine 0:e1a608bb55e8 646 */
jamesadevine 0:e1a608bb55e8 647 #define __USAT(ARG1,ARG2) \
jamesadevine 0:e1a608bb55e8 648 ({ \
jamesadevine 0:e1a608bb55e8 649 uint32_t __RES, __ARG1 = (ARG1); \
jamesadevine 0:e1a608bb55e8 650 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
jamesadevine 0:e1a608bb55e8 651 __RES; \
jamesadevine 0:e1a608bb55e8 652 })
jamesadevine 0:e1a608bb55e8 653
jamesadevine 0:e1a608bb55e8 654
jamesadevine 0:e1a608bb55e8 655 /** \brief Count leading zeros
jamesadevine 0:e1a608bb55e8 656
jamesadevine 0:e1a608bb55e8 657 This function counts the number of leading zeros of a data value.
jamesadevine 0:e1a608bb55e8 658
jamesadevine 0:e1a608bb55e8 659 \param [in] value Value to count the leading zeros
jamesadevine 0:e1a608bb55e8 660 \return number of leading zeros in value
jamesadevine 0:e1a608bb55e8 661 */
jamesadevine 0:e1a608bb55e8 662 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
jamesadevine 0:e1a608bb55e8 663 {
jamesadevine 0:e1a608bb55e8 664 uint32_t result;
jamesadevine 0:e1a608bb55e8 665
jamesadevine 0:e1a608bb55e8 666 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
jamesadevine 0:e1a608bb55e8 667 return(result);
jamesadevine 0:e1a608bb55e8 668 }
jamesadevine 0:e1a608bb55e8 669
jamesadevine 0:e1a608bb55e8 670 #endif /* (__CORTEX_M >= 0x03) */
jamesadevine 0:e1a608bb55e8 671
jamesadevine 0:e1a608bb55e8 672
jamesadevine 0:e1a608bb55e8 673
jamesadevine 0:e1a608bb55e8 674
jamesadevine 0:e1a608bb55e8 675 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
jamesadevine 0:e1a608bb55e8 676 /* TASKING carm specific functions */
jamesadevine 0:e1a608bb55e8 677
jamesadevine 0:e1a608bb55e8 678 /*
jamesadevine 0:e1a608bb55e8 679 * The CMSIS functions have been implemented as intrinsics in the compiler.
jamesadevine 0:e1a608bb55e8 680 * Please use "carm -?i" to get an up to date list of all intrinsics,
jamesadevine 0:e1a608bb55e8 681 * Including the CMSIS ones.
jamesadevine 0:e1a608bb55e8 682 */
jamesadevine 0:e1a608bb55e8 683
jamesadevine 0:e1a608bb55e8 684 #endif
jamesadevine 0:e1a608bb55e8 685
jamesadevine 0:e1a608bb55e8 686 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
jamesadevine 0:e1a608bb55e8 687
jamesadevine 0:e1a608bb55e8 688 #endif /* __CORE_CMINSTR_H */