Lancaster University / mbed-dev-bin

Binary version of Lancaster University's mbed branch, soon to be merged. The source lives here:https://developer.mbed.org/teams/Lancaster-University/code/mbed-src/

Dependents:   microbit-dal microbit-ble-open microbit-dal-eddystone microbit-dal ... more

Fork of mbed-lite-test by Lancaster University

TARGET_NRF51_MICROBIT/core_cmFunc.h@3:768173a57492, 2016-07-13 (annotated)

Committer:
jamesadevine
Date:
Wed Jul 13 15:12:06 2016 +0100
Revision:
3:768173a57492
Parent:
0:e1a608bb55e8 
further updates to mbed-dev-bin

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jamesadevine 0:e1a608bb55e8 1 /**************************************************************************//**
jamesadevine 0:e1a608bb55e8 2 * @file core_cmFunc.h
jamesadevine 0:e1a608bb55e8 3 * @brief CMSIS Cortex-M Core Function Access Header File
jamesadevine 0:e1a608bb55e8 4 * @version V3.20
jamesadevine 0:e1a608bb55e8 5 * @date 25. February 2013
jamesadevine 0:e1a608bb55e8 6 *
jamesadevine 0:e1a608bb55e8 7 * @note
jamesadevine 0:e1a608bb55e8 8 *
jamesadevine 0:e1a608bb55e8 9 ******************************************************************************/
jamesadevine 0:e1a608bb55e8 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
jamesadevine 0:e1a608bb55e8 11
jamesadevine 0:e1a608bb55e8 12 All rights reserved.
jamesadevine 0:e1a608bb55e8 13 Redistribution and use in source and binary forms, with or without
jamesadevine 0:e1a608bb55e8 14 modification, are permitted provided that the following conditions are met:
jamesadevine 0:e1a608bb55e8 15 - Redistributions of source code must retain the above copyright
jamesadevine 0:e1a608bb55e8 16 notice, this list of conditions and the following disclaimer.
jamesadevine 0:e1a608bb55e8 17 - Redistributions in binary form must reproduce the above copyright
jamesadevine 0:e1a608bb55e8 18 notice, this list of conditions and the following disclaimer in the
jamesadevine 0:e1a608bb55e8 19 documentation and/or other materials provided with the distribution.
jamesadevine 0:e1a608bb55e8 20 - Neither the name of ARM nor the names of its contributors may be used
jamesadevine 0:e1a608bb55e8 21 to endorse or promote products derived from this software without
jamesadevine 0:e1a608bb55e8 22 specific prior written permission.
jamesadevine 0:e1a608bb55e8 23 *
jamesadevine 0:e1a608bb55e8 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jamesadevine 0:e1a608bb55e8 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jamesadevine 0:e1a608bb55e8 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
jamesadevine 0:e1a608bb55e8 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
jamesadevine 0:e1a608bb55e8 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
jamesadevine 0:e1a608bb55e8 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
jamesadevine 0:e1a608bb55e8 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
jamesadevine 0:e1a608bb55e8 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
jamesadevine 0:e1a608bb55e8 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
jamesadevine 0:e1a608bb55e8 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
jamesadevine 0:e1a608bb55e8 34 POSSIBILITY OF SUCH DAMAGE.
jamesadevine 0:e1a608bb55e8 35 ---------------------------------------------------------------------------*/
jamesadevine 0:e1a608bb55e8 36
jamesadevine 0:e1a608bb55e8 37
jamesadevine 0:e1a608bb55e8 38 #ifndef __CORE_CMFUNC_H
jamesadevine 0:e1a608bb55e8 39 #define __CORE_CMFUNC_H
jamesadevine 0:e1a608bb55e8 40
jamesadevine 0:e1a608bb55e8 41
jamesadevine 0:e1a608bb55e8 42 /* ########################### Core Function Access ########################### */
jamesadevine 0:e1a608bb55e8 43 /** \ingroup CMSIS_Core_FunctionInterface
jamesadevine 0:e1a608bb55e8 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
jamesadevine 0:e1a608bb55e8 45 @{
jamesadevine 0:e1a608bb55e8 46 */
jamesadevine 0:e1a608bb55e8 47
jamesadevine 0:e1a608bb55e8 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
jamesadevine 0:e1a608bb55e8 49 /* ARM armcc specific functions */
jamesadevine 0:e1a608bb55e8 50
jamesadevine 0:e1a608bb55e8 51 #if (__ARMCC_VERSION < 400677)
jamesadevine 0:e1a608bb55e8 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
jamesadevine 0:e1a608bb55e8 53 #endif
jamesadevine 0:e1a608bb55e8 54
jamesadevine 0:e1a608bb55e8 55 /* intrinsic void __enable_irq(); */
jamesadevine 0:e1a608bb55e8 56 /* intrinsic void __disable_irq(); */
jamesadevine 0:e1a608bb55e8 57
jamesadevine 0:e1a608bb55e8 58 /** \brief Get Control Register
jamesadevine 0:e1a608bb55e8 59
jamesadevine 0:e1a608bb55e8 60 This function returns the content of the Control Register.
jamesadevine 0:e1a608bb55e8 61
jamesadevine 0:e1a608bb55e8 62 \return Control Register value
jamesadevine 0:e1a608bb55e8 63 */
jamesadevine 0:e1a608bb55e8 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
jamesadevine 0:e1a608bb55e8 65 {
jamesadevine 0:e1a608bb55e8 66 register uint32_t __regControl __ASM("control");
jamesadevine 0:e1a608bb55e8 67 return(__regControl);
jamesadevine 0:e1a608bb55e8 68 }
jamesadevine 0:e1a608bb55e8 69
jamesadevine 0:e1a608bb55e8 70
jamesadevine 0:e1a608bb55e8 71 /** \brief Set Control Register
jamesadevine 0:e1a608bb55e8 72
jamesadevine 0:e1a608bb55e8 73 This function writes the given value to the Control Register.
jamesadevine 0:e1a608bb55e8 74
jamesadevine 0:e1a608bb55e8 75 \param [in] control Control Register value to set
jamesadevine 0:e1a608bb55e8 76 */
jamesadevine 0:e1a608bb55e8 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
jamesadevine 0:e1a608bb55e8 78 {
jamesadevine 0:e1a608bb55e8 79 register uint32_t __regControl __ASM("control");
jamesadevine 0:e1a608bb55e8 80 __regControl = control;
jamesadevine 0:e1a608bb55e8 81 }
jamesadevine 0:e1a608bb55e8 82
jamesadevine 0:e1a608bb55e8 83
jamesadevine 0:e1a608bb55e8 84 /** \brief Get IPSR Register
jamesadevine 0:e1a608bb55e8 85
jamesadevine 0:e1a608bb55e8 86 This function returns the content of the IPSR Register.
jamesadevine 0:e1a608bb55e8 87
jamesadevine 0:e1a608bb55e8 88 \return IPSR Register value
jamesadevine 0:e1a608bb55e8 89 */
jamesadevine 0:e1a608bb55e8 90 __STATIC_INLINE uint32_t __get_IPSR(void)
jamesadevine 0:e1a608bb55e8 91 {
jamesadevine 0:e1a608bb55e8 92 register uint32_t __regIPSR __ASM("ipsr");
jamesadevine 0:e1a608bb55e8 93 return(__regIPSR);
jamesadevine 0:e1a608bb55e8 94 }
jamesadevine 0:e1a608bb55e8 95
jamesadevine 0:e1a608bb55e8 96
jamesadevine 0:e1a608bb55e8 97 /** \brief Get APSR Register
jamesadevine 0:e1a608bb55e8 98
jamesadevine 0:e1a608bb55e8 99 This function returns the content of the APSR Register.
jamesadevine 0:e1a608bb55e8 100
jamesadevine 0:e1a608bb55e8 101 \return APSR Register value
jamesadevine 0:e1a608bb55e8 102 */
jamesadevine 0:e1a608bb55e8 103 __STATIC_INLINE uint32_t __get_APSR(void)
jamesadevine 0:e1a608bb55e8 104 {
jamesadevine 0:e1a608bb55e8 105 register uint32_t __regAPSR __ASM("apsr");
jamesadevine 0:e1a608bb55e8 106 return(__regAPSR);
jamesadevine 0:e1a608bb55e8 107 }
jamesadevine 0:e1a608bb55e8 108
jamesadevine 0:e1a608bb55e8 109
jamesadevine 0:e1a608bb55e8 110 /** \brief Get xPSR Register
jamesadevine 0:e1a608bb55e8 111
jamesadevine 0:e1a608bb55e8 112 This function returns the content of the xPSR Register.
jamesadevine 0:e1a608bb55e8 113
jamesadevine 0:e1a608bb55e8 114 \return xPSR Register value
jamesadevine 0:e1a608bb55e8 115 */
jamesadevine 0:e1a608bb55e8 116 __STATIC_INLINE uint32_t __get_xPSR(void)
jamesadevine 0:e1a608bb55e8 117 {
jamesadevine 0:e1a608bb55e8 118 register uint32_t __regXPSR __ASM("xpsr");
jamesadevine 0:e1a608bb55e8 119 return(__regXPSR);
jamesadevine 0:e1a608bb55e8 120 }
jamesadevine 0:e1a608bb55e8 121
jamesadevine 0:e1a608bb55e8 122
jamesadevine 0:e1a608bb55e8 123 /** \brief Get Process Stack Pointer
jamesadevine 0:e1a608bb55e8 124
jamesadevine 0:e1a608bb55e8 125 This function returns the current value of the Process Stack Pointer (PSP).
jamesadevine 0:e1a608bb55e8 126
jamesadevine 0:e1a608bb55e8 127 \return PSP Register value
jamesadevine 0:e1a608bb55e8 128 */
jamesadevine 0:e1a608bb55e8 129 __STATIC_INLINE uint32_t __get_PSP(void)
jamesadevine 0:e1a608bb55e8 130 {
jamesadevine 0:e1a608bb55e8 131 register uint32_t __regProcessStackPointer __ASM("psp");
jamesadevine 0:e1a608bb55e8 132 return(__regProcessStackPointer);
jamesadevine 0:e1a608bb55e8 133 }
jamesadevine 0:e1a608bb55e8 134
jamesadevine 0:e1a608bb55e8 135
jamesadevine 0:e1a608bb55e8 136 /** \brief Set Process Stack Pointer
jamesadevine 0:e1a608bb55e8 137
jamesadevine 0:e1a608bb55e8 138 This function assigns the given value to the Process Stack Pointer (PSP).
jamesadevine 0:e1a608bb55e8 139
jamesadevine 0:e1a608bb55e8 140 \param [in] topOfProcStack Process Stack Pointer value to set
jamesadevine 0:e1a608bb55e8 141 */
jamesadevine 0:e1a608bb55e8 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
jamesadevine 0:e1a608bb55e8 143 {
jamesadevine 0:e1a608bb55e8 144 register uint32_t __regProcessStackPointer __ASM("psp");
jamesadevine 0:e1a608bb55e8 145 __regProcessStackPointer = topOfProcStack;
jamesadevine 0:e1a608bb55e8 146 }
jamesadevine 0:e1a608bb55e8 147
jamesadevine 0:e1a608bb55e8 148
jamesadevine 0:e1a608bb55e8 149 /** \brief Get Main Stack Pointer
jamesadevine 0:e1a608bb55e8 150
jamesadevine 0:e1a608bb55e8 151 This function returns the current value of the Main Stack Pointer (MSP).
jamesadevine 0:e1a608bb55e8 152
jamesadevine 0:e1a608bb55e8 153 \return MSP Register value
jamesadevine 0:e1a608bb55e8 154 */
jamesadevine 0:e1a608bb55e8 155 __STATIC_INLINE uint32_t __get_MSP(void)
jamesadevine 0:e1a608bb55e8 156 {
jamesadevine 0:e1a608bb55e8 157 register uint32_t __regMainStackPointer __ASM("msp");
jamesadevine 0:e1a608bb55e8 158 return(__regMainStackPointer);
jamesadevine 0:e1a608bb55e8 159 }
jamesadevine 0:e1a608bb55e8 160
jamesadevine 0:e1a608bb55e8 161
jamesadevine 0:e1a608bb55e8 162 /** \brief Set Main Stack Pointer
jamesadevine 0:e1a608bb55e8 163
jamesadevine 0:e1a608bb55e8 164 This function assigns the given value to the Main Stack Pointer (MSP).
jamesadevine 0:e1a608bb55e8 165
jamesadevine 0:e1a608bb55e8 166 \param [in] topOfMainStack Main Stack Pointer value to set
jamesadevine 0:e1a608bb55e8 167 */
jamesadevine 0:e1a608bb55e8 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
jamesadevine 0:e1a608bb55e8 169 {
jamesadevine 0:e1a608bb55e8 170 register uint32_t __regMainStackPointer __ASM("msp");
jamesadevine 0:e1a608bb55e8 171 __regMainStackPointer = topOfMainStack;
jamesadevine 0:e1a608bb55e8 172 }
jamesadevine 0:e1a608bb55e8 173
jamesadevine 0:e1a608bb55e8 174
jamesadevine 0:e1a608bb55e8 175 /** \brief Get Priority Mask
jamesadevine 0:e1a608bb55e8 176
jamesadevine 0:e1a608bb55e8 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
jamesadevine 0:e1a608bb55e8 178
jamesadevine 0:e1a608bb55e8 179 \return Priority Mask value
jamesadevine 0:e1a608bb55e8 180 */
jamesadevine 0:e1a608bb55e8 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
jamesadevine 0:e1a608bb55e8 182 {
jamesadevine 0:e1a608bb55e8 183 register uint32_t __regPriMask __ASM("primask");
jamesadevine 0:e1a608bb55e8 184 return(__regPriMask);
jamesadevine 0:e1a608bb55e8 185 }
jamesadevine 0:e1a608bb55e8 186
jamesadevine 0:e1a608bb55e8 187
jamesadevine 0:e1a608bb55e8 188 /** \brief Set Priority Mask
jamesadevine 0:e1a608bb55e8 189
jamesadevine 0:e1a608bb55e8 190 This function assigns the given value to the Priority Mask Register.
jamesadevine 0:e1a608bb55e8 191
jamesadevine 0:e1a608bb55e8 192 \param [in] priMask Priority Mask
jamesadevine 0:e1a608bb55e8 193 */
jamesadevine 0:e1a608bb55e8 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
jamesadevine 0:e1a608bb55e8 195 {
jamesadevine 0:e1a608bb55e8 196 register uint32_t __regPriMask __ASM("primask");
jamesadevine 0:e1a608bb55e8 197 __regPriMask = (priMask);
jamesadevine 0:e1a608bb55e8 198 }
jamesadevine 0:e1a608bb55e8 199
jamesadevine 0:e1a608bb55e8 200
jamesadevine 0:e1a608bb55e8 201 #if (__CORTEX_M >= 0x03)
jamesadevine 0:e1a608bb55e8 202
jamesadevine 0:e1a608bb55e8 203 /** \brief Enable FIQ
jamesadevine 0:e1a608bb55e8 204
jamesadevine 0:e1a608bb55e8 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
jamesadevine 0:e1a608bb55e8 206 Can only be executed in Privileged modes.
jamesadevine 0:e1a608bb55e8 207 */
jamesadevine 0:e1a608bb55e8 208 #define __enable_fault_irq __enable_fiq
jamesadevine 0:e1a608bb55e8 209
jamesadevine 0:e1a608bb55e8 210
jamesadevine 0:e1a608bb55e8 211 /** \brief Disable FIQ
jamesadevine 0:e1a608bb55e8 212
jamesadevine 0:e1a608bb55e8 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
jamesadevine 0:e1a608bb55e8 214 Can only be executed in Privileged modes.
jamesadevine 0:e1a608bb55e8 215 */
jamesadevine 0:e1a608bb55e8 216 #define __disable_fault_irq __disable_fiq
jamesadevine 0:e1a608bb55e8 217
jamesadevine 0:e1a608bb55e8 218
jamesadevine 0:e1a608bb55e8 219 /** \brief Get Base Priority
jamesadevine 0:e1a608bb55e8 220
jamesadevine 0:e1a608bb55e8 221 This function returns the current value of the Base Priority register.
jamesadevine 0:e1a608bb55e8 222
jamesadevine 0:e1a608bb55e8 223 \return Base Priority register value
jamesadevine 0:e1a608bb55e8 224 */
jamesadevine 0:e1a608bb55e8 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
jamesadevine 0:e1a608bb55e8 226 {
jamesadevine 0:e1a608bb55e8 227 register uint32_t __regBasePri __ASM("basepri");
jamesadevine 0:e1a608bb55e8 228 return(__regBasePri);
jamesadevine 0:e1a608bb55e8 229 }
jamesadevine 0:e1a608bb55e8 230
jamesadevine 0:e1a608bb55e8 231
jamesadevine 0:e1a608bb55e8 232 /** \brief Set Base Priority
jamesadevine 0:e1a608bb55e8 233
jamesadevine 0:e1a608bb55e8 234 This function assigns the given value to the Base Priority register.
jamesadevine 0:e1a608bb55e8 235
jamesadevine 0:e1a608bb55e8 236 \param [in] basePri Base Priority value to set
jamesadevine 0:e1a608bb55e8 237 */
jamesadevine 0:e1a608bb55e8 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
jamesadevine 0:e1a608bb55e8 239 {
jamesadevine 0:e1a608bb55e8 240 register uint32_t __regBasePri __ASM("basepri");
jamesadevine 0:e1a608bb55e8 241 __regBasePri = (basePri & 0xff);
jamesadevine 0:e1a608bb55e8 242 }
jamesadevine 0:e1a608bb55e8 243
jamesadevine 0:e1a608bb55e8 244
jamesadevine 0:e1a608bb55e8 245 /** \brief Get Fault Mask
jamesadevine 0:e1a608bb55e8 246
jamesadevine 0:e1a608bb55e8 247 This function returns the current value of the Fault Mask register.
jamesadevine 0:e1a608bb55e8 248
jamesadevine 0:e1a608bb55e8 249 \return Fault Mask register value
jamesadevine 0:e1a608bb55e8 250 */
jamesadevine 0:e1a608bb55e8 251 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
jamesadevine 0:e1a608bb55e8 252 {
jamesadevine 0:e1a608bb55e8 253 register uint32_t __regFaultMask __ASM("faultmask");
jamesadevine 0:e1a608bb55e8 254 return(__regFaultMask);
jamesadevine 0:e1a608bb55e8 255 }
jamesadevine 0:e1a608bb55e8 256
jamesadevine 0:e1a608bb55e8 257
jamesadevine 0:e1a608bb55e8 258 /** \brief Set Fault Mask
jamesadevine 0:e1a608bb55e8 259
jamesadevine 0:e1a608bb55e8 260 This function assigns the given value to the Fault Mask register.
jamesadevine 0:e1a608bb55e8 261
jamesadevine 0:e1a608bb55e8 262 \param [in] faultMask Fault Mask value to set
jamesadevine 0:e1a608bb55e8 263 */
jamesadevine 0:e1a608bb55e8 264 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
jamesadevine 0:e1a608bb55e8 265 {
jamesadevine 0:e1a608bb55e8 266 register uint32_t __regFaultMask __ASM("faultmask");
jamesadevine 0:e1a608bb55e8 267 __regFaultMask = (faultMask & (uint32_t)1);
jamesadevine 0:e1a608bb55e8 268 }
jamesadevine 0:e1a608bb55e8 269
jamesadevine 0:e1a608bb55e8 270 #endif /* (__CORTEX_M >= 0x03) */
jamesadevine 0:e1a608bb55e8 271
jamesadevine 0:e1a608bb55e8 272
jamesadevine 0:e1a608bb55e8 273 #if (__CORTEX_M == 0x04)
jamesadevine 0:e1a608bb55e8 274
jamesadevine 0:e1a608bb55e8 275 /** \brief Get FPSCR
jamesadevine 0:e1a608bb55e8 276
jamesadevine 0:e1a608bb55e8 277 This function returns the current value of the Floating Point Status/Control register.
jamesadevine 0:e1a608bb55e8 278
jamesadevine 0:e1a608bb55e8 279 \return Floating Point Status/Control register value
jamesadevine 0:e1a608bb55e8 280 */
jamesadevine 0:e1a608bb55e8 281 __STATIC_INLINE uint32_t __get_FPSCR(void)
jamesadevine 0:e1a608bb55e8 282 {
jamesadevine 0:e1a608bb55e8 283 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jamesadevine 0:e1a608bb55e8 284 register uint32_t __regfpscr __ASM("fpscr");
jamesadevine 0:e1a608bb55e8 285 return(__regfpscr);
jamesadevine 0:e1a608bb55e8 286 #else
jamesadevine 0:e1a608bb55e8 287 return(0);
jamesadevine 0:e1a608bb55e8 288 #endif
jamesadevine 0:e1a608bb55e8 289 }
jamesadevine 0:e1a608bb55e8 290
jamesadevine 0:e1a608bb55e8 291
jamesadevine 0:e1a608bb55e8 292 /** \brief Set FPSCR
jamesadevine 0:e1a608bb55e8 293
jamesadevine 0:e1a608bb55e8 294 This function assigns the given value to the Floating Point Status/Control register.
jamesadevine 0:e1a608bb55e8 295
jamesadevine 0:e1a608bb55e8 296 \param [in] fpscr Floating Point Status/Control value to set
jamesadevine 0:e1a608bb55e8 297 */
jamesadevine 0:e1a608bb55e8 298 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
jamesadevine 0:e1a608bb55e8 299 {
jamesadevine 0:e1a608bb55e8 300 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jamesadevine 0:e1a608bb55e8 301 register uint32_t __regfpscr __ASM("fpscr");
jamesadevine 0:e1a608bb55e8 302 __regfpscr = (fpscr);
jamesadevine 0:e1a608bb55e8 303 #endif
jamesadevine 0:e1a608bb55e8 304 }
jamesadevine 0:e1a608bb55e8 305
jamesadevine 0:e1a608bb55e8 306 #endif /* (__CORTEX_M == 0x04) */
jamesadevine 0:e1a608bb55e8 307
jamesadevine 0:e1a608bb55e8 308
jamesadevine 0:e1a608bb55e8 309 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
jamesadevine 0:e1a608bb55e8 310 /* IAR iccarm specific functions */
jamesadevine 0:e1a608bb55e8 311
jamesadevine 0:e1a608bb55e8 312 #include <cmsis_iar.h>
jamesadevine 0:e1a608bb55e8 313
jamesadevine 0:e1a608bb55e8 314
jamesadevine 0:e1a608bb55e8 315 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
jamesadevine 0:e1a608bb55e8 316 /* TI CCS specific functions */
jamesadevine 0:e1a608bb55e8 317
jamesadevine 0:e1a608bb55e8 318 #include <cmsis_ccs.h>
jamesadevine 0:e1a608bb55e8 319
jamesadevine 0:e1a608bb55e8 320
jamesadevine 0:e1a608bb55e8 321 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
jamesadevine 0:e1a608bb55e8 322 /* GNU gcc specific functions */
jamesadevine 0:e1a608bb55e8 323
jamesadevine 0:e1a608bb55e8 324 /** \brief Enable IRQ Interrupts
jamesadevine 0:e1a608bb55e8 325
jamesadevine 0:e1a608bb55e8 326 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
jamesadevine 0:e1a608bb55e8 327 Can only be executed in Privileged modes.
jamesadevine 0:e1a608bb55e8 328 */
jamesadevine 0:e1a608bb55e8 329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
jamesadevine 0:e1a608bb55e8 330 {
jamesadevine 0:e1a608bb55e8 331 __ASM volatile ("cpsie i" : : : "memory");
jamesadevine 0:e1a608bb55e8 332 }
jamesadevine 0:e1a608bb55e8 333
jamesadevine 0:e1a608bb55e8 334
jamesadevine 0:e1a608bb55e8 335 /** \brief Disable IRQ Interrupts
jamesadevine 0:e1a608bb55e8 336
jamesadevine 0:e1a608bb55e8 337 This function disables IRQ interrupts by setting the I-bit in the CPSR.
jamesadevine 0:e1a608bb55e8 338 Can only be executed in Privileged modes.
jamesadevine 0:e1a608bb55e8 339 */
jamesadevine 0:e1a608bb55e8 340 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
jamesadevine 0:e1a608bb55e8 341 {
jamesadevine 0:e1a608bb55e8 342 __ASM volatile ("cpsid i" : : : "memory");
jamesadevine 0:e1a608bb55e8 343 }
jamesadevine 0:e1a608bb55e8 344
jamesadevine 0:e1a608bb55e8 345
jamesadevine 0:e1a608bb55e8 346 /** \brief Get Control Register
jamesadevine 0:e1a608bb55e8 347
jamesadevine 0:e1a608bb55e8 348 This function returns the content of the Control Register.
jamesadevine 0:e1a608bb55e8 349
jamesadevine 0:e1a608bb55e8 350 \return Control Register value
jamesadevine 0:e1a608bb55e8 351 */
jamesadevine 0:e1a608bb55e8 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
jamesadevine 0:e1a608bb55e8 353 {
jamesadevine 0:e1a608bb55e8 354 uint32_t result;
jamesadevine 0:e1a608bb55e8 355
jamesadevine 0:e1a608bb55e8 356 __ASM volatile ("MRS %0, control" : "=r" (result) );
jamesadevine 0:e1a608bb55e8 357 return(result);
jamesadevine 0:e1a608bb55e8 358 }
jamesadevine 0:e1a608bb55e8 359
jamesadevine 0:e1a608bb55e8 360
jamesadevine 0:e1a608bb55e8 361 /** \brief Set Control Register
jamesadevine 0:e1a608bb55e8 362
jamesadevine 0:e1a608bb55e8 363 This function writes the given value to the Control Register.
jamesadevine 0:e1a608bb55e8 364
jamesadevine 0:e1a608bb55e8 365 \param [in] control Control Register value to set
jamesadevine 0:e1a608bb55e8 366 */
jamesadevine 0:e1a608bb55e8 367 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
jamesadevine 0:e1a608bb55e8 368 {
jamesadevine 0:e1a608bb55e8 369 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
jamesadevine 0:e1a608bb55e8 370 }
jamesadevine 0:e1a608bb55e8 371
jamesadevine 0:e1a608bb55e8 372
jamesadevine 0:e1a608bb55e8 373 /** \brief Get IPSR Register
jamesadevine 0:e1a608bb55e8 374
jamesadevine 0:e1a608bb55e8 375 This function returns the content of the IPSR Register.
jamesadevine 0:e1a608bb55e8 376
jamesadevine 0:e1a608bb55e8 377 \return IPSR Register value
jamesadevine 0:e1a608bb55e8 378 */
jamesadevine 0:e1a608bb55e8 379 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
jamesadevine 0:e1a608bb55e8 380 {
jamesadevine 0:e1a608bb55e8 381 uint32_t result;
jamesadevine 0:e1a608bb55e8 382
jamesadevine 0:e1a608bb55e8 383 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
jamesadevine 0:e1a608bb55e8 384 return(result);
jamesadevine 0:e1a608bb55e8 385 }
jamesadevine 0:e1a608bb55e8 386
jamesadevine 0:e1a608bb55e8 387
jamesadevine 0:e1a608bb55e8 388 /** \brief Get APSR Register
jamesadevine 0:e1a608bb55e8 389
jamesadevine 0:e1a608bb55e8 390 This function returns the content of the APSR Register.
jamesadevine 0:e1a608bb55e8 391
jamesadevine 0:e1a608bb55e8 392 \return APSR Register value
jamesadevine 0:e1a608bb55e8 393 */
jamesadevine 0:e1a608bb55e8 394 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
jamesadevine 0:e1a608bb55e8 395 {
jamesadevine 0:e1a608bb55e8 396 uint32_t result;
jamesadevine 0:e1a608bb55e8 397
jamesadevine 0:e1a608bb55e8 398 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
jamesadevine 0:e1a608bb55e8 399 return(result);
jamesadevine 0:e1a608bb55e8 400 }
jamesadevine 0:e1a608bb55e8 401
jamesadevine 0:e1a608bb55e8 402
jamesadevine 0:e1a608bb55e8 403 /** \brief Get xPSR Register
jamesadevine 0:e1a608bb55e8 404
jamesadevine 0:e1a608bb55e8 405 This function returns the content of the xPSR Register.
jamesadevine 0:e1a608bb55e8 406
jamesadevine 0:e1a608bb55e8 407 \return xPSR Register value
jamesadevine 0:e1a608bb55e8 408 */
jamesadevine 0:e1a608bb55e8 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
jamesadevine 0:e1a608bb55e8 410 {
jamesadevine 0:e1a608bb55e8 411 uint32_t result;
jamesadevine 0:e1a608bb55e8 412
jamesadevine 0:e1a608bb55e8 413 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
jamesadevine 0:e1a608bb55e8 414 return(result);
jamesadevine 0:e1a608bb55e8 415 }
jamesadevine 0:e1a608bb55e8 416
jamesadevine 0:e1a608bb55e8 417
jamesadevine 0:e1a608bb55e8 418 /** \brief Get Process Stack Pointer
jamesadevine 0:e1a608bb55e8 419
jamesadevine 0:e1a608bb55e8 420 This function returns the current value of the Process Stack Pointer (PSP).
jamesadevine 0:e1a608bb55e8 421
jamesadevine 0:e1a608bb55e8 422 \return PSP Register value
jamesadevine 0:e1a608bb55e8 423 */
jamesadevine 0:e1a608bb55e8 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
jamesadevine 0:e1a608bb55e8 425 {
jamesadevine 0:e1a608bb55e8 426 register uint32_t result;
jamesadevine 0:e1a608bb55e8 427
jamesadevine 0:e1a608bb55e8 428 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
jamesadevine 0:e1a608bb55e8 429 return(result);
jamesadevine 0:e1a608bb55e8 430 }
jamesadevine 0:e1a608bb55e8 431
jamesadevine 0:e1a608bb55e8 432
jamesadevine 0:e1a608bb55e8 433 /** \brief Set Process Stack Pointer
jamesadevine 0:e1a608bb55e8 434
jamesadevine 0:e1a608bb55e8 435 This function assigns the given value to the Process Stack Pointer (PSP).
jamesadevine 0:e1a608bb55e8 436
jamesadevine 0:e1a608bb55e8 437 \param [in] topOfProcStack Process Stack Pointer value to set
jamesadevine 0:e1a608bb55e8 438 */
jamesadevine 0:e1a608bb55e8 439 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
jamesadevine 0:e1a608bb55e8 440 {
jamesadevine 0:e1a608bb55e8 441 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
jamesadevine 0:e1a608bb55e8 442 }
jamesadevine 0:e1a608bb55e8 443
jamesadevine 0:e1a608bb55e8 444
jamesadevine 0:e1a608bb55e8 445 /** \brief Get Main Stack Pointer
jamesadevine 0:e1a608bb55e8 446
jamesadevine 0:e1a608bb55e8 447 This function returns the current value of the Main Stack Pointer (MSP).
jamesadevine 0:e1a608bb55e8 448
jamesadevine 0:e1a608bb55e8 449 \return MSP Register value
jamesadevine 0:e1a608bb55e8 450 */
jamesadevine 0:e1a608bb55e8 451 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
jamesadevine 0:e1a608bb55e8 452 {
jamesadevine 0:e1a608bb55e8 453 register uint32_t result;
jamesadevine 0:e1a608bb55e8 454
jamesadevine 0:e1a608bb55e8 455 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
jamesadevine 0:e1a608bb55e8 456 return(result);
jamesadevine 0:e1a608bb55e8 457 }
jamesadevine 0:e1a608bb55e8 458
jamesadevine 0:e1a608bb55e8 459
jamesadevine 0:e1a608bb55e8 460 /** \brief Set Main Stack Pointer
jamesadevine 0:e1a608bb55e8 461
jamesadevine 0:e1a608bb55e8 462 This function assigns the given value to the Main Stack Pointer (MSP).
jamesadevine 0:e1a608bb55e8 463
jamesadevine 0:e1a608bb55e8 464 \param [in] topOfMainStack Main Stack Pointer value to set
jamesadevine 0:e1a608bb55e8 465 */
jamesadevine 0:e1a608bb55e8 466 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
jamesadevine 0:e1a608bb55e8 467 {
jamesadevine 0:e1a608bb55e8 468 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
jamesadevine 0:e1a608bb55e8 469 }
jamesadevine 0:e1a608bb55e8 470
jamesadevine 0:e1a608bb55e8 471
jamesadevine 0:e1a608bb55e8 472 /** \brief Get Priority Mask
jamesadevine 0:e1a608bb55e8 473
jamesadevine 0:e1a608bb55e8 474 This function returns the current state of the priority mask bit from the Priority Mask Register.
jamesadevine 0:e1a608bb55e8 475
jamesadevine 0:e1a608bb55e8 476 \return Priority Mask value
jamesadevine 0:e1a608bb55e8 477 */
jamesadevine 0:e1a608bb55e8 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
jamesadevine 0:e1a608bb55e8 479 {
jamesadevine 0:e1a608bb55e8 480 uint32_t result;
jamesadevine 0:e1a608bb55e8 481
jamesadevine 0:e1a608bb55e8 482 __ASM volatile ("MRS %0, primask" : "=r" (result) );
jamesadevine 0:e1a608bb55e8 483 return(result);
jamesadevine 0:e1a608bb55e8 484 }
jamesadevine 0:e1a608bb55e8 485
jamesadevine 0:e1a608bb55e8 486
jamesadevine 0:e1a608bb55e8 487 /** \brief Set Priority Mask
jamesadevine 0:e1a608bb55e8 488
jamesadevine 0:e1a608bb55e8 489 This function assigns the given value to the Priority Mask Register.
jamesadevine 0:e1a608bb55e8 490
jamesadevine 0:e1a608bb55e8 491 \param [in] priMask Priority Mask
jamesadevine 0:e1a608bb55e8 492 */
jamesadevine 0:e1a608bb55e8 493 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
jamesadevine 0:e1a608bb55e8 494 {
jamesadevine 0:e1a608bb55e8 495 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
jamesadevine 0:e1a608bb55e8 496 }
jamesadevine 0:e1a608bb55e8 497
jamesadevine 0:e1a608bb55e8 498
jamesadevine 0:e1a608bb55e8 499 #if (__CORTEX_M >= 0x03)
jamesadevine 0:e1a608bb55e8 500
jamesadevine 0:e1a608bb55e8 501 /** \brief Enable FIQ
jamesadevine 0:e1a608bb55e8 502
jamesadevine 0:e1a608bb55e8 503 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
jamesadevine 0:e1a608bb55e8 504 Can only be executed in Privileged modes.
jamesadevine 0:e1a608bb55e8 505 */
jamesadevine 0:e1a608bb55e8 506 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
jamesadevine 0:e1a608bb55e8 507 {
jamesadevine 0:e1a608bb55e8 508 __ASM volatile ("cpsie f" : : : "memory");
jamesadevine 0:e1a608bb55e8 509 }
jamesadevine 0:e1a608bb55e8 510
jamesadevine 0:e1a608bb55e8 511
jamesadevine 0:e1a608bb55e8 512 /** \brief Disable FIQ
jamesadevine 0:e1a608bb55e8 513
jamesadevine 0:e1a608bb55e8 514 This function disables FIQ interrupts by setting the F-bit in the CPSR.
jamesadevine 0:e1a608bb55e8 515 Can only be executed in Privileged modes.
jamesadevine 0:e1a608bb55e8 516 */
jamesadevine 0:e1a608bb55e8 517 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
jamesadevine 0:e1a608bb55e8 518 {
jamesadevine 0:e1a608bb55e8 519 __ASM volatile ("cpsid f" : : : "memory");
jamesadevine 0:e1a608bb55e8 520 }
jamesadevine 0:e1a608bb55e8 521
jamesadevine 0:e1a608bb55e8 522
jamesadevine 0:e1a608bb55e8 523 /** \brief Get Base Priority
jamesadevine 0:e1a608bb55e8 524
jamesadevine 0:e1a608bb55e8 525 This function returns the current value of the Base Priority register.
jamesadevine 0:e1a608bb55e8 526
jamesadevine 0:e1a608bb55e8 527 \return Base Priority register value
jamesadevine 0:e1a608bb55e8 528 */
jamesadevine 0:e1a608bb55e8 529 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
jamesadevine 0:e1a608bb55e8 530 {
jamesadevine 0:e1a608bb55e8 531 uint32_t result;
jamesadevine 0:e1a608bb55e8 532
jamesadevine 0:e1a608bb55e8 533 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
jamesadevine 0:e1a608bb55e8 534 return(result);
jamesadevine 0:e1a608bb55e8 535 }
jamesadevine 0:e1a608bb55e8 536
jamesadevine 0:e1a608bb55e8 537
jamesadevine 0:e1a608bb55e8 538 /** \brief Set Base Priority
jamesadevine 0:e1a608bb55e8 539
jamesadevine 0:e1a608bb55e8 540 This function assigns the given value to the Base Priority register.
jamesadevine 0:e1a608bb55e8 541
jamesadevine 0:e1a608bb55e8 542 \param [in] basePri Base Priority value to set
jamesadevine 0:e1a608bb55e8 543 */
jamesadevine 0:e1a608bb55e8 544 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
jamesadevine 0:e1a608bb55e8 545 {
jamesadevine 0:e1a608bb55e8 546 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
jamesadevine 0:e1a608bb55e8 547 }
jamesadevine 0:e1a608bb55e8 548
jamesadevine 0:e1a608bb55e8 549
jamesadevine 0:e1a608bb55e8 550 /** \brief Get Fault Mask
jamesadevine 0:e1a608bb55e8 551
jamesadevine 0:e1a608bb55e8 552 This function returns the current value of the Fault Mask register.
jamesadevine 0:e1a608bb55e8 553
jamesadevine 0:e1a608bb55e8 554 \return Fault Mask register value
jamesadevine 0:e1a608bb55e8 555 */
jamesadevine 0:e1a608bb55e8 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
jamesadevine 0:e1a608bb55e8 557 {
jamesadevine 0:e1a608bb55e8 558 uint32_t result;
jamesadevine 0:e1a608bb55e8 559
jamesadevine 0:e1a608bb55e8 560 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
jamesadevine 0:e1a608bb55e8 561 return(result);
jamesadevine 0:e1a608bb55e8 562 }
jamesadevine 0:e1a608bb55e8 563
jamesadevine 0:e1a608bb55e8 564
jamesadevine 0:e1a608bb55e8 565 /** \brief Set Fault Mask
jamesadevine 0:e1a608bb55e8 566
jamesadevine 0:e1a608bb55e8 567 This function assigns the given value to the Fault Mask register.
jamesadevine 0:e1a608bb55e8 568
jamesadevine 0:e1a608bb55e8 569 \param [in] faultMask Fault Mask value to set
jamesadevine 0:e1a608bb55e8 570 */
jamesadevine 0:e1a608bb55e8 571 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
jamesadevine 0:e1a608bb55e8 572 {
jamesadevine 0:e1a608bb55e8 573 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
jamesadevine 0:e1a608bb55e8 574 }
jamesadevine 0:e1a608bb55e8 575
jamesadevine 0:e1a608bb55e8 576 #endif /* (__CORTEX_M >= 0x03) */
jamesadevine 0:e1a608bb55e8 577
jamesadevine 0:e1a608bb55e8 578
jamesadevine 0:e1a608bb55e8 579 #if (__CORTEX_M == 0x04)
jamesadevine 0:e1a608bb55e8 580
jamesadevine 0:e1a608bb55e8 581 /** \brief Get FPSCR
jamesadevine 0:e1a608bb55e8 582
jamesadevine 0:e1a608bb55e8 583 This function returns the current value of the Floating Point Status/Control register.
jamesadevine 0:e1a608bb55e8 584
jamesadevine 0:e1a608bb55e8 585 \return Floating Point Status/Control register value
jamesadevine 0:e1a608bb55e8 586 */
jamesadevine 0:e1a608bb55e8 587 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
jamesadevine 0:e1a608bb55e8 588 {
jamesadevine 0:e1a608bb55e8 589 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jamesadevine 0:e1a608bb55e8 590 uint32_t result;
jamesadevine 0:e1a608bb55e8 591
jamesadevine 0:e1a608bb55e8 592 /* Empty asm statement works as a scheduling barrier */
jamesadevine 0:e1a608bb55e8 593 __ASM volatile ("");
jamesadevine 0:e1a608bb55e8 594 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
jamesadevine 0:e1a608bb55e8 595 __ASM volatile ("");
jamesadevine 0:e1a608bb55e8 596 return(result);
jamesadevine 0:e1a608bb55e8 597 #else
jamesadevine 0:e1a608bb55e8 598 return(0);
jamesadevine 0:e1a608bb55e8 599 #endif
jamesadevine 0:e1a608bb55e8 600 }
jamesadevine 0:e1a608bb55e8 601
jamesadevine 0:e1a608bb55e8 602
jamesadevine 0:e1a608bb55e8 603 /** \brief Set FPSCR
jamesadevine 0:e1a608bb55e8 604
jamesadevine 0:e1a608bb55e8 605 This function assigns the given value to the Floating Point Status/Control register.
jamesadevine 0:e1a608bb55e8 606
jamesadevine 0:e1a608bb55e8 607 \param [in] fpscr Floating Point Status/Control value to set
jamesadevine 0:e1a608bb55e8 608 */
jamesadevine 0:e1a608bb55e8 609 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
jamesadevine 0:e1a608bb55e8 610 {
jamesadevine 0:e1a608bb55e8 611 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jamesadevine 0:e1a608bb55e8 612 /* Empty asm statement works as a scheduling barrier */
jamesadevine 0:e1a608bb55e8 613 __ASM volatile ("");
jamesadevine 0:e1a608bb55e8 614 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
jamesadevine 0:e1a608bb55e8 615 __ASM volatile ("");
jamesadevine 0:e1a608bb55e8 616 #endif
jamesadevine 0:e1a608bb55e8 617 }
jamesadevine 0:e1a608bb55e8 618
jamesadevine 0:e1a608bb55e8 619 #endif /* (__CORTEX_M == 0x04) */
jamesadevine 0:e1a608bb55e8 620
jamesadevine 0:e1a608bb55e8 621
jamesadevine 0:e1a608bb55e8 622 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
jamesadevine 0:e1a608bb55e8 623 /* TASKING carm specific functions */
jamesadevine 0:e1a608bb55e8 624
jamesadevine 0:e1a608bb55e8 625 /*
jamesadevine 0:e1a608bb55e8 626 * The CMSIS functions have been implemented as intrinsics in the compiler.
jamesadevine 0:e1a608bb55e8 627 * Please use "carm -?i" to get an up to date list of all instrinsics,
jamesadevine 0:e1a608bb55e8 628 * Including the CMSIS ones.
jamesadevine 0:e1a608bb55e8 629 */
jamesadevine 0:e1a608bb55e8 630
jamesadevine 0:e1a608bb55e8 631 #endif
jamesadevine 0:e1a608bb55e8 632
jamesadevine 0:e1a608bb55e8 633 /*@} end of CMSIS_Core_RegAccFunctions */
jamesadevine 0:e1a608bb55e8 634
jamesadevine 0:e1a608bb55e8 635
jamesadevine 0:e1a608bb55e8 636 #endif /* __CORE_CMFUNC_H */