Lancaster University / mbed-dev-bin

Binary version of Lancaster University's mbed branch, soon to be merged. The source lives here:https://developer.mbed.org/teams/Lancaster-University/code/mbed-src/

Dependents:   microbit-dal microbit-ble-open microbit-dal-eddystone microbit-dal ... more

Fork of mbed-lite-test by Lancaster University

TARGET_NRF51_MICROBIT/core_cm3.h@3:768173a57492, 2016-07-13 (annotated)

Committer:
jamesadevine
Date:
Wed Jul 13 15:12:06 2016 +0100
Revision:
3:768173a57492
Parent:
0:e1a608bb55e8 
further updates to mbed-dev-bin

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jamesadevine 0:e1a608bb55e8 1 /**************************************************************************//**
jamesadevine 0:e1a608bb55e8 2 * @file core_cm3.h
jamesadevine 0:e1a608bb55e8 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
jamesadevine 0:e1a608bb55e8 4 * @version V3.20
jamesadevine 0:e1a608bb55e8 5 * @date 25. February 2013
jamesadevine 0:e1a608bb55e8 6 *
jamesadevine 0:e1a608bb55e8 7 * @note
jamesadevine 0:e1a608bb55e8 8 *
jamesadevine 0:e1a608bb55e8 9 ******************************************************************************/
jamesadevine 0:e1a608bb55e8 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
jamesadevine 0:e1a608bb55e8 11
jamesadevine 0:e1a608bb55e8 12 All rights reserved.
jamesadevine 0:e1a608bb55e8 13 Redistribution and use in source and binary forms, with or without
jamesadevine 0:e1a608bb55e8 14 modification, are permitted provided that the following conditions are met:
jamesadevine 0:e1a608bb55e8 15 - Redistributions of source code must retain the above copyright
jamesadevine 0:e1a608bb55e8 16 notice, this list of conditions and the following disclaimer.
jamesadevine 0:e1a608bb55e8 17 - Redistributions in binary form must reproduce the above copyright
jamesadevine 0:e1a608bb55e8 18 notice, this list of conditions and the following disclaimer in the
jamesadevine 0:e1a608bb55e8 19 documentation and/or other materials provided with the distribution.
jamesadevine 0:e1a608bb55e8 20 - Neither the name of ARM nor the names of its contributors may be used
jamesadevine 0:e1a608bb55e8 21 to endorse or promote products derived from this software without
jamesadevine 0:e1a608bb55e8 22 specific prior written permission.
jamesadevine 0:e1a608bb55e8 23 *
jamesadevine 0:e1a608bb55e8 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jamesadevine 0:e1a608bb55e8 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jamesadevine 0:e1a608bb55e8 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
jamesadevine 0:e1a608bb55e8 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
jamesadevine 0:e1a608bb55e8 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
jamesadevine 0:e1a608bb55e8 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
jamesadevine 0:e1a608bb55e8 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
jamesadevine 0:e1a608bb55e8 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
jamesadevine 0:e1a608bb55e8 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
jamesadevine 0:e1a608bb55e8 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
jamesadevine 0:e1a608bb55e8 34 POSSIBILITY OF SUCH DAMAGE.
jamesadevine 0:e1a608bb55e8 35 ---------------------------------------------------------------------------*/
jamesadevine 0:e1a608bb55e8 36
jamesadevine 0:e1a608bb55e8 37
jamesadevine 0:e1a608bb55e8 38 #if defined ( __ICCARM__ )
jamesadevine 0:e1a608bb55e8 39 #pragma system_include /* treat file as system include file for MISRA check */
jamesadevine 0:e1a608bb55e8 40 #endif
jamesadevine 0:e1a608bb55e8 41
jamesadevine 0:e1a608bb55e8 42 #ifdef __cplusplus
jamesadevine 0:e1a608bb55e8 43 extern "C" {
jamesadevine 0:e1a608bb55e8 44 #endif
jamesadevine 0:e1a608bb55e8 45
jamesadevine 0:e1a608bb55e8 46 #ifndef __CORE_CM3_H_GENERIC
jamesadevine 0:e1a608bb55e8 47 #define __CORE_CM3_H_GENERIC
jamesadevine 0:e1a608bb55e8 48
jamesadevine 0:e1a608bb55e8 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
jamesadevine 0:e1a608bb55e8 50 CMSIS violates the following MISRA-C:2004 rules:
jamesadevine 0:e1a608bb55e8 51
jamesadevine 0:e1a608bb55e8 52 \li Required Rule 8.5, object/function definition in header file.<br>
jamesadevine 0:e1a608bb55e8 53 Function definitions in header files are used to allow 'inlining'.
jamesadevine 0:e1a608bb55e8 54
jamesadevine 0:e1a608bb55e8 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
jamesadevine 0:e1a608bb55e8 56 Unions are used for effective representation of core registers.
jamesadevine 0:e1a608bb55e8 57
jamesadevine 0:e1a608bb55e8 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
jamesadevine 0:e1a608bb55e8 59 Function-like macros are used to allow more efficient code.
jamesadevine 0:e1a608bb55e8 60 */
jamesadevine 0:e1a608bb55e8 61
jamesadevine 0:e1a608bb55e8 62
jamesadevine 0:e1a608bb55e8 63 /*******************************************************************************
jamesadevine 0:e1a608bb55e8 64 * CMSIS definitions
jamesadevine 0:e1a608bb55e8 65 ******************************************************************************/
jamesadevine 0:e1a608bb55e8 66 /** \ingroup Cortex_M3
jamesadevine 0:e1a608bb55e8 67 @{
jamesadevine 0:e1a608bb55e8 68 */
jamesadevine 0:e1a608bb55e8 69
jamesadevine 0:e1a608bb55e8 70 /* CMSIS CM3 definitions */
jamesadevine 0:e1a608bb55e8 71 #define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
jamesadevine 0:e1a608bb55e8 72 #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
jamesadevine 0:e1a608bb55e8 73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
jamesadevine 0:e1a608bb55e8 74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
jamesadevine 0:e1a608bb55e8 75
jamesadevine 0:e1a608bb55e8 76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
jamesadevine 0:e1a608bb55e8 77
jamesadevine 0:e1a608bb55e8 78
jamesadevine 0:e1a608bb55e8 79 #if defined ( __CC_ARM )
jamesadevine 0:e1a608bb55e8 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
jamesadevine 0:e1a608bb55e8 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
jamesadevine 0:e1a608bb55e8 82 #define __STATIC_INLINE static __inline
jamesadevine 0:e1a608bb55e8 83
jamesadevine 0:e1a608bb55e8 84 #elif defined ( __ICCARM__ )
jamesadevine 0:e1a608bb55e8 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
jamesadevine 0:e1a608bb55e8 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
jamesadevine 0:e1a608bb55e8 87 #define __STATIC_INLINE static inline
jamesadevine 0:e1a608bb55e8 88
jamesadevine 0:e1a608bb55e8 89 #elif defined ( __TMS470__ )
jamesadevine 0:e1a608bb55e8 90 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
jamesadevine 0:e1a608bb55e8 91 #define __STATIC_INLINE static inline
jamesadevine 0:e1a608bb55e8 92
jamesadevine 0:e1a608bb55e8 93 #elif defined ( __GNUC__ )
jamesadevine 0:e1a608bb55e8 94 #define __ASM __asm /*!< asm keyword for GNU Compiler */
jamesadevine 0:e1a608bb55e8 95 #define __INLINE inline /*!< inline keyword for GNU Compiler */
jamesadevine 0:e1a608bb55e8 96 #define __STATIC_INLINE static inline
jamesadevine 0:e1a608bb55e8 97
jamesadevine 0:e1a608bb55e8 98 #elif defined ( __TASKING__ )
jamesadevine 0:e1a608bb55e8 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
jamesadevine 0:e1a608bb55e8 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
jamesadevine 0:e1a608bb55e8 101 #define __STATIC_INLINE static inline
jamesadevine 0:e1a608bb55e8 102
jamesadevine 0:e1a608bb55e8 103 #endif
jamesadevine 0:e1a608bb55e8 104
jamesadevine 0:e1a608bb55e8 105 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
jamesadevine 0:e1a608bb55e8 106 */
jamesadevine 0:e1a608bb55e8 107 #define __FPU_USED 0
jamesadevine 0:e1a608bb55e8 108
jamesadevine 0:e1a608bb55e8 109 #if defined ( __CC_ARM )
jamesadevine 0:e1a608bb55e8 110 #if defined __TARGET_FPU_VFP
jamesadevine 0:e1a608bb55e8 111 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jamesadevine 0:e1a608bb55e8 112 #endif
jamesadevine 0:e1a608bb55e8 113
jamesadevine 0:e1a608bb55e8 114 #elif defined ( __ICCARM__ )
jamesadevine 0:e1a608bb55e8 115 #if defined __ARMVFP__
jamesadevine 0:e1a608bb55e8 116 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jamesadevine 0:e1a608bb55e8 117 #endif
jamesadevine 0:e1a608bb55e8 118
jamesadevine 0:e1a608bb55e8 119 #elif defined ( __TMS470__ )
jamesadevine 0:e1a608bb55e8 120 #if defined __TI__VFP_SUPPORT____
jamesadevine 0:e1a608bb55e8 121 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jamesadevine 0:e1a608bb55e8 122 #endif
jamesadevine 0:e1a608bb55e8 123
jamesadevine 0:e1a608bb55e8 124 #elif defined ( __GNUC__ )
jamesadevine 0:e1a608bb55e8 125 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
jamesadevine 0:e1a608bb55e8 126 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jamesadevine 0:e1a608bb55e8 127 #endif
jamesadevine 0:e1a608bb55e8 128
jamesadevine 0:e1a608bb55e8 129 #elif defined ( __TASKING__ )
jamesadevine 0:e1a608bb55e8 130 #if defined __FPU_VFP__
jamesadevine 0:e1a608bb55e8 131 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jamesadevine 0:e1a608bb55e8 132 #endif
jamesadevine 0:e1a608bb55e8 133 #endif
jamesadevine 0:e1a608bb55e8 134
jamesadevine 0:e1a608bb55e8 135 #include <stdint.h> /* standard types definitions */
jamesadevine 0:e1a608bb55e8 136 #include <core_cmInstr.h> /* Core Instruction Access */
jamesadevine 0:e1a608bb55e8 137 #include <core_cmFunc.h> /* Core Function Access */
jamesadevine 0:e1a608bb55e8 138
jamesadevine 0:e1a608bb55e8 139 #endif /* __CORE_CM3_H_GENERIC */
jamesadevine 0:e1a608bb55e8 140
jamesadevine 0:e1a608bb55e8 141 #ifndef __CMSIS_GENERIC
jamesadevine 0:e1a608bb55e8 142
jamesadevine 0:e1a608bb55e8 143 #ifndef __CORE_CM3_H_DEPENDANT
jamesadevine 0:e1a608bb55e8 144 #define __CORE_CM3_H_DEPENDANT
jamesadevine 0:e1a608bb55e8 145
jamesadevine 0:e1a608bb55e8 146 /* check device defines and use defaults */
jamesadevine 0:e1a608bb55e8 147 #if defined __CHECK_DEVICE_DEFINES
jamesadevine 0:e1a608bb55e8 148 #ifndef __CM3_REV
jamesadevine 0:e1a608bb55e8 149 #define __CM3_REV 0x0200
jamesadevine 0:e1a608bb55e8 150 #warning "__CM3_REV not defined in device header file; using default!"
jamesadevine 0:e1a608bb55e8 151 #endif
jamesadevine 0:e1a608bb55e8 152
jamesadevine 0:e1a608bb55e8 153 #ifndef __MPU_PRESENT
jamesadevine 0:e1a608bb55e8 154 #define __MPU_PRESENT 0
jamesadevine 0:e1a608bb55e8 155 #warning "__MPU_PRESENT not defined in device header file; using default!"
jamesadevine 0:e1a608bb55e8 156 #endif
jamesadevine 0:e1a608bb55e8 157
jamesadevine 0:e1a608bb55e8 158 #ifndef __NVIC_PRIO_BITS
jamesadevine 0:e1a608bb55e8 159 #define __NVIC_PRIO_BITS 4
jamesadevine 0:e1a608bb55e8 160 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
jamesadevine 0:e1a608bb55e8 161 #endif
jamesadevine 0:e1a608bb55e8 162
jamesadevine 0:e1a608bb55e8 163 #ifndef __Vendor_SysTickConfig
jamesadevine 0:e1a608bb55e8 164 #define __Vendor_SysTickConfig 0
jamesadevine 0:e1a608bb55e8 165 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
jamesadevine 0:e1a608bb55e8 166 #endif
jamesadevine 0:e1a608bb55e8 167 #endif
jamesadevine 0:e1a608bb55e8 168
jamesadevine 0:e1a608bb55e8 169 /* IO definitions (access restrictions to peripheral registers) */
jamesadevine 0:e1a608bb55e8 170 /**
jamesadevine 0:e1a608bb55e8 171 \defgroup CMSIS_glob_defs CMSIS Global Defines
jamesadevine 0:e1a608bb55e8 172
jamesadevine 0:e1a608bb55e8 173 <strong>IO Type Qualifiers</strong> are used
jamesadevine 0:e1a608bb55e8 174 \li to specify the access to peripheral variables.
jamesadevine 0:e1a608bb55e8 175 \li for automatic generation of peripheral register debug information.
jamesadevine 0:e1a608bb55e8 176 */
jamesadevine 0:e1a608bb55e8 177 #ifdef __cplusplus
jamesadevine 0:e1a608bb55e8 178 #define __I volatile /*!< Defines 'read only' permissions */
jamesadevine 0:e1a608bb55e8 179 #else
jamesadevine 0:e1a608bb55e8 180 #define __I volatile const /*!< Defines 'read only' permissions */
jamesadevine 0:e1a608bb55e8 181 #endif
jamesadevine 0:e1a608bb55e8 182 #define __O volatile /*!< Defines 'write only' permissions */
jamesadevine 0:e1a608bb55e8 183 #define __IO volatile /*!< Defines 'read / write' permissions */
jamesadevine 0:e1a608bb55e8 184
jamesadevine 0:e1a608bb55e8 185 /*@} end of group Cortex_M3 */
jamesadevine 0:e1a608bb55e8 186
jamesadevine 0:e1a608bb55e8 187
jamesadevine 0:e1a608bb55e8 188
jamesadevine 0:e1a608bb55e8 189 /*******************************************************************************
jamesadevine 0:e1a608bb55e8 190 * Register Abstraction
jamesadevine 0:e1a608bb55e8 191 Core Register contain:
jamesadevine 0:e1a608bb55e8 192 - Core Register
jamesadevine 0:e1a608bb55e8 193 - Core NVIC Register
jamesadevine 0:e1a608bb55e8 194 - Core SCB Register
jamesadevine 0:e1a608bb55e8 195 - Core SysTick Register
jamesadevine 0:e1a608bb55e8 196 - Core Debug Register
jamesadevine 0:e1a608bb55e8 197 - Core MPU Register
jamesadevine 0:e1a608bb55e8 198 ******************************************************************************/
jamesadevine 0:e1a608bb55e8 199 /** \defgroup CMSIS_core_register Defines and Type Definitions
jamesadevine 0:e1a608bb55e8 200 \brief Type definitions and defines for Cortex-M processor based devices.
jamesadevine 0:e1a608bb55e8 201 */
jamesadevine 0:e1a608bb55e8 202
jamesadevine 0:e1a608bb55e8 203 /** \ingroup CMSIS_core_register
jamesadevine 0:e1a608bb55e8 204 \defgroup CMSIS_CORE Status and Control Registers
jamesadevine 0:e1a608bb55e8 205 \brief Core Register type definitions.
jamesadevine 0:e1a608bb55e8 206 @{
jamesadevine 0:e1a608bb55e8 207 */
jamesadevine 0:e1a608bb55e8 208
jamesadevine 0:e1a608bb55e8 209 /** \brief Union type to access the Application Program Status Register (APSR).
jamesadevine 0:e1a608bb55e8 210 */
jamesadevine 0:e1a608bb55e8 211 typedef union
jamesadevine 0:e1a608bb55e8 212 {
jamesadevine 0:e1a608bb55e8 213 struct
jamesadevine 0:e1a608bb55e8 214 {
jamesadevine 0:e1a608bb55e8 215 #if (__CORTEX_M != 0x04)
jamesadevine 0:e1a608bb55e8 216 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
jamesadevine 0:e1a608bb55e8 217 #else
jamesadevine 0:e1a608bb55e8 218 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
jamesadevine 0:e1a608bb55e8 219 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
jamesadevine 0:e1a608bb55e8 220 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
jamesadevine 0:e1a608bb55e8 221 #endif
jamesadevine 0:e1a608bb55e8 222 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
jamesadevine 0:e1a608bb55e8 223 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
jamesadevine 0:e1a608bb55e8 224 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
jamesadevine 0:e1a608bb55e8 225 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
jamesadevine 0:e1a608bb55e8 226 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
jamesadevine 0:e1a608bb55e8 227 } b; /*!< Structure used for bit access */
jamesadevine 0:e1a608bb55e8 228 uint32_t w; /*!< Type used for word access */
jamesadevine 0:e1a608bb55e8 229 } APSR_Type;
jamesadevine 0:e1a608bb55e8 230
jamesadevine 0:e1a608bb55e8 231
jamesadevine 0:e1a608bb55e8 232 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
jamesadevine 0:e1a608bb55e8 233 */
jamesadevine 0:e1a608bb55e8 234 typedef union
jamesadevine 0:e1a608bb55e8 235 {
jamesadevine 0:e1a608bb55e8 236 struct
jamesadevine 0:e1a608bb55e8 237 {
jamesadevine 0:e1a608bb55e8 238 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
jamesadevine 0:e1a608bb55e8 239 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
jamesadevine 0:e1a608bb55e8 240 } b; /*!< Structure used for bit access */
jamesadevine 0:e1a608bb55e8 241 uint32_t w; /*!< Type used for word access */
jamesadevine 0:e1a608bb55e8 242 } IPSR_Type;
jamesadevine 0:e1a608bb55e8 243
jamesadevine 0:e1a608bb55e8 244
jamesadevine 0:e1a608bb55e8 245 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
jamesadevine 0:e1a608bb55e8 246 */
jamesadevine 0:e1a608bb55e8 247 typedef union
jamesadevine 0:e1a608bb55e8 248 {
jamesadevine 0:e1a608bb55e8 249 struct
jamesadevine 0:e1a608bb55e8 250 {
jamesadevine 0:e1a608bb55e8 251 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
jamesadevine 0:e1a608bb55e8 252 #if (__CORTEX_M != 0x04)
jamesadevine 0:e1a608bb55e8 253 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
jamesadevine 0:e1a608bb55e8 254 #else
jamesadevine 0:e1a608bb55e8 255 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
jamesadevine 0:e1a608bb55e8 256 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
jamesadevine 0:e1a608bb55e8 257 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
jamesadevine 0:e1a608bb55e8 258 #endif
jamesadevine 0:e1a608bb55e8 259 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
jamesadevine 0:e1a608bb55e8 260 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
jamesadevine 0:e1a608bb55e8 261 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
jamesadevine 0:e1a608bb55e8 262 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
jamesadevine 0:e1a608bb55e8 263 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
jamesadevine 0:e1a608bb55e8 264 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
jamesadevine 0:e1a608bb55e8 265 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
jamesadevine 0:e1a608bb55e8 266 } b; /*!< Structure used for bit access */
jamesadevine 0:e1a608bb55e8 267 uint32_t w; /*!< Type used for word access */
jamesadevine 0:e1a608bb55e8 268 } xPSR_Type;
jamesadevine 0:e1a608bb55e8 269
jamesadevine 0:e1a608bb55e8 270
jamesadevine 0:e1a608bb55e8 271 /** \brief Union type to access the Control Registers (CONTROL).
jamesadevine 0:e1a608bb55e8 272 */
jamesadevine 0:e1a608bb55e8 273 typedef union
jamesadevine 0:e1a608bb55e8 274 {
jamesadevine 0:e1a608bb55e8 275 struct
jamesadevine 0:e1a608bb55e8 276 {
jamesadevine 0:e1a608bb55e8 277 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
jamesadevine 0:e1a608bb55e8 278 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
jamesadevine 0:e1a608bb55e8 279 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
jamesadevine 0:e1a608bb55e8 280 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
jamesadevine 0:e1a608bb55e8 281 } b; /*!< Structure used for bit access */
jamesadevine 0:e1a608bb55e8 282 uint32_t w; /*!< Type used for word access */
jamesadevine 0:e1a608bb55e8 283 } CONTROL_Type;
jamesadevine 0:e1a608bb55e8 284
jamesadevine 0:e1a608bb55e8 285 /*@} end of group CMSIS_CORE */
jamesadevine 0:e1a608bb55e8 286
jamesadevine 0:e1a608bb55e8 287
jamesadevine 0:e1a608bb55e8 288 /** \ingroup CMSIS_core_register
jamesadevine 0:e1a608bb55e8 289 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
jamesadevine 0:e1a608bb55e8 290 \brief Type definitions for the NVIC Registers
jamesadevine 0:e1a608bb55e8 291 @{
jamesadevine 0:e1a608bb55e8 292 */
jamesadevine 0:e1a608bb55e8 293
jamesadevine 0:e1a608bb55e8 294 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
jamesadevine 0:e1a608bb55e8 295 */
jamesadevine 0:e1a608bb55e8 296 typedef struct
jamesadevine 0:e1a608bb55e8 297 {
jamesadevine 0:e1a608bb55e8 298 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
jamesadevine 0:e1a608bb55e8 299 uint32_t RESERVED0[24];
jamesadevine 0:e1a608bb55e8 300 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
jamesadevine 0:e1a608bb55e8 301 uint32_t RSERVED1[24];
jamesadevine 0:e1a608bb55e8 302 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
jamesadevine 0:e1a608bb55e8 303 uint32_t RESERVED2[24];
jamesadevine 0:e1a608bb55e8 304 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
jamesadevine 0:e1a608bb55e8 305 uint32_t RESERVED3[24];
jamesadevine 0:e1a608bb55e8 306 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
jamesadevine 0:e1a608bb55e8 307 uint32_t RESERVED4[56];
jamesadevine 0:e1a608bb55e8 308 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
jamesadevine 0:e1a608bb55e8 309 uint32_t RESERVED5[644];
jamesadevine 0:e1a608bb55e8 310 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
jamesadevine 0:e1a608bb55e8 311 } NVIC_Type;
jamesadevine 0:e1a608bb55e8 312
jamesadevine 0:e1a608bb55e8 313 /* Software Triggered Interrupt Register Definitions */
jamesadevine 0:e1a608bb55e8 314 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
jamesadevine 0:e1a608bb55e8 315 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
jamesadevine 0:e1a608bb55e8 316
jamesadevine 0:e1a608bb55e8 317 /*@} end of group CMSIS_NVIC */
jamesadevine 0:e1a608bb55e8 318
jamesadevine 0:e1a608bb55e8 319
jamesadevine 0:e1a608bb55e8 320 /** \ingroup CMSIS_core_register
jamesadevine 0:e1a608bb55e8 321 \defgroup CMSIS_SCB System Control Block (SCB)
jamesadevine 0:e1a608bb55e8 322 \brief Type definitions for the System Control Block Registers
jamesadevine 0:e1a608bb55e8 323 @{
jamesadevine 0:e1a608bb55e8 324 */
jamesadevine 0:e1a608bb55e8 325
jamesadevine 0:e1a608bb55e8 326 /** \brief Structure type to access the System Control Block (SCB).
jamesadevine 0:e1a608bb55e8 327 */
jamesadevine 0:e1a608bb55e8 328 typedef struct
jamesadevine 0:e1a608bb55e8 329 {
jamesadevine 0:e1a608bb55e8 330 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
jamesadevine 0:e1a608bb55e8 331 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
jamesadevine 0:e1a608bb55e8 332 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
jamesadevine 0:e1a608bb55e8 333 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
jamesadevine 0:e1a608bb55e8 334 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
jamesadevine 0:e1a608bb55e8 335 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
jamesadevine 0:e1a608bb55e8 336 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
jamesadevine 0:e1a608bb55e8 337 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
jamesadevine 0:e1a608bb55e8 338 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
jamesadevine 0:e1a608bb55e8 339 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
jamesadevine 0:e1a608bb55e8 340 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
jamesadevine 0:e1a608bb55e8 341 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
jamesadevine 0:e1a608bb55e8 342 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
jamesadevine 0:e1a608bb55e8 343 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
jamesadevine 0:e1a608bb55e8 344 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
jamesadevine 0:e1a608bb55e8 345 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
jamesadevine 0:e1a608bb55e8 346 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
jamesadevine 0:e1a608bb55e8 347 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
jamesadevine 0:e1a608bb55e8 348 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
jamesadevine 0:e1a608bb55e8 349 uint32_t RESERVED0[5];
jamesadevine 0:e1a608bb55e8 350 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
jamesadevine 0:e1a608bb55e8 351 } SCB_Type;
jamesadevine 0:e1a608bb55e8 352
jamesadevine 0:e1a608bb55e8 353 /* SCB CPUID Register Definitions */
jamesadevine 0:e1a608bb55e8 354 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
jamesadevine 0:e1a608bb55e8 355 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
jamesadevine 0:e1a608bb55e8 356
jamesadevine 0:e1a608bb55e8 357 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
jamesadevine 0:e1a608bb55e8 358 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
jamesadevine 0:e1a608bb55e8 359
jamesadevine 0:e1a608bb55e8 360 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
jamesadevine 0:e1a608bb55e8 361 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
jamesadevine 0:e1a608bb55e8 362
jamesadevine 0:e1a608bb55e8 363 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
jamesadevine 0:e1a608bb55e8 364 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
jamesadevine 0:e1a608bb55e8 365
jamesadevine 0:e1a608bb55e8 366 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
jamesadevine 0:e1a608bb55e8 367 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
jamesadevine 0:e1a608bb55e8 368
jamesadevine 0:e1a608bb55e8 369 /* SCB Interrupt Control State Register Definitions */
jamesadevine 0:e1a608bb55e8 370 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
jamesadevine 0:e1a608bb55e8 371 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
jamesadevine 0:e1a608bb55e8 372
jamesadevine 0:e1a608bb55e8 373 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
jamesadevine 0:e1a608bb55e8 374 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
jamesadevine 0:e1a608bb55e8 375
jamesadevine 0:e1a608bb55e8 376 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
jamesadevine 0:e1a608bb55e8 377 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
jamesadevine 0:e1a608bb55e8 378
jamesadevine 0:e1a608bb55e8 379 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
jamesadevine 0:e1a608bb55e8 380 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
jamesadevine 0:e1a608bb55e8 381
jamesadevine 0:e1a608bb55e8 382 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
jamesadevine 0:e1a608bb55e8 383 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
jamesadevine 0:e1a608bb55e8 384
jamesadevine 0:e1a608bb55e8 385 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
jamesadevine 0:e1a608bb55e8 386 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
jamesadevine 0:e1a608bb55e8 387
jamesadevine 0:e1a608bb55e8 388 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
jamesadevine 0:e1a608bb55e8 389 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
jamesadevine 0:e1a608bb55e8 390
jamesadevine 0:e1a608bb55e8 391 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
jamesadevine 0:e1a608bb55e8 392 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
jamesadevine 0:e1a608bb55e8 393
jamesadevine 0:e1a608bb55e8 394 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
jamesadevine 0:e1a608bb55e8 395 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
jamesadevine 0:e1a608bb55e8 396
jamesadevine 0:e1a608bb55e8 397 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
jamesadevine 0:e1a608bb55e8 398 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
jamesadevine 0:e1a608bb55e8 399
jamesadevine 0:e1a608bb55e8 400 /* SCB Vector Table Offset Register Definitions */
jamesadevine 0:e1a608bb55e8 401 #if (__CM3_REV < 0x0201) /* core r2p1 */
jamesadevine 0:e1a608bb55e8 402 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
jamesadevine 0:e1a608bb55e8 403 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
jamesadevine 0:e1a608bb55e8 404
jamesadevine 0:e1a608bb55e8 405 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
jamesadevine 0:e1a608bb55e8 406 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
jamesadevine 0:e1a608bb55e8 407 #else
jamesadevine 0:e1a608bb55e8 408 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
jamesadevine 0:e1a608bb55e8 409 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
jamesadevine 0:e1a608bb55e8 410 #endif
jamesadevine 0:e1a608bb55e8 411
jamesadevine 0:e1a608bb55e8 412 /* SCB Application Interrupt and Reset Control Register Definitions */
jamesadevine 0:e1a608bb55e8 413 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
jamesadevine 0:e1a608bb55e8 414 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
jamesadevine 0:e1a608bb55e8 415
jamesadevine 0:e1a608bb55e8 416 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
jamesadevine 0:e1a608bb55e8 417 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
jamesadevine 0:e1a608bb55e8 418
jamesadevine 0:e1a608bb55e8 419 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
jamesadevine 0:e1a608bb55e8 420 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
jamesadevine 0:e1a608bb55e8 421
jamesadevine 0:e1a608bb55e8 422 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
jamesadevine 0:e1a608bb55e8 423 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
jamesadevine 0:e1a608bb55e8 424
jamesadevine 0:e1a608bb55e8 425 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
jamesadevine 0:e1a608bb55e8 426 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
jamesadevine 0:e1a608bb55e8 427
jamesadevine 0:e1a608bb55e8 428 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
jamesadevine 0:e1a608bb55e8 429 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
jamesadevine 0:e1a608bb55e8 430
jamesadevine 0:e1a608bb55e8 431 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
jamesadevine 0:e1a608bb55e8 432 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
jamesadevine 0:e1a608bb55e8 433
jamesadevine 0:e1a608bb55e8 434 /* SCB System Control Register Definitions */
jamesadevine 0:e1a608bb55e8 435 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
jamesadevine 0:e1a608bb55e8 436 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
jamesadevine 0:e1a608bb55e8 437
jamesadevine 0:e1a608bb55e8 438 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
jamesadevine 0:e1a608bb55e8 439 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
jamesadevine 0:e1a608bb55e8 440
jamesadevine 0:e1a608bb55e8 441 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
jamesadevine 0:e1a608bb55e8 442 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
jamesadevine 0:e1a608bb55e8 443
jamesadevine 0:e1a608bb55e8 444 /* SCB Configuration Control Register Definitions */
jamesadevine 0:e1a608bb55e8 445 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
jamesadevine 0:e1a608bb55e8 446 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
jamesadevine 0:e1a608bb55e8 447
jamesadevine 0:e1a608bb55e8 448 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
jamesadevine 0:e1a608bb55e8 449 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
jamesadevine 0:e1a608bb55e8 450
jamesadevine 0:e1a608bb55e8 451 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
jamesadevine 0:e1a608bb55e8 452 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
jamesadevine 0:e1a608bb55e8 453
jamesadevine 0:e1a608bb55e8 454 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
jamesadevine 0:e1a608bb55e8 455 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
jamesadevine 0:e1a608bb55e8 456
jamesadevine 0:e1a608bb55e8 457 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
jamesadevine 0:e1a608bb55e8 458 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
jamesadevine 0:e1a608bb55e8 459
jamesadevine 0:e1a608bb55e8 460 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
jamesadevine 0:e1a608bb55e8 461 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
jamesadevine 0:e1a608bb55e8 462
jamesadevine 0:e1a608bb55e8 463 /* SCB System Handler Control and State Register Definitions */
jamesadevine 0:e1a608bb55e8 464 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
jamesadevine 0:e1a608bb55e8 465 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
jamesadevine 0:e1a608bb55e8 466
jamesadevine 0:e1a608bb55e8 467 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
jamesadevine 0:e1a608bb55e8 468 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
jamesadevine 0:e1a608bb55e8 469
jamesadevine 0:e1a608bb55e8 470 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
jamesadevine 0:e1a608bb55e8 471 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
jamesadevine 0:e1a608bb55e8 472
jamesadevine 0:e1a608bb55e8 473 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
jamesadevine 0:e1a608bb55e8 474 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
jamesadevine 0:e1a608bb55e8 475
jamesadevine 0:e1a608bb55e8 476 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
jamesadevine 0:e1a608bb55e8 477 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
jamesadevine 0:e1a608bb55e8 478
jamesadevine 0:e1a608bb55e8 479 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
jamesadevine 0:e1a608bb55e8 480 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
jamesadevine 0:e1a608bb55e8 481
jamesadevine 0:e1a608bb55e8 482 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
jamesadevine 0:e1a608bb55e8 483 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
jamesadevine 0:e1a608bb55e8 484
jamesadevine 0:e1a608bb55e8 485 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
jamesadevine 0:e1a608bb55e8 486 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
jamesadevine 0:e1a608bb55e8 487
jamesadevine 0:e1a608bb55e8 488 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
jamesadevine 0:e1a608bb55e8 489 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
jamesadevine 0:e1a608bb55e8 490
jamesadevine 0:e1a608bb55e8 491 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
jamesadevine 0:e1a608bb55e8 492 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
jamesadevine 0:e1a608bb55e8 493
jamesadevine 0:e1a608bb55e8 494 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
jamesadevine 0:e1a608bb55e8 495 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
jamesadevine 0:e1a608bb55e8 496
jamesadevine 0:e1a608bb55e8 497 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
jamesadevine 0:e1a608bb55e8 498 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
jamesadevine 0:e1a608bb55e8 499
jamesadevine 0:e1a608bb55e8 500 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
jamesadevine 0:e1a608bb55e8 501 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
jamesadevine 0:e1a608bb55e8 502
jamesadevine 0:e1a608bb55e8 503 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
jamesadevine 0:e1a608bb55e8 504 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
jamesadevine 0:e1a608bb55e8 505
jamesadevine 0:e1a608bb55e8 506 /* SCB Configurable Fault Status Registers Definitions */
jamesadevine 0:e1a608bb55e8 507 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
jamesadevine 0:e1a608bb55e8 508 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
jamesadevine 0:e1a608bb55e8 509
jamesadevine 0:e1a608bb55e8 510 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
jamesadevine 0:e1a608bb55e8 511 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
jamesadevine 0:e1a608bb55e8 512
jamesadevine 0:e1a608bb55e8 513 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
jamesadevine 0:e1a608bb55e8 514 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
jamesadevine 0:e1a608bb55e8 515
jamesadevine 0:e1a608bb55e8 516 /* SCB Hard Fault Status Registers Definitions */
jamesadevine 0:e1a608bb55e8 517 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
jamesadevine 0:e1a608bb55e8 518 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
jamesadevine 0:e1a608bb55e8 519
jamesadevine 0:e1a608bb55e8 520 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
jamesadevine 0:e1a608bb55e8 521 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
jamesadevine 0:e1a608bb55e8 522
jamesadevine 0:e1a608bb55e8 523 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
jamesadevine 0:e1a608bb55e8 524 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
jamesadevine 0:e1a608bb55e8 525
jamesadevine 0:e1a608bb55e8 526 /* SCB Debug Fault Status Register Definitions */
jamesadevine 0:e1a608bb55e8 527 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
jamesadevine 0:e1a608bb55e8 528 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
jamesadevine 0:e1a608bb55e8 529
jamesadevine 0:e1a608bb55e8 530 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
jamesadevine 0:e1a608bb55e8 531 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
jamesadevine 0:e1a608bb55e8 532
jamesadevine 0:e1a608bb55e8 533 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
jamesadevine 0:e1a608bb55e8 534 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
jamesadevine 0:e1a608bb55e8 535
jamesadevine 0:e1a608bb55e8 536 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
jamesadevine 0:e1a608bb55e8 537 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
jamesadevine 0:e1a608bb55e8 538
jamesadevine 0:e1a608bb55e8 539 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
jamesadevine 0:e1a608bb55e8 540 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
jamesadevine 0:e1a608bb55e8 541
jamesadevine 0:e1a608bb55e8 542 /*@} end of group CMSIS_SCB */
jamesadevine 0:e1a608bb55e8 543
jamesadevine 0:e1a608bb55e8 544
jamesadevine 0:e1a608bb55e8 545 /** \ingroup CMSIS_core_register
jamesadevine 0:e1a608bb55e8 546 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
jamesadevine 0:e1a608bb55e8 547 \brief Type definitions for the System Control and ID Register not in the SCB
jamesadevine 0:e1a608bb55e8 548 @{
jamesadevine 0:e1a608bb55e8 549 */
jamesadevine 0:e1a608bb55e8 550
jamesadevine 0:e1a608bb55e8 551 /** \brief Structure type to access the System Control and ID Register not in the SCB.
jamesadevine 0:e1a608bb55e8 552 */
jamesadevine 0:e1a608bb55e8 553 typedef struct
jamesadevine 0:e1a608bb55e8 554 {
jamesadevine 0:e1a608bb55e8 555 uint32_t RESERVED0[1];
jamesadevine 0:e1a608bb55e8 556 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
jamesadevine 0:e1a608bb55e8 557 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
jamesadevine 0:e1a608bb55e8 558 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
jamesadevine 0:e1a608bb55e8 559 #else
jamesadevine 0:e1a608bb55e8 560 uint32_t RESERVED1[1];
jamesadevine 0:e1a608bb55e8 561 #endif
jamesadevine 0:e1a608bb55e8 562 } SCnSCB_Type;
jamesadevine 0:e1a608bb55e8 563
jamesadevine 0:e1a608bb55e8 564 /* Interrupt Controller Type Register Definitions */
jamesadevine 0:e1a608bb55e8 565 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
jamesadevine 0:e1a608bb55e8 566 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
jamesadevine 0:e1a608bb55e8 567
jamesadevine 0:e1a608bb55e8 568 /* Auxiliary Control Register Definitions */
jamesadevine 0:e1a608bb55e8 569
jamesadevine 0:e1a608bb55e8 570 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
jamesadevine 0:e1a608bb55e8 571 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
jamesadevine 0:e1a608bb55e8 572
jamesadevine 0:e1a608bb55e8 573 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
jamesadevine 0:e1a608bb55e8 574 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
jamesadevine 0:e1a608bb55e8 575
jamesadevine 0:e1a608bb55e8 576 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
jamesadevine 0:e1a608bb55e8 577 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
jamesadevine 0:e1a608bb55e8 578
jamesadevine 0:e1a608bb55e8 579 /*@} end of group CMSIS_SCnotSCB */
jamesadevine 0:e1a608bb55e8 580
jamesadevine 0:e1a608bb55e8 581
jamesadevine 0:e1a608bb55e8 582 /** \ingroup CMSIS_core_register
jamesadevine 0:e1a608bb55e8 583 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
jamesadevine 0:e1a608bb55e8 584 \brief Type definitions for the System Timer Registers.
jamesadevine 0:e1a608bb55e8 585 @{
jamesadevine 0:e1a608bb55e8 586 */
jamesadevine 0:e1a608bb55e8 587
jamesadevine 0:e1a608bb55e8 588 /** \brief Structure type to access the System Timer (SysTick).
jamesadevine 0:e1a608bb55e8 589 */
jamesadevine 0:e1a608bb55e8 590 typedef struct
jamesadevine 0:e1a608bb55e8 591 {
jamesadevine 0:e1a608bb55e8 592 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
jamesadevine 0:e1a608bb55e8 593 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
jamesadevine 0:e1a608bb55e8 594 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
jamesadevine 0:e1a608bb55e8 595 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
jamesadevine 0:e1a608bb55e8 596 } SysTick_Type;
jamesadevine 0:e1a608bb55e8 597
jamesadevine 0:e1a608bb55e8 598 /* SysTick Control / Status Register Definitions */
jamesadevine 0:e1a608bb55e8 599 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
jamesadevine 0:e1a608bb55e8 600 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
jamesadevine 0:e1a608bb55e8 601
jamesadevine 0:e1a608bb55e8 602 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
jamesadevine 0:e1a608bb55e8 603 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
jamesadevine 0:e1a608bb55e8 604
jamesadevine 0:e1a608bb55e8 605 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
jamesadevine 0:e1a608bb55e8 606 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
jamesadevine 0:e1a608bb55e8 607
jamesadevine 0:e1a608bb55e8 608 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
jamesadevine 0:e1a608bb55e8 609 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
jamesadevine 0:e1a608bb55e8 610
jamesadevine 0:e1a608bb55e8 611 /* SysTick Reload Register Definitions */
jamesadevine 0:e1a608bb55e8 612 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
jamesadevine 0:e1a608bb55e8 613 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
jamesadevine 0:e1a608bb55e8 614
jamesadevine 0:e1a608bb55e8 615 /* SysTick Current Register Definitions */
jamesadevine 0:e1a608bb55e8 616 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
jamesadevine 0:e1a608bb55e8 617 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
jamesadevine 0:e1a608bb55e8 618
jamesadevine 0:e1a608bb55e8 619 /* SysTick Calibration Register Definitions */
jamesadevine 0:e1a608bb55e8 620 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
jamesadevine 0:e1a608bb55e8 621 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
jamesadevine 0:e1a608bb55e8 622
jamesadevine 0:e1a608bb55e8 623 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
jamesadevine 0:e1a608bb55e8 624 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
jamesadevine 0:e1a608bb55e8 625
jamesadevine 0:e1a608bb55e8 626 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
jamesadevine 0:e1a608bb55e8 627 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
jamesadevine 0:e1a608bb55e8 628
jamesadevine 0:e1a608bb55e8 629 /*@} end of group CMSIS_SysTick */
jamesadevine 0:e1a608bb55e8 630
jamesadevine 0:e1a608bb55e8 631
jamesadevine 0:e1a608bb55e8 632 /** \ingroup CMSIS_core_register
jamesadevine 0:e1a608bb55e8 633 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
jamesadevine 0:e1a608bb55e8 634 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
jamesadevine 0:e1a608bb55e8 635 @{
jamesadevine 0:e1a608bb55e8 636 */
jamesadevine 0:e1a608bb55e8 637
jamesadevine 0:e1a608bb55e8 638 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
jamesadevine 0:e1a608bb55e8 639 */
jamesadevine 0:e1a608bb55e8 640 typedef struct
jamesadevine 0:e1a608bb55e8 641 {
jamesadevine 0:e1a608bb55e8 642 __O union
jamesadevine 0:e1a608bb55e8 643 {
jamesadevine 0:e1a608bb55e8 644 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
jamesadevine 0:e1a608bb55e8 645 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
jamesadevine 0:e1a608bb55e8 646 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
jamesadevine 0:e1a608bb55e8 647 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
jamesadevine 0:e1a608bb55e8 648 uint32_t RESERVED0[864];
jamesadevine 0:e1a608bb55e8 649 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
jamesadevine 0:e1a608bb55e8 650 uint32_t RESERVED1[15];
jamesadevine 0:e1a608bb55e8 651 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
jamesadevine 0:e1a608bb55e8 652 uint32_t RESERVED2[15];
jamesadevine 0:e1a608bb55e8 653 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
jamesadevine 0:e1a608bb55e8 654 uint32_t RESERVED3[29];
jamesadevine 0:e1a608bb55e8 655 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
jamesadevine 0:e1a608bb55e8 656 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
jamesadevine 0:e1a608bb55e8 657 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
jamesadevine 0:e1a608bb55e8 658 uint32_t RESERVED4[43];
jamesadevine 0:e1a608bb55e8 659 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
jamesadevine 0:e1a608bb55e8 660 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
jamesadevine 0:e1a608bb55e8 661 uint32_t RESERVED5[6];
jamesadevine 0:e1a608bb55e8 662 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
jamesadevine 0:e1a608bb55e8 663 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
jamesadevine 0:e1a608bb55e8 664 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
jamesadevine 0:e1a608bb55e8 665 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
jamesadevine 0:e1a608bb55e8 666 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
jamesadevine 0:e1a608bb55e8 667 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
jamesadevine 0:e1a608bb55e8 668 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
jamesadevine 0:e1a608bb55e8 669 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
jamesadevine 0:e1a608bb55e8 670 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
jamesadevine 0:e1a608bb55e8 671 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
jamesadevine 0:e1a608bb55e8 672 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
jamesadevine 0:e1a608bb55e8 673 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
jamesadevine 0:e1a608bb55e8 674 } ITM_Type;
jamesadevine 0:e1a608bb55e8 675
jamesadevine 0:e1a608bb55e8 676 /* ITM Trace Privilege Register Definitions */
jamesadevine 0:e1a608bb55e8 677 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
jamesadevine 0:e1a608bb55e8 678 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
jamesadevine 0:e1a608bb55e8 679
jamesadevine 0:e1a608bb55e8 680 /* ITM Trace Control Register Definitions */
jamesadevine 0:e1a608bb55e8 681 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
jamesadevine 0:e1a608bb55e8 682 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
jamesadevine 0:e1a608bb55e8 683
jamesadevine 0:e1a608bb55e8 684 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
jamesadevine 0:e1a608bb55e8 685 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
jamesadevine 0:e1a608bb55e8 686
jamesadevine 0:e1a608bb55e8 687 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
jamesadevine 0:e1a608bb55e8 688 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
jamesadevine 0:e1a608bb55e8 689
jamesadevine 0:e1a608bb55e8 690 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
jamesadevine 0:e1a608bb55e8 691 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
jamesadevine 0:e1a608bb55e8 692
jamesadevine 0:e1a608bb55e8 693 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
jamesadevine 0:e1a608bb55e8 694 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
jamesadevine 0:e1a608bb55e8 695
jamesadevine 0:e1a608bb55e8 696 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
jamesadevine 0:e1a608bb55e8 697 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
jamesadevine 0:e1a608bb55e8 698
jamesadevine 0:e1a608bb55e8 699 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
jamesadevine 0:e1a608bb55e8 700 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
jamesadevine 0:e1a608bb55e8 701
jamesadevine 0:e1a608bb55e8 702 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
jamesadevine 0:e1a608bb55e8 703 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
jamesadevine 0:e1a608bb55e8 704
jamesadevine 0:e1a608bb55e8 705 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
jamesadevine 0:e1a608bb55e8 706 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
jamesadevine 0:e1a608bb55e8 707
jamesadevine 0:e1a608bb55e8 708 /* ITM Integration Write Register Definitions */
jamesadevine 0:e1a608bb55e8 709 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
jamesadevine 0:e1a608bb55e8 710 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
jamesadevine 0:e1a608bb55e8 711
jamesadevine 0:e1a608bb55e8 712 /* ITM Integration Read Register Definitions */
jamesadevine 0:e1a608bb55e8 713 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
jamesadevine 0:e1a608bb55e8 714 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
jamesadevine 0:e1a608bb55e8 715
jamesadevine 0:e1a608bb55e8 716 /* ITM Integration Mode Control Register Definitions */
jamesadevine 0:e1a608bb55e8 717 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
jamesadevine 0:e1a608bb55e8 718 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
jamesadevine 0:e1a608bb55e8 719
jamesadevine 0:e1a608bb55e8 720 /* ITM Lock Status Register Definitions */
jamesadevine 0:e1a608bb55e8 721 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
jamesadevine 0:e1a608bb55e8 722 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
jamesadevine 0:e1a608bb55e8 723
jamesadevine 0:e1a608bb55e8 724 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
jamesadevine 0:e1a608bb55e8 725 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
jamesadevine 0:e1a608bb55e8 726
jamesadevine 0:e1a608bb55e8 727 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
jamesadevine 0:e1a608bb55e8 728 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
jamesadevine 0:e1a608bb55e8 729
jamesadevine 0:e1a608bb55e8 730 /*@}*/ /* end of group CMSIS_ITM */
jamesadevine 0:e1a608bb55e8 731
jamesadevine 0:e1a608bb55e8 732
jamesadevine 0:e1a608bb55e8 733 /** \ingroup CMSIS_core_register
jamesadevine 0:e1a608bb55e8 734 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
jamesadevine 0:e1a608bb55e8 735 \brief Type definitions for the Data Watchpoint and Trace (DWT)
jamesadevine 0:e1a608bb55e8 736 @{
jamesadevine 0:e1a608bb55e8 737 */
jamesadevine 0:e1a608bb55e8 738
jamesadevine 0:e1a608bb55e8 739 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
jamesadevine 0:e1a608bb55e8 740 */
jamesadevine 0:e1a608bb55e8 741 typedef struct
jamesadevine 0:e1a608bb55e8 742 {
jamesadevine 0:e1a608bb55e8 743 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
jamesadevine 0:e1a608bb55e8 744 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
jamesadevine 0:e1a608bb55e8 745 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
jamesadevine 0:e1a608bb55e8 746 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
jamesadevine 0:e1a608bb55e8 747 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
jamesadevine 0:e1a608bb55e8 748 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
jamesadevine 0:e1a608bb55e8 749 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
jamesadevine 0:e1a608bb55e8 750 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
jamesadevine 0:e1a608bb55e8 751 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
jamesadevine 0:e1a608bb55e8 752 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
jamesadevine 0:e1a608bb55e8 753 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
jamesadevine 0:e1a608bb55e8 754 uint32_t RESERVED0[1];
jamesadevine 0:e1a608bb55e8 755 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
jamesadevine 0:e1a608bb55e8 756 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
jamesadevine 0:e1a608bb55e8 757 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
jamesadevine 0:e1a608bb55e8 758 uint32_t RESERVED1[1];
jamesadevine 0:e1a608bb55e8 759 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
jamesadevine 0:e1a608bb55e8 760 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
jamesadevine 0:e1a608bb55e8 761 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
jamesadevine 0:e1a608bb55e8 762 uint32_t RESERVED2[1];
jamesadevine 0:e1a608bb55e8 763 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
jamesadevine 0:e1a608bb55e8 764 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
jamesadevine 0:e1a608bb55e8 765 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
jamesadevine 0:e1a608bb55e8 766 } DWT_Type;
jamesadevine 0:e1a608bb55e8 767
jamesadevine 0:e1a608bb55e8 768 /* DWT Control Register Definitions */
jamesadevine 0:e1a608bb55e8 769 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
jamesadevine 0:e1a608bb55e8 770 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
jamesadevine 0:e1a608bb55e8 771
jamesadevine 0:e1a608bb55e8 772 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
jamesadevine 0:e1a608bb55e8 773 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
jamesadevine 0:e1a608bb55e8 774
jamesadevine 0:e1a608bb55e8 775 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
jamesadevine 0:e1a608bb55e8 776 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
jamesadevine 0:e1a608bb55e8 777
jamesadevine 0:e1a608bb55e8 778 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
jamesadevine 0:e1a608bb55e8 779 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
jamesadevine 0:e1a608bb55e8 780
jamesadevine 0:e1a608bb55e8 781 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
jamesadevine 0:e1a608bb55e8 782 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
jamesadevine 0:e1a608bb55e8 783
jamesadevine 0:e1a608bb55e8 784 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
jamesadevine 0:e1a608bb55e8 785 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
jamesadevine 0:e1a608bb55e8 786
jamesadevine 0:e1a608bb55e8 787 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
jamesadevine 0:e1a608bb55e8 788 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
jamesadevine 0:e1a608bb55e8 789
jamesadevine 0:e1a608bb55e8 790 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
jamesadevine 0:e1a608bb55e8 791 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
jamesadevine 0:e1a608bb55e8 792
jamesadevine 0:e1a608bb55e8 793 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
jamesadevine 0:e1a608bb55e8 794 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
jamesadevine 0:e1a608bb55e8 795
jamesadevine 0:e1a608bb55e8 796 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
jamesadevine 0:e1a608bb55e8 797 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
jamesadevine 0:e1a608bb55e8 798
jamesadevine 0:e1a608bb55e8 799 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
jamesadevine 0:e1a608bb55e8 800 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
jamesadevine 0:e1a608bb55e8 801
jamesadevine 0:e1a608bb55e8 802 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
jamesadevine 0:e1a608bb55e8 803 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
jamesadevine 0:e1a608bb55e8 804
jamesadevine 0:e1a608bb55e8 805 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
jamesadevine 0:e1a608bb55e8 806 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
jamesadevine 0:e1a608bb55e8 807
jamesadevine 0:e1a608bb55e8 808 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
jamesadevine 0:e1a608bb55e8 809 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
jamesadevine 0:e1a608bb55e8 810
jamesadevine 0:e1a608bb55e8 811 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
jamesadevine 0:e1a608bb55e8 812 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
jamesadevine 0:e1a608bb55e8 813
jamesadevine 0:e1a608bb55e8 814 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
jamesadevine 0:e1a608bb55e8 815 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
jamesadevine 0:e1a608bb55e8 816
jamesadevine 0:e1a608bb55e8 817 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
jamesadevine 0:e1a608bb55e8 818 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
jamesadevine 0:e1a608bb55e8 819
jamesadevine 0:e1a608bb55e8 820 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
jamesadevine 0:e1a608bb55e8 821 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
jamesadevine 0:e1a608bb55e8 822
jamesadevine 0:e1a608bb55e8 823 /* DWT CPI Count Register Definitions */
jamesadevine 0:e1a608bb55e8 824 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
jamesadevine 0:e1a608bb55e8 825 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
jamesadevine 0:e1a608bb55e8 826
jamesadevine 0:e1a608bb55e8 827 /* DWT Exception Overhead Count Register Definitions */
jamesadevine 0:e1a608bb55e8 828 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
jamesadevine 0:e1a608bb55e8 829 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
jamesadevine 0:e1a608bb55e8 830
jamesadevine 0:e1a608bb55e8 831 /* DWT Sleep Count Register Definitions */
jamesadevine 0:e1a608bb55e8 832 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
jamesadevine 0:e1a608bb55e8 833 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
jamesadevine 0:e1a608bb55e8 834
jamesadevine 0:e1a608bb55e8 835 /* DWT LSU Count Register Definitions */
jamesadevine 0:e1a608bb55e8 836 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
jamesadevine 0:e1a608bb55e8 837 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
jamesadevine 0:e1a608bb55e8 838
jamesadevine 0:e1a608bb55e8 839 /* DWT Folded-instruction Count Register Definitions */
jamesadevine 0:e1a608bb55e8 840 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
jamesadevine 0:e1a608bb55e8 841 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
jamesadevine 0:e1a608bb55e8 842
jamesadevine 0:e1a608bb55e8 843 /* DWT Comparator Mask Register Definitions */
jamesadevine 0:e1a608bb55e8 844 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
jamesadevine 0:e1a608bb55e8 845 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
jamesadevine 0:e1a608bb55e8 846
jamesadevine 0:e1a608bb55e8 847 /* DWT Comparator Function Register Definitions */
jamesadevine 0:e1a608bb55e8 848 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
jamesadevine 0:e1a608bb55e8 849 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
jamesadevine 0:e1a608bb55e8 850
jamesadevine 0:e1a608bb55e8 851 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
jamesadevine 0:e1a608bb55e8 852 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
jamesadevine 0:e1a608bb55e8 853
jamesadevine 0:e1a608bb55e8 854 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
jamesadevine 0:e1a608bb55e8 855 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
jamesadevine 0:e1a608bb55e8 856
jamesadevine 0:e1a608bb55e8 857 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
jamesadevine 0:e1a608bb55e8 858 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
jamesadevine 0:e1a608bb55e8 859
jamesadevine 0:e1a608bb55e8 860 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
jamesadevine 0:e1a608bb55e8 861 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
jamesadevine 0:e1a608bb55e8 862
jamesadevine 0:e1a608bb55e8 863 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
jamesadevine 0:e1a608bb55e8 864 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
jamesadevine 0:e1a608bb55e8 865
jamesadevine 0:e1a608bb55e8 866 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
jamesadevine 0:e1a608bb55e8 867 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
jamesadevine 0:e1a608bb55e8 868
jamesadevine 0:e1a608bb55e8 869 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
jamesadevine 0:e1a608bb55e8 870 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
jamesadevine 0:e1a608bb55e8 871
jamesadevine 0:e1a608bb55e8 872 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
jamesadevine 0:e1a608bb55e8 873 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
jamesadevine 0:e1a608bb55e8 874
jamesadevine 0:e1a608bb55e8 875 /*@}*/ /* end of group CMSIS_DWT */
jamesadevine 0:e1a608bb55e8 876
jamesadevine 0:e1a608bb55e8 877
jamesadevine 0:e1a608bb55e8 878 /** \ingroup CMSIS_core_register
jamesadevine 0:e1a608bb55e8 879 \defgroup CMSIS_TPI Trace Port Interface (TPI)
jamesadevine 0:e1a608bb55e8 880 \brief Type definitions for the Trace Port Interface (TPI)
jamesadevine 0:e1a608bb55e8 881 @{
jamesadevine 0:e1a608bb55e8 882 */
jamesadevine 0:e1a608bb55e8 883
jamesadevine 0:e1a608bb55e8 884 /** \brief Structure type to access the Trace Port Interface Register (TPI).
jamesadevine 0:e1a608bb55e8 885 */
jamesadevine 0:e1a608bb55e8 886 typedef struct
jamesadevine 0:e1a608bb55e8 887 {
jamesadevine 0:e1a608bb55e8 888 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
jamesadevine 0:e1a608bb55e8 889 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
jamesadevine 0:e1a608bb55e8 890 uint32_t RESERVED0[2];
jamesadevine 0:e1a608bb55e8 891 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
jamesadevine 0:e1a608bb55e8 892 uint32_t RESERVED1[55];
jamesadevine 0:e1a608bb55e8 893 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
jamesadevine 0:e1a608bb55e8 894 uint32_t RESERVED2[131];
jamesadevine 0:e1a608bb55e8 895 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
jamesadevine 0:e1a608bb55e8 896 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
jamesadevine 0:e1a608bb55e8 897 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
jamesadevine 0:e1a608bb55e8 898 uint32_t RESERVED3[759];
jamesadevine 0:e1a608bb55e8 899 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
jamesadevine 0:e1a608bb55e8 900 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
jamesadevine 0:e1a608bb55e8 901 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
jamesadevine 0:e1a608bb55e8 902 uint32_t RESERVED4[1];
jamesadevine 0:e1a608bb55e8 903 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
jamesadevine 0:e1a608bb55e8 904 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
jamesadevine 0:e1a608bb55e8 905 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
jamesadevine 0:e1a608bb55e8 906 uint32_t RESERVED5[39];
jamesadevine 0:e1a608bb55e8 907 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
jamesadevine 0:e1a608bb55e8 908 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
jamesadevine 0:e1a608bb55e8 909 uint32_t RESERVED7[8];
jamesadevine 0:e1a608bb55e8 910 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
jamesadevine 0:e1a608bb55e8 911 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
jamesadevine 0:e1a608bb55e8 912 } TPI_Type;
jamesadevine 0:e1a608bb55e8 913
jamesadevine 0:e1a608bb55e8 914 /* TPI Asynchronous Clock Prescaler Register Definitions */
jamesadevine 0:e1a608bb55e8 915 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
jamesadevine 0:e1a608bb55e8 916 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
jamesadevine 0:e1a608bb55e8 917
jamesadevine 0:e1a608bb55e8 918 /* TPI Selected Pin Protocol Register Definitions */
jamesadevine 0:e1a608bb55e8 919 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
jamesadevine 0:e1a608bb55e8 920 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
jamesadevine 0:e1a608bb55e8 921
jamesadevine 0:e1a608bb55e8 922 /* TPI Formatter and Flush Status Register Definitions */
jamesadevine 0:e1a608bb55e8 923 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
jamesadevine 0:e1a608bb55e8 924 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
jamesadevine 0:e1a608bb55e8 925
jamesadevine 0:e1a608bb55e8 926 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
jamesadevine 0:e1a608bb55e8 927 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
jamesadevine 0:e1a608bb55e8 928
jamesadevine 0:e1a608bb55e8 929 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
jamesadevine 0:e1a608bb55e8 930 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
jamesadevine 0:e1a608bb55e8 931
jamesadevine 0:e1a608bb55e8 932 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
jamesadevine 0:e1a608bb55e8 933 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
jamesadevine 0:e1a608bb55e8 934
jamesadevine 0:e1a608bb55e8 935 /* TPI Formatter and Flush Control Register Definitions */
jamesadevine 0:e1a608bb55e8 936 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
jamesadevine 0:e1a608bb55e8 937 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
jamesadevine 0:e1a608bb55e8 938
jamesadevine 0:e1a608bb55e8 939 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
jamesadevine 0:e1a608bb55e8 940 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
jamesadevine 0:e1a608bb55e8 941
jamesadevine 0:e1a608bb55e8 942 /* TPI TRIGGER Register Definitions */
jamesadevine 0:e1a608bb55e8 943 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
jamesadevine 0:e1a608bb55e8 944 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
jamesadevine 0:e1a608bb55e8 945
jamesadevine 0:e1a608bb55e8 946 /* TPI Integration ETM Data Register Definitions (FIFO0) */
jamesadevine 0:e1a608bb55e8 947 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
jamesadevine 0:e1a608bb55e8 948 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
jamesadevine 0:e1a608bb55e8 949
jamesadevine 0:e1a608bb55e8 950 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
jamesadevine 0:e1a608bb55e8 951 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
jamesadevine 0:e1a608bb55e8 952
jamesadevine 0:e1a608bb55e8 953 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
jamesadevine 0:e1a608bb55e8 954 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
jamesadevine 0:e1a608bb55e8 955
jamesadevine 0:e1a608bb55e8 956 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
jamesadevine 0:e1a608bb55e8 957 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
jamesadevine 0:e1a608bb55e8 958
jamesadevine 0:e1a608bb55e8 959 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
jamesadevine 0:e1a608bb55e8 960 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
jamesadevine 0:e1a608bb55e8 961
jamesadevine 0:e1a608bb55e8 962 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
jamesadevine 0:e1a608bb55e8 963 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
jamesadevine 0:e1a608bb55e8 964
jamesadevine 0:e1a608bb55e8 965 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
jamesadevine 0:e1a608bb55e8 966 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
jamesadevine 0:e1a608bb55e8 967
jamesadevine 0:e1a608bb55e8 968 /* TPI ITATBCTR2 Register Definitions */
jamesadevine 0:e1a608bb55e8 969 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
jamesadevine 0:e1a608bb55e8 970 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
jamesadevine 0:e1a608bb55e8 971
jamesadevine 0:e1a608bb55e8 972 /* TPI Integration ITM Data Register Definitions (FIFO1) */
jamesadevine 0:e1a608bb55e8 973 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
jamesadevine 0:e1a608bb55e8 974 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
jamesadevine 0:e1a608bb55e8 975
jamesadevine 0:e1a608bb55e8 976 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
jamesadevine 0:e1a608bb55e8 977 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
jamesadevine 0:e1a608bb55e8 978
jamesadevine 0:e1a608bb55e8 979 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
jamesadevine 0:e1a608bb55e8 980 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
jamesadevine 0:e1a608bb55e8 981
jamesadevine 0:e1a608bb55e8 982 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
jamesadevine 0:e1a608bb55e8 983 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
jamesadevine 0:e1a608bb55e8 984
jamesadevine 0:e1a608bb55e8 985 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
jamesadevine 0:e1a608bb55e8 986 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
jamesadevine 0:e1a608bb55e8 987
jamesadevine 0:e1a608bb55e8 988 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
jamesadevine 0:e1a608bb55e8 989 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
jamesadevine 0:e1a608bb55e8 990
jamesadevine 0:e1a608bb55e8 991 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
jamesadevine 0:e1a608bb55e8 992 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
jamesadevine 0:e1a608bb55e8 993
jamesadevine 0:e1a608bb55e8 994 /* TPI ITATBCTR0 Register Definitions */
jamesadevine 0:e1a608bb55e8 995 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
jamesadevine 0:e1a608bb55e8 996 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
jamesadevine 0:e1a608bb55e8 997
jamesadevine 0:e1a608bb55e8 998 /* TPI Integration Mode Control Register Definitions */
jamesadevine 0:e1a608bb55e8 999 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
jamesadevine 0:e1a608bb55e8 1000 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
jamesadevine 0:e1a608bb55e8 1001
jamesadevine 0:e1a608bb55e8 1002 /* TPI DEVID Register Definitions */
jamesadevine 0:e1a608bb55e8 1003 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
jamesadevine 0:e1a608bb55e8 1004 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
jamesadevine 0:e1a608bb55e8 1005
jamesadevine 0:e1a608bb55e8 1006 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
jamesadevine 0:e1a608bb55e8 1007 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
jamesadevine 0:e1a608bb55e8 1008
jamesadevine 0:e1a608bb55e8 1009 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
jamesadevine 0:e1a608bb55e8 1010 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
jamesadevine 0:e1a608bb55e8 1011
jamesadevine 0:e1a608bb55e8 1012 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
jamesadevine 0:e1a608bb55e8 1013 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
jamesadevine 0:e1a608bb55e8 1014
jamesadevine 0:e1a608bb55e8 1015 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
jamesadevine 0:e1a608bb55e8 1016 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
jamesadevine 0:e1a608bb55e8 1017
jamesadevine 0:e1a608bb55e8 1018 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
jamesadevine 0:e1a608bb55e8 1019 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
jamesadevine 0:e1a608bb55e8 1020
jamesadevine 0:e1a608bb55e8 1021 /* TPI DEVTYPE Register Definitions */
jamesadevine 0:e1a608bb55e8 1022 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
jamesadevine 0:e1a608bb55e8 1023 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
jamesadevine 0:e1a608bb55e8 1024
jamesadevine 0:e1a608bb55e8 1025 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
jamesadevine 0:e1a608bb55e8 1026 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
jamesadevine 0:e1a608bb55e8 1027
jamesadevine 0:e1a608bb55e8 1028 /*@}*/ /* end of group CMSIS_TPI */
jamesadevine 0:e1a608bb55e8 1029
jamesadevine 0:e1a608bb55e8 1030
jamesadevine 0:e1a608bb55e8 1031 #if (__MPU_PRESENT == 1)
jamesadevine 0:e1a608bb55e8 1032 /** \ingroup CMSIS_core_register
jamesadevine 0:e1a608bb55e8 1033 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
jamesadevine 0:e1a608bb55e8 1034 \brief Type definitions for the Memory Protection Unit (MPU)
jamesadevine 0:e1a608bb55e8 1035 @{
jamesadevine 0:e1a608bb55e8 1036 */
jamesadevine 0:e1a608bb55e8 1037
jamesadevine 0:e1a608bb55e8 1038 /** \brief Structure type to access the Memory Protection Unit (MPU).
jamesadevine 0:e1a608bb55e8 1039 */
jamesadevine 0:e1a608bb55e8 1040 typedef struct
jamesadevine 0:e1a608bb55e8 1041 {
jamesadevine 0:e1a608bb55e8 1042 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
jamesadevine 0:e1a608bb55e8 1043 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
jamesadevine 0:e1a608bb55e8 1044 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
jamesadevine 0:e1a608bb55e8 1045 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
jamesadevine 0:e1a608bb55e8 1046 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
jamesadevine 0:e1a608bb55e8 1047 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
jamesadevine 0:e1a608bb55e8 1048 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
jamesadevine 0:e1a608bb55e8 1049 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
jamesadevine 0:e1a608bb55e8 1050 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
jamesadevine 0:e1a608bb55e8 1051 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
jamesadevine 0:e1a608bb55e8 1052 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
jamesadevine 0:e1a608bb55e8 1053 } MPU_Type;
jamesadevine 0:e1a608bb55e8 1054
jamesadevine 0:e1a608bb55e8 1055 /* MPU Type Register */
jamesadevine 0:e1a608bb55e8 1056 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
jamesadevine 0:e1a608bb55e8 1057 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
jamesadevine 0:e1a608bb55e8 1058
jamesadevine 0:e1a608bb55e8 1059 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
jamesadevine 0:e1a608bb55e8 1060 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
jamesadevine 0:e1a608bb55e8 1061
jamesadevine 0:e1a608bb55e8 1062 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
jamesadevine 0:e1a608bb55e8 1063 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
jamesadevine 0:e1a608bb55e8 1064
jamesadevine 0:e1a608bb55e8 1065 /* MPU Control Register */
jamesadevine 0:e1a608bb55e8 1066 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
jamesadevine 0:e1a608bb55e8 1067 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
jamesadevine 0:e1a608bb55e8 1068
jamesadevine 0:e1a608bb55e8 1069 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
jamesadevine 0:e1a608bb55e8 1070 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
jamesadevine 0:e1a608bb55e8 1071
jamesadevine 0:e1a608bb55e8 1072 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
jamesadevine 0:e1a608bb55e8 1073 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
jamesadevine 0:e1a608bb55e8 1074
jamesadevine 0:e1a608bb55e8 1075 /* MPU Region Number Register */
jamesadevine 0:e1a608bb55e8 1076 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
jamesadevine 0:e1a608bb55e8 1077 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
jamesadevine 0:e1a608bb55e8 1078
jamesadevine 0:e1a608bb55e8 1079 /* MPU Region Base Address Register */
jamesadevine 0:e1a608bb55e8 1080 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
jamesadevine 0:e1a608bb55e8 1081 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
jamesadevine 0:e1a608bb55e8 1082
jamesadevine 0:e1a608bb55e8 1083 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
jamesadevine 0:e1a608bb55e8 1084 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
jamesadevine 0:e1a608bb55e8 1085
jamesadevine 0:e1a608bb55e8 1086 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
jamesadevine 0:e1a608bb55e8 1087 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
jamesadevine 0:e1a608bb55e8 1088
jamesadevine 0:e1a608bb55e8 1089 /* MPU Region Attribute and Size Register */
jamesadevine 0:e1a608bb55e8 1090 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
jamesadevine 0:e1a608bb55e8 1091 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
jamesadevine 0:e1a608bb55e8 1092
jamesadevine 0:e1a608bb55e8 1093 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
jamesadevine 0:e1a608bb55e8 1094 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
jamesadevine 0:e1a608bb55e8 1095
jamesadevine 0:e1a608bb55e8 1096 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
jamesadevine 0:e1a608bb55e8 1097 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
jamesadevine 0:e1a608bb55e8 1098
jamesadevine 0:e1a608bb55e8 1099 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
jamesadevine 0:e1a608bb55e8 1100 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
jamesadevine 0:e1a608bb55e8 1101
jamesadevine 0:e1a608bb55e8 1102 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
jamesadevine 0:e1a608bb55e8 1103 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
jamesadevine 0:e1a608bb55e8 1104
jamesadevine 0:e1a608bb55e8 1105 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
jamesadevine 0:e1a608bb55e8 1106 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
jamesadevine 0:e1a608bb55e8 1107
jamesadevine 0:e1a608bb55e8 1108 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
jamesadevine 0:e1a608bb55e8 1109 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
jamesadevine 0:e1a608bb55e8 1110
jamesadevine 0:e1a608bb55e8 1111 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
jamesadevine 0:e1a608bb55e8 1112 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
jamesadevine 0:e1a608bb55e8 1113
jamesadevine 0:e1a608bb55e8 1114 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
jamesadevine 0:e1a608bb55e8 1115 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
jamesadevine 0:e1a608bb55e8 1116
jamesadevine 0:e1a608bb55e8 1117 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
jamesadevine 0:e1a608bb55e8 1118 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
jamesadevine 0:e1a608bb55e8 1119
jamesadevine 0:e1a608bb55e8 1120 /*@} end of group CMSIS_MPU */
jamesadevine 0:e1a608bb55e8 1121 #endif
jamesadevine 0:e1a608bb55e8 1122
jamesadevine 0:e1a608bb55e8 1123
jamesadevine 0:e1a608bb55e8 1124 /** \ingroup CMSIS_core_register
jamesadevine 0:e1a608bb55e8 1125 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
jamesadevine 0:e1a608bb55e8 1126 \brief Type definitions for the Core Debug Registers
jamesadevine 0:e1a608bb55e8 1127 @{
jamesadevine 0:e1a608bb55e8 1128 */
jamesadevine 0:e1a608bb55e8 1129
jamesadevine 0:e1a608bb55e8 1130 /** \brief Structure type to access the Core Debug Register (CoreDebug).
jamesadevine 0:e1a608bb55e8 1131 */
jamesadevine 0:e1a608bb55e8 1132 typedef struct
jamesadevine 0:e1a608bb55e8 1133 {
jamesadevine 0:e1a608bb55e8 1134 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
jamesadevine 0:e1a608bb55e8 1135 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
jamesadevine 0:e1a608bb55e8 1136 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
jamesadevine 0:e1a608bb55e8 1137 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
jamesadevine 0:e1a608bb55e8 1138 } CoreDebug_Type;
jamesadevine 0:e1a608bb55e8 1139
jamesadevine 0:e1a608bb55e8 1140 /* Debug Halting Control and Status Register */
jamesadevine 0:e1a608bb55e8 1141 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
jamesadevine 0:e1a608bb55e8 1142 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
jamesadevine 0:e1a608bb55e8 1143
jamesadevine 0:e1a608bb55e8 1144 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
jamesadevine 0:e1a608bb55e8 1145 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
jamesadevine 0:e1a608bb55e8 1146
jamesadevine 0:e1a608bb55e8 1147 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
jamesadevine 0:e1a608bb55e8 1148 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
jamesadevine 0:e1a608bb55e8 1149
jamesadevine 0:e1a608bb55e8 1150 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
jamesadevine 0:e1a608bb55e8 1151 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
jamesadevine 0:e1a608bb55e8 1152
jamesadevine 0:e1a608bb55e8 1153 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
jamesadevine 0:e1a608bb55e8 1154 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
jamesadevine 0:e1a608bb55e8 1155
jamesadevine 0:e1a608bb55e8 1156 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
jamesadevine 0:e1a608bb55e8 1157 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
jamesadevine 0:e1a608bb55e8 1158
jamesadevine 0:e1a608bb55e8 1159 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
jamesadevine 0:e1a608bb55e8 1160 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
jamesadevine 0:e1a608bb55e8 1161
jamesadevine 0:e1a608bb55e8 1162 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
jamesadevine 0:e1a608bb55e8 1163 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
jamesadevine 0:e1a608bb55e8 1164
jamesadevine 0:e1a608bb55e8 1165 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
jamesadevine 0:e1a608bb55e8 1166 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
jamesadevine 0:e1a608bb55e8 1167
jamesadevine 0:e1a608bb55e8 1168 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
jamesadevine 0:e1a608bb55e8 1169 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
jamesadevine 0:e1a608bb55e8 1170
jamesadevine 0:e1a608bb55e8 1171 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
jamesadevine 0:e1a608bb55e8 1172 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
jamesadevine 0:e1a608bb55e8 1173
jamesadevine 0:e1a608bb55e8 1174 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
jamesadevine 0:e1a608bb55e8 1175 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
jamesadevine 0:e1a608bb55e8 1176
jamesadevine 0:e1a608bb55e8 1177 /* Debug Core Register Selector Register */
jamesadevine 0:e1a608bb55e8 1178 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
jamesadevine 0:e1a608bb55e8 1179 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
jamesadevine 0:e1a608bb55e8 1180
jamesadevine 0:e1a608bb55e8 1181 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
jamesadevine 0:e1a608bb55e8 1182 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
jamesadevine 0:e1a608bb55e8 1183
jamesadevine 0:e1a608bb55e8 1184 /* Debug Exception and Monitor Control Register */
jamesadevine 0:e1a608bb55e8 1185 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
jamesadevine 0:e1a608bb55e8 1186 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
jamesadevine 0:e1a608bb55e8 1187
jamesadevine 0:e1a608bb55e8 1188 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
jamesadevine 0:e1a608bb55e8 1189 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
jamesadevine 0:e1a608bb55e8 1190
jamesadevine 0:e1a608bb55e8 1191 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
jamesadevine 0:e1a608bb55e8 1192 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
jamesadevine 0:e1a608bb55e8 1193
jamesadevine 0:e1a608bb55e8 1194 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
jamesadevine 0:e1a608bb55e8 1195 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
jamesadevine 0:e1a608bb55e8 1196
jamesadevine 0:e1a608bb55e8 1197 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
jamesadevine 0:e1a608bb55e8 1198 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
jamesadevine 0:e1a608bb55e8 1199
jamesadevine 0:e1a608bb55e8 1200 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
jamesadevine 0:e1a608bb55e8 1201 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
jamesadevine 0:e1a608bb55e8 1202
jamesadevine 0:e1a608bb55e8 1203 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
jamesadevine 0:e1a608bb55e8 1204 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
jamesadevine 0:e1a608bb55e8 1205
jamesadevine 0:e1a608bb55e8 1206 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
jamesadevine 0:e1a608bb55e8 1207 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
jamesadevine 0:e1a608bb55e8 1208
jamesadevine 0:e1a608bb55e8 1209 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
jamesadevine 0:e1a608bb55e8 1210 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
jamesadevine 0:e1a608bb55e8 1211
jamesadevine 0:e1a608bb55e8 1212 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
jamesadevine 0:e1a608bb55e8 1213 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
jamesadevine 0:e1a608bb55e8 1214
jamesadevine 0:e1a608bb55e8 1215 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
jamesadevine 0:e1a608bb55e8 1216 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
jamesadevine 0:e1a608bb55e8 1217
jamesadevine 0:e1a608bb55e8 1218 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
jamesadevine 0:e1a608bb55e8 1219 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
jamesadevine 0:e1a608bb55e8 1220
jamesadevine 0:e1a608bb55e8 1221 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
jamesadevine 0:e1a608bb55e8 1222 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
jamesadevine 0:e1a608bb55e8 1223
jamesadevine 0:e1a608bb55e8 1224 /*@} end of group CMSIS_CoreDebug */
jamesadevine 0:e1a608bb55e8 1225
jamesadevine 0:e1a608bb55e8 1226
jamesadevine 0:e1a608bb55e8 1227 /** \ingroup CMSIS_core_register
jamesadevine 0:e1a608bb55e8 1228 \defgroup CMSIS_core_base Core Definitions
jamesadevine 0:e1a608bb55e8 1229 \brief Definitions for base addresses, unions, and structures.
jamesadevine 0:e1a608bb55e8 1230 @{
jamesadevine 0:e1a608bb55e8 1231 */
jamesadevine 0:e1a608bb55e8 1232
jamesadevine 0:e1a608bb55e8 1233 /* Memory mapping of Cortex-M3 Hardware */
jamesadevine 0:e1a608bb55e8 1234 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
jamesadevine 0:e1a608bb55e8 1235 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
jamesadevine 0:e1a608bb55e8 1236 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
jamesadevine 0:e1a608bb55e8 1237 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
jamesadevine 0:e1a608bb55e8 1238 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
jamesadevine 0:e1a608bb55e8 1239 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
jamesadevine 0:e1a608bb55e8 1240 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
jamesadevine 0:e1a608bb55e8 1241 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
jamesadevine 0:e1a608bb55e8 1242
jamesadevine 0:e1a608bb55e8 1243 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
jamesadevine 0:e1a608bb55e8 1244 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
jamesadevine 0:e1a608bb55e8 1245 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
jamesadevine 0:e1a608bb55e8 1246 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
jamesadevine 0:e1a608bb55e8 1247 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
jamesadevine 0:e1a608bb55e8 1248 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
jamesadevine 0:e1a608bb55e8 1249 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
jamesadevine 0:e1a608bb55e8 1250 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
jamesadevine 0:e1a608bb55e8 1251
jamesadevine 0:e1a608bb55e8 1252 #if (__MPU_PRESENT == 1)
jamesadevine 0:e1a608bb55e8 1253 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
jamesadevine 0:e1a608bb55e8 1254 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
jamesadevine 0:e1a608bb55e8 1255 #endif
jamesadevine 0:e1a608bb55e8 1256
jamesadevine 0:e1a608bb55e8 1257 /*@} */
jamesadevine 0:e1a608bb55e8 1258
jamesadevine 0:e1a608bb55e8 1259
jamesadevine 0:e1a608bb55e8 1260
jamesadevine 0:e1a608bb55e8 1261 /*******************************************************************************
jamesadevine 0:e1a608bb55e8 1262 * Hardware Abstraction Layer
jamesadevine 0:e1a608bb55e8 1263 Core Function Interface contains:
jamesadevine 0:e1a608bb55e8 1264 - Core NVIC Functions
jamesadevine 0:e1a608bb55e8 1265 - Core SysTick Functions
jamesadevine 0:e1a608bb55e8 1266 - Core Debug Functions
jamesadevine 0:e1a608bb55e8 1267 - Core Register Access Functions
jamesadevine 0:e1a608bb55e8 1268 ******************************************************************************/
jamesadevine 0:e1a608bb55e8 1269 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
jamesadevine 0:e1a608bb55e8 1270 */
jamesadevine 0:e1a608bb55e8 1271
jamesadevine 0:e1a608bb55e8 1272
jamesadevine 0:e1a608bb55e8 1273
jamesadevine 0:e1a608bb55e8 1274 /* ########################## NVIC functions #################################### */
jamesadevine 0:e1a608bb55e8 1275 /** \ingroup CMSIS_Core_FunctionInterface
jamesadevine 0:e1a608bb55e8 1276 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
jamesadevine 0:e1a608bb55e8 1277 \brief Functions that manage interrupts and exceptions via the NVIC.
jamesadevine 0:e1a608bb55e8 1278 @{
jamesadevine 0:e1a608bb55e8 1279 */
jamesadevine 0:e1a608bb55e8 1280
jamesadevine 0:e1a608bb55e8 1281 /** \brief Set Priority Grouping
jamesadevine 0:e1a608bb55e8 1282
jamesadevine 0:e1a608bb55e8 1283 The function sets the priority grouping field using the required unlock sequence.
jamesadevine 0:e1a608bb55e8 1284 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
jamesadevine 0:e1a608bb55e8 1285 Only values from 0..7 are used.
jamesadevine 0:e1a608bb55e8 1286 In case of a conflict between priority grouping and available
jamesadevine 0:e1a608bb55e8 1287 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
jamesadevine 0:e1a608bb55e8 1288
jamesadevine 0:e1a608bb55e8 1289 \param [in] PriorityGroup Priority grouping field.
jamesadevine 0:e1a608bb55e8 1290 */
jamesadevine 0:e1a608bb55e8 1291 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
jamesadevine 0:e1a608bb55e8 1292 {
jamesadevine 0:e1a608bb55e8 1293 uint32_t reg_value;
jamesadevine 0:e1a608bb55e8 1294 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
jamesadevine 0:e1a608bb55e8 1295
jamesadevine 0:e1a608bb55e8 1296 reg_value = SCB->AIRCR; /* read old register configuration */
jamesadevine 0:e1a608bb55e8 1297 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
jamesadevine 0:e1a608bb55e8 1298 reg_value = (reg_value |
jamesadevine 0:e1a608bb55e8 1299 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
jamesadevine 0:e1a608bb55e8 1300 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
jamesadevine 0:e1a608bb55e8 1301 SCB->AIRCR = reg_value;
jamesadevine 0:e1a608bb55e8 1302 }
jamesadevine 0:e1a608bb55e8 1303
jamesadevine 0:e1a608bb55e8 1304
jamesadevine 0:e1a608bb55e8 1305 /** \brief Get Priority Grouping
jamesadevine 0:e1a608bb55e8 1306
jamesadevine 0:e1a608bb55e8 1307 The function reads the priority grouping field from the NVIC Interrupt Controller.
jamesadevine 0:e1a608bb55e8 1308
jamesadevine 0:e1a608bb55e8 1309 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
jamesadevine 0:e1a608bb55e8 1310 */
jamesadevine 0:e1a608bb55e8 1311 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
jamesadevine 0:e1a608bb55e8 1312 {
jamesadevine 0:e1a608bb55e8 1313 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
jamesadevine 0:e1a608bb55e8 1314 }
jamesadevine 0:e1a608bb55e8 1315
jamesadevine 0:e1a608bb55e8 1316
jamesadevine 0:e1a608bb55e8 1317 /** \brief Enable External Interrupt
jamesadevine 0:e1a608bb55e8 1318
jamesadevine 0:e1a608bb55e8 1319 The function enables a device-specific interrupt in the NVIC interrupt controller.
jamesadevine 0:e1a608bb55e8 1320
jamesadevine 0:e1a608bb55e8 1321 \param [in] IRQn External interrupt number. Value cannot be negative.
jamesadevine 0:e1a608bb55e8 1322 */
jamesadevine 0:e1a608bb55e8 1323 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
jamesadevine 0:e1a608bb55e8 1324 {
jamesadevine 0:e1a608bb55e8 1325 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
jamesadevine 0:e1a608bb55e8 1326 }
jamesadevine 0:e1a608bb55e8 1327
jamesadevine 0:e1a608bb55e8 1328
jamesadevine 0:e1a608bb55e8 1329 /** \brief Disable External Interrupt
jamesadevine 0:e1a608bb55e8 1330
jamesadevine 0:e1a608bb55e8 1331 The function disables a device-specific interrupt in the NVIC interrupt controller.
jamesadevine 0:e1a608bb55e8 1332
jamesadevine 0:e1a608bb55e8 1333 \param [in] IRQn External interrupt number. Value cannot be negative.
jamesadevine 0:e1a608bb55e8 1334 */
jamesadevine 0:e1a608bb55e8 1335 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
jamesadevine 0:e1a608bb55e8 1336 {
jamesadevine 0:e1a608bb55e8 1337 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
jamesadevine 0:e1a608bb55e8 1338 }
jamesadevine 0:e1a608bb55e8 1339
jamesadevine 0:e1a608bb55e8 1340
jamesadevine 0:e1a608bb55e8 1341 /** \brief Get Pending Interrupt
jamesadevine 0:e1a608bb55e8 1342
jamesadevine 0:e1a608bb55e8 1343 The function reads the pending register in the NVIC and returns the pending bit
jamesadevine 0:e1a608bb55e8 1344 for the specified interrupt.
jamesadevine 0:e1a608bb55e8 1345
jamesadevine 0:e1a608bb55e8 1346 \param [in] IRQn Interrupt number.
jamesadevine 0:e1a608bb55e8 1347
jamesadevine 0:e1a608bb55e8 1348 \return 0 Interrupt status is not pending.
jamesadevine 0:e1a608bb55e8 1349 \return 1 Interrupt status is pending.
jamesadevine 0:e1a608bb55e8 1350 */
jamesadevine 0:e1a608bb55e8 1351 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
jamesadevine 0:e1a608bb55e8 1352 {
jamesadevine 0:e1a608bb55e8 1353 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
jamesadevine 0:e1a608bb55e8 1354 }
jamesadevine 0:e1a608bb55e8 1355
jamesadevine 0:e1a608bb55e8 1356
jamesadevine 0:e1a608bb55e8 1357 /** \brief Set Pending Interrupt
jamesadevine 0:e1a608bb55e8 1358
jamesadevine 0:e1a608bb55e8 1359 The function sets the pending bit of an external interrupt.
jamesadevine 0:e1a608bb55e8 1360
jamesadevine 0:e1a608bb55e8 1361 \param [in] IRQn Interrupt number. Value cannot be negative.
jamesadevine 0:e1a608bb55e8 1362 */
jamesadevine 0:e1a608bb55e8 1363 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
jamesadevine 0:e1a608bb55e8 1364 {
jamesadevine 0:e1a608bb55e8 1365 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
jamesadevine 0:e1a608bb55e8 1366 }
jamesadevine 0:e1a608bb55e8 1367
jamesadevine 0:e1a608bb55e8 1368
jamesadevine 0:e1a608bb55e8 1369 /** \brief Clear Pending Interrupt
jamesadevine 0:e1a608bb55e8 1370
jamesadevine 0:e1a608bb55e8 1371 The function clears the pending bit of an external interrupt.
jamesadevine 0:e1a608bb55e8 1372
jamesadevine 0:e1a608bb55e8 1373 \param [in] IRQn External interrupt number. Value cannot be negative.
jamesadevine 0:e1a608bb55e8 1374 */
jamesadevine 0:e1a608bb55e8 1375 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
jamesadevine 0:e1a608bb55e8 1376 {
jamesadevine 0:e1a608bb55e8 1377 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
jamesadevine 0:e1a608bb55e8 1378 }
jamesadevine 0:e1a608bb55e8 1379
jamesadevine 0:e1a608bb55e8 1380
jamesadevine 0:e1a608bb55e8 1381 /** \brief Get Active Interrupt
jamesadevine 0:e1a608bb55e8 1382
jamesadevine 0:e1a608bb55e8 1383 The function reads the active register in NVIC and returns the active bit.
jamesadevine 0:e1a608bb55e8 1384
jamesadevine 0:e1a608bb55e8 1385 \param [in] IRQn Interrupt number.
jamesadevine 0:e1a608bb55e8 1386
jamesadevine 0:e1a608bb55e8 1387 \return 0 Interrupt status is not active.
jamesadevine 0:e1a608bb55e8 1388 \return 1 Interrupt status is active.
jamesadevine 0:e1a608bb55e8 1389 */
jamesadevine 0:e1a608bb55e8 1390 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
jamesadevine 0:e1a608bb55e8 1391 {
jamesadevine 0:e1a608bb55e8 1392 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
jamesadevine 0:e1a608bb55e8 1393 }
jamesadevine 0:e1a608bb55e8 1394
jamesadevine 0:e1a608bb55e8 1395
jamesadevine 0:e1a608bb55e8 1396 /** \brief Set Interrupt Priority
jamesadevine 0:e1a608bb55e8 1397
jamesadevine 0:e1a608bb55e8 1398 The function sets the priority of an interrupt.
jamesadevine 0:e1a608bb55e8 1399
jamesadevine 0:e1a608bb55e8 1400 \note The priority cannot be set for every core interrupt.
jamesadevine 0:e1a608bb55e8 1401
jamesadevine 0:e1a608bb55e8 1402 \param [in] IRQn Interrupt number.
jamesadevine 0:e1a608bb55e8 1403 \param [in] priority Priority to set.
jamesadevine 0:e1a608bb55e8 1404 */
jamesadevine 0:e1a608bb55e8 1405 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
jamesadevine 0:e1a608bb55e8 1406 {
jamesadevine 0:e1a608bb55e8 1407 if(IRQn < 0) {
jamesadevine 0:e1a608bb55e8 1408 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
jamesadevine 0:e1a608bb55e8 1409 else {
jamesadevine 0:e1a608bb55e8 1410 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
jamesadevine 0:e1a608bb55e8 1411 }
jamesadevine 0:e1a608bb55e8 1412
jamesadevine 0:e1a608bb55e8 1413
jamesadevine 0:e1a608bb55e8 1414 /** \brief Get Interrupt Priority
jamesadevine 0:e1a608bb55e8 1415
jamesadevine 0:e1a608bb55e8 1416 The function reads the priority of an interrupt. The interrupt
jamesadevine 0:e1a608bb55e8 1417 number can be positive to specify an external (device specific)
jamesadevine 0:e1a608bb55e8 1418 interrupt, or negative to specify an internal (core) interrupt.
jamesadevine 0:e1a608bb55e8 1419
jamesadevine 0:e1a608bb55e8 1420
jamesadevine 0:e1a608bb55e8 1421 \param [in] IRQn Interrupt number.
jamesadevine 0:e1a608bb55e8 1422 \return Interrupt Priority. Value is aligned automatically to the implemented
jamesadevine 0:e1a608bb55e8 1423 priority bits of the microcontroller.
jamesadevine 0:e1a608bb55e8 1424 */
jamesadevine 0:e1a608bb55e8 1425 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
jamesadevine 0:e1a608bb55e8 1426 {
jamesadevine 0:e1a608bb55e8 1427
jamesadevine 0:e1a608bb55e8 1428 if(IRQn < 0) {
jamesadevine 0:e1a608bb55e8 1429 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
jamesadevine 0:e1a608bb55e8 1430 else {
jamesadevine 0:e1a608bb55e8 1431 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
jamesadevine 0:e1a608bb55e8 1432 }
jamesadevine 0:e1a608bb55e8 1433
jamesadevine 0:e1a608bb55e8 1434
jamesadevine 0:e1a608bb55e8 1435 /** \brief Encode Priority
jamesadevine 0:e1a608bb55e8 1436
jamesadevine 0:e1a608bb55e8 1437 The function encodes the priority for an interrupt with the given priority group,
jamesadevine 0:e1a608bb55e8 1438 preemptive priority value, and subpriority value.
jamesadevine 0:e1a608bb55e8 1439 In case of a conflict between priority grouping and available
jamesadevine 0:e1a608bb55e8 1440 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
jamesadevine 0:e1a608bb55e8 1441
jamesadevine 0:e1a608bb55e8 1442 \param [in] PriorityGroup Used priority group.
jamesadevine 0:e1a608bb55e8 1443 \param [in] PreemptPriority Preemptive priority value (starting from 0).
jamesadevine 0:e1a608bb55e8 1444 \param [in] SubPriority Subpriority value (starting from 0).
jamesadevine 0:e1a608bb55e8 1445 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
jamesadevine 0:e1a608bb55e8 1446 */
jamesadevine 0:e1a608bb55e8 1447 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
jamesadevine 0:e1a608bb55e8 1448 {
jamesadevine 0:e1a608bb55e8 1449 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
jamesadevine 0:e1a608bb55e8 1450 uint32_t PreemptPriorityBits;
jamesadevine 0:e1a608bb55e8 1451 uint32_t SubPriorityBits;
jamesadevine 0:e1a608bb55e8 1452
jamesadevine 0:e1a608bb55e8 1453 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
jamesadevine 0:e1a608bb55e8 1454 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
jamesadevine 0:e1a608bb55e8 1455
jamesadevine 0:e1a608bb55e8 1456 return (
jamesadevine 0:e1a608bb55e8 1457 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
jamesadevine 0:e1a608bb55e8 1458 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
jamesadevine 0:e1a608bb55e8 1459 );
jamesadevine 0:e1a608bb55e8 1460 }
jamesadevine 0:e1a608bb55e8 1461
jamesadevine 0:e1a608bb55e8 1462
jamesadevine 0:e1a608bb55e8 1463 /** \brief Decode Priority
jamesadevine 0:e1a608bb55e8 1464
jamesadevine 0:e1a608bb55e8 1465 The function decodes an interrupt priority value with a given priority group to
jamesadevine 0:e1a608bb55e8 1466 preemptive priority value and subpriority value.
jamesadevine 0:e1a608bb55e8 1467 In case of a conflict between priority grouping and available
jamesadevine 0:e1a608bb55e8 1468 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
jamesadevine 0:e1a608bb55e8 1469
jamesadevine 0:e1a608bb55e8 1470 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
jamesadevine 0:e1a608bb55e8 1471 \param [in] PriorityGroup Used priority group.
jamesadevine 0:e1a608bb55e8 1472 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
jamesadevine 0:e1a608bb55e8 1473 \param [out] pSubPriority Subpriority value (starting from 0).
jamesadevine 0:e1a608bb55e8 1474 */
jamesadevine 0:e1a608bb55e8 1475 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
jamesadevine 0:e1a608bb55e8 1476 {
jamesadevine 0:e1a608bb55e8 1477 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
jamesadevine 0:e1a608bb55e8 1478 uint32_t PreemptPriorityBits;
jamesadevine 0:e1a608bb55e8 1479 uint32_t SubPriorityBits;
jamesadevine 0:e1a608bb55e8 1480
jamesadevine 0:e1a608bb55e8 1481 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
jamesadevine 0:e1a608bb55e8 1482 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
jamesadevine 0:e1a608bb55e8 1483
jamesadevine 0:e1a608bb55e8 1484 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
jamesadevine 0:e1a608bb55e8 1485 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
jamesadevine 0:e1a608bb55e8 1486 }
jamesadevine 0:e1a608bb55e8 1487
jamesadevine 0:e1a608bb55e8 1488
jamesadevine 0:e1a608bb55e8 1489 /** \brief System Reset
jamesadevine 0:e1a608bb55e8 1490
jamesadevine 0:e1a608bb55e8 1491 The function initiates a system reset request to reset the MCU.
jamesadevine 0:e1a608bb55e8 1492 */
jamesadevine 0:e1a608bb55e8 1493 __STATIC_INLINE void NVIC_SystemReset(void)
jamesadevine 0:e1a608bb55e8 1494 {
jamesadevine 0:e1a608bb55e8 1495 __DSB(); /* Ensure all outstanding memory accesses included
jamesadevine 0:e1a608bb55e8 1496 buffered write are completed before reset */
jamesadevine 0:e1a608bb55e8 1497 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
jamesadevine 0:e1a608bb55e8 1498 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
jamesadevine 0:e1a608bb55e8 1499 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
jamesadevine 0:e1a608bb55e8 1500 __DSB(); /* Ensure completion of memory access */
jamesadevine 0:e1a608bb55e8 1501 while(1); /* wait until reset */
jamesadevine 0:e1a608bb55e8 1502 }
jamesadevine 0:e1a608bb55e8 1503
jamesadevine 0:e1a608bb55e8 1504 /*@} end of CMSIS_Core_NVICFunctions */
jamesadevine 0:e1a608bb55e8 1505
jamesadevine 0:e1a608bb55e8 1506
jamesadevine 0:e1a608bb55e8 1507
jamesadevine 0:e1a608bb55e8 1508 /* ################################## SysTick function ############################################ */
jamesadevine 0:e1a608bb55e8 1509 /** \ingroup CMSIS_Core_FunctionInterface
jamesadevine 0:e1a608bb55e8 1510 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
jamesadevine 0:e1a608bb55e8 1511 \brief Functions that configure the System.
jamesadevine 0:e1a608bb55e8 1512 @{
jamesadevine 0:e1a608bb55e8 1513 */
jamesadevine 0:e1a608bb55e8 1514
jamesadevine 0:e1a608bb55e8 1515 #if (__Vendor_SysTickConfig == 0)
jamesadevine 0:e1a608bb55e8 1516
jamesadevine 0:e1a608bb55e8 1517 /** \brief System Tick Configuration
jamesadevine 0:e1a608bb55e8 1518
jamesadevine 0:e1a608bb55e8 1519 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
jamesadevine 0:e1a608bb55e8 1520 Counter is in free running mode to generate periodic interrupts.
jamesadevine 0:e1a608bb55e8 1521
jamesadevine 0:e1a608bb55e8 1522 \param [in] ticks Number of ticks between two interrupts.
jamesadevine 0:e1a608bb55e8 1523
jamesadevine 0:e1a608bb55e8 1524 \return 0 Function succeeded.
jamesadevine 0:e1a608bb55e8 1525 \return 1 Function failed.
jamesadevine 0:e1a608bb55e8 1526
jamesadevine 0:e1a608bb55e8 1527 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
jamesadevine 0:e1a608bb55e8 1528 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
jamesadevine 0:e1a608bb55e8 1529 must contain a vendor-specific implementation of this function.
jamesadevine 0:e1a608bb55e8 1530
jamesadevine 0:e1a608bb55e8 1531 */
jamesadevine 0:e1a608bb55e8 1532 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
jamesadevine 0:e1a608bb55e8 1533 {
jamesadevine 0:e1a608bb55e8 1534 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
jamesadevine 0:e1a608bb55e8 1535
jamesadevine 0:e1a608bb55e8 1536 SysTick->LOAD = ticks - 1; /* set reload register */
jamesadevine 0:e1a608bb55e8 1537 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
jamesadevine 0:e1a608bb55e8 1538 SysTick->VAL = 0; /* Load the SysTick Counter Value */
jamesadevine 0:e1a608bb55e8 1539 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
jamesadevine 0:e1a608bb55e8 1540 SysTick_CTRL_TICKINT_Msk |
jamesadevine 0:e1a608bb55e8 1541 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
jamesadevine 0:e1a608bb55e8 1542 return (0); /* Function successful */
jamesadevine 0:e1a608bb55e8 1543 }
jamesadevine 0:e1a608bb55e8 1544
jamesadevine 0:e1a608bb55e8 1545 #endif
jamesadevine 0:e1a608bb55e8 1546
jamesadevine 0:e1a608bb55e8 1547 /*@} end of CMSIS_Core_SysTickFunctions */
jamesadevine 0:e1a608bb55e8 1548
jamesadevine 0:e1a608bb55e8 1549
jamesadevine 0:e1a608bb55e8 1550
jamesadevine 0:e1a608bb55e8 1551 /* ##################################### Debug In/Output function ########################################### */
jamesadevine 0:e1a608bb55e8 1552 /** \ingroup CMSIS_Core_FunctionInterface
jamesadevine 0:e1a608bb55e8 1553 \defgroup CMSIS_core_DebugFunctions ITM Functions
jamesadevine 0:e1a608bb55e8 1554 \brief Functions that access the ITM debug interface.
jamesadevine 0:e1a608bb55e8 1555 @{
jamesadevine 0:e1a608bb55e8 1556 */
jamesadevine 0:e1a608bb55e8 1557
jamesadevine 0:e1a608bb55e8 1558 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
jamesadevine 0:e1a608bb55e8 1559 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
jamesadevine 0:e1a608bb55e8 1560
jamesadevine 0:e1a608bb55e8 1561
jamesadevine 0:e1a608bb55e8 1562 /** \brief ITM Send Character
jamesadevine 0:e1a608bb55e8 1563
jamesadevine 0:e1a608bb55e8 1564 The function transmits a character via the ITM channel 0, and
jamesadevine 0:e1a608bb55e8 1565 \li Just returns when no debugger is connected that has booked the output.
jamesadevine 0:e1a608bb55e8 1566 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
jamesadevine 0:e1a608bb55e8 1567
jamesadevine 0:e1a608bb55e8 1568 \param [in] ch Character to transmit.
jamesadevine 0:e1a608bb55e8 1569
jamesadevine 0:e1a608bb55e8 1570 \returns Character to transmit.
jamesadevine 0:e1a608bb55e8 1571 */
jamesadevine 0:e1a608bb55e8 1572 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
jamesadevine 0:e1a608bb55e8 1573 {
jamesadevine 0:e1a608bb55e8 1574 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
jamesadevine 0:e1a608bb55e8 1575 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
jamesadevine 0:e1a608bb55e8 1576 {
jamesadevine 0:e1a608bb55e8 1577 while (ITM->PORT[0].u32 == 0);
jamesadevine 0:e1a608bb55e8 1578 ITM->PORT[0].u8 = (uint8_t) ch;
jamesadevine 0:e1a608bb55e8 1579 }
jamesadevine 0:e1a608bb55e8 1580 return (ch);
jamesadevine 0:e1a608bb55e8 1581 }
jamesadevine 0:e1a608bb55e8 1582
jamesadevine 0:e1a608bb55e8 1583
jamesadevine 0:e1a608bb55e8 1584 /** \brief ITM Receive Character
jamesadevine 0:e1a608bb55e8 1585
jamesadevine 0:e1a608bb55e8 1586 The function inputs a character via the external variable \ref ITM_RxBuffer.
jamesadevine 0:e1a608bb55e8 1587
jamesadevine 0:e1a608bb55e8 1588 \return Received character.
jamesadevine 0:e1a608bb55e8 1589 \return -1 No character pending.
jamesadevine 0:e1a608bb55e8 1590 */
jamesadevine 0:e1a608bb55e8 1591 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
jamesadevine 0:e1a608bb55e8 1592 int32_t ch = -1; /* no character available */
jamesadevine 0:e1a608bb55e8 1593
jamesadevine 0:e1a608bb55e8 1594 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
jamesadevine 0:e1a608bb55e8 1595 ch = ITM_RxBuffer;
jamesadevine 0:e1a608bb55e8 1596 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
jamesadevine 0:e1a608bb55e8 1597 }
jamesadevine 0:e1a608bb55e8 1598
jamesadevine 0:e1a608bb55e8 1599 return (ch);
jamesadevine 0:e1a608bb55e8 1600 }
jamesadevine 0:e1a608bb55e8 1601
jamesadevine 0:e1a608bb55e8 1602
jamesadevine 0:e1a608bb55e8 1603 /** \brief ITM Check Character
jamesadevine 0:e1a608bb55e8 1604
jamesadevine 0:e1a608bb55e8 1605 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
jamesadevine 0:e1a608bb55e8 1606
jamesadevine 0:e1a608bb55e8 1607 \return 0 No character available.
jamesadevine 0:e1a608bb55e8 1608 \return 1 Character available.
jamesadevine 0:e1a608bb55e8 1609 */
jamesadevine 0:e1a608bb55e8 1610 __STATIC_INLINE int32_t ITM_CheckChar (void) {
jamesadevine 0:e1a608bb55e8 1611
jamesadevine 0:e1a608bb55e8 1612 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
jamesadevine 0:e1a608bb55e8 1613 return (0); /* no character available */
jamesadevine 0:e1a608bb55e8 1614 } else {
jamesadevine 0:e1a608bb55e8 1615 return (1); /* character available */
jamesadevine 0:e1a608bb55e8 1616 }
jamesadevine 0:e1a608bb55e8 1617 }
jamesadevine 0:e1a608bb55e8 1618
jamesadevine 0:e1a608bb55e8 1619 /*@} end of CMSIS_core_DebugFunctions */
jamesadevine 0:e1a608bb55e8 1620
jamesadevine 0:e1a608bb55e8 1621 #endif /* __CORE_CM3_H_DEPENDANT */
jamesadevine 0:e1a608bb55e8 1622
jamesadevine 0:e1a608bb55e8 1623 #endif /* __CMSIS_GENERIC */
jamesadevine 0:e1a608bb55e8 1624
jamesadevine 0:e1a608bb55e8 1625 #ifdef __cplusplus
jamesadevine 0:e1a608bb55e8 1626 }
jamesadevine 0:e1a608bb55e8 1627 #endif