Lancaster University / mbed-dev-bin

Binary version of Lancaster University's mbed branch, soon to be merged. The source lives here:https://developer.mbed.org/teams/Lancaster-University/code/mbed-src/

Dependents:   microbit-dal microbit-ble-open microbit-dal-eddystone microbit-dal ... more

Fork of mbed-lite-test by Lancaster University

TARGET_NRF51_MICROBIT/core_cm0plus.h@3:768173a57492, 2016-07-13 (annotated)

Committer:
jamesadevine
Date:
Wed Jul 13 15:12:06 2016 +0100
Revision:
3:768173a57492
Parent:
0:e1a608bb55e8 
further updates to mbed-dev-bin

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jamesadevine 0:e1a608bb55e8 1 /**************************************************************************//**
jamesadevine 0:e1a608bb55e8 2 * @file core_cm0plus.h
jamesadevine 0:e1a608bb55e8 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
jamesadevine 0:e1a608bb55e8 4 * @version V3.20
jamesadevine 0:e1a608bb55e8 5 * @date 25. February 2013
jamesadevine 0:e1a608bb55e8 6 *
jamesadevine 0:e1a608bb55e8 7 * @note
jamesadevine 0:e1a608bb55e8 8 *
jamesadevine 0:e1a608bb55e8 9 ******************************************************************************/
jamesadevine 0:e1a608bb55e8 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
jamesadevine 0:e1a608bb55e8 11
jamesadevine 0:e1a608bb55e8 12 All rights reserved.
jamesadevine 0:e1a608bb55e8 13 Redistribution and use in source and binary forms, with or without
jamesadevine 0:e1a608bb55e8 14 modification, are permitted provided that the following conditions are met:
jamesadevine 0:e1a608bb55e8 15 - Redistributions of source code must retain the above copyright
jamesadevine 0:e1a608bb55e8 16 notice, this list of conditions and the following disclaimer.
jamesadevine 0:e1a608bb55e8 17 - Redistributions in binary form must reproduce the above copyright
jamesadevine 0:e1a608bb55e8 18 notice, this list of conditions and the following disclaimer in the
jamesadevine 0:e1a608bb55e8 19 documentation and/or other materials provided with the distribution.
jamesadevine 0:e1a608bb55e8 20 - Neither the name of ARM nor the names of its contributors may be used
jamesadevine 0:e1a608bb55e8 21 to endorse or promote products derived from this software without
jamesadevine 0:e1a608bb55e8 22 specific prior written permission.
jamesadevine 0:e1a608bb55e8 23 *
jamesadevine 0:e1a608bb55e8 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jamesadevine 0:e1a608bb55e8 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jamesadevine 0:e1a608bb55e8 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
jamesadevine 0:e1a608bb55e8 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
jamesadevine 0:e1a608bb55e8 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
jamesadevine 0:e1a608bb55e8 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
jamesadevine 0:e1a608bb55e8 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
jamesadevine 0:e1a608bb55e8 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
jamesadevine 0:e1a608bb55e8 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
jamesadevine 0:e1a608bb55e8 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
jamesadevine 0:e1a608bb55e8 34 POSSIBILITY OF SUCH DAMAGE.
jamesadevine 0:e1a608bb55e8 35 ---------------------------------------------------------------------------*/
jamesadevine 0:e1a608bb55e8 36
jamesadevine 0:e1a608bb55e8 37
jamesadevine 0:e1a608bb55e8 38 #if defined ( __ICCARM__ )
jamesadevine 0:e1a608bb55e8 39 #pragma system_include /* treat file as system include file for MISRA check */
jamesadevine 0:e1a608bb55e8 40 #endif
jamesadevine 0:e1a608bb55e8 41
jamesadevine 0:e1a608bb55e8 42 #ifdef __cplusplus
jamesadevine 0:e1a608bb55e8 43 extern "C" {
jamesadevine 0:e1a608bb55e8 44 #endif
jamesadevine 0:e1a608bb55e8 45
jamesadevine 0:e1a608bb55e8 46 #ifndef __CORE_CM0PLUS_H_GENERIC
jamesadevine 0:e1a608bb55e8 47 #define __CORE_CM0PLUS_H_GENERIC
jamesadevine 0:e1a608bb55e8 48
jamesadevine 0:e1a608bb55e8 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
jamesadevine 0:e1a608bb55e8 50 CMSIS violates the following MISRA-C:2004 rules:
jamesadevine 0:e1a608bb55e8 51
jamesadevine 0:e1a608bb55e8 52 \li Required Rule 8.5, object/function definition in header file.<br>
jamesadevine 0:e1a608bb55e8 53 Function definitions in header files are used to allow 'inlining'.
jamesadevine 0:e1a608bb55e8 54
jamesadevine 0:e1a608bb55e8 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
jamesadevine 0:e1a608bb55e8 56 Unions are used for effective representation of core registers.
jamesadevine 0:e1a608bb55e8 57
jamesadevine 0:e1a608bb55e8 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
jamesadevine 0:e1a608bb55e8 59 Function-like macros are used to allow more efficient code.
jamesadevine 0:e1a608bb55e8 60 */
jamesadevine 0:e1a608bb55e8 61
jamesadevine 0:e1a608bb55e8 62
jamesadevine 0:e1a608bb55e8 63 /*******************************************************************************
jamesadevine 0:e1a608bb55e8 64 * CMSIS definitions
jamesadevine 0:e1a608bb55e8 65 ******************************************************************************/
jamesadevine 0:e1a608bb55e8 66 /** \ingroup Cortex-M0+
jamesadevine 0:e1a608bb55e8 67 @{
jamesadevine 0:e1a608bb55e8 68 */
jamesadevine 0:e1a608bb55e8 69
jamesadevine 0:e1a608bb55e8 70 /* CMSIS CM0P definitions */
jamesadevine 0:e1a608bb55e8 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
jamesadevine 0:e1a608bb55e8 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
jamesadevine 0:e1a608bb55e8 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
jamesadevine 0:e1a608bb55e8 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
jamesadevine 0:e1a608bb55e8 75
jamesadevine 0:e1a608bb55e8 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
jamesadevine 0:e1a608bb55e8 77
jamesadevine 0:e1a608bb55e8 78
jamesadevine 0:e1a608bb55e8 79 #if defined ( __CC_ARM )
jamesadevine 0:e1a608bb55e8 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
jamesadevine 0:e1a608bb55e8 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
jamesadevine 0:e1a608bb55e8 82 #define __STATIC_INLINE static __inline
jamesadevine 0:e1a608bb55e8 83
jamesadevine 0:e1a608bb55e8 84 #elif defined ( __ICCARM__ )
jamesadevine 0:e1a608bb55e8 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
jamesadevine 0:e1a608bb55e8 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
jamesadevine 0:e1a608bb55e8 87 #define __STATIC_INLINE static inline
jamesadevine 0:e1a608bb55e8 88
jamesadevine 0:e1a608bb55e8 89 #elif defined ( __GNUC__ )
jamesadevine 0:e1a608bb55e8 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
jamesadevine 0:e1a608bb55e8 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
jamesadevine 0:e1a608bb55e8 92 #define __STATIC_INLINE static inline
jamesadevine 0:e1a608bb55e8 93
jamesadevine 0:e1a608bb55e8 94 #elif defined ( __TASKING__ )
jamesadevine 0:e1a608bb55e8 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
jamesadevine 0:e1a608bb55e8 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
jamesadevine 0:e1a608bb55e8 97 #define __STATIC_INLINE static inline
jamesadevine 0:e1a608bb55e8 98
jamesadevine 0:e1a608bb55e8 99 #endif
jamesadevine 0:e1a608bb55e8 100
jamesadevine 0:e1a608bb55e8 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
jamesadevine 0:e1a608bb55e8 102 */
jamesadevine 0:e1a608bb55e8 103 #define __FPU_USED 0
jamesadevine 0:e1a608bb55e8 104
jamesadevine 0:e1a608bb55e8 105 #if defined ( __CC_ARM )
jamesadevine 0:e1a608bb55e8 106 #if defined __TARGET_FPU_VFP
jamesadevine 0:e1a608bb55e8 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jamesadevine 0:e1a608bb55e8 108 #endif
jamesadevine 0:e1a608bb55e8 109
jamesadevine 0:e1a608bb55e8 110 #elif defined ( __ICCARM__ )
jamesadevine 0:e1a608bb55e8 111 #if defined __ARMVFP__
jamesadevine 0:e1a608bb55e8 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jamesadevine 0:e1a608bb55e8 113 #endif
jamesadevine 0:e1a608bb55e8 114
jamesadevine 0:e1a608bb55e8 115 #elif defined ( __GNUC__ )
jamesadevine 0:e1a608bb55e8 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
jamesadevine 0:e1a608bb55e8 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jamesadevine 0:e1a608bb55e8 118 #endif
jamesadevine 0:e1a608bb55e8 119
jamesadevine 0:e1a608bb55e8 120 #elif defined ( __TASKING__ )
jamesadevine 0:e1a608bb55e8 121 #if defined __FPU_VFP__
jamesadevine 0:e1a608bb55e8 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jamesadevine 0:e1a608bb55e8 123 #endif
jamesadevine 0:e1a608bb55e8 124 #endif
jamesadevine 0:e1a608bb55e8 125
jamesadevine 0:e1a608bb55e8 126 #include <stdint.h> /* standard types definitions */
jamesadevine 0:e1a608bb55e8 127 #include <core_cmInstr.h> /* Core Instruction Access */
jamesadevine 0:e1a608bb55e8 128 #include <core_cmFunc.h> /* Core Function Access */
jamesadevine 0:e1a608bb55e8 129
jamesadevine 0:e1a608bb55e8 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
jamesadevine 0:e1a608bb55e8 131
jamesadevine 0:e1a608bb55e8 132 #ifndef __CMSIS_GENERIC
jamesadevine 0:e1a608bb55e8 133
jamesadevine 0:e1a608bb55e8 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
jamesadevine 0:e1a608bb55e8 135 #define __CORE_CM0PLUS_H_DEPENDANT
jamesadevine 0:e1a608bb55e8 136
jamesadevine 0:e1a608bb55e8 137 /* check device defines and use defaults */
jamesadevine 0:e1a608bb55e8 138 #if defined __CHECK_DEVICE_DEFINES
jamesadevine 0:e1a608bb55e8 139 #ifndef __CM0PLUS_REV
jamesadevine 0:e1a608bb55e8 140 #define __CM0PLUS_REV 0x0000
jamesadevine 0:e1a608bb55e8 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
jamesadevine 0:e1a608bb55e8 142 #endif
jamesadevine 0:e1a608bb55e8 143
jamesadevine 0:e1a608bb55e8 144 #ifndef __MPU_PRESENT
jamesadevine 0:e1a608bb55e8 145 #define __MPU_PRESENT 0
jamesadevine 0:e1a608bb55e8 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
jamesadevine 0:e1a608bb55e8 147 #endif
jamesadevine 0:e1a608bb55e8 148
jamesadevine 0:e1a608bb55e8 149 #ifndef __VTOR_PRESENT
jamesadevine 0:e1a608bb55e8 150 #define __VTOR_PRESENT 0
jamesadevine 0:e1a608bb55e8 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
jamesadevine 0:e1a608bb55e8 152 #endif
jamesadevine 0:e1a608bb55e8 153
jamesadevine 0:e1a608bb55e8 154 #ifndef __NVIC_PRIO_BITS
jamesadevine 0:e1a608bb55e8 155 #define __NVIC_PRIO_BITS 2
jamesadevine 0:e1a608bb55e8 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
jamesadevine 0:e1a608bb55e8 157 #endif
jamesadevine 0:e1a608bb55e8 158
jamesadevine 0:e1a608bb55e8 159 #ifndef __Vendor_SysTickConfig
jamesadevine 0:e1a608bb55e8 160 #define __Vendor_SysTickConfig 0
jamesadevine 0:e1a608bb55e8 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
jamesadevine 0:e1a608bb55e8 162 #endif
jamesadevine 0:e1a608bb55e8 163 #endif
jamesadevine 0:e1a608bb55e8 164
jamesadevine 0:e1a608bb55e8 165 /* IO definitions (access restrictions to peripheral registers) */
jamesadevine 0:e1a608bb55e8 166 /**
jamesadevine 0:e1a608bb55e8 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
jamesadevine 0:e1a608bb55e8 168
jamesadevine 0:e1a608bb55e8 169 <strong>IO Type Qualifiers</strong> are used
jamesadevine 0:e1a608bb55e8 170 \li to specify the access to peripheral variables.
jamesadevine 0:e1a608bb55e8 171 \li for automatic generation of peripheral register debug information.
jamesadevine 0:e1a608bb55e8 172 */
jamesadevine 0:e1a608bb55e8 173 #ifdef __cplusplus
jamesadevine 0:e1a608bb55e8 174 #define __I volatile /*!< Defines 'read only' permissions */
jamesadevine 0:e1a608bb55e8 175 #else
jamesadevine 0:e1a608bb55e8 176 #define __I volatile const /*!< Defines 'read only' permissions */
jamesadevine 0:e1a608bb55e8 177 #endif
jamesadevine 0:e1a608bb55e8 178 #define __O volatile /*!< Defines 'write only' permissions */
jamesadevine 0:e1a608bb55e8 179 #define __IO volatile /*!< Defines 'read / write' permissions */
jamesadevine 0:e1a608bb55e8 180
jamesadevine 0:e1a608bb55e8 181 /*@} end of group Cortex-M0+ */
jamesadevine 0:e1a608bb55e8 182
jamesadevine 0:e1a608bb55e8 183
jamesadevine 0:e1a608bb55e8 184
jamesadevine 0:e1a608bb55e8 185 /*******************************************************************************
jamesadevine 0:e1a608bb55e8 186 * Register Abstraction
jamesadevine 0:e1a608bb55e8 187 Core Register contain:
jamesadevine 0:e1a608bb55e8 188 - Core Register
jamesadevine 0:e1a608bb55e8 189 - Core NVIC Register
jamesadevine 0:e1a608bb55e8 190 - Core SCB Register
jamesadevine 0:e1a608bb55e8 191 - Core SysTick Register
jamesadevine 0:e1a608bb55e8 192 - Core MPU Register
jamesadevine 0:e1a608bb55e8 193 ******************************************************************************/
jamesadevine 0:e1a608bb55e8 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
jamesadevine 0:e1a608bb55e8 195 \brief Type definitions and defines for Cortex-M processor based devices.
jamesadevine 0:e1a608bb55e8 196 */
jamesadevine 0:e1a608bb55e8 197
jamesadevine 0:e1a608bb55e8 198 /** \ingroup CMSIS_core_register
jamesadevine 0:e1a608bb55e8 199 \defgroup CMSIS_CORE Status and Control Registers
jamesadevine 0:e1a608bb55e8 200 \brief Core Register type definitions.
jamesadevine 0:e1a608bb55e8 201 @{
jamesadevine 0:e1a608bb55e8 202 */
jamesadevine 0:e1a608bb55e8 203
jamesadevine 0:e1a608bb55e8 204 /** \brief Union type to access the Application Program Status Register (APSR).
jamesadevine 0:e1a608bb55e8 205 */
jamesadevine 0:e1a608bb55e8 206 typedef union
jamesadevine 0:e1a608bb55e8 207 {
jamesadevine 0:e1a608bb55e8 208 struct
jamesadevine 0:e1a608bb55e8 209 {
jamesadevine 0:e1a608bb55e8 210 #if (__CORTEX_M != 0x04)
jamesadevine 0:e1a608bb55e8 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
jamesadevine 0:e1a608bb55e8 212 #else
jamesadevine 0:e1a608bb55e8 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
jamesadevine 0:e1a608bb55e8 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
jamesadevine 0:e1a608bb55e8 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
jamesadevine 0:e1a608bb55e8 216 #endif
jamesadevine 0:e1a608bb55e8 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
jamesadevine 0:e1a608bb55e8 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
jamesadevine 0:e1a608bb55e8 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
jamesadevine 0:e1a608bb55e8 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
jamesadevine 0:e1a608bb55e8 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
jamesadevine 0:e1a608bb55e8 222 } b; /*!< Structure used for bit access */
jamesadevine 0:e1a608bb55e8 223 uint32_t w; /*!< Type used for word access */
jamesadevine 0:e1a608bb55e8 224 } APSR_Type;
jamesadevine 0:e1a608bb55e8 225
jamesadevine 0:e1a608bb55e8 226
jamesadevine 0:e1a608bb55e8 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
jamesadevine 0:e1a608bb55e8 228 */
jamesadevine 0:e1a608bb55e8 229 typedef union
jamesadevine 0:e1a608bb55e8 230 {
jamesadevine 0:e1a608bb55e8 231 struct
jamesadevine 0:e1a608bb55e8 232 {
jamesadevine 0:e1a608bb55e8 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
jamesadevine 0:e1a608bb55e8 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
jamesadevine 0:e1a608bb55e8 235 } b; /*!< Structure used for bit access */
jamesadevine 0:e1a608bb55e8 236 uint32_t w; /*!< Type used for word access */
jamesadevine 0:e1a608bb55e8 237 } IPSR_Type;
jamesadevine 0:e1a608bb55e8 238
jamesadevine 0:e1a608bb55e8 239
jamesadevine 0:e1a608bb55e8 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
jamesadevine 0:e1a608bb55e8 241 */
jamesadevine 0:e1a608bb55e8 242 typedef union
jamesadevine 0:e1a608bb55e8 243 {
jamesadevine 0:e1a608bb55e8 244 struct
jamesadevine 0:e1a608bb55e8 245 {
jamesadevine 0:e1a608bb55e8 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
jamesadevine 0:e1a608bb55e8 247 #if (__CORTEX_M != 0x04)
jamesadevine 0:e1a608bb55e8 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
jamesadevine 0:e1a608bb55e8 249 #else
jamesadevine 0:e1a608bb55e8 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
jamesadevine 0:e1a608bb55e8 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
jamesadevine 0:e1a608bb55e8 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
jamesadevine 0:e1a608bb55e8 253 #endif
jamesadevine 0:e1a608bb55e8 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
jamesadevine 0:e1a608bb55e8 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
jamesadevine 0:e1a608bb55e8 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
jamesadevine 0:e1a608bb55e8 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
jamesadevine 0:e1a608bb55e8 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
jamesadevine 0:e1a608bb55e8 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
jamesadevine 0:e1a608bb55e8 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
jamesadevine 0:e1a608bb55e8 261 } b; /*!< Structure used for bit access */
jamesadevine 0:e1a608bb55e8 262 uint32_t w; /*!< Type used for word access */
jamesadevine 0:e1a608bb55e8 263 } xPSR_Type;
jamesadevine 0:e1a608bb55e8 264
jamesadevine 0:e1a608bb55e8 265
jamesadevine 0:e1a608bb55e8 266 /** \brief Union type to access the Control Registers (CONTROL).
jamesadevine 0:e1a608bb55e8 267 */
jamesadevine 0:e1a608bb55e8 268 typedef union
jamesadevine 0:e1a608bb55e8 269 {
jamesadevine 0:e1a608bb55e8 270 struct
jamesadevine 0:e1a608bb55e8 271 {
jamesadevine 0:e1a608bb55e8 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
jamesadevine 0:e1a608bb55e8 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
jamesadevine 0:e1a608bb55e8 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
jamesadevine 0:e1a608bb55e8 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
jamesadevine 0:e1a608bb55e8 276 } b; /*!< Structure used for bit access */
jamesadevine 0:e1a608bb55e8 277 uint32_t w; /*!< Type used for word access */
jamesadevine 0:e1a608bb55e8 278 } CONTROL_Type;
jamesadevine 0:e1a608bb55e8 279
jamesadevine 0:e1a608bb55e8 280 /*@} end of group CMSIS_CORE */
jamesadevine 0:e1a608bb55e8 281
jamesadevine 0:e1a608bb55e8 282
jamesadevine 0:e1a608bb55e8 283 /** \ingroup CMSIS_core_register
jamesadevine 0:e1a608bb55e8 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
jamesadevine 0:e1a608bb55e8 285 \brief Type definitions for the NVIC Registers
jamesadevine 0:e1a608bb55e8 286 @{
jamesadevine 0:e1a608bb55e8 287 */
jamesadevine 0:e1a608bb55e8 288
jamesadevine 0:e1a608bb55e8 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
jamesadevine 0:e1a608bb55e8 290 */
jamesadevine 0:e1a608bb55e8 291 typedef struct
jamesadevine 0:e1a608bb55e8 292 {
jamesadevine 0:e1a608bb55e8 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
jamesadevine 0:e1a608bb55e8 294 uint32_t RESERVED0[31];
jamesadevine 0:e1a608bb55e8 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
jamesadevine 0:e1a608bb55e8 296 uint32_t RSERVED1[31];
jamesadevine 0:e1a608bb55e8 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
jamesadevine 0:e1a608bb55e8 298 uint32_t RESERVED2[31];
jamesadevine 0:e1a608bb55e8 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
jamesadevine 0:e1a608bb55e8 300 uint32_t RESERVED3[31];
jamesadevine 0:e1a608bb55e8 301 uint32_t RESERVED4[64];
jamesadevine 0:e1a608bb55e8 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
jamesadevine 0:e1a608bb55e8 303 } NVIC_Type;
jamesadevine 0:e1a608bb55e8 304
jamesadevine 0:e1a608bb55e8 305 /*@} end of group CMSIS_NVIC */
jamesadevine 0:e1a608bb55e8 306
jamesadevine 0:e1a608bb55e8 307
jamesadevine 0:e1a608bb55e8 308 /** \ingroup CMSIS_core_register
jamesadevine 0:e1a608bb55e8 309 \defgroup CMSIS_SCB System Control Block (SCB)
jamesadevine 0:e1a608bb55e8 310 \brief Type definitions for the System Control Block Registers
jamesadevine 0:e1a608bb55e8 311 @{
jamesadevine 0:e1a608bb55e8 312 */
jamesadevine 0:e1a608bb55e8 313
jamesadevine 0:e1a608bb55e8 314 /** \brief Structure type to access the System Control Block (SCB).
jamesadevine 0:e1a608bb55e8 315 */
jamesadevine 0:e1a608bb55e8 316 typedef struct
jamesadevine 0:e1a608bb55e8 317 {
jamesadevine 0:e1a608bb55e8 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
jamesadevine 0:e1a608bb55e8 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
jamesadevine 0:e1a608bb55e8 320 #if (__VTOR_PRESENT == 1)
jamesadevine 0:e1a608bb55e8 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
jamesadevine 0:e1a608bb55e8 322 #else
jamesadevine 0:e1a608bb55e8 323 uint32_t RESERVED0;
jamesadevine 0:e1a608bb55e8 324 #endif
jamesadevine 0:e1a608bb55e8 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
jamesadevine 0:e1a608bb55e8 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
jamesadevine 0:e1a608bb55e8 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
jamesadevine 0:e1a608bb55e8 328 uint32_t RESERVED1;
jamesadevine 0:e1a608bb55e8 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
jamesadevine 0:e1a608bb55e8 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
jamesadevine 0:e1a608bb55e8 331 } SCB_Type;
jamesadevine 0:e1a608bb55e8 332
jamesadevine 0:e1a608bb55e8 333 /* SCB CPUID Register Definitions */
jamesadevine 0:e1a608bb55e8 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
jamesadevine 0:e1a608bb55e8 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
jamesadevine 0:e1a608bb55e8 336
jamesadevine 0:e1a608bb55e8 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
jamesadevine 0:e1a608bb55e8 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
jamesadevine 0:e1a608bb55e8 339
jamesadevine 0:e1a608bb55e8 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
jamesadevine 0:e1a608bb55e8 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
jamesadevine 0:e1a608bb55e8 342
jamesadevine 0:e1a608bb55e8 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
jamesadevine 0:e1a608bb55e8 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
jamesadevine 0:e1a608bb55e8 345
jamesadevine 0:e1a608bb55e8 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
jamesadevine 0:e1a608bb55e8 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
jamesadevine 0:e1a608bb55e8 348
jamesadevine 0:e1a608bb55e8 349 /* SCB Interrupt Control State Register Definitions */
jamesadevine 0:e1a608bb55e8 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
jamesadevine 0:e1a608bb55e8 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
jamesadevine 0:e1a608bb55e8 352
jamesadevine 0:e1a608bb55e8 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
jamesadevine 0:e1a608bb55e8 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
jamesadevine 0:e1a608bb55e8 355
jamesadevine 0:e1a608bb55e8 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
jamesadevine 0:e1a608bb55e8 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
jamesadevine 0:e1a608bb55e8 358
jamesadevine 0:e1a608bb55e8 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
jamesadevine 0:e1a608bb55e8 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
jamesadevine 0:e1a608bb55e8 361
jamesadevine 0:e1a608bb55e8 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
jamesadevine 0:e1a608bb55e8 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
jamesadevine 0:e1a608bb55e8 364
jamesadevine 0:e1a608bb55e8 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
jamesadevine 0:e1a608bb55e8 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
jamesadevine 0:e1a608bb55e8 367
jamesadevine 0:e1a608bb55e8 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
jamesadevine 0:e1a608bb55e8 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
jamesadevine 0:e1a608bb55e8 370
jamesadevine 0:e1a608bb55e8 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
jamesadevine 0:e1a608bb55e8 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
jamesadevine 0:e1a608bb55e8 373
jamesadevine 0:e1a608bb55e8 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
jamesadevine 0:e1a608bb55e8 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
jamesadevine 0:e1a608bb55e8 376
jamesadevine 0:e1a608bb55e8 377 #if (__VTOR_PRESENT == 1)
jamesadevine 0:e1a608bb55e8 378 /* SCB Interrupt Control State Register Definitions */
jamesadevine 0:e1a608bb55e8 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
jamesadevine 0:e1a608bb55e8 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
jamesadevine 0:e1a608bb55e8 381 #endif
jamesadevine 0:e1a608bb55e8 382
jamesadevine 0:e1a608bb55e8 383 /* SCB Application Interrupt and Reset Control Register Definitions */
jamesadevine 0:e1a608bb55e8 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
jamesadevine 0:e1a608bb55e8 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
jamesadevine 0:e1a608bb55e8 386
jamesadevine 0:e1a608bb55e8 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
jamesadevine 0:e1a608bb55e8 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
jamesadevine 0:e1a608bb55e8 389
jamesadevine 0:e1a608bb55e8 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
jamesadevine 0:e1a608bb55e8 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
jamesadevine 0:e1a608bb55e8 392
jamesadevine 0:e1a608bb55e8 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
jamesadevine 0:e1a608bb55e8 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
jamesadevine 0:e1a608bb55e8 395
jamesadevine 0:e1a608bb55e8 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
jamesadevine 0:e1a608bb55e8 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
jamesadevine 0:e1a608bb55e8 398
jamesadevine 0:e1a608bb55e8 399 /* SCB System Control Register Definitions */
jamesadevine 0:e1a608bb55e8 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
jamesadevine 0:e1a608bb55e8 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
jamesadevine 0:e1a608bb55e8 402
jamesadevine 0:e1a608bb55e8 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
jamesadevine 0:e1a608bb55e8 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
jamesadevine 0:e1a608bb55e8 405
jamesadevine 0:e1a608bb55e8 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
jamesadevine 0:e1a608bb55e8 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
jamesadevine 0:e1a608bb55e8 408
jamesadevine 0:e1a608bb55e8 409 /* SCB Configuration Control Register Definitions */
jamesadevine 0:e1a608bb55e8 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
jamesadevine 0:e1a608bb55e8 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
jamesadevine 0:e1a608bb55e8 412
jamesadevine 0:e1a608bb55e8 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
jamesadevine 0:e1a608bb55e8 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
jamesadevine 0:e1a608bb55e8 415
jamesadevine 0:e1a608bb55e8 416 /* SCB System Handler Control and State Register Definitions */
jamesadevine 0:e1a608bb55e8 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
jamesadevine 0:e1a608bb55e8 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
jamesadevine 0:e1a608bb55e8 419
jamesadevine 0:e1a608bb55e8 420 /*@} end of group CMSIS_SCB */
jamesadevine 0:e1a608bb55e8 421
jamesadevine 0:e1a608bb55e8 422
jamesadevine 0:e1a608bb55e8 423 /** \ingroup CMSIS_core_register
jamesadevine 0:e1a608bb55e8 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
jamesadevine 0:e1a608bb55e8 425 \brief Type definitions for the System Timer Registers.
jamesadevine 0:e1a608bb55e8 426 @{
jamesadevine 0:e1a608bb55e8 427 */
jamesadevine 0:e1a608bb55e8 428
jamesadevine 0:e1a608bb55e8 429 /** \brief Structure type to access the System Timer (SysTick).
jamesadevine 0:e1a608bb55e8 430 */
jamesadevine 0:e1a608bb55e8 431 typedef struct
jamesadevine 0:e1a608bb55e8 432 {
jamesadevine 0:e1a608bb55e8 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
jamesadevine 0:e1a608bb55e8 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
jamesadevine 0:e1a608bb55e8 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
jamesadevine 0:e1a608bb55e8 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
jamesadevine 0:e1a608bb55e8 437 } SysTick_Type;
jamesadevine 0:e1a608bb55e8 438
jamesadevine 0:e1a608bb55e8 439 /* SysTick Control / Status Register Definitions */
jamesadevine 0:e1a608bb55e8 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
jamesadevine 0:e1a608bb55e8 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
jamesadevine 0:e1a608bb55e8 442
jamesadevine 0:e1a608bb55e8 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
jamesadevine 0:e1a608bb55e8 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
jamesadevine 0:e1a608bb55e8 445
jamesadevine 0:e1a608bb55e8 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
jamesadevine 0:e1a608bb55e8 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
jamesadevine 0:e1a608bb55e8 448
jamesadevine 0:e1a608bb55e8 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
jamesadevine 0:e1a608bb55e8 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
jamesadevine 0:e1a608bb55e8 451
jamesadevine 0:e1a608bb55e8 452 /* SysTick Reload Register Definitions */
jamesadevine 0:e1a608bb55e8 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
jamesadevine 0:e1a608bb55e8 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
jamesadevine 0:e1a608bb55e8 455
jamesadevine 0:e1a608bb55e8 456 /* SysTick Current Register Definitions */
jamesadevine 0:e1a608bb55e8 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
jamesadevine 0:e1a608bb55e8 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
jamesadevine 0:e1a608bb55e8 459
jamesadevine 0:e1a608bb55e8 460 /* SysTick Calibration Register Definitions */
jamesadevine 0:e1a608bb55e8 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
jamesadevine 0:e1a608bb55e8 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
jamesadevine 0:e1a608bb55e8 463
jamesadevine 0:e1a608bb55e8 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
jamesadevine 0:e1a608bb55e8 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
jamesadevine 0:e1a608bb55e8 466
jamesadevine 0:e1a608bb55e8 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
jamesadevine 0:e1a608bb55e8 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
jamesadevine 0:e1a608bb55e8 469
jamesadevine 0:e1a608bb55e8 470 /*@} end of group CMSIS_SysTick */
jamesadevine 0:e1a608bb55e8 471
jamesadevine 0:e1a608bb55e8 472 #if (__MPU_PRESENT == 1)
jamesadevine 0:e1a608bb55e8 473 /** \ingroup CMSIS_core_register
jamesadevine 0:e1a608bb55e8 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
jamesadevine 0:e1a608bb55e8 475 \brief Type definitions for the Memory Protection Unit (MPU)
jamesadevine 0:e1a608bb55e8 476 @{
jamesadevine 0:e1a608bb55e8 477 */
jamesadevine 0:e1a608bb55e8 478
jamesadevine 0:e1a608bb55e8 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
jamesadevine 0:e1a608bb55e8 480 */
jamesadevine 0:e1a608bb55e8 481 typedef struct
jamesadevine 0:e1a608bb55e8 482 {
jamesadevine 0:e1a608bb55e8 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
jamesadevine 0:e1a608bb55e8 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
jamesadevine 0:e1a608bb55e8 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
jamesadevine 0:e1a608bb55e8 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
jamesadevine 0:e1a608bb55e8 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
jamesadevine 0:e1a608bb55e8 488 } MPU_Type;
jamesadevine 0:e1a608bb55e8 489
jamesadevine 0:e1a608bb55e8 490 /* MPU Type Register */
jamesadevine 0:e1a608bb55e8 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
jamesadevine 0:e1a608bb55e8 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
jamesadevine 0:e1a608bb55e8 493
jamesadevine 0:e1a608bb55e8 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
jamesadevine 0:e1a608bb55e8 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
jamesadevine 0:e1a608bb55e8 496
jamesadevine 0:e1a608bb55e8 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
jamesadevine 0:e1a608bb55e8 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
jamesadevine 0:e1a608bb55e8 499
jamesadevine 0:e1a608bb55e8 500 /* MPU Control Register */
jamesadevine 0:e1a608bb55e8 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
jamesadevine 0:e1a608bb55e8 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
jamesadevine 0:e1a608bb55e8 503
jamesadevine 0:e1a608bb55e8 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
jamesadevine 0:e1a608bb55e8 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
jamesadevine 0:e1a608bb55e8 506
jamesadevine 0:e1a608bb55e8 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
jamesadevine 0:e1a608bb55e8 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
jamesadevine 0:e1a608bb55e8 509
jamesadevine 0:e1a608bb55e8 510 /* MPU Region Number Register */
jamesadevine 0:e1a608bb55e8 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
jamesadevine 0:e1a608bb55e8 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
jamesadevine 0:e1a608bb55e8 513
jamesadevine 0:e1a608bb55e8 514 /* MPU Region Base Address Register */
jamesadevine 0:e1a608bb55e8 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
jamesadevine 0:e1a608bb55e8 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
jamesadevine 0:e1a608bb55e8 517
jamesadevine 0:e1a608bb55e8 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
jamesadevine 0:e1a608bb55e8 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
jamesadevine 0:e1a608bb55e8 520
jamesadevine 0:e1a608bb55e8 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
jamesadevine 0:e1a608bb55e8 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
jamesadevine 0:e1a608bb55e8 523
jamesadevine 0:e1a608bb55e8 524 /* MPU Region Attribute and Size Register */
jamesadevine 0:e1a608bb55e8 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
jamesadevine 0:e1a608bb55e8 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
jamesadevine 0:e1a608bb55e8 527
jamesadevine 0:e1a608bb55e8 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
jamesadevine 0:e1a608bb55e8 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
jamesadevine 0:e1a608bb55e8 530
jamesadevine 0:e1a608bb55e8 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
jamesadevine 0:e1a608bb55e8 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
jamesadevine 0:e1a608bb55e8 533
jamesadevine 0:e1a608bb55e8 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
jamesadevine 0:e1a608bb55e8 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
jamesadevine 0:e1a608bb55e8 536
jamesadevine 0:e1a608bb55e8 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
jamesadevine 0:e1a608bb55e8 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
jamesadevine 0:e1a608bb55e8 539
jamesadevine 0:e1a608bb55e8 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
jamesadevine 0:e1a608bb55e8 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
jamesadevine 0:e1a608bb55e8 542
jamesadevine 0:e1a608bb55e8 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
jamesadevine 0:e1a608bb55e8 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
jamesadevine 0:e1a608bb55e8 545
jamesadevine 0:e1a608bb55e8 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
jamesadevine 0:e1a608bb55e8 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
jamesadevine 0:e1a608bb55e8 548
jamesadevine 0:e1a608bb55e8 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
jamesadevine 0:e1a608bb55e8 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
jamesadevine 0:e1a608bb55e8 551
jamesadevine 0:e1a608bb55e8 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
jamesadevine 0:e1a608bb55e8 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
jamesadevine 0:e1a608bb55e8 554
jamesadevine 0:e1a608bb55e8 555 /*@} end of group CMSIS_MPU */
jamesadevine 0:e1a608bb55e8 556 #endif
jamesadevine 0:e1a608bb55e8 557
jamesadevine 0:e1a608bb55e8 558
jamesadevine 0:e1a608bb55e8 559 /** \ingroup CMSIS_core_register
jamesadevine 0:e1a608bb55e8 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
jamesadevine 0:e1a608bb55e8 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
jamesadevine 0:e1a608bb55e8 562 are only accessible over DAP and not via processor. Therefore
jamesadevine 0:e1a608bb55e8 563 they are not covered by the Cortex-M0 header file.
jamesadevine 0:e1a608bb55e8 564 @{
jamesadevine 0:e1a608bb55e8 565 */
jamesadevine 0:e1a608bb55e8 566 /*@} end of group CMSIS_CoreDebug */
jamesadevine 0:e1a608bb55e8 567
jamesadevine 0:e1a608bb55e8 568
jamesadevine 0:e1a608bb55e8 569 /** \ingroup CMSIS_core_register
jamesadevine 0:e1a608bb55e8 570 \defgroup CMSIS_core_base Core Definitions
jamesadevine 0:e1a608bb55e8 571 \brief Definitions for base addresses, unions, and structures.
jamesadevine 0:e1a608bb55e8 572 @{
jamesadevine 0:e1a608bb55e8 573 */
jamesadevine 0:e1a608bb55e8 574
jamesadevine 0:e1a608bb55e8 575 /* Memory mapping of Cortex-M0+ Hardware */
jamesadevine 0:e1a608bb55e8 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
jamesadevine 0:e1a608bb55e8 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
jamesadevine 0:e1a608bb55e8 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
jamesadevine 0:e1a608bb55e8 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
jamesadevine 0:e1a608bb55e8 580
jamesadevine 0:e1a608bb55e8 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
jamesadevine 0:e1a608bb55e8 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
jamesadevine 0:e1a608bb55e8 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
jamesadevine 0:e1a608bb55e8 584
jamesadevine 0:e1a608bb55e8 585 #if (__MPU_PRESENT == 1)
jamesadevine 0:e1a608bb55e8 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
jamesadevine 0:e1a608bb55e8 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
jamesadevine 0:e1a608bb55e8 588 #endif
jamesadevine 0:e1a608bb55e8 589
jamesadevine 0:e1a608bb55e8 590 /*@} */
jamesadevine 0:e1a608bb55e8 591
jamesadevine 0:e1a608bb55e8 592
jamesadevine 0:e1a608bb55e8 593
jamesadevine 0:e1a608bb55e8 594 /*******************************************************************************
jamesadevine 0:e1a608bb55e8 595 * Hardware Abstraction Layer
jamesadevine 0:e1a608bb55e8 596 Core Function Interface contains:
jamesadevine 0:e1a608bb55e8 597 - Core NVIC Functions
jamesadevine 0:e1a608bb55e8 598 - Core SysTick Functions
jamesadevine 0:e1a608bb55e8 599 - Core Register Access Functions
jamesadevine 0:e1a608bb55e8 600 ******************************************************************************/
jamesadevine 0:e1a608bb55e8 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
jamesadevine 0:e1a608bb55e8 602 */
jamesadevine 0:e1a608bb55e8 603
jamesadevine 0:e1a608bb55e8 604
jamesadevine 0:e1a608bb55e8 605
jamesadevine 0:e1a608bb55e8 606 /* ########################## NVIC functions #################################### */
jamesadevine 0:e1a608bb55e8 607 /** \ingroup CMSIS_Core_FunctionInterface
jamesadevine 0:e1a608bb55e8 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
jamesadevine 0:e1a608bb55e8 609 \brief Functions that manage interrupts and exceptions via the NVIC.
jamesadevine 0:e1a608bb55e8 610 @{
jamesadevine 0:e1a608bb55e8 611 */
jamesadevine 0:e1a608bb55e8 612
jamesadevine 0:e1a608bb55e8 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
jamesadevine 0:e1a608bb55e8 614 /* The following MACROS handle generation of the register offset and byte masks */
jamesadevine 0:e1a608bb55e8 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
jamesadevine 0:e1a608bb55e8 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
jamesadevine 0:e1a608bb55e8 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
jamesadevine 0:e1a608bb55e8 618
jamesadevine 0:e1a608bb55e8 619
jamesadevine 0:e1a608bb55e8 620 /** \brief Enable External Interrupt
jamesadevine 0:e1a608bb55e8 621
jamesadevine 0:e1a608bb55e8 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
jamesadevine 0:e1a608bb55e8 623
jamesadevine 0:e1a608bb55e8 624 \param [in] IRQn External interrupt number. Value cannot be negative.
jamesadevine 0:e1a608bb55e8 625 */
jamesadevine 0:e1a608bb55e8 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
jamesadevine 0:e1a608bb55e8 627 {
jamesadevine 0:e1a608bb55e8 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
jamesadevine 0:e1a608bb55e8 629 }
jamesadevine 0:e1a608bb55e8 630
jamesadevine 0:e1a608bb55e8 631
jamesadevine 0:e1a608bb55e8 632 /** \brief Disable External Interrupt
jamesadevine 0:e1a608bb55e8 633
jamesadevine 0:e1a608bb55e8 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
jamesadevine 0:e1a608bb55e8 635
jamesadevine 0:e1a608bb55e8 636 \param [in] IRQn External interrupt number. Value cannot be negative.
jamesadevine 0:e1a608bb55e8 637 */
jamesadevine 0:e1a608bb55e8 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
jamesadevine 0:e1a608bb55e8 639 {
jamesadevine 0:e1a608bb55e8 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
jamesadevine 0:e1a608bb55e8 641 }
jamesadevine 0:e1a608bb55e8 642
jamesadevine 0:e1a608bb55e8 643
jamesadevine 0:e1a608bb55e8 644 /** \brief Get Pending Interrupt
jamesadevine 0:e1a608bb55e8 645
jamesadevine 0:e1a608bb55e8 646 The function reads the pending register in the NVIC and returns the pending bit
jamesadevine 0:e1a608bb55e8 647 for the specified interrupt.
jamesadevine 0:e1a608bb55e8 648
jamesadevine 0:e1a608bb55e8 649 \param [in] IRQn Interrupt number.
jamesadevine 0:e1a608bb55e8 650
jamesadevine 0:e1a608bb55e8 651 \return 0 Interrupt status is not pending.
jamesadevine 0:e1a608bb55e8 652 \return 1 Interrupt status is pending.
jamesadevine 0:e1a608bb55e8 653 */
jamesadevine 0:e1a608bb55e8 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
jamesadevine 0:e1a608bb55e8 655 {
jamesadevine 0:e1a608bb55e8 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
jamesadevine 0:e1a608bb55e8 657 }
jamesadevine 0:e1a608bb55e8 658
jamesadevine 0:e1a608bb55e8 659
jamesadevine 0:e1a608bb55e8 660 /** \brief Set Pending Interrupt
jamesadevine 0:e1a608bb55e8 661
jamesadevine 0:e1a608bb55e8 662 The function sets the pending bit of an external interrupt.
jamesadevine 0:e1a608bb55e8 663
jamesadevine 0:e1a608bb55e8 664 \param [in] IRQn Interrupt number. Value cannot be negative.
jamesadevine 0:e1a608bb55e8 665 */
jamesadevine 0:e1a608bb55e8 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
jamesadevine 0:e1a608bb55e8 667 {
jamesadevine 0:e1a608bb55e8 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
jamesadevine 0:e1a608bb55e8 669 }
jamesadevine 0:e1a608bb55e8 670
jamesadevine 0:e1a608bb55e8 671
jamesadevine 0:e1a608bb55e8 672 /** \brief Clear Pending Interrupt
jamesadevine 0:e1a608bb55e8 673
jamesadevine 0:e1a608bb55e8 674 The function clears the pending bit of an external interrupt.
jamesadevine 0:e1a608bb55e8 675
jamesadevine 0:e1a608bb55e8 676 \param [in] IRQn External interrupt number. Value cannot be negative.
jamesadevine 0:e1a608bb55e8 677 */
jamesadevine 0:e1a608bb55e8 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
jamesadevine 0:e1a608bb55e8 679 {
jamesadevine 0:e1a608bb55e8 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
jamesadevine 0:e1a608bb55e8 681 }
jamesadevine 0:e1a608bb55e8 682
jamesadevine 0:e1a608bb55e8 683
jamesadevine 0:e1a608bb55e8 684 /** \brief Set Interrupt Priority
jamesadevine 0:e1a608bb55e8 685
jamesadevine 0:e1a608bb55e8 686 The function sets the priority of an interrupt.
jamesadevine 0:e1a608bb55e8 687
jamesadevine 0:e1a608bb55e8 688 \note The priority cannot be set for every core interrupt.
jamesadevine 0:e1a608bb55e8 689
jamesadevine 0:e1a608bb55e8 690 \param [in] IRQn Interrupt number.
jamesadevine 0:e1a608bb55e8 691 \param [in] priority Priority to set.
jamesadevine 0:e1a608bb55e8 692 */
jamesadevine 0:e1a608bb55e8 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
jamesadevine 0:e1a608bb55e8 694 {
jamesadevine 0:e1a608bb55e8 695 if(IRQn < 0) {
jamesadevine 0:e1a608bb55e8 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
jamesadevine 0:e1a608bb55e8 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
jamesadevine 0:e1a608bb55e8 698 else {
jamesadevine 0:e1a608bb55e8 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
jamesadevine 0:e1a608bb55e8 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
jamesadevine 0:e1a608bb55e8 701 }
jamesadevine 0:e1a608bb55e8 702
jamesadevine 0:e1a608bb55e8 703
jamesadevine 0:e1a608bb55e8 704 /** \brief Get Interrupt Priority
jamesadevine 0:e1a608bb55e8 705
jamesadevine 0:e1a608bb55e8 706 The function reads the priority of an interrupt. The interrupt
jamesadevine 0:e1a608bb55e8 707 number can be positive to specify an external (device specific)
jamesadevine 0:e1a608bb55e8 708 interrupt, or negative to specify an internal (core) interrupt.
jamesadevine 0:e1a608bb55e8 709
jamesadevine 0:e1a608bb55e8 710
jamesadevine 0:e1a608bb55e8 711 \param [in] IRQn Interrupt number.
jamesadevine 0:e1a608bb55e8 712 \return Interrupt Priority. Value is aligned automatically to the implemented
jamesadevine 0:e1a608bb55e8 713 priority bits of the microcontroller.
jamesadevine 0:e1a608bb55e8 714 */
jamesadevine 0:e1a608bb55e8 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
jamesadevine 0:e1a608bb55e8 716 {
jamesadevine 0:e1a608bb55e8 717
jamesadevine 0:e1a608bb55e8 718 if(IRQn < 0) {
jamesadevine 0:e1a608bb55e8 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
jamesadevine 0:e1a608bb55e8 720 else {
jamesadevine 0:e1a608bb55e8 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
jamesadevine 0:e1a608bb55e8 722 }
jamesadevine 0:e1a608bb55e8 723
jamesadevine 0:e1a608bb55e8 724
jamesadevine 0:e1a608bb55e8 725 /** \brief System Reset
jamesadevine 0:e1a608bb55e8 726
jamesadevine 0:e1a608bb55e8 727 The function initiates a system reset request to reset the MCU.
jamesadevine 0:e1a608bb55e8 728 */
jamesadevine 0:e1a608bb55e8 729 __STATIC_INLINE void NVIC_SystemReset(void)
jamesadevine 0:e1a608bb55e8 730 {
jamesadevine 0:e1a608bb55e8 731 __DSB(); /* Ensure all outstanding memory accesses included
jamesadevine 0:e1a608bb55e8 732 buffered write are completed before reset */
jamesadevine 0:e1a608bb55e8 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
jamesadevine 0:e1a608bb55e8 734 SCB_AIRCR_SYSRESETREQ_Msk);
jamesadevine 0:e1a608bb55e8 735 __DSB(); /* Ensure completion of memory access */
jamesadevine 0:e1a608bb55e8 736 while(1); /* wait until reset */
jamesadevine 0:e1a608bb55e8 737 }
jamesadevine 0:e1a608bb55e8 738
jamesadevine 0:e1a608bb55e8 739 /*@} end of CMSIS_Core_NVICFunctions */
jamesadevine 0:e1a608bb55e8 740
jamesadevine 0:e1a608bb55e8 741
jamesadevine 0:e1a608bb55e8 742
jamesadevine 0:e1a608bb55e8 743 /* ################################## SysTick function ############################################ */
jamesadevine 0:e1a608bb55e8 744 /** \ingroup CMSIS_Core_FunctionInterface
jamesadevine 0:e1a608bb55e8 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
jamesadevine 0:e1a608bb55e8 746 \brief Functions that configure the System.
jamesadevine 0:e1a608bb55e8 747 @{
jamesadevine 0:e1a608bb55e8 748 */
jamesadevine 0:e1a608bb55e8 749
jamesadevine 0:e1a608bb55e8 750 #if (__Vendor_SysTickConfig == 0)
jamesadevine 0:e1a608bb55e8 751
jamesadevine 0:e1a608bb55e8 752 /** \brief System Tick Configuration
jamesadevine 0:e1a608bb55e8 753
jamesadevine 0:e1a608bb55e8 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
jamesadevine 0:e1a608bb55e8 755 Counter is in free running mode to generate periodic interrupts.
jamesadevine 0:e1a608bb55e8 756
jamesadevine 0:e1a608bb55e8 757 \param [in] ticks Number of ticks between two interrupts.
jamesadevine 0:e1a608bb55e8 758
jamesadevine 0:e1a608bb55e8 759 \return 0 Function succeeded.
jamesadevine 0:e1a608bb55e8 760 \return 1 Function failed.
jamesadevine 0:e1a608bb55e8 761
jamesadevine 0:e1a608bb55e8 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
jamesadevine 0:e1a608bb55e8 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
jamesadevine 0:e1a608bb55e8 764 must contain a vendor-specific implementation of this function.
jamesadevine 0:e1a608bb55e8 765
jamesadevine 0:e1a608bb55e8 766 */
jamesadevine 0:e1a608bb55e8 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
jamesadevine 0:e1a608bb55e8 768 {
jamesadevine 0:e1a608bb55e8 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
jamesadevine 0:e1a608bb55e8 770
jamesadevine 0:e1a608bb55e8 771 SysTick->LOAD = ticks - 1; /* set reload register */
jamesadevine 0:e1a608bb55e8 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
jamesadevine 0:e1a608bb55e8 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
jamesadevine 0:e1a608bb55e8 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
jamesadevine 0:e1a608bb55e8 775 SysTick_CTRL_TICKINT_Msk |
jamesadevine 0:e1a608bb55e8 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
jamesadevine 0:e1a608bb55e8 777 return (0); /* Function successful */
jamesadevine 0:e1a608bb55e8 778 }
jamesadevine 0:e1a608bb55e8 779
jamesadevine 0:e1a608bb55e8 780 #endif
jamesadevine 0:e1a608bb55e8 781
jamesadevine 0:e1a608bb55e8 782 /*@} end of CMSIS_Core_SysTickFunctions */
jamesadevine 0:e1a608bb55e8 783
jamesadevine 0:e1a608bb55e8 784
jamesadevine 0:e1a608bb55e8 785
jamesadevine 0:e1a608bb55e8 786
jamesadevine 0:e1a608bb55e8 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
jamesadevine 0:e1a608bb55e8 788
jamesadevine 0:e1a608bb55e8 789 #endif /* __CMSIS_GENERIC */
jamesadevine 0:e1a608bb55e8 790
jamesadevine 0:e1a608bb55e8 791 #ifdef __cplusplus
jamesadevine 0:e1a608bb55e8 792 }
jamesadevine 0:e1a608bb55e8 793 #endif