Lancaster University / mbed-dev-bin

Binary version of Lancaster University's mbed branch, soon to be merged. The source lives here:https://developer.mbed.org/teams/Lancaster-University/code/mbed-src/

Dependents:   microbit-dal microbit-ble-open microbit-dal-eddystone microbit-dal ... more

Fork of mbed-lite-test by Lancaster University

TARGET_NRF51_MICROBIT/core_ca9.h@3:768173a57492, 2016-07-13 (annotated)

Committer:
jamesadevine
Date:
Wed Jul 13 15:12:06 2016 +0100
Revision:
3:768173a57492
Parent:
0:e1a608bb55e8 
further updates to mbed-dev-bin

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jamesadevine 0:e1a608bb55e8 1 /**************************************************************************//**
jamesadevine 0:e1a608bb55e8 2 * @file core_ca9.h
jamesadevine 0:e1a608bb55e8 3 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
jamesadevine 0:e1a608bb55e8 4 * @version
jamesadevine 0:e1a608bb55e8 5 * @date 25 March 2013
jamesadevine 0:e1a608bb55e8 6 *
jamesadevine 0:e1a608bb55e8 7 * @note
jamesadevine 0:e1a608bb55e8 8 *
jamesadevine 0:e1a608bb55e8 9 ******************************************************************************/
jamesadevine 0:e1a608bb55e8 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
jamesadevine 0:e1a608bb55e8 11
jamesadevine 0:e1a608bb55e8 12 All rights reserved.
jamesadevine 0:e1a608bb55e8 13 Redistribution and use in source and binary forms, with or without
jamesadevine 0:e1a608bb55e8 14 modification, are permitted provided that the following conditions are met:
jamesadevine 0:e1a608bb55e8 15 - Redistributions of source code must retain the above copyright
jamesadevine 0:e1a608bb55e8 16 notice, this list of conditions and the following disclaimer.
jamesadevine 0:e1a608bb55e8 17 - Redistributions in binary form must reproduce the above copyright
jamesadevine 0:e1a608bb55e8 18 notice, this list of conditions and the following disclaimer in the
jamesadevine 0:e1a608bb55e8 19 documentation and/or other materials provided with the distribution.
jamesadevine 0:e1a608bb55e8 20 - Neither the name of ARM nor the names of its contributors may be used
jamesadevine 0:e1a608bb55e8 21 to endorse or promote products derived from this software without
jamesadevine 0:e1a608bb55e8 22 specific prior written permission.
jamesadevine 0:e1a608bb55e8 23 *
jamesadevine 0:e1a608bb55e8 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jamesadevine 0:e1a608bb55e8 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jamesadevine 0:e1a608bb55e8 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
jamesadevine 0:e1a608bb55e8 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
jamesadevine 0:e1a608bb55e8 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
jamesadevine 0:e1a608bb55e8 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
jamesadevine 0:e1a608bb55e8 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
jamesadevine 0:e1a608bb55e8 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
jamesadevine 0:e1a608bb55e8 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
jamesadevine 0:e1a608bb55e8 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
jamesadevine 0:e1a608bb55e8 34 POSSIBILITY OF SUCH DAMAGE.
jamesadevine 0:e1a608bb55e8 35 ---------------------------------------------------------------------------*/
jamesadevine 0:e1a608bb55e8 36
jamesadevine 0:e1a608bb55e8 37
jamesadevine 0:e1a608bb55e8 38 #if defined ( __ICCARM__ )
jamesadevine 0:e1a608bb55e8 39 #pragma system_include /* treat file as system include file for MISRA check */
jamesadevine 0:e1a608bb55e8 40 #endif
jamesadevine 0:e1a608bb55e8 41
jamesadevine 0:e1a608bb55e8 42 #ifdef __cplusplus
jamesadevine 0:e1a608bb55e8 43 extern "C" {
jamesadevine 0:e1a608bb55e8 44 #endif
jamesadevine 0:e1a608bb55e8 45
jamesadevine 0:e1a608bb55e8 46 #ifndef __CORE_CA9_H_GENERIC
jamesadevine 0:e1a608bb55e8 47 #define __CORE_CA9_H_GENERIC
jamesadevine 0:e1a608bb55e8 48
jamesadevine 0:e1a608bb55e8 49
jamesadevine 0:e1a608bb55e8 50 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
jamesadevine 0:e1a608bb55e8 51 CMSIS violates the following MISRA-C:2004 rules:
jamesadevine 0:e1a608bb55e8 52
jamesadevine 0:e1a608bb55e8 53 \li Required Rule 8.5, object/function definition in header file.<br>
jamesadevine 0:e1a608bb55e8 54 Function definitions in header files are used to allow 'inlining'.
jamesadevine 0:e1a608bb55e8 55
jamesadevine 0:e1a608bb55e8 56 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
jamesadevine 0:e1a608bb55e8 57 Unions are used for effective representation of core registers.
jamesadevine 0:e1a608bb55e8 58
jamesadevine 0:e1a608bb55e8 59 \li Advisory Rule 19.7, Function-like macro defined.<br>
jamesadevine 0:e1a608bb55e8 60 Function-like macros are used to allow more efficient code.
jamesadevine 0:e1a608bb55e8 61 */
jamesadevine 0:e1a608bb55e8 62
jamesadevine 0:e1a608bb55e8 63
jamesadevine 0:e1a608bb55e8 64 /*******************************************************************************
jamesadevine 0:e1a608bb55e8 65 * CMSIS definitions
jamesadevine 0:e1a608bb55e8 66 ******************************************************************************/
jamesadevine 0:e1a608bb55e8 67 /** \ingroup Cortex_A9
jamesadevine 0:e1a608bb55e8 68 @{
jamesadevine 0:e1a608bb55e8 69 */
jamesadevine 0:e1a608bb55e8 70
jamesadevine 0:e1a608bb55e8 71 /* CMSIS CA9 definitions */
jamesadevine 0:e1a608bb55e8 72 #define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
jamesadevine 0:e1a608bb55e8 73 #define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
jamesadevine 0:e1a608bb55e8 74 #define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
jamesadevine 0:e1a608bb55e8 75 __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
jamesadevine 0:e1a608bb55e8 76
jamesadevine 0:e1a608bb55e8 77 #define __CORTEX_A (0x09) /*!< Cortex-A Core */
jamesadevine 0:e1a608bb55e8 78
jamesadevine 0:e1a608bb55e8 79
jamesadevine 0:e1a608bb55e8 80 #if defined ( __CC_ARM )
jamesadevine 0:e1a608bb55e8 81 #define __ASM __asm /*!< asm keyword for ARM Compiler */
jamesadevine 0:e1a608bb55e8 82 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
jamesadevine 0:e1a608bb55e8 83 #define __STATIC_INLINE static __inline
jamesadevine 0:e1a608bb55e8 84 #define __STATIC_ASM static __asm
jamesadevine 0:e1a608bb55e8 85
jamesadevine 0:e1a608bb55e8 86 #elif defined ( __ICCARM__ )
jamesadevine 0:e1a608bb55e8 87 #define __ASM __asm /*!< asm keyword for IAR Compiler */
jamesadevine 0:e1a608bb55e8 88 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
jamesadevine 0:e1a608bb55e8 89 #define __STATIC_INLINE static inline
jamesadevine 0:e1a608bb55e8 90 #define __STATIC_ASM static __asm
jamesadevine 0:e1a608bb55e8 91
jamesadevine 0:e1a608bb55e8 92 #elif defined ( __TMS470__ )
jamesadevine 0:e1a608bb55e8 93 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
jamesadevine 0:e1a608bb55e8 94 #define __STATIC_INLINE static inline
jamesadevine 0:e1a608bb55e8 95 #define __STATIC_ASM static __asm
jamesadevine 0:e1a608bb55e8 96
jamesadevine 0:e1a608bb55e8 97 #elif defined ( __GNUC__ )
jamesadevine 0:e1a608bb55e8 98 #define __ASM __asm /*!< asm keyword for GNU Compiler */
jamesadevine 0:e1a608bb55e8 99 #define __INLINE inline /*!< inline keyword for GNU Compiler */
jamesadevine 0:e1a608bb55e8 100 #define __STATIC_INLINE static inline
jamesadevine 0:e1a608bb55e8 101 #define __STATIC_ASM static __asm
jamesadevine 0:e1a608bb55e8 102
jamesadevine 0:e1a608bb55e8 103 #elif defined ( __TASKING__ )
jamesadevine 0:e1a608bb55e8 104 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
jamesadevine 0:e1a608bb55e8 105 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
jamesadevine 0:e1a608bb55e8 106 #define __STATIC_INLINE static inline
jamesadevine 0:e1a608bb55e8 107 #define __STATIC_ASM static __asm
jamesadevine 0:e1a608bb55e8 108
jamesadevine 0:e1a608bb55e8 109 #endif
jamesadevine 0:e1a608bb55e8 110
jamesadevine 0:e1a608bb55e8 111 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
jamesadevine 0:e1a608bb55e8 112 */
jamesadevine 0:e1a608bb55e8 113 #if defined ( __CC_ARM )
jamesadevine 0:e1a608bb55e8 114 #if defined __TARGET_FPU_VFP
jamesadevine 0:e1a608bb55e8 115 #if (__FPU_PRESENT == 1)
jamesadevine 0:e1a608bb55e8 116 #define __FPU_USED 1
jamesadevine 0:e1a608bb55e8 117 #else
jamesadevine 0:e1a608bb55e8 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jamesadevine 0:e1a608bb55e8 119 #define __FPU_USED 0
jamesadevine 0:e1a608bb55e8 120 #endif
jamesadevine 0:e1a608bb55e8 121 #else
jamesadevine 0:e1a608bb55e8 122 #define __FPU_USED 0
jamesadevine 0:e1a608bb55e8 123 #endif
jamesadevine 0:e1a608bb55e8 124
jamesadevine 0:e1a608bb55e8 125 #elif defined ( __ICCARM__ )
jamesadevine 0:e1a608bb55e8 126 #if defined __ARMVFP__
jamesadevine 0:e1a608bb55e8 127 #if (__FPU_PRESENT == 1)
jamesadevine 0:e1a608bb55e8 128 #define __FPU_USED 1
jamesadevine 0:e1a608bb55e8 129 #else
jamesadevine 0:e1a608bb55e8 130 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jamesadevine 0:e1a608bb55e8 131 #define __FPU_USED 0
jamesadevine 0:e1a608bb55e8 132 #endif
jamesadevine 0:e1a608bb55e8 133 #else
jamesadevine 0:e1a608bb55e8 134 #define __FPU_USED 0
jamesadevine 0:e1a608bb55e8 135 #endif
jamesadevine 0:e1a608bb55e8 136
jamesadevine 0:e1a608bb55e8 137 #elif defined ( __TMS470__ )
jamesadevine 0:e1a608bb55e8 138 #if defined __TI_VFP_SUPPORT__
jamesadevine 0:e1a608bb55e8 139 #if (__FPU_PRESENT == 1)
jamesadevine 0:e1a608bb55e8 140 #define __FPU_USED 1
jamesadevine 0:e1a608bb55e8 141 #else
jamesadevine 0:e1a608bb55e8 142 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jamesadevine 0:e1a608bb55e8 143 #define __FPU_USED 0
jamesadevine 0:e1a608bb55e8 144 #endif
jamesadevine 0:e1a608bb55e8 145 #else
jamesadevine 0:e1a608bb55e8 146 #define __FPU_USED 0
jamesadevine 0:e1a608bb55e8 147 #endif
jamesadevine 0:e1a608bb55e8 148
jamesadevine 0:e1a608bb55e8 149 #elif defined ( __GNUC__ )
jamesadevine 0:e1a608bb55e8 150 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
jamesadevine 0:e1a608bb55e8 151 #if (__FPU_PRESENT == 1)
jamesadevine 0:e1a608bb55e8 152 #define __FPU_USED 1
jamesadevine 0:e1a608bb55e8 153 #else
jamesadevine 0:e1a608bb55e8 154 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jamesadevine 0:e1a608bb55e8 155 #define __FPU_USED 0
jamesadevine 0:e1a608bb55e8 156 #endif
jamesadevine 0:e1a608bb55e8 157 #else
jamesadevine 0:e1a608bb55e8 158 #define __FPU_USED 0
jamesadevine 0:e1a608bb55e8 159 #endif
jamesadevine 0:e1a608bb55e8 160
jamesadevine 0:e1a608bb55e8 161 #elif defined ( __TASKING__ )
jamesadevine 0:e1a608bb55e8 162 #if defined __FPU_VFP__
jamesadevine 0:e1a608bb55e8 163 #if (__FPU_PRESENT == 1)
jamesadevine 0:e1a608bb55e8 164 #define __FPU_USED 1
jamesadevine 0:e1a608bb55e8 165 #else
jamesadevine 0:e1a608bb55e8 166 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jamesadevine 0:e1a608bb55e8 167 #define __FPU_USED 0
jamesadevine 0:e1a608bb55e8 168 #endif
jamesadevine 0:e1a608bb55e8 169 #else
jamesadevine 0:e1a608bb55e8 170 #define __FPU_USED 0
jamesadevine 0:e1a608bb55e8 171 #endif
jamesadevine 0:e1a608bb55e8 172 #endif
jamesadevine 0:e1a608bb55e8 173
jamesadevine 0:e1a608bb55e8 174 #include <stdint.h> /*!< standard types definitions */
jamesadevine 0:e1a608bb55e8 175 #include "core_caInstr.h" /*!< Core Instruction Access */
jamesadevine 0:e1a608bb55e8 176 #include "core_caFunc.h" /*!< Core Function Access */
jamesadevine 0:e1a608bb55e8 177 #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
jamesadevine 0:e1a608bb55e8 178
jamesadevine 0:e1a608bb55e8 179 #endif /* __CORE_CA9_H_GENERIC */
jamesadevine 0:e1a608bb55e8 180
jamesadevine 0:e1a608bb55e8 181 #ifndef __CMSIS_GENERIC
jamesadevine 0:e1a608bb55e8 182
jamesadevine 0:e1a608bb55e8 183 #ifndef __CORE_CA9_H_DEPENDANT
jamesadevine 0:e1a608bb55e8 184 #define __CORE_CA9_H_DEPENDANT
jamesadevine 0:e1a608bb55e8 185
jamesadevine 0:e1a608bb55e8 186 /* check device defines and use defaults */
jamesadevine 0:e1a608bb55e8 187 #if defined __CHECK_DEVICE_DEFINES
jamesadevine 0:e1a608bb55e8 188 #ifndef __CA9_REV
jamesadevine 0:e1a608bb55e8 189 #define __CA9_REV 0x0000
jamesadevine 0:e1a608bb55e8 190 #warning "__CA9_REV not defined in device header file; using default!"
jamesadevine 0:e1a608bb55e8 191 #endif
jamesadevine 0:e1a608bb55e8 192
jamesadevine 0:e1a608bb55e8 193 #ifndef __FPU_PRESENT
jamesadevine 0:e1a608bb55e8 194 #define __FPU_PRESENT 1
jamesadevine 0:e1a608bb55e8 195 #warning "__FPU_PRESENT not defined in device header file; using default!"
jamesadevine 0:e1a608bb55e8 196 #endif
jamesadevine 0:e1a608bb55e8 197
jamesadevine 0:e1a608bb55e8 198 #ifndef __Vendor_SysTickConfig
jamesadevine 0:e1a608bb55e8 199 #define __Vendor_SysTickConfig 1
jamesadevine 0:e1a608bb55e8 200 #endif
jamesadevine 0:e1a608bb55e8 201
jamesadevine 0:e1a608bb55e8 202 #if __Vendor_SysTickConfig == 0
jamesadevine 0:e1a608bb55e8 203 #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
jamesadevine 0:e1a608bb55e8 204 #endif
jamesadevine 0:e1a608bb55e8 205 #endif
jamesadevine 0:e1a608bb55e8 206
jamesadevine 0:e1a608bb55e8 207 /* IO definitions (access restrictions to peripheral registers) */
jamesadevine 0:e1a608bb55e8 208 /**
jamesadevine 0:e1a608bb55e8 209 \defgroup CMSIS_glob_defs CMSIS Global Defines
jamesadevine 0:e1a608bb55e8 210
jamesadevine 0:e1a608bb55e8 211 <strong>IO Type Qualifiers</strong> are used
jamesadevine 0:e1a608bb55e8 212 \li to specify the access to peripheral variables.
jamesadevine 0:e1a608bb55e8 213 \li for automatic generation of peripheral register debug information.
jamesadevine 0:e1a608bb55e8 214 */
jamesadevine 0:e1a608bb55e8 215 #ifdef __cplusplus
jamesadevine 0:e1a608bb55e8 216 #define __I volatile /*!< Defines 'read only' permissions */
jamesadevine 0:e1a608bb55e8 217 #else
jamesadevine 0:e1a608bb55e8 218 #define __I volatile const /*!< Defines 'read only' permissions */
jamesadevine 0:e1a608bb55e8 219 #endif
jamesadevine 0:e1a608bb55e8 220 #define __O volatile /*!< Defines 'write only' permissions */
jamesadevine 0:e1a608bb55e8 221 #define __IO volatile /*!< Defines 'read / write' permissions */
jamesadevine 0:e1a608bb55e8 222
jamesadevine 0:e1a608bb55e8 223 /*@} end of group Cortex_A9 */
jamesadevine 0:e1a608bb55e8 224
jamesadevine 0:e1a608bb55e8 225
jamesadevine 0:e1a608bb55e8 226 /*******************************************************************************
jamesadevine 0:e1a608bb55e8 227 * Register Abstraction
jamesadevine 0:e1a608bb55e8 228 ******************************************************************************/
jamesadevine 0:e1a608bb55e8 229 /** \defgroup CMSIS_core_register Defines and Type Definitions
jamesadevine 0:e1a608bb55e8 230 \brief Type definitions and defines for Cortex-A processor based devices.
jamesadevine 0:e1a608bb55e8 231 */
jamesadevine 0:e1a608bb55e8 232
jamesadevine 0:e1a608bb55e8 233 /** \ingroup CMSIS_core_register
jamesadevine 0:e1a608bb55e8 234 \defgroup CMSIS_CORE Status and Control Registers
jamesadevine 0:e1a608bb55e8 235 \brief Core Register type definitions.
jamesadevine 0:e1a608bb55e8 236 @{
jamesadevine 0:e1a608bb55e8 237 */
jamesadevine 0:e1a608bb55e8 238
jamesadevine 0:e1a608bb55e8 239 /** \brief Union type to access the Application Program Status Register (APSR).
jamesadevine 0:e1a608bb55e8 240 */
jamesadevine 0:e1a608bb55e8 241 typedef union
jamesadevine 0:e1a608bb55e8 242 {
jamesadevine 0:e1a608bb55e8 243 struct
jamesadevine 0:e1a608bb55e8 244 {
jamesadevine 0:e1a608bb55e8 245 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
jamesadevine 0:e1a608bb55e8 246 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
jamesadevine 0:e1a608bb55e8 247 uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
jamesadevine 0:e1a608bb55e8 248 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
jamesadevine 0:e1a608bb55e8 249 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
jamesadevine 0:e1a608bb55e8 250 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
jamesadevine 0:e1a608bb55e8 251 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
jamesadevine 0:e1a608bb55e8 252 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
jamesadevine 0:e1a608bb55e8 253 } b; /*!< Structure used for bit access */
jamesadevine 0:e1a608bb55e8 254 uint32_t w; /*!< Type used for word access */
jamesadevine 0:e1a608bb55e8 255 } APSR_Type;
jamesadevine 0:e1a608bb55e8 256
jamesadevine 0:e1a608bb55e8 257
jamesadevine 0:e1a608bb55e8 258 /*@} end of group CMSIS_CORE */
jamesadevine 0:e1a608bb55e8 259
jamesadevine 0:e1a608bb55e8 260 /*@} end of CMSIS_Core_FPUFunctions */
jamesadevine 0:e1a608bb55e8 261
jamesadevine 0:e1a608bb55e8 262
jamesadevine 0:e1a608bb55e8 263 #endif /* __CORE_CA9_H_GENERIC */
jamesadevine 0:e1a608bb55e8 264
jamesadevine 0:e1a608bb55e8 265 #endif /* __CMSIS_GENERIC */
jamesadevine 0:e1a608bb55e8 266
jamesadevine 0:e1a608bb55e8 267 #ifdef __cplusplus
jamesadevine 0:e1a608bb55e8 268 }
jamesadevine 0:e1a608bb55e8 269
jamesadevine 0:e1a608bb55e8 270
jamesadevine 0:e1a608bb55e8 271 #endif