RF24 library for STM32F446RE
Fork of RF24 by
nRF24L01.h@6:5cc7136648d1, 2016-04-21 (annotated)
- Committer:
- akashvibhute
- Date:
- Thu Apr 21 04:10:58 2016 +0000
- Revision:
- 6:5cc7136648d1
- Parent:
- 2:3bdf0d9bb71f
Library re-ported with all the latest and greatest stuff from Manicbug; Synced with TMRh20's RF24 library on Apr/18/2015 from https://github.com/TMRh20
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
akashvibhute | 2:3bdf0d9bb71f | 1 | /* |
akashvibhute | 2:3bdf0d9bb71f | 2 | Copyright (c) 2007 Stefan Engelke <mbox@stefanengelke.de> |
akashvibhute | 6:5cc7136648d1 | 3 | Portions Copyright (C) 2011 Greg Copeland |
akashvibhute | 2:3bdf0d9bb71f | 4 | |
akashvibhute | 2:3bdf0d9bb71f | 5 | Permission is hereby granted, free of charge, to any person |
akashvibhute | 2:3bdf0d9bb71f | 6 | obtaining a copy of this software and associated documentation |
akashvibhute | 2:3bdf0d9bb71f | 7 | files (the "Software"), to deal in the Software without |
akashvibhute | 2:3bdf0d9bb71f | 8 | restriction, including without limitation the rights to use, copy, |
akashvibhute | 2:3bdf0d9bb71f | 9 | modify, merge, publish, distribute, sublicense, and/or sell copies |
akashvibhute | 2:3bdf0d9bb71f | 10 | of the Software, and to permit persons to whom the Software is |
akashvibhute | 2:3bdf0d9bb71f | 11 | furnished to do so, subject to the following conditions: |
akashvibhute | 2:3bdf0d9bb71f | 12 | |
akashvibhute | 2:3bdf0d9bb71f | 13 | The above copyright notice and this permission notice shall be |
akashvibhute | 2:3bdf0d9bb71f | 14 | included in all copies or substantial portions of the Software. |
akashvibhute | 2:3bdf0d9bb71f | 15 | |
akashvibhute | 2:3bdf0d9bb71f | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
akashvibhute | 2:3bdf0d9bb71f | 17 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
akashvibhute | 2:3bdf0d9bb71f | 18 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
akashvibhute | 2:3bdf0d9bb71f | 19 | NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
akashvibhute | 2:3bdf0d9bb71f | 20 | HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
akashvibhute | 2:3bdf0d9bb71f | 21 | WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
akashvibhute | 2:3bdf0d9bb71f | 22 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
akashvibhute | 2:3bdf0d9bb71f | 23 | DEALINGS IN THE SOFTWARE. |
akashvibhute | 2:3bdf0d9bb71f | 24 | */ |
akashvibhute | 2:3bdf0d9bb71f | 25 | |
akashvibhute | 6:5cc7136648d1 | 26 | /* |
akashvibhute | 6:5cc7136648d1 | 27 | * Mbed support added by Akash Vibhute <akash.roboticist@gmail.com> |
akashvibhute | 6:5cc7136648d1 | 28 | * Porting completed on Nov/05/2015 |
akashvibhute | 6:5cc7136648d1 | 29 | * |
akashvibhute | 6:5cc7136648d1 | 30 | * Updated 1: Synced with TMRh20's RF24 library on Nov/04/2015 from https://github.com/TMRh20 |
akashvibhute | 6:5cc7136648d1 | 31 | * Updated 2: Synced with TMRh20's RF24 library on Apr/18/2015 from https://github.com/TMRh20 |
akashvibhute | 6:5cc7136648d1 | 32 | * |
akashvibhute | 6:5cc7136648d1 | 33 | */ |
akashvibhute | 6:5cc7136648d1 | 34 | |
akashvibhute | 2:3bdf0d9bb71f | 35 | /* Memory Map */ |
akashvibhute | 6:5cc7136648d1 | 36 | #define NRF_CONFIG 0x00 |
akashvibhute | 2:3bdf0d9bb71f | 37 | #define EN_AA 0x01 |
akashvibhute | 2:3bdf0d9bb71f | 38 | #define EN_RXADDR 0x02 |
akashvibhute | 2:3bdf0d9bb71f | 39 | #define SETUP_AW 0x03 |
akashvibhute | 2:3bdf0d9bb71f | 40 | #define SETUP_RETR 0x04 |
akashvibhute | 2:3bdf0d9bb71f | 41 | #define RF_CH 0x05 |
akashvibhute | 2:3bdf0d9bb71f | 42 | #define RF_SETUP 0x06 |
akashvibhute | 2:3bdf0d9bb71f | 43 | #define NRF_STATUS 0x07 |
akashvibhute | 2:3bdf0d9bb71f | 44 | #define OBSERVE_TX 0x08 |
akashvibhute | 2:3bdf0d9bb71f | 45 | #define CD 0x09 |
akashvibhute | 2:3bdf0d9bb71f | 46 | #define RX_ADDR_P0 0x0A |
akashvibhute | 2:3bdf0d9bb71f | 47 | #define RX_ADDR_P1 0x0B |
akashvibhute | 2:3bdf0d9bb71f | 48 | #define RX_ADDR_P2 0x0C |
akashvibhute | 2:3bdf0d9bb71f | 49 | #define RX_ADDR_P3 0x0D |
akashvibhute | 2:3bdf0d9bb71f | 50 | #define RX_ADDR_P4 0x0E |
akashvibhute | 2:3bdf0d9bb71f | 51 | #define RX_ADDR_P5 0x0F |
akashvibhute | 2:3bdf0d9bb71f | 52 | #define TX_ADDR 0x10 |
akashvibhute | 2:3bdf0d9bb71f | 53 | #define RX_PW_P0 0x11 |
akashvibhute | 2:3bdf0d9bb71f | 54 | #define RX_PW_P1 0x12 |
akashvibhute | 2:3bdf0d9bb71f | 55 | #define RX_PW_P2 0x13 |
akashvibhute | 2:3bdf0d9bb71f | 56 | #define RX_PW_P3 0x14 |
akashvibhute | 2:3bdf0d9bb71f | 57 | #define RX_PW_P4 0x15 |
akashvibhute | 2:3bdf0d9bb71f | 58 | #define RX_PW_P5 0x16 |
akashvibhute | 2:3bdf0d9bb71f | 59 | #define FIFO_STATUS 0x17 |
akashvibhute | 6:5cc7136648d1 | 60 | #define DYNPD 0x1C |
akashvibhute | 6:5cc7136648d1 | 61 | #define FEATURE 0x1D |
akashvibhute | 2:3bdf0d9bb71f | 62 | |
akashvibhute | 2:3bdf0d9bb71f | 63 | /* Bit Mnemonics */ |
akashvibhute | 2:3bdf0d9bb71f | 64 | #define MASK_RX_DR 6 |
akashvibhute | 2:3bdf0d9bb71f | 65 | #define MASK_TX_DS 5 |
akashvibhute | 2:3bdf0d9bb71f | 66 | #define MASK_MAX_RT 4 |
akashvibhute | 2:3bdf0d9bb71f | 67 | #define EN_CRC 3 |
akashvibhute | 2:3bdf0d9bb71f | 68 | #define CRCO 2 |
akashvibhute | 2:3bdf0d9bb71f | 69 | #define PWR_UP 1 |
akashvibhute | 2:3bdf0d9bb71f | 70 | #define PRIM_RX 0 |
akashvibhute | 2:3bdf0d9bb71f | 71 | #define ENAA_P5 5 |
akashvibhute | 2:3bdf0d9bb71f | 72 | #define ENAA_P4 4 |
akashvibhute | 2:3bdf0d9bb71f | 73 | #define ENAA_P3 3 |
akashvibhute | 2:3bdf0d9bb71f | 74 | #define ENAA_P2 2 |
akashvibhute | 2:3bdf0d9bb71f | 75 | #define ENAA_P1 1 |
akashvibhute | 2:3bdf0d9bb71f | 76 | #define ENAA_P0 0 |
akashvibhute | 2:3bdf0d9bb71f | 77 | #define ERX_P5 5 |
akashvibhute | 2:3bdf0d9bb71f | 78 | #define ERX_P4 4 |
akashvibhute | 2:3bdf0d9bb71f | 79 | #define ERX_P3 3 |
akashvibhute | 2:3bdf0d9bb71f | 80 | #define ERX_P2 2 |
akashvibhute | 2:3bdf0d9bb71f | 81 | #define ERX_P1 1 |
akashvibhute | 2:3bdf0d9bb71f | 82 | #define ERX_P0 0 |
akashvibhute | 2:3bdf0d9bb71f | 83 | #define AW 0 |
akashvibhute | 2:3bdf0d9bb71f | 84 | #define ARD 4 |
akashvibhute | 2:3bdf0d9bb71f | 85 | #define ARC 0 |
akashvibhute | 2:3bdf0d9bb71f | 86 | #define PLL_LOCK 4 |
akashvibhute | 2:3bdf0d9bb71f | 87 | #define RF_DR 3 |
akashvibhute | 2:3bdf0d9bb71f | 88 | #define RF_PWR 6 |
akashvibhute | 2:3bdf0d9bb71f | 89 | #define RX_DR 6 |
akashvibhute | 2:3bdf0d9bb71f | 90 | #define TX_DS 5 |
akashvibhute | 2:3bdf0d9bb71f | 91 | #define MAX_RT 4 |
akashvibhute | 2:3bdf0d9bb71f | 92 | #define RX_P_NO 1 |
akashvibhute | 2:3bdf0d9bb71f | 93 | #define TX_FULL 0 |
akashvibhute | 2:3bdf0d9bb71f | 94 | #define PLOS_CNT 4 |
akashvibhute | 2:3bdf0d9bb71f | 95 | #define ARC_CNT 0 |
akashvibhute | 2:3bdf0d9bb71f | 96 | #define TX_REUSE 6 |
akashvibhute | 2:3bdf0d9bb71f | 97 | #define FIFO_FULL 5 |
akashvibhute | 2:3bdf0d9bb71f | 98 | #define TX_EMPTY 4 |
akashvibhute | 2:3bdf0d9bb71f | 99 | #define RX_FULL 1 |
akashvibhute | 2:3bdf0d9bb71f | 100 | #define RX_EMPTY 0 |
akashvibhute | 6:5cc7136648d1 | 101 | #define DPL_P5 5 |
akashvibhute | 6:5cc7136648d1 | 102 | #define DPL_P4 4 |
akashvibhute | 6:5cc7136648d1 | 103 | #define DPL_P3 3 |
akashvibhute | 6:5cc7136648d1 | 104 | #define DPL_P2 2 |
akashvibhute | 6:5cc7136648d1 | 105 | #define DPL_P1 1 |
akashvibhute | 6:5cc7136648d1 | 106 | #define DPL_P0 0 |
akashvibhute | 6:5cc7136648d1 | 107 | #define EN_DPL 2 |
akashvibhute | 2:3bdf0d9bb71f | 108 | #define EN_ACK_PAY 1 |
akashvibhute | 2:3bdf0d9bb71f | 109 | #define EN_DYN_ACK 0 |
akashvibhute | 2:3bdf0d9bb71f | 110 | |
akashvibhute | 2:3bdf0d9bb71f | 111 | /* Instruction Mnemonics */ |
akashvibhute | 2:3bdf0d9bb71f | 112 | #define R_REGISTER 0x00 |
akashvibhute | 2:3bdf0d9bb71f | 113 | #define W_REGISTER 0x20 |
akashvibhute | 2:3bdf0d9bb71f | 114 | #define REGISTER_MASK 0x1F |
akashvibhute | 2:3bdf0d9bb71f | 115 | #define ACTIVATE 0x50 |
akashvibhute | 2:3bdf0d9bb71f | 116 | #define R_RX_PL_WID 0x60 |
akashvibhute | 2:3bdf0d9bb71f | 117 | #define R_RX_PAYLOAD 0x61 |
akashvibhute | 2:3bdf0d9bb71f | 118 | #define W_TX_PAYLOAD 0xA0 |
akashvibhute | 2:3bdf0d9bb71f | 119 | #define W_ACK_PAYLOAD 0xA8 |
akashvibhute | 2:3bdf0d9bb71f | 120 | #define FLUSH_TX 0xE1 |
akashvibhute | 2:3bdf0d9bb71f | 121 | #define FLUSH_RX 0xE2 |
akashvibhute | 2:3bdf0d9bb71f | 122 | #define REUSE_TX_PL 0xE3 |
akashvibhute | 2:3bdf0d9bb71f | 123 | #define NOP 0xFF |
akashvibhute | 2:3bdf0d9bb71f | 124 | |
akashvibhute | 2:3bdf0d9bb71f | 125 | /* Non-P omissions */ |
akashvibhute | 2:3bdf0d9bb71f | 126 | #define LNA_HCURR 0 |
akashvibhute | 2:3bdf0d9bb71f | 127 | |
akashvibhute | 2:3bdf0d9bb71f | 128 | /* P model memory Map */ |
akashvibhute | 2:3bdf0d9bb71f | 129 | #define RPD 0x09 |
akashvibhute | 2:3bdf0d9bb71f | 130 | #define W_TX_PAYLOAD_NO_ACK 0xB0 |
akashvibhute | 2:3bdf0d9bb71f | 131 | |
akashvibhute | 2:3bdf0d9bb71f | 132 | /* P model bit Mnemonics */ |
akashvibhute | 2:3bdf0d9bb71f | 133 | #define RF_DR_LOW 5 |
akashvibhute | 2:3bdf0d9bb71f | 134 | #define RF_DR_HIGH 3 |
akashvibhute | 2:3bdf0d9bb71f | 135 | #define RF_PWR_LOW 1 |
akashvibhute | 2:3bdf0d9bb71f | 136 | #define RF_PWR_HIGH 2 |
akashvibhute | 6:5cc7136648d1 | 137 | |
akashvibhute | 6:5cc7136648d1 | 138 |