interrupt handling
readerComm.h@3:eaae5433ab45, 2015-03-12 (annotated)
- Committer:
- rwclough
- Date:
- Thu Mar 12 15:05:36 2015 +0000
- Revision:
- 3:eaae5433ab45
- Parent:
- 2:bd5afc5aa139
- Child:
- 4:9ab0d84bbd07
Finally getting many, many IRQs. Now to see what's going on :)
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
rwclough | 1:1eb96189824d | 1 | /* |
rwclough | 2:bd5afc5aa139 | 2 | Header file for readerComm.cpp |
rwclough | 1:1eb96189824d | 3 | */ |
rwclough | 1:1eb96189824d | 4 | |
rwclough | 1:1eb96189824d | 5 | // Prototypes |
rwclough | 2:bd5afc5aa139 | 6 | void initialSettings(void); |
rwclough | 2:bd5afc5aa139 | 7 | void spiDirectCommand(uint8_t *buffer); |
rwclough | 2:bd5afc5aa139 | 8 | void spiWriteSingle(uint8_t *buffer, uint8_t length); |
rwclough | 2:bd5afc5aa139 | 9 | void spiReadSingle(uint8_t *buffer, uint8_t number); |
rwclough | 2:bd5afc5aa139 | 10 | void spiReadContinuous(uint8_t *buffer, uint8_t length); |
rwclough | 2:bd5afc5aa139 | 11 | void spiRawWrite(uint8_t *buffer, uint8_t length); |
rwclough | 2:bd5afc5aa139 | 12 | void stopDecoders(void); |
rwclough | 2:bd5afc5aa139 | 13 | void runDecoders(void); |
rwclough | 2:bd5afc5aa139 | 14 | void txNextSlot(void); |
rwclough | 2:bd5afc5aa139 | 15 | void disableSlotCounter(void); |
rwclough | 2:bd5afc5aa139 | 16 | void trf7970Reset(void); |
rwclough | 1:1eb96189824d | 17 | void turnRfOn(void); |
rwclough | 1:1eb96189824d | 18 | void turnRfOff(void); |
rwclough | 2:bd5afc5aa139 | 19 | void writeIsoControl(uint8_t iso_control); |
rwclough | 1:1eb96189824d | 20 | void iso15693FindTag(void); |
rwclough | 2:bd5afc5aa139 | 21 | void Iso15693Anticollision(uint8_t *mask, uint8_t length); |
rwclough | 1:1eb96189824d | 22 | |
rwclough | 1:1eb96189824d | 23 | // Booleans |
rwclough | 1:1eb96189824d | 24 | #define DESELECT 1 |
rwclough | 1:1eb96189824d | 25 | #define SELECT 0 |
rwclough | 1:1eb96189824d | 26 | #define ADDRESS 0 |
rwclough | 1:1eb96189824d | 27 | #define COMMAND 1 |
rwclough | 1:1eb96189824d | 28 | #define WRITE 0 |
rwclough | 1:1eb96189824d | 29 | #define READ 1 |
rwclough | 1:1eb96189824d | 30 | |
rwclough | 1:1eb96189824d | 31 | // Direct commands |
rwclough | 1:1eb96189824d | 32 | #define IDLE 0x00 |
rwclough | 1:1eb96189824d | 33 | #define SOFT_INIT 0x03 |
rwclough | 1:1eb96189824d | 34 | #define INITIAL_RF_COLLISION 0x04 |
rwclough | 1:1eb96189824d | 35 | #define RESPONSE_RF_COLLISION_N 0x05 |
rwclough | 1:1eb96189824d | 36 | #define RESPONSE_RF_COLLISION_0 0x06 |
rwclough | 1:1eb96189824d | 37 | #define RESET 0x0F |
rwclough | 1:1eb96189824d | 38 | #define TRANSMIT_NO_CRC 0x10 |
rwclough | 1:1eb96189824d | 39 | #define TRANSMIT_CRC 0x11 |
rwclough | 1:1eb96189824d | 40 | #define DELAY_TRANSMIT_NO_CRC 0x12 |
rwclough | 1:1eb96189824d | 41 | #define DELAY_TRANSMIT_CRC 0x13 |
rwclough | 1:1eb96189824d | 42 | #define TRANSMIT_NEXT_SLOT 0x14 |
rwclough | 1:1eb96189824d | 43 | #define CLOSE_SLOT_SEQUENCE 0x15 |
rwclough | 1:1eb96189824d | 44 | #define STOP_DECODERS 0x16 |
rwclough | 1:1eb96189824d | 45 | #define RUN_DECODERS 0x17 |
rwclough | 1:1eb96189824d | 46 | #define CHECK_INTERNAL_RF 0x18 |
rwclough | 1:1eb96189824d | 47 | #define CHECK_EXTERNAL_RF 0x19 |
rwclough | 1:1eb96189824d | 48 | #define ADJUST_GAIN 0x1A |
rwclough | 1:1eb96189824d | 49 | |
rwclough | 1:1eb96189824d | 50 | // Registers |
rwclough | 1:1eb96189824d | 51 | #define CHIP_STATUS_CONTROL 0x00 |
rwclough | 1:1eb96189824d | 52 | #define ISO_CONTROL 0x01 |
rwclough | 1:1eb96189824d | 53 | #define ISO_14443B_OPTIONS 0x02 |
rwclough | 1:1eb96189824d | 54 | #define ISO_14443A_OPTIONS 0x03 |
rwclough | 1:1eb96189824d | 55 | #define TX_TIMER_EPC_HIGH 0x04 |
rwclough | 1:1eb96189824d | 56 | #define TX_TIMER_EPC_LOW 0x05 |
rwclough | 1:1eb96189824d | 57 | #define TX_PULSE_LENGTH_CONTROL 0x06 |
rwclough | 1:1eb96189824d | 58 | #define RX_NO_RESPONSE_WAIT_TIME 0x07 |
rwclough | 1:1eb96189824d | 59 | #define RX_WAIT_TIME 0x08 |
rwclough | 1:1eb96189824d | 60 | #define MODULATOR_CONTROL 0x09 |
rwclough | 1:1eb96189824d | 61 | #define RX_SPECIAL_SETTINGS 0x0A |
rwclough | 1:1eb96189824d | 62 | #define REGULATOR_CONTROL 0x0B |
rwclough | 1:1eb96189824d | 63 | #define IRQ_STATUS 0x0C |
rwclough | 1:1eb96189824d | 64 | #define IRQ_MASK 0x0D |
rwclough | 1:1eb96189824d | 65 | #define COLLISION_POSITION 0x0E |
rwclough | 1:1eb96189824d | 66 | #define RSSI_LEVELS 0x0F |
rwclough | 1:1eb96189824d | 67 | #define SPECIAL_FUNCTION_1 0x10 |
rwclough | 1:1eb96189824d | 68 | #define SPECIAL_FUNCTION_2 0x11 |
rwclough | 1:1eb96189824d | 69 | #define RAM_0 0x12 |
rwclough | 1:1eb96189824d | 70 | #define RAM_1 0x13 |
rwclough | 1:1eb96189824d | 71 | #define FIFO_IRQ_LEVELS_ADJ 0x14 |
rwclough | 1:1eb96189824d | 72 | #define RESERVED 0x15 |
rwclough | 1:1eb96189824d | 73 | #define NFC_LOW_DETECTION 0x16 |
rwclough | 2:bd5afc5aa139 | 74 | #define NFCID 0x17 |
rwclough | 1:1eb96189824d | 75 | #define NFC_TARGET_LEVEL 0x18 |
rwclough | 1:1eb96189824d | 76 | #define NFC_TARGET_PROTOCOL 0x19 |
rwclough | 1:1eb96189824d | 77 | #define TEST_SETTINGS_1 0x1A |
rwclough | 1:1eb96189824d | 78 | #define TEST_SETTINGS_2 0x1B |
rwclough | 2:bd5afc5aa139 | 79 | #define FIFO_CONTROL 0x1C |
rwclough | 2:bd5afc5aa139 | 80 | #define TX_LENGTH_BYTE_1 0x1D |
rwclough | 2:bd5afc5aa139 | 81 | #define TX_LENGTH_BYTE_2 0x1E |
rwclough | 2:bd5afc5aa139 | 82 | #define FIFO 0x1F |
rwclough | 2:bd5afc5aa139 | 83 | |
rwclough | 2:bd5afc5aa139 | 84 | // BITs |
rwclough | 2:bd5afc5aa139 | 85 | #define BIT0 0x01 // 0b00000001 |
rwclough | 2:bd5afc5aa139 | 86 | #define BIT1 0x02 // 0b00000010 |
rwclough | 2:bd5afc5aa139 | 87 | #define BIT2 0x40 // 0b00000100 |
rwclough | 2:bd5afc5aa139 | 88 | #define BIT3 0x08 // 0b00001000 |
rwclough | 2:bd5afc5aa139 | 89 | #define BIT4 0x10 // 0b00010000 |
rwclough | 2:bd5afc5aa139 | 90 | #define BIT5 0x20 // 0b00100000 |
rwclough | 2:bd5afc5aa139 | 91 | #define BIT6 0x40 // 0b01000000 |
rwclough | 2:bd5afc5aa139 | 92 | #define BIT7 0x80 // 0b10000000 |
rwclough | 2:bd5afc5aa139 | 93 | |
rwclough | 2:bd5afc5aa139 | 94 | // Misc |
rwclough | 2:bd5afc5aa139 | 95 | #define SIXTEEN_SLOTS 0x06 |
rwclough | 2:bd5afc5aa139 | 96 | #define ONE_SLOT 0x26 |