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Dependencies:   MMA8451Q mbed xbee_lib

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SIM_MemMap Struct Reference
Data Fields

SIM_MemMap Struct Reference
[SIM]

SIM - Peripheral register structure. More...

#include <MKL25Z4.h>

Data Fields

uint32_t SOPT1
 System Options Register 1, offset: 0x0.
uint32_t SOPT1CFG
 SOPT1 Configuration Register, offset: 0x4.
uint32_t SOPT2
 System Options Register 2, offset: 0x1004.
uint32_t SOPT4
 System Options Register 4, offset: 0x100C.
uint32_t SOPT5
 System Options Register 5, offset: 0x1010.
uint32_t SOPT7
 System Options Register 7, offset: 0x1018.
uint32_t SDID
 System Device Identification Register, offset: 0x1024.
uint32_t SCGC4
 System Clock Gating Control Register 4, offset: 0x1034.
uint32_t SCGC5
 System Clock Gating Control Register 5, offset: 0x1038.
uint32_t SCGC6
 System Clock Gating Control Register 6, offset: 0x103C.
uint32_t SCGC7
 System Clock Gating Control Register 7, offset: 0x1040.
uint32_t CLKDIV1
 System Clock Divider Register 1, offset: 0x1044.
uint32_t FCFG1
 Flash Configuration Register 1, offset: 0x104C.
uint32_t FCFG2
 Flash Configuration Register 2, offset: 0x1050.
uint32_t UIDMH
 Unique Identification Register Mid-High, offset: 0x1058.
uint32_t UIDML
 Unique Identification Register Mid Low, offset: 0x105C.
uint32_t UIDL
 Unique Identification Register Low, offset: 0x1060.
uint32_t COPC
 COP Control Register, offset: 0x1100.
uint32_t SRVCOP
 Service COP Register, offset: 0x1104.

Detailed Description

SIM - Peripheral register structure.

Definition at line 4947 of file MKL25Z4.h.

Field Documentation

uint32_t CLKDIV1

System Clock Divider Register 1, offset: 0x1044.

Definition at line 4964 of file MKL25Z4.h.

uint32_t COPC

COP Control Register, offset: 0x1100.

Definition at line 4973 of file MKL25Z4.h.

uint32_t FCFG1

Flash Configuration Register 1, offset: 0x104C.

Definition at line 4966 of file MKL25Z4.h.

uint32_t FCFG2

Flash Configuration Register 2, offset: 0x1050.

Definition at line 4967 of file MKL25Z4.h.

uint32_t SCGC4

System Clock Gating Control Register 4, offset: 0x1034.

Definition at line 4960 of file MKL25Z4.h.

uint32_t SCGC5

System Clock Gating Control Register 5, offset: 0x1038.

Definition at line 4961 of file MKL25Z4.h.

uint32_t SCGC6

System Clock Gating Control Register 6, offset: 0x103C.

Definition at line 4962 of file MKL25Z4.h.

uint32_t SCGC7

System Clock Gating Control Register 7, offset: 0x1040.

Definition at line 4963 of file MKL25Z4.h.

uint32_t SDID

System Device Identification Register, offset: 0x1024.

Definition at line 4958 of file MKL25Z4.h.

uint32_t SOPT1

System Options Register 1, offset: 0x0.

Definition at line 4948 of file MKL25Z4.h.

uint32_t SOPT1CFG

SOPT1 Configuration Register, offset: 0x4.

Definition at line 4949 of file MKL25Z4.h.

uint32_t SOPT2

System Options Register 2, offset: 0x1004.

Definition at line 4951 of file MKL25Z4.h.

uint32_t SOPT4

System Options Register 4, offset: 0x100C.

Definition at line 4953 of file MKL25Z4.h.

uint32_t SOPT5

System Options Register 5, offset: 0x1010.

Definition at line 4954 of file MKL25Z4.h.

uint32_t SOPT7

System Options Register 7, offset: 0x1018.

Definition at line 4956 of file MKL25Z4.h.

uint32_t SRVCOP

Service COP Register, offset: 0x1104.

Definition at line 4974 of file MKL25Z4.h.

uint32_t UIDL

Unique Identification Register Low, offset: 0x1060.

Definition at line 4971 of file MKL25Z4.h.

uint32_t UIDMH

Unique Identification Register Mid-High, offset: 0x1058.

Definition at line 4969 of file MKL25Z4.h.

uint32_t UIDML

Unique Identification Register Mid Low, offset: 0x105C.

Definition at line 4970 of file MKL25Z4.h.

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