Freescale_Cachan / Mbed 2 deprecated Programme_course_base

Dependencies:   MMA8451Q mbed xbee_lib

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SCB_MemMap Struct Reference

SCB_MemMap Struct Reference
[SCB]

SCB - Peripheral register structure. More...

#include <MKL25Z4.h>

Data Fields

uint32_t ACTLR
 Auxiliary Control Register,, offset: 0x8.
uint32_t CPUID
 CPUID Base Register, offset: 0xD00.
uint32_t ICSR
 Interrupt Control and State Register, offset: 0xD04.
uint32_t VTOR
 Vector Table Offset Register, offset: 0xD08.
uint32_t AIRCR
 Application Interrupt and Reset Control Register, offset: 0xD0C.
uint32_t SCR
 System Control Register, offset: 0xD10.
uint32_t CCR
 Configuration and Control Register, offset: 0xD14.
uint32_t SHPR2
 System Handler Priority Register 2, offset: 0xD1C.
uint32_t SHPR3
 System Handler Priority Register 3, offset: 0xD20.
uint32_t SHCSR
 System Handler Control and State Register, offset: 0xD24.
uint32_t DFSR
 Debug Fault Status Register, offset: 0xD30.

Detailed Description

SCB - Peripheral register structure.

Definition at line 4753 of file MKL25Z4.h.


Field Documentation

uint32_t ACTLR

Auxiliary Control Register,, offset: 0x8.

Definition at line 4755 of file MKL25Z4.h.

uint32_t AIRCR

Application Interrupt and Reset Control Register, offset: 0xD0C.

Definition at line 4760 of file MKL25Z4.h.

uint32_t CCR

Configuration and Control Register, offset: 0xD14.

Definition at line 4762 of file MKL25Z4.h.

uint32_t CPUID

CPUID Base Register, offset: 0xD00.

Definition at line 4757 of file MKL25Z4.h.

uint32_t DFSR

Debug Fault Status Register, offset: 0xD30.

Definition at line 4768 of file MKL25Z4.h.

uint32_t ICSR

Interrupt Control and State Register, offset: 0xD04.

Definition at line 4758 of file MKL25Z4.h.

uint32_t SCR

System Control Register, offset: 0xD10.

Definition at line 4761 of file MKL25Z4.h.

uint32_t SHCSR

System Handler Control and State Register, offset: 0xD24.

Definition at line 4766 of file MKL25Z4.h.

uint32_t SHPR2

System Handler Priority Register 2, offset: 0xD1C.

Definition at line 4764 of file MKL25Z4.h.

uint32_t SHPR3

System Handler Priority Register 3, offset: 0xD20.

Definition at line 4765 of file MKL25Z4.h.

uint32_t VTOR

Vector Table Offset Register, offset: 0xD08.

Definition at line 4759 of file MKL25Z4.h.