n-Blocks-HALL / RM25C512C-L_driver
Committer:
ianaherne
Date:
Thu Sep 13 16:14:06 2018 +0000
Revision:
7:c562fe4d48de
Parent:
6:0434e89c2d68
Child:
8:d71c8068ace2
added timeouts to all write and erase functions changed some constants

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ianaherne 0:890f322344f2 1 #include "rm25c512cl.h"
ianaherne 0:890f322344f2 2
ianaherne 0:890f322344f2 3
ianaherne 0:890f322344f2 4 rm25c512cl::rm25c512cl(PinName MOSI,PinName MISO,PinName SCLK,PinName CS): _spi(MOSI,MISO,SCLK),_cs(CS){
ianaherne 1:67d99e4ce310 5
ianaherne 4:17e602b21ac5 6 _cs = HIGH; // always set chip select to initial state of high
ianaherne 0:890f322344f2 7
ianaherne 0:890f322344f2 8 }
ianaherne 0:890f322344f2 9
ianaherne 1:67d99e4ce310 10 /**
ianaherne 1:67d99e4ce310 11 * @brief write_enable()
ianaherne 1:67d99e4ce310 12 * @details Sets write enable latch to 1 to enable writing to eeprom uses the WREN opcode
ianaherne 1:67d99e4ce310 13 * @param NA
ianaherne 6:0434e89c2d68 14 * @return Success or failure of command
ianaherne 1:67d99e4ce310 15 * @warning Write or erase instructions will be ignored if this instruction is not issued first
ianaherne 1:67d99e4ce310 16 *
ianaherne 1:67d99e4ce310 17 */
ianaherne 1:67d99e4ce310 18
ianaherne 6:0434e89c2d68 19 bool rm25c512cl :: write_enable(){
ianaherne 0:890f322344f2 20
ianaherne 1:67d99e4ce310 21 char cmd[1];
ianaherne 1:67d99e4ce310 22 char data_buffer[1];// not used here but required for spi.write() as a parameter
ianaherne 6:0434e89c2d68 23 char status;
ianaherne 1:67d99e4ce310 24
ianaherne 1:67d99e4ce310 25 cmd[0] = WREN;
ianaherne 1:67d99e4ce310 26
ianaherne 1:67d99e4ce310 27 _spi.lock();
ianaherne 1:67d99e4ce310 28
ianaherne 4:17e602b21ac5 29 _cs = LOW;
ianaherne 1:67d99e4ce310 30
ianaherne 1:67d99e4ce310 31 _spi.write(&cmd[0],1,&data_buffer[0],0);
ianaherne 1:67d99e4ce310 32
ianaherne 4:17e602b21ac5 33 _cs = HIGH;
ianaherne 1:67d99e4ce310 34
ianaherne 1:67d99e4ce310 35 _spi.unlock();
ianaherne 1:67d99e4ce310 36
ianaherne 6:0434e89c2d68 37 status = read_status_reg();
ianaherne 6:0434e89c2d68 38 status = status & 0x2;
ianaherne 6:0434e89c2d68 39
ianaherne 6:0434e89c2d68 40 /* make sure write enable is completed, if not somthing is wrong with device*/
ianaherne 1:67d99e4ce310 41
ianaherne 6:0434e89c2d68 42 if(status == 2){ // device is enabled WEL bit = 1
ianaherne 6:0434e89c2d68 43
ianaherne 6:0434e89c2d68 44 return SUCCESS;
ianaherne 6:0434e89c2d68 45
ianaherne 6:0434e89c2d68 46 }
ianaherne 6:0434e89c2d68 47 else{// WEL bit is 0 device is dissabled
ianaherne 6:0434e89c2d68 48
ianaherne 6:0434e89c2d68 49 return FAILURE;
ianaherne 6:0434e89c2d68 50
ianaherne 6:0434e89c2d68 51 }
ianaherne 0:890f322344f2 52
ianaherne 0:890f322344f2 53 }
ianaherne 0:890f322344f2 54
ianaherne 1:67d99e4ce310 55 /**
ianaherne 1:67d99e4ce310 56 * @brief read_status_reg()
ianaherne 1:67d99e4ce310 57 * @details Reads the status register of EEprom using the RDSR opcode, the register
ianaherne 1:67d99e4ce310 58 * read can be used to determine if a write has completed, or the write protection status
ianaherne 1:67d99e4ce310 59 * @param NA
ianaherne 1:67d99e4ce310 60 * @return Current eight bit value of register
ianaherne 1:67d99e4ce310 61 * @warning
ianaherne 1:67d99e4ce310 62 *
ianaherne 1:67d99e4ce310 63 */
ianaherne 1:67d99e4ce310 64
ianaherne 1:67d99e4ce310 65 char rm25c512cl :: read_status_reg(){
ianaherne 1:67d99e4ce310 66
ianaherne 1:67d99e4ce310 67 char cmd[1];
ianaherne 1:67d99e4ce310 68 char data_buffer[1]; // to store value returned from EEprom status register
ianaherne 1:67d99e4ce310 69
ianaherne 1:67d99e4ce310 70
ianaherne 1:67d99e4ce310 71 cmd[0] = RDSR;
ianaherne 1:67d99e4ce310 72
ianaherne 1:67d99e4ce310 73 _spi.lock();
ianaherne 1:67d99e4ce310 74
ianaherne 4:17e602b21ac5 75 _cs = LOW;
ianaherne 1:67d99e4ce310 76
ianaherne 1:67d99e4ce310 77 _spi.write(&cmd[0],1,&data_buffer[0],0);
ianaherne 1:67d99e4ce310 78
ianaherne 1:67d99e4ce310 79 cmd[0] = 0xFF; // write garbage to read something back
ianaherne 1:67d99e4ce310 80
ianaherne 1:67d99e4ce310 81 _spi.write(&cmd[0],1,&data_buffer[0],1);
ianaherne 1:67d99e4ce310 82
ianaherne 4:17e602b21ac5 83 _cs = HIGH;
ianaherne 1:67d99e4ce310 84
ianaherne 1:67d99e4ce310 85 _spi.unlock();
ianaherne 1:67d99e4ce310 86
ianaherne 7:c562fe4d48de 87
ianaherne 1:67d99e4ce310 88
ianaherne 1:67d99e4ce310 89 return data_buffer[0];
ianaherne 1:67d99e4ce310 90
ianaherne 1:67d99e4ce310 91
ianaherne 1:67d99e4ce310 92 }
ianaherne 1:67d99e4ce310 93
ianaherne 1:67d99e4ce310 94 /**
ianaherne 1:67d99e4ce310 95 * @brief write_bytes()
ianaherne 1:67d99e4ce310 96 * @details Writes multiple bytes to the specified address given.
ianaherne 1:67d99e4ce310 97 * @param Starting address to write to.
ianaherne 1:67d99e4ce310 98 * @param Pointer to the data array containg bytes to be stored.
ianaherne 2:183d1d96f917 99 * @param Size of the data array in bytes.
ianaherne 7:c562fe4d48de 100 * @return if a timeout has occured i.e. device is busy for too long
ianaherne 1:67d99e4ce310 101 * @warning A page write(128 bytes) can take up to 5 ms to complete
ianaherne 1:67d99e4ce310 102 *
ianaherne 1:67d99e4ce310 103 */
ianaherne 1:67d99e4ce310 104
ianaherne 6:0434e89c2d68 105 bool rm25c512cl :: write_bytes(uint16_t address, char* data, uint16_t data_size){
ianaherne 1:67d99e4ce310 106
ianaherne 1:67d99e4ce310 107 char cmd[3];
ianaherne 1:67d99e4ce310 108 char data_buffer[1];// not used here but required for spi.write() as a parameter
ianaherne 6:0434e89c2d68 109 char status;
ianaherne 6:0434e89c2d68 110 uint32_t i = TIMEOUT_BYTES;
ianaherne 6:0434e89c2d68 111
ianaherne 0:890f322344f2 112
ianaherne 1:67d99e4ce310 113 cmd[0] = WR;
ianaherne 1:67d99e4ce310 114 cmd[1] = address >> 8;
ianaherne 1:67d99e4ce310 115 cmd[2] = address & 0x00FF;
ianaherne 1:67d99e4ce310 116
ianaherne 1:67d99e4ce310 117 _spi.lock();
ianaherne 1:67d99e4ce310 118
ianaherne 4:17e602b21ac5 119 _cs = LOW;
ianaherne 1:67d99e4ce310 120
ianaherne 1:67d99e4ce310 121 _spi.write(&cmd[0],3,&data_buffer[0],0);
ianaherne 2:183d1d96f917 122 _spi.write(&data[0],data_size,&data_buffer[0],0);
ianaherne 1:67d99e4ce310 123
ianaherne 4:17e602b21ac5 124 _cs = HIGH;
ianaherne 1:67d99e4ce310 125
ianaherne 1:67d99e4ce310 126 _spi.unlock();
ianaherne 1:67d99e4ce310 127
ianaherne 6:0434e89c2d68 128 /* make sure data has been written sucessfully by reading bit zero in status register*/
ianaherne 6:0434e89c2d68 129
ianaherne 6:0434e89c2d68 130 do{
ianaherne 6:0434e89c2d68 131
ianaherne 6:0434e89c2d68 132 status = read_status_reg();
ianaherne 6:0434e89c2d68 133 status = status & 0x1;
ianaherne 0:890f322344f2 134
ianaherne 6:0434e89c2d68 135 i--;
ianaherne 6:0434e89c2d68 136
ianaherne 7:c562fe4d48de 137 }while(status == BUSY && i>0);
ianaherne 6:0434e89c2d68 138
ianaherne 6:0434e89c2d68 139 /* if timeout elapses*/
ianaherne 6:0434e89c2d68 140
ianaherne 7:c562fe4d48de 141 if( i < 1 && status == BUSY){
ianaherne 6:0434e89c2d68 142
ianaherne 7:c562fe4d48de 143 return TIMEOUT_ERROR;
ianaherne 6:0434e89c2d68 144 }
ianaherne 6:0434e89c2d68 145 else {
ianaherne 7:c562fe4d48de 146 return TIMEOUT_OK;
ianaherne 6:0434e89c2d68 147 }
ianaherne 0:890f322344f2 148
ianaherne 0:890f322344f2 149 }
ianaherne 0:890f322344f2 150
ianaherne 1:67d99e4ce310 151 /**
ianaherne 1:67d99e4ce310 152 * @brief write_byte()
ianaherne 1:67d99e4ce310 153 * @details Writes a single byte to EEprom at the given address
ianaherne 1:67d99e4ce310 154 * @param Address to write to
ianaherne 1:67d99e4ce310 155 * @param Value to write in given address
ianaherne 7:c562fe4d48de 156 * @return if a timeout has occured i.e. device is busy for too long
ianaherne 1:67d99e4ce310 157 * @warning Byte write can take up to 100 us to complete
ianaherne 1:67d99e4ce310 158 *
ianaherne 1:67d99e4ce310 159 */
ianaherne 1:67d99e4ce310 160
ianaherne 7:c562fe4d48de 161 bool rm25c512cl :: write_byte(uint16_t address,char value){
ianaherne 1:67d99e4ce310 162
ianaherne 1:67d99e4ce310 163 char cmd[4];
ianaherne 1:67d99e4ce310 164 char data_buffer[1]; // not used here but required for spi.write() as a parameter
ianaherne 7:c562fe4d48de 165 char status;
ianaherne 7:c562fe4d48de 166 uint32_t i = TIMEOUT_BYTE;
ianaherne 1:67d99e4ce310 167
ianaherne 1:67d99e4ce310 168 cmd[0] = WR;
ianaherne 1:67d99e4ce310 169 cmd[1] = address >> 8;
ianaherne 1:67d99e4ce310 170 cmd[2] = address & 0x00FF;
ianaherne 1:67d99e4ce310 171 cmd[3] = value;
ianaherne 1:67d99e4ce310 172
ianaherne 1:67d99e4ce310 173 _spi.lock();
ianaherne 1:67d99e4ce310 174
ianaherne 4:17e602b21ac5 175 _cs = LOW;
ianaherne 1:67d99e4ce310 176
ianaherne 1:67d99e4ce310 177 _spi.write(&cmd[0],4,&data_buffer[0],0);
ianaherne 1:67d99e4ce310 178
ianaherne 4:17e602b21ac5 179 _cs = HIGH;
ianaherne 1:67d99e4ce310 180
ianaherne 1:67d99e4ce310 181 _spi.unlock();
ianaherne 1:67d99e4ce310 182
ianaherne 7:c562fe4d48de 183 /* keeps checking the WEL bit i status reg to make sure write completes*/
ianaherne 7:c562fe4d48de 184
ianaherne 7:c562fe4d48de 185 do{
ianaherne 7:c562fe4d48de 186
ianaherne 7:c562fe4d48de 187 status = read_status_reg();
ianaherne 7:c562fe4d48de 188 status = status & 0x1;
ianaherne 7:c562fe4d48de 189
ianaherne 7:c562fe4d48de 190 i--;
ianaherne 7:c562fe4d48de 191
ianaherne 7:c562fe4d48de 192 }while(status == BUSY && i>0);
ianaherne 7:c562fe4d48de 193
ianaherne 7:c562fe4d48de 194 /* if timeout elapses*/
ianaherne 7:c562fe4d48de 195
ianaherne 7:c562fe4d48de 196 if( i < 1 && status == BUSY){
ianaherne 7:c562fe4d48de 197
ianaherne 7:c562fe4d48de 198 return TIMEOUT_ERROR;
ianaherne 7:c562fe4d48de 199 }
ianaherne 7:c562fe4d48de 200 else {
ianaherne 7:c562fe4d48de 201 return TIMEOUT_OK;
ianaherne 7:c562fe4d48de 202 }
ianaherne 7:c562fe4d48de 203
ianaherne 7:c562fe4d48de 204
ianaherne 0:890f322344f2 205
ianaherne 0:890f322344f2 206 }
ianaherne 0:890f322344f2 207
ianaherne 1:67d99e4ce310 208 /**
ianaherne 1:67d99e4ce310 209 * @brief read_bytes()
ianaherne 3:e846980a1536 210 * @details Reads multiple bytes starting at given address.
ianaherne 1:67d99e4ce310 211 * @param Page Address to start reading from.
ianaherne 2:183d1d96f917 212 * @param Pointer to data buffer to store multiple bytes read from EEprom.
ianaherne 2:183d1d96f917 213 * @param Size of the data buffer in bytes.
ianaherne 1:67d99e4ce310 214 * @return
ianaherne 1:67d99e4ce310 215 * @warning Data buffer must be of size 128 bytes to read entire page.
ianaherne 1:67d99e4ce310 216 *
ianaherne 1:67d99e4ce310 217 */
ianaherne 1:67d99e4ce310 218
ianaherne 2:183d1d96f917 219 void rm25c512cl :: read_bytes(uint16_t address, char* data_buffer, uint16_t data_buffer_size){
ianaherne 1:67d99e4ce310 220
ianaherne 1:67d99e4ce310 221 char cmd[3];
ianaherne 1:67d99e4ce310 222
ianaherne 1:67d99e4ce310 223
ianaherne 1:67d99e4ce310 224 cmd[0] = READ;
ianaherne 1:67d99e4ce310 225 cmd[1] = address >> 8;
ianaherne 1:67d99e4ce310 226 cmd[2] = address & 0x00FF;
ianaherne 1:67d99e4ce310 227
ianaherne 1:67d99e4ce310 228
ianaherne 1:67d99e4ce310 229 _spi.lock();
ianaherne 1:67d99e4ce310 230
ianaherne 4:17e602b21ac5 231 _cs = LOW;
ianaherne 1:67d99e4ce310 232
ianaherne 1:67d99e4ce310 233 _spi.write(&cmd[0],3,&data_buffer[0],0);
ianaherne 1:67d99e4ce310 234
ianaherne 1:67d99e4ce310 235 cmd[0] = 0xFF;
ianaherne 1:67d99e4ce310 236
ianaherne 2:183d1d96f917 237 _spi.write(&cmd[0],1,&data_buffer[0],data_buffer_size);
ianaherne 1:67d99e4ce310 238
ianaherne 4:17e602b21ac5 239 _cs = HIGH;
ianaherne 1:67d99e4ce310 240
ianaherne 1:67d99e4ce310 241 _spi.unlock();
ianaherne 0:890f322344f2 242
ianaherne 0:890f322344f2 243
ianaherne 0:890f322344f2 244 }
ianaherne 0:890f322344f2 245
ianaherne 1:67d99e4ce310 246 /**
ianaherne 1:67d99e4ce310 247 * @brief read_byte()
ianaherne 1:67d99e4ce310 248 * @details Reads a byte of data at given address.
ianaherne 1:67d99e4ce310 249 * @param Address to read byte from.
ianaherne 1:67d99e4ce310 250 * @return Byte of data read from address.
ianaherne 1:67d99e4ce310 251 * @warning
ianaherne 1:67d99e4ce310 252 *
ianaherne 1:67d99e4ce310 253 */
ianaherne 1:67d99e4ce310 254
ianaherne 1:67d99e4ce310 255 char rm25c512cl :: read_byte(uint16_t address){
ianaherne 1:67d99e4ce310 256
ianaherne 1:67d99e4ce310 257 char cmd[3];
ianaherne 1:67d99e4ce310 258 char data_buffer[1];// To store data byte returned from EEprom
ianaherne 1:67d99e4ce310 259
ianaherne 1:67d99e4ce310 260 cmd[0] = READ;
ianaherne 1:67d99e4ce310 261 cmd[1] = address >> 8;
ianaherne 1:67d99e4ce310 262 cmd[2] = address & 0x00FF;
ianaherne 1:67d99e4ce310 263
ianaherne 1:67d99e4ce310 264 _spi.lock();
ianaherne 1:67d99e4ce310 265
ianaherne 4:17e602b21ac5 266 _cs = LOW;
ianaherne 1:67d99e4ce310 267
ianaherne 1:67d99e4ce310 268 _spi.write(&cmd[0],3,&data_buffer[0],0);
ianaherne 1:67d99e4ce310 269
ianaherne 1:67d99e4ce310 270 cmd[0] = 0xFF;
ianaherne 1:67d99e4ce310 271
ianaherne 1:67d99e4ce310 272 _spi.write(&cmd[0],1,&data_buffer[0],1);
ianaherne 1:67d99e4ce310 273
ianaherne 4:17e602b21ac5 274 _cs = HIGH;
ianaherne 1:67d99e4ce310 275
ianaherne 1:67d99e4ce310 276 _spi.unlock();
ianaherne 1:67d99e4ce310 277
ianaherne 1:67d99e4ce310 278 return data_buffer[0];
ianaherne 0:890f322344f2 279
ianaherne 3:e846980a1536 280 }
ianaherne 3:e846980a1536 281
ianaherne 3:e846980a1536 282 /**
ianaherne 3:e846980a1536 283 * @brief page_erase()
ianaherne 3:e846980a1536 284 * @details 128 byte erase at page address
ianaherne 3:e846980a1536 285 * @param Page address
ianaherne 7:c562fe4d48de 286 * @return if a timeout has occured i.e. device is busy for too long.
ianaherne 7:c562fe4d48de 287 * @warning Write enable must be called prior to calling this function or
ianaherne 3:e846980a1536 288 * instruction will be ignored.
ianaherne 3:e846980a1536 289 *
ianaherne 3:e846980a1536 290 */
ianaherne 3:e846980a1536 291
ianaherne 3:e846980a1536 292
ianaherne 7:c562fe4d48de 293 bool rm25c512cl :: page_erase(uint16_t address){
ianaherne 3:e846980a1536 294
ianaherne 3:e846980a1536 295 char cmd[3];
ianaherne 3:e846980a1536 296 char data_buffer[1];// not used here but required as function parameter
ianaherne 7:c562fe4d48de 297 char status;
ianaherne 7:c562fe4d48de 298 uint32_t i = TIMEOUT_BYTES;
ianaherne 3:e846980a1536 299
ianaherne 3:e846980a1536 300 cmd[0] = PERS;
ianaherne 3:e846980a1536 301 cmd[1] = address >> 8;
ianaherne 3:e846980a1536 302 cmd[2] = address & 0x00FF;
ianaherne 3:e846980a1536 303
ianaherne 3:e846980a1536 304 _spi.lock();
ianaherne 3:e846980a1536 305
ianaherne 4:17e602b21ac5 306 _cs = LOW;
ianaherne 3:e846980a1536 307
ianaherne 3:e846980a1536 308 _spi.write(&cmd[0],3,&data_buffer[0],0);
ianaherne 3:e846980a1536 309
ianaherne 4:17e602b21ac5 310 _cs = HIGH;
ianaherne 3:e846980a1536 311
ianaherne 3:e846980a1536 312 _spi.unlock();
ianaherne 3:e846980a1536 313
ianaherne 7:c562fe4d48de 314 /* keeps checking the WEL bit i status reg to make sure erase completes*/
ianaherne 7:c562fe4d48de 315
ianaherne 7:c562fe4d48de 316 do{
ianaherne 7:c562fe4d48de 317
ianaherne 7:c562fe4d48de 318 status = read_status_reg();
ianaherne 7:c562fe4d48de 319 status = status & 0x1;
ianaherne 7:c562fe4d48de 320
ianaherne 7:c562fe4d48de 321 i--;
ianaherne 7:c562fe4d48de 322
ianaherne 7:c562fe4d48de 323 }while(status == BUSY && i>0);
ianaherne 3:e846980a1536 324
ianaherne 7:c562fe4d48de 325 /* if timeout elapses*/
ianaherne 7:c562fe4d48de 326
ianaherne 7:c562fe4d48de 327 if( i < 1 && status == BUSY){
ianaherne 7:c562fe4d48de 328
ianaherne 7:c562fe4d48de 329 return TIMEOUT_ERROR;
ianaherne 7:c562fe4d48de 330 }
ianaherne 7:c562fe4d48de 331 else {
ianaherne 7:c562fe4d48de 332 return TIMEOUT_OK;
ianaherne 7:c562fe4d48de 333 }
ianaherne 7:c562fe4d48de 334
ianaherne 3:e846980a1536 335 }
ianaherne 3:e846980a1536 336
ianaherne 3:e846980a1536 337 /**
ianaherne 3:e846980a1536 338 * @brief chip_erase()
ianaherne 3:e846980a1536 339 * @details erases all memory on chip
ianaherne 3:e846980a1536 340 * @param NA
ianaherne 7:c562fe4d48de 341 * @return if a timeout has occured i.e. device is busy for too long
ianaherne 3:e846980a1536 342 * @warning write enable must be called prior to calling this function or or
ianaherne 7:c562fe4d48de 343 * instruction will be ignored.
ianaherne 3:e846980a1536 344 *
ianaherne 3:e846980a1536 345 */
ianaherne 3:e846980a1536 346
ianaherne 7:c562fe4d48de 347 bool rm25c512cl :: chip_erase(){
ianaherne 3:e846980a1536 348
ianaherne 3:e846980a1536 349 char cmd[1];
ianaherne 3:e846980a1536 350 char data_buffer[1];// not used here but required as function parameter
ianaherne 7:c562fe4d48de 351 char status;
ianaherne 7:c562fe4d48de 352 uint32_t i = TIMEOUT_BYTES;
ianaherne 3:e846980a1536 353
ianaherne 3:e846980a1536 354 cmd[0] = CERS;
ianaherne 3:e846980a1536 355
ianaherne 3:e846980a1536 356 _spi.lock();
ianaherne 3:e846980a1536 357
ianaherne 4:17e602b21ac5 358 _cs = LOW;
ianaherne 3:e846980a1536 359
ianaherne 3:e846980a1536 360 _spi.write(&cmd[0],1,&data_buffer[0],0);
ianaherne 3:e846980a1536 361
ianaherne 4:17e602b21ac5 362 _cs = HIGH;
ianaherne 3:e846980a1536 363
ianaherne 3:e846980a1536 364 _spi.unlock();
ianaherne 3:e846980a1536 365
ianaherne 7:c562fe4d48de 366 /* keeps checking the WEL bit i status reg to make sure erase completes*/
ianaherne 7:c562fe4d48de 367
ianaherne 7:c562fe4d48de 368 do{
ianaherne 7:c562fe4d48de 369
ianaherne 7:c562fe4d48de 370 status = read_status_reg();
ianaherne 7:c562fe4d48de 371 status = status & 0x1;
ianaherne 7:c562fe4d48de 372
ianaherne 7:c562fe4d48de 373 i--;
ianaherne 7:c562fe4d48de 374
ianaherne 7:c562fe4d48de 375 }while(status == BUSY && i>0);
ianaherne 7:c562fe4d48de 376
ianaherne 7:c562fe4d48de 377 /* if timeout elapses*/
ianaherne 7:c562fe4d48de 378
ianaherne 7:c562fe4d48de 379 if( i < 1 && status == BUSY){
ianaherne 7:c562fe4d48de 380
ianaherne 7:c562fe4d48de 381 return TIMEOUT_ERROR;
ianaherne 7:c562fe4d48de 382 }
ianaherne 7:c562fe4d48de 383 else {
ianaherne 7:c562fe4d48de 384 return TIMEOUT_OK;
ianaherne 7:c562fe4d48de 385 }
ianaherne 7:c562fe4d48de 386
ianaherne 3:e846980a1536 387
ianaherne 3:e846980a1536 388
ianaherne 3:e846980a1536 389 }
ianaherne 3:e846980a1536 390