Semtech SX1272 radio chipset driver - ported based on Semtech SX1276 driver.
Dependents: Elmo-Terminal LoRaWAN-test-app Elmo-Terminal-App LoRaWAN_Semtech_stack ... more
Diff: sx1272/sx1272.cpp
- Revision:
- 9:f53b11725565
- Parent:
- 8:ead3f4cc5923
- Child:
- 11:3133174407a2
diff -r ead3f4cc5923 -r f53b11725565 sx1272/sx1272.cpp --- a/sx1272/sx1272.cpp Wed Dec 16 14:25:04 2015 +0000 +++ b/sx1272/sx1272.cpp Tue Mar 15 23:27:19 2016 +0000 @@ -55,7 +55,7 @@ { wait_ms( 10 ); this->rxTx = 0; - this->rxBuffer = new uint8_t[RX_BUFFER_SIZE]; + this->rxTxBuffer = new uint8_t[RX_BUFFER_SIZE]; previousOpMode = RF_OPMODE_STANDBY; this->dioIrq = new DioIrqHandler[6]; @@ -77,7 +77,7 @@ SX1272::~SX1272( ) { - delete this->rxBuffer; + delete this->rxTxBuffer; delete this->dioIrq; } @@ -217,6 +217,14 @@ Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) ); Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) ); + if( fixLen == 1 ) + { + Write( REG_PAYLOADLENGTH, payloadLen ); + } + else + { + Write( REG_PAYLOADLENGTH, 0xFF ); // Set payload length to the maximum + } Write( REG_PACKETCONFIG1, ( Read( REG_PACKETCONFIG1 ) & RF_PACKETCONFIG1_CRC_MASK & @@ -230,6 +238,7 @@ this->settings.LoRa.Bandwidth = bandwidth; this->settings.LoRa.Datarate = datarate; this->settings.LoRa.Coderate = coderate; + this->settings.LoRa.PreambleLen = preambleLen; this->settings.LoRa.FixLen = fixLen; this->settings.LoRa.PayloadLen = payloadLen; this->settings.LoRa.CrcOn = crcOn; @@ -341,7 +350,7 @@ paConfig = Read( REG_PACONFIG ); paDac = Read( REG_PADAC ); - paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | (paBoost ? RF_PACONFIG_PASELECT_PABOOST : RF_PACONFIG_PASELECT_RFO); + paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel ); if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST ) { @@ -552,7 +561,7 @@ 28 + 16 * this->settings.LoRa.CrcOn - ( this->settings.LoRa.FixLen ? 20 : 0 ) ) / ( double )( 4 * this->settings.LoRa.Datarate - - ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 8 : 0 ) ) ) * + ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) * ( this->settings.LoRa.Coderate + 4 ); double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 ); double tPayload = nPayload * ts; @@ -592,6 +601,7 @@ } else { + memcpy1( rxTxBuffer, buffer, size ); this->settings.FskPacketHandler.ChunkSize = 32; } @@ -606,10 +616,12 @@ if( this->settings.LoRa.IqInverted == true ) { Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) ); + Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON ); } else { Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) ); + Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF ); } this->settings.LoRaPacketHandler.Size = size; @@ -671,8 +683,10 @@ // DIO4=Preamble // DIO5=ModeReady Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & + RF_DIOMAPPING1_DIO1_MASK & RF_DIOMAPPING1_DIO2_MASK ) | RF_DIOMAPPING1_DIO0_00 | + RF_DIOMAPPING1_DIO1_00 | RF_DIOMAPPING1_DIO2_11 ); Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK & @@ -693,10 +707,12 @@ if( this->settings.LoRa.IqInverted == true ) { Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) ); + Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON ); } else { Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) ); + Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF ); } rxContinuous = this->settings.LoRa.RxContinuous; @@ -735,7 +751,7 @@ break; } - memset( rxBuffer, 0, ( size_t )RX_BUFFER_SIZE ); + memset( rxTxBuffer, 0, ( size_t )RX_BUFFER_SIZE ); this->settings.State = RX; if( timeout != 0 ) @@ -752,7 +768,7 @@ rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen + ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + - 1.0 ) + 1.0 ) / + 1.0 ) + 10.0 ) / ( double )this->settings.Fsk.Datarate ) * 1e6 ) ; } @@ -784,7 +800,9 @@ // DIO4=LowBat // DIO5=ModeReady Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & - RF_DIOMAPPING1_DIO2_MASK ) ); + RF_DIOMAPPING1_DIO1_MASK & + RF_DIOMAPPING1_DIO2_MASK ) | + RF_DIOMAPPING1_DIO1_01 ); Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK & RF_DIOMAPPING2_MAP_MASK ) ); @@ -882,7 +900,6 @@ break; } return rssi; - } void SX1272::SetOpMode( uint8_t opMode ) @@ -996,46 +1013,49 @@ switch( this->settings.Modem ) { case MODEM_FSK: - irqFlags = Read( REG_IRQFLAGS2 ); - if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK ) + if( this->settings.Fsk.CrcOn == true ) { - // Clear Irqs - Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI | - RF_IRQFLAGS1_PREAMBLEDETECT | - RF_IRQFLAGS1_SYNCADDRESSMATCH ); - Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN ); + irqFlags = Read( REG_IRQFLAGS2 ); + if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK ) + { + // Clear Irqs + Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI | + RF_IRQFLAGS1_PREAMBLEDETECT | + RF_IRQFLAGS1_SYNCADDRESSMATCH ); + Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN ); - if( this->settings.Fsk.RxContinuous == false ) - { - //this->settings.State = RF_IDLE; - //TimerStart( &RxTimeoutSyncWord ); - this->settings.State = IDLE; - rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen + - ( ( Read( REG_SYNCCONFIG ) & - ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + - 1.0 ) + 1.0 ) / - ( double )this->settings.Fsk.Datarate ) * 1e6 ) ; + if( this->settings.Fsk.RxContinuous == false ) + { + //this->settings.State = RF_IDLE; + //TimerStart( &RxTimeoutSyncWord ); + this->settings.State = IDLE; + rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen + + ( ( Read( REG_SYNCCONFIG ) & + ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + + 1.0 ) + 1.0 ) / + ( double )this->settings.Fsk.Datarate ) * 1e6 ) ; - } - else - { - // Continuous mode restart Rx chain - Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK ); - } + } + else + { + // Continuous mode restart Rx chain + Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK ); + } - //TimerStop( &RxTimeoutTimer ); - rxTimeoutTimer.detach( ); + //TimerStop( &RxTimeoutTimer ); + rxTimeoutTimer.detach( ); - if( ( rxError != NULL ) ) - { - rxError( ); - } + if( ( rxError != NULL ) ) + { + rxError( ); + } - this->settings.FskPacketHandler.PreambleDetected = false; - this->settings.FskPacketHandler.SyncWordDetected = false; - this->settings.FskPacketHandler.NbBytes = 0; - this->settings.FskPacketHandler.Size = 0; - break; + this->settings.FskPacketHandler.PreambleDetected = false; + this->settings.FskPacketHandler.SyncWordDetected = false; + this->settings.FskPacketHandler.NbBytes = 0; + this->settings.FskPacketHandler.Size = 0; + break; + } } // Read received packet size @@ -1049,12 +1069,12 @@ { this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH ); } - ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); + ReadFifo( rxTxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); } else { - ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); + ReadFifo( rxTxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); } @@ -1076,7 +1096,7 @@ if( (rxDone != NULL ) ) { - rxDone( rxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 ); + rxDone( rxTxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 ); } this->settings.FskPacketHandler.PreambleDetected = false; this->settings.FskPacketHandler.SyncWordDetected = false; @@ -1140,7 +1160,7 @@ } this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES ); - ReadFifo( rxBuffer, this->settings.LoRaPacketHandler.Size ); + ReadFifo( rxTxBuffer, this->settings.LoRaPacketHandler.Size ); if( this->settings.LoRa.RxContinuous == false ) @@ -1151,7 +1171,7 @@ if( ( rxDone != NULL ) ) { - rxDone( rxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue ); + rxDone( rxTxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue ); } } break; @@ -1208,12 +1228,12 @@ if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh ) { - ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh ); + ReadFifo( ( rxTxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh ); this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh; } else { - ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); + ReadFifo( ( rxTxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); } break; @@ -1237,13 +1257,13 @@ // FifoLevel interrupt if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize ) { - WriteFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize ); + WriteFifo( ( rxTxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize ); this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize; } else { // Write the last chunk of data - WriteFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); + WriteFifo( rxTxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ); this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes; } break; @@ -1329,7 +1349,7 @@ case MODEM_FSK: break; case MODEM_LORA: - if( ( Read( REG_LR_IRQFLAGS ) & 0x01 ) == 0x01 ) + if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED ) { // Clear Irq Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED_MASK | RFLR_IRQFLAGS_CADDONE);