Engravity-CDU
Webserver basic for CDU
Dependencies: mbed
Fork of
EasyWebCR
by 
Igor Skochinsky
ethmac.h@0:12b53511e212, 2010-01-29 (annotated)
- Committer:
- igorsk
- Date:
- Fri Jan 29 21:46:31 2010 +0000
- Revision:
- 0:12b53511e212
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| igorsk | 0:12b53511e212 | 1 | /****************************************************************** |
| igorsk | 0:12b53511e212 | 2 | ***** ***** |
| igorsk | 0:12b53511e212 | 3 | ***** Name: cs8900.h ***** |
| igorsk | 0:12b53511e212 | 4 | ***** Ver.: 1.0 ***** |
| igorsk | 0:12b53511e212 | 5 | ***** Date: 07/05/2001 ***** |
| igorsk | 0:12b53511e212 | 6 | ***** Auth: Andreas Dannenberg ***** |
| igorsk | 0:12b53511e212 | 7 | ***** HTWK Leipzig ***** |
| igorsk | 0:12b53511e212 | 8 | ***** university of applied sciences ***** |
| igorsk | 0:12b53511e212 | 9 | ***** Germany ***** |
| igorsk | 0:12b53511e212 | 10 | ***** adannenb@et.htwk-leipzig.de ***** |
| igorsk | 0:12b53511e212 | 11 | ***** Func: header-file for cs8900.c ***** |
| igorsk | 0:12b53511e212 | 12 | ***** ***** |
| igorsk | 0:12b53511e212 | 13 | ******************************************************************/ |
| igorsk | 0:12b53511e212 | 14 | |
| igorsk | 0:12b53511e212 | 15 | // Modifications by Code Red Technologies for NXP LPC1768 |
| igorsk | 0:12b53511e212 | 16 | // Filename changed to ethmac.h as no longer for cs8900 |
| igorsk | 0:12b53511e212 | 17 | |
| igorsk | 0:12b53511e212 | 18 | // CodeRed - update for new header filename |
| igorsk | 0:12b53511e212 | 19 | //#ifndef __CS8900_H |
| igorsk | 0:12b53511e212 | 20 | //#define __CS8900_H |
| igorsk | 0:12b53511e212 | 21 | #ifndef __ETHMAC_H |
| igorsk | 0:12b53511e212 | 22 | #define __ETHMAC_H |
| igorsk | 0:12b53511e212 | 23 | |
| igorsk | 0:12b53511e212 | 24 | #define MYMAC_1 1 // our ethernet (MAC) address |
| igorsk | 0:12b53511e212 | 25 | #define MYMAC_2 2 // (MUST be unique in LAN!) |
| igorsk | 0:12b53511e212 | 26 | #define MYMAC_3 3 |
| igorsk | 0:12b53511e212 | 27 | #define MYMAC_4 4 |
| igorsk | 0:12b53511e212 | 28 | #define MYMAC_5 5 |
| igorsk | 0:12b53511e212 | 29 | #define MYMAC_6 6 |
| igorsk | 0:12b53511e212 | 30 | |
| igorsk | 0:12b53511e212 | 31 | |
| igorsk | 0:12b53511e212 | 32 | // CodeRed - commented out original CS8900 defines |
| igorsk | 0:12b53511e212 | 33 | /* |
| igorsk | 0:12b53511e212 | 34 | #define IOR BIT6 // CS8900's ISA-bus interface pins |
| igorsk | 0:12b53511e212 | 35 | #define IOW BIT7 |
| igorsk | 0:12b53511e212 | 36 | |
| igorsk | 0:12b53511e212 | 37 | // definitions for Crystal CS8900 ethernet-controller |
| igorsk | 0:12b53511e212 | 38 | // based on linux-header by Russel Nelson |
| igorsk | 0:12b53511e212 | 39 | |
| igorsk | 0:12b53511e212 | 40 | #define PP_ChipID 0x0000 // offset 0h -> Corp-ID |
| igorsk | 0:12b53511e212 | 41 | // offset 2h -> Model/Product Number |
| igorsk | 0:12b53511e212 | 42 | // offset 3h -> Chip Revision Number |
| igorsk | 0:12b53511e212 | 43 | |
| igorsk | 0:12b53511e212 | 44 | #define PP_ISAIOB 0x0020 // IO base address |
| igorsk | 0:12b53511e212 | 45 | #define PP_CS8900_ISAINT 0x0022 // ISA interrupt select |
| igorsk | 0:12b53511e212 | 46 | #define PP_CS8900_ISADMA 0x0024 // ISA Rec DMA channel |
| igorsk | 0:12b53511e212 | 47 | #define PP_ISASOF 0x0026 // ISA DMA offset |
| igorsk | 0:12b53511e212 | 48 | #define PP_DmaFrameCnt 0x0028 // ISA DMA Frame count |
| igorsk | 0:12b53511e212 | 49 | #define PP_DmaByteCnt 0x002A // ISA DMA Byte count |
| igorsk | 0:12b53511e212 | 50 | #define PP_CS8900_ISAMemB 0x002C // Memory base |
| igorsk | 0:12b53511e212 | 51 | #define PP_ISABootBase 0x0030 // Boot Prom base |
| igorsk | 0:12b53511e212 | 52 | #define PP_ISABootMask 0x0034 // Boot Prom Mask |
| igorsk | 0:12b53511e212 | 53 | |
| igorsk | 0:12b53511e212 | 54 | // EEPROM data and command registers |
| igorsk | 0:12b53511e212 | 55 | #define PP_EECMD 0x0040 // NVR Interface Command register |
| igorsk | 0:12b53511e212 | 56 | #define PP_EEData 0x0042 // NVR Interface Data Register |
| igorsk | 0:12b53511e212 | 57 | |
| igorsk | 0:12b53511e212 | 58 | // Configuration and control registers |
| igorsk | 0:12b53511e212 | 59 | #define PP_RxCFG 0x0102 // Rx Bus config |
| igorsk | 0:12b53511e212 | 60 | #define PP_RxCTL 0x0104 // Receive Control Register |
| igorsk | 0:12b53511e212 | 61 | #define PP_TxCFG 0x0106 // Transmit Config Register |
| igorsk | 0:12b53511e212 | 62 | #define PP_TxCMD 0x0108 // Transmit Command Register |
| igorsk | 0:12b53511e212 | 63 | #define PP_BufCFG 0x010A // Bus configuration Register |
| igorsk | 0:12b53511e212 | 64 | #define PP_LineCTL 0x0112 // Line Config Register |
| igorsk | 0:12b53511e212 | 65 | #define PP_SelfCTL 0x0114 // Self Command Register |
| igorsk | 0:12b53511e212 | 66 | #define PP_BusCTL 0x0116 // ISA bus control Register |
| igorsk | 0:12b53511e212 | 67 | #define PP_TestCTL 0x0118 // Test Register |
| igorsk | 0:12b53511e212 | 68 | |
| igorsk | 0:12b53511e212 | 69 | // Status and Event Registers |
| igorsk | 0:12b53511e212 | 70 | #define PP_ISQ 0x0120 // Interrupt Status |
| igorsk | 0:12b53511e212 | 71 | #define PP_RxEvent 0x0124 // Rx Event Register |
| igorsk | 0:12b53511e212 | 72 | #define PP_TxEvent 0x0128 // Tx Event Register |
| igorsk | 0:12b53511e212 | 73 | #define PP_BufEvent 0x012C // Bus Event Register |
| igorsk | 0:12b53511e212 | 74 | #define PP_RxMiss 0x0130 // Receive Miss Count |
| igorsk | 0:12b53511e212 | 75 | #define PP_TxCol 0x0132 // Transmit Collision Count |
| igorsk | 0:12b53511e212 | 76 | #define PP_LineST 0x0134 // Line State Register |
| igorsk | 0:12b53511e212 | 77 | #define PP_SelfST 0x0136 // Self State register |
| igorsk | 0:12b53511e212 | 78 | #define PP_BusST 0x0138 // Bus Status |
| igorsk | 0:12b53511e212 | 79 | #define PP_TDR 0x013C // Time Domain Reflectometry |
| igorsk | 0:12b53511e212 | 80 | |
| igorsk | 0:12b53511e212 | 81 | // Initiate Transmit Registers |
| igorsk | 0:12b53511e212 | 82 | #define PP_TxCommand 0x0144 // Tx Command |
| igorsk | 0:12b53511e212 | 83 | #define PP_TxLength 0x0146 // Tx Length |
| igorsk | 0:12b53511e212 | 84 | |
| igorsk | 0:12b53511e212 | 85 | // Adress Filter Registers |
| igorsk | 0:12b53511e212 | 86 | #define PP_LAF 0x0150 // Hash Table |
| igorsk | 0:12b53511e212 | 87 | #define PP_IA 0x0158 // Physical Address Register |
| igorsk | 0:12b53511e212 | 88 | |
| igorsk | 0:12b53511e212 | 89 | // Frame Location |
| igorsk | 0:12b53511e212 | 90 | #define PP_RxStatus 0x0400 // Receive start of frame |
| igorsk | 0:12b53511e212 | 91 | #define PP_RxLength 0x0402 // Receive Length of frame |
| igorsk | 0:12b53511e212 | 92 | #define PP_RxFrame 0x0404 // Receive frame pointer |
| igorsk | 0:12b53511e212 | 93 | #define PP_TxFrame 0x0A00 // Transmit frame pointer |
| igorsk | 0:12b53511e212 | 94 | |
| igorsk | 0:12b53511e212 | 95 | // Primary I/O Base Address. If no I/O base is supplied by the user, then this |
| igorsk | 0:12b53511e212 | 96 | // can be used as the default I/O base to access the PacketPage Area. |
| igorsk | 0:12b53511e212 | 97 | #define DEFAULTIOBASE 0x0300 |
| igorsk | 0:12b53511e212 | 98 | |
| igorsk | 0:12b53511e212 | 99 | // PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write |
| igorsk | 0:12b53511e212 | 100 | #define SKIP_1 0x0040 |
| igorsk | 0:12b53511e212 | 101 | #define RX_STREAM_ENBL 0x0080 |
| igorsk | 0:12b53511e212 | 102 | #define RX_OK_ENBL 0x0100 |
| igorsk | 0:12b53511e212 | 103 | #define RX_DMA_ONLY 0x0200 |
| igorsk | 0:12b53511e212 | 104 | #define AUTO_RX_DMA 0x0400 |
| igorsk | 0:12b53511e212 | 105 | #define BUFFER_CRC 0x0800 |
| igorsk | 0:12b53511e212 | 106 | #define RX_CRC_ERROR_ENBL 0x1000 |
| igorsk | 0:12b53511e212 | 107 | #define RX_RUNT_ENBL 0x2000 |
| igorsk | 0:12b53511e212 | 108 | #define RX_EXTRA_DATA_ENBL 0x4000 |
| igorsk | 0:12b53511e212 | 109 | |
| igorsk | 0:12b53511e212 | 110 | // PP_RxCTL - Receive Control bit definition - Read/write |
| igorsk | 0:12b53511e212 | 111 | #define RX_IA_HASH_ACCEPT 0x0040 |
| igorsk | 0:12b53511e212 | 112 | #define RX_PROM_ACCEPT 0x0080 |
| igorsk | 0:12b53511e212 | 113 | #define RX_OK_ACCEPT 0x0100 |
| igorsk | 0:12b53511e212 | 114 | #define RX_MULTCAST_ACCEPT 0x0200 |
| igorsk | 0:12b53511e212 | 115 | #define RX_IA_ACCEPT 0x0400 |
| igorsk | 0:12b53511e212 | 116 | #define RX_BROADCAST_ACCEPT 0x0800 |
| igorsk | 0:12b53511e212 | 117 | #define RX_BAD_CRC_ACCEPT 0x1000 |
| igorsk | 0:12b53511e212 | 118 | #define RX_RUNT_ACCEPT 0x2000 |
| igorsk | 0:12b53511e212 | 119 | #define RX_EXTRA_DATA_ACCEPT 0x4000 |
| igorsk | 0:12b53511e212 | 120 | |
| igorsk | 0:12b53511e212 | 121 | // PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write |
| igorsk | 0:12b53511e212 | 122 | #define TX_LOST_CRS_ENBL 0x0040 |
| igorsk | 0:12b53511e212 | 123 | #define TX_SQE_ERROR_ENBL 0x0080 |
| igorsk | 0:12b53511e212 | 124 | #define TX_OK_ENBL 0x0100 |
| igorsk | 0:12b53511e212 | 125 | #define TX_LATE_COL_ENBL 0x0200 |
| igorsk | 0:12b53511e212 | 126 | #define TX_JBR_ENBL 0x0400 |
| igorsk | 0:12b53511e212 | 127 | #define TX_ANY_COL_ENBL 0x0800 |
| igorsk | 0:12b53511e212 | 128 | #define TX_16_COL_ENBL 0x8000 |
| igorsk | 0:12b53511e212 | 129 | |
| igorsk | 0:12b53511e212 | 130 | // PP_TxCMD - Transmit Command bit definition - Read-only and |
| igorsk | 0:12b53511e212 | 131 | // PP_TxCommand - Write-only |
| igorsk | 0:12b53511e212 | 132 | #define TX_START_5_BYTES 0x0000 |
| igorsk | 0:12b53511e212 | 133 | #define TX_START_381_BYTES 0x0040 |
| igorsk | 0:12b53511e212 | 134 | #define TX_START_1021_BYTES 0x0080 |
| igorsk | 0:12b53511e212 | 135 | #define TX_START_ALL_BYTES 0x00C0 |
| igorsk | 0:12b53511e212 | 136 | #define TX_FORCE 0x0100 |
| igorsk | 0:12b53511e212 | 137 | #define TX_ONE_COL 0x0200 |
| igorsk | 0:12b53511e212 | 138 | #define TX_NO_CRC 0x1000 |
| igorsk | 0:12b53511e212 | 139 | #define TX_RUNT 0x2000 |
| igorsk | 0:12b53511e212 | 140 | |
| igorsk | 0:12b53511e212 | 141 | // PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write |
| igorsk | 0:12b53511e212 | 142 | #define GENERATE_SW_INTERRUPT 0x0040 |
| igorsk | 0:12b53511e212 | 143 | #define RX_DMA_ENBL 0x0080 |
| igorsk | 0:12b53511e212 | 144 | #define READY_FOR_TX_ENBL 0x0100 |
| igorsk | 0:12b53511e212 | 145 | #define TX_UNDERRUN_ENBL 0x0200 |
| igorsk | 0:12b53511e212 | 146 | #define RX_MISS_ENBL 0x0400 |
| igorsk | 0:12b53511e212 | 147 | #define RX_128_BYTE_ENBL 0x0800 |
| igorsk | 0:12b53511e212 | 148 | #define TX_COL_COUNT_OVRFLOW_ENBL 0x1000 |
| igorsk | 0:12b53511e212 | 149 | #define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000 |
| igorsk | 0:12b53511e212 | 150 | #define RX_DEST_MATCH_ENBL 0x8000 |
| igorsk | 0:12b53511e212 | 151 | |
| igorsk | 0:12b53511e212 | 152 | // PP_LineCTL - Line Control bit definition - Read/write |
| igorsk | 0:12b53511e212 | 153 | #define SERIAL_RX_ON 0x0040 |
| igorsk | 0:12b53511e212 | 154 | #define SERIAL_TX_ON 0x0080 |
| igorsk | 0:12b53511e212 | 155 | #define AUI_ONLY 0x0100 |
| igorsk | 0:12b53511e212 | 156 | #define AUTO_AUI_10BASET 0x0200 |
| igorsk | 0:12b53511e212 | 157 | #define MODIFIED_BACKOFF 0x0800 |
| igorsk | 0:12b53511e212 | 158 | #define NO_AUTO_POLARITY 0x1000 |
| igorsk | 0:12b53511e212 | 159 | #define TWO_PART_DEFDIS 0x2000 |
| igorsk | 0:12b53511e212 | 160 | #define LOW_RX_SQUELCH 0x4000 |
| igorsk | 0:12b53511e212 | 161 | |
| igorsk | 0:12b53511e212 | 162 | // PP_SelfCTL - Software Self Control bit definition - Read/write |
| igorsk | 0:12b53511e212 | 163 | #define POWER_ON_RESET 0x0040 |
| igorsk | 0:12b53511e212 | 164 | #define SW_STOP 0x0100 |
| igorsk | 0:12b53511e212 | 165 | #define SLEEP_ON 0x0200 |
| igorsk | 0:12b53511e212 | 166 | #define AUTO_WAKEUP 0x0400 |
| igorsk | 0:12b53511e212 | 167 | #define HCB0_ENBL 0x1000 |
| igorsk | 0:12b53511e212 | 168 | #define HCB1_ENBL 0x2000 |
| igorsk | 0:12b53511e212 | 169 | #define HCB0 0x4000 |
| igorsk | 0:12b53511e212 | 170 | #define HCB1 0x8000 |
| igorsk | 0:12b53511e212 | 171 | |
| igorsk | 0:12b53511e212 | 172 | // PP_BusCTL - ISA Bus Control bit definition - Read/write |
| igorsk | 0:12b53511e212 | 173 | #define RESET_RX_DMA 0x0040 |
| igorsk | 0:12b53511e212 | 174 | #define MEMORY_ON 0x0400 |
| igorsk | 0:12b53511e212 | 175 | #define DMA_BURST_MODE 0x0800 |
| igorsk | 0:12b53511e212 | 176 | #define IO_CHANNEL_READY_ON 0x1000 |
| igorsk | 0:12b53511e212 | 177 | #define RX_DMA_SIZE_64K 0x2000 |
| igorsk | 0:12b53511e212 | 178 | #define ENABLE_IRQ 0x8000 |
| igorsk | 0:12b53511e212 | 179 | |
| igorsk | 0:12b53511e212 | 180 | // PP_TestCTL - Test Control bit definition - Read/write |
| igorsk | 0:12b53511e212 | 181 | #define LINK_OFF 0x0080 |
| igorsk | 0:12b53511e212 | 182 | #define ENDEC_LOOPBACK 0x0200 |
| igorsk | 0:12b53511e212 | 183 | #define AUI_LOOPBACK 0x0400 |
| igorsk | 0:12b53511e212 | 184 | #define BACKOFF_OFF 0x0800 |
| igorsk | 0:12b53511e212 | 185 | #define FDX_8900 0x4000 |
| igorsk | 0:12b53511e212 | 186 | |
| igorsk | 0:12b53511e212 | 187 | // PP_RxEvent - Receive Event Bit definition - Read-only |
| igorsk | 0:12b53511e212 | 188 | #define RX_IA_HASHED 0x0040 |
| igorsk | 0:12b53511e212 | 189 | #define RX_DRIBBLE 0x0080 |
| igorsk | 0:12b53511e212 | 190 | #define RX_OK 0x0100 |
| igorsk | 0:12b53511e212 | 191 | #define RX_HASHED 0x0200 |
| igorsk | 0:12b53511e212 | 192 | #define RX_IA 0x0400 |
| igorsk | 0:12b53511e212 | 193 | #define RX_BROADCAST 0x0800 |
| igorsk | 0:12b53511e212 | 194 | #define RX_CRC_ERROR 0x1000 |
| igorsk | 0:12b53511e212 | 195 | #define RX_RUNT 0x2000 |
| igorsk | 0:12b53511e212 | 196 | #define RX_EXTRA_DATA 0x4000 |
| igorsk | 0:12b53511e212 | 197 | #define HASH_INDEX_MASK 0xFC00 // Hash-Table Index Mask (6 Bit) |
| igorsk | 0:12b53511e212 | 198 | |
| igorsk | 0:12b53511e212 | 199 | // PP_TxEvent - Transmit Event Bit definition - Read-only |
| igorsk | 0:12b53511e212 | 200 | #define TX_LOST_CRS 0x0040 |
| igorsk | 0:12b53511e212 | 201 | #define TX_SQE_ERROR 0x0080 |
| igorsk | 0:12b53511e212 | 202 | #define TX_OK 0x0100 |
| igorsk | 0:12b53511e212 | 203 | #define TX_LATE_COL 0x0200 |
| igorsk | 0:12b53511e212 | 204 | #define TX_JBR 0x0400 |
| igorsk | 0:12b53511e212 | 205 | #define TX_16_COL 0x8000 |
| igorsk | 0:12b53511e212 | 206 | #define TX_COL_COUNT_MASK 0x7800 |
| igorsk | 0:12b53511e212 | 207 | |
| igorsk | 0:12b53511e212 | 208 | // PP_BufEvent - Buffer Event Bit definition - Read-only |
| igorsk | 0:12b53511e212 | 209 | #define SW_INTERRUPT 0x0040 |
| igorsk | 0:12b53511e212 | 210 | #define RX_DMA 0x0080 |
| igorsk | 0:12b53511e212 | 211 | #define READY_FOR_TX 0x0100 |
| igorsk | 0:12b53511e212 | 212 | #define TX_UNDERRUN 0x0200 |
| igorsk | 0:12b53511e212 | 213 | #define RX_MISS 0x0400 |
| igorsk | 0:12b53511e212 | 214 | #define RX_128_BYTE 0x0800 |
| igorsk | 0:12b53511e212 | 215 | #define TX_COL_OVRFLW 0x1000 |
| igorsk | 0:12b53511e212 | 216 | #define RX_MISS_OVRFLW 0x2000 |
| igorsk | 0:12b53511e212 | 217 | #define RX_DEST_MATCH 0x8000 |
| igorsk | 0:12b53511e212 | 218 | |
| igorsk | 0:12b53511e212 | 219 | // PP_LineST - Ethernet Line Status bit definition - Read-only |
| igorsk | 0:12b53511e212 | 220 | #define LINK_OK 0x0080 |
| igorsk | 0:12b53511e212 | 221 | #define AUI_ON 0x0100 |
| igorsk | 0:12b53511e212 | 222 | #define TENBASET_ON 0x0200 |
| igorsk | 0:12b53511e212 | 223 | #define POLARITY_OK 0x1000 |
| igorsk | 0:12b53511e212 | 224 | #define CRS_OK 0x4000 |
| igorsk | 0:12b53511e212 | 225 | |
| igorsk | 0:12b53511e212 | 226 | // PP_SelfST - Chip Software Status bit definition |
| igorsk | 0:12b53511e212 | 227 | #define ACTIVE_33V 0x0040 |
| igorsk | 0:12b53511e212 | 228 | #define INIT_DONE 0x0080 |
| igorsk | 0:12b53511e212 | 229 | #define SI_BUSY 0x0100 |
| igorsk | 0:12b53511e212 | 230 | #define EEPROM_PRESENT 0x0200 |
| igorsk | 0:12b53511e212 | 231 | #define EEPROM_OK 0x0400 |
| igorsk | 0:12b53511e212 | 232 | #define EL_PRESENT 0x0800 |
| igorsk | 0:12b53511e212 | 233 | #define EE_SIZE_64 0x1000 |
| igorsk | 0:12b53511e212 | 234 | |
| igorsk | 0:12b53511e212 | 235 | // PP_BusST - ISA Bus Status bit definition |
| igorsk | 0:12b53511e212 | 236 | #define TX_BID_ERROR 0x0080 |
| igorsk | 0:12b53511e212 | 237 | #define READY_FOR_TX_NOW 0x0100 |
| igorsk | 0:12b53511e212 | 238 | |
| igorsk | 0:12b53511e212 | 239 | // The following block defines the ISQ event types |
| igorsk | 0:12b53511e212 | 240 | #define ISQ_RX_EVENT 0x0004 |
| igorsk | 0:12b53511e212 | 241 | #define ISQ_TX_EVENT 0x0008 |
| igorsk | 0:12b53511e212 | 242 | #define ISQ_BUFFER_EVENT 0x000C |
| igorsk | 0:12b53511e212 | 243 | #define ISQ_RX_MISS_EVENT 0x0010 |
| igorsk | 0:12b53511e212 | 244 | #define ISQ_TX_COL_EVENT 0x0012 |
| igorsk | 0:12b53511e212 | 245 | |
| igorsk | 0:12b53511e212 | 246 | #define ISQ_EVENT_MASK 0x003F // ISQ mask to find out type of event |
| igorsk | 0:12b53511e212 | 247 | |
| igorsk | 0:12b53511e212 | 248 | // Ports for I/O-Mode |
| igorsk | 0:12b53511e212 | 249 | #define RX_FRAME_PORT 0x0000 |
| igorsk | 0:12b53511e212 | 250 | #define TX_FRAME_PORT 0x0000 |
| igorsk | 0:12b53511e212 | 251 | #define TX_CMD_PORT 0x0004 |
| igorsk | 0:12b53511e212 | 252 | #define TX_LEN_PORT 0x0006 |
| igorsk | 0:12b53511e212 | 253 | #define ISQ_PORT 0x0008 |
| igorsk | 0:12b53511e212 | 254 | #define ADD_PORT 0x000A |
| igorsk | 0:12b53511e212 | 255 | #define DATA_PORT 0x000C |
| igorsk | 0:12b53511e212 | 256 | |
| igorsk | 0:12b53511e212 | 257 | #define AUTOINCREMENT 0x8000 // Bit mask to set Bit-15 for autoincrement |
| igorsk | 0:12b53511e212 | 258 | |
| igorsk | 0:12b53511e212 | 259 | // EEProm Commands |
| igorsk | 0:12b53511e212 | 260 | #define EEPROM_WRITE_EN 0x00F0 |
| igorsk | 0:12b53511e212 | 261 | #define EEPROM_WRITE_DIS 0x0000 |
| igorsk | 0:12b53511e212 | 262 | #define EEPROM_WRITE_CMD 0x0100 |
| igorsk | 0:12b53511e212 | 263 | #define EEPROM_READ_CMD 0x0200 |
| igorsk | 0:12b53511e212 | 264 | |
| igorsk | 0:12b53511e212 | 265 | // Receive Header of each packet in receive area of memory for DMA-Mode |
| igorsk | 0:12b53511e212 | 266 | #define RBUF_EVENT_LOW 0x0000 // Low byte of RxEvent |
| igorsk | 0:12b53511e212 | 267 | #define RBUF_EVENT_HIGH 0x0001 // High byte of RxEvent |
| igorsk | 0:12b53511e212 | 268 | #define RBUF_LEN_LOW 0x0002 // Length of received data - low byte |
| igorsk | 0:12b53511e212 | 269 | #define RBUF_LEN_HI 0x0003 // Length of received data - high byte |
| igorsk | 0:12b53511e212 | 270 | #define RBUF_HEAD_LEN 0x0004 // Length of this header |
| igorsk | 0:12b53511e212 | 271 | |
| igorsk | 0:12b53511e212 | 272 | // CodeRed - end of original CS8900 defines |
| igorsk | 0:12b53511e212 | 273 | */ |
| igorsk | 0:12b53511e212 | 274 | |
| igorsk | 0:12b53511e212 | 275 | // ******* |
| igorsk | 0:12b53511e212 | 276 | // CodeRed - defines for LPC1768 ethernet |
| igorsk | 0:12b53511e212 | 277 | // ******* |
| igorsk | 0:12b53511e212 | 278 | |
| igorsk | 0:12b53511e212 | 279 | /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ |
| igorsk | 0:12b53511e212 | 280 | #define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ |
| igorsk | 0:12b53511e212 | 281 | #define NUM_TX_FRAG 2 /* Num.of TX Fragments 3*1536= 4.6kB */ |
| igorsk | 0:12b53511e212 | 282 | #define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ |
| igorsk | 0:12b53511e212 | 283 | |
| igorsk | 0:12b53511e212 | 284 | #define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ |
| igorsk | 0:12b53511e212 | 285 | |
| igorsk | 0:12b53511e212 | 286 | /* EMAC variables located in AHB SRAM bank 1*/ |
| igorsk | 0:12b53511e212 | 287 | // Below is base address for first silicon |
| igorsk | 0:12b53511e212 | 288 | //#define RX_DESC_BASE 0x20004000 |
| igorsk | 0:12b53511e212 | 289 | // Below is base address for production silicon |
| igorsk | 0:12b53511e212 | 290 | #define RX_DESC_BASE 0x2007c000 |
| igorsk | 0:12b53511e212 | 291 | #define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8) |
| igorsk | 0:12b53511e212 | 292 | #define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8) |
| igorsk | 0:12b53511e212 | 293 | #define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8) |
| igorsk | 0:12b53511e212 | 294 | #define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4) |
| igorsk | 0:12b53511e212 | 295 | #define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE) |
| igorsk | 0:12b53511e212 | 296 | |
| igorsk | 0:12b53511e212 | 297 | /* RX and TX descriptor and status definitions. */ |
| igorsk | 0:12b53511e212 | 298 | #define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i)) |
| igorsk | 0:12b53511e212 | 299 | #define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i)) |
| igorsk | 0:12b53511e212 | 300 | #define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i)) |
| igorsk | 0:12b53511e212 | 301 | #define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i)) |
| igorsk | 0:12b53511e212 | 302 | #define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i)) |
| igorsk | 0:12b53511e212 | 303 | #define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i)) |
| igorsk | 0:12b53511e212 | 304 | #define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i)) |
| igorsk | 0:12b53511e212 | 305 | #define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i) |
| igorsk | 0:12b53511e212 | 306 | #define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i) |
| igorsk | 0:12b53511e212 | 307 | |
| igorsk | 0:12b53511e212 | 308 | /* MAC Configuration Register 1 */ |
| igorsk | 0:12b53511e212 | 309 | #define MAC1_REC_EN 0x00000001 /* Receive Enable */ |
| igorsk | 0:12b53511e212 | 310 | #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ |
| igorsk | 0:12b53511e212 | 311 | #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ |
| igorsk | 0:12b53511e212 | 312 | #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ |
| igorsk | 0:12b53511e212 | 313 | #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ |
| igorsk | 0:12b53511e212 | 314 | #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ |
| igorsk | 0:12b53511e212 | 315 | #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ |
| igorsk | 0:12b53511e212 | 316 | #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ |
| igorsk | 0:12b53511e212 | 317 | #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ |
| igorsk | 0:12b53511e212 | 318 | #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ |
| igorsk | 0:12b53511e212 | 319 | #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ |
| igorsk | 0:12b53511e212 | 320 | |
| igorsk | 0:12b53511e212 | 321 | /* MAC Configuration Register 2 */ |
| igorsk | 0:12b53511e212 | 322 | #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ |
| igorsk | 0:12b53511e212 | 323 | #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ |
| igorsk | 0:12b53511e212 | 324 | #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ |
| igorsk | 0:12b53511e212 | 325 | #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ |
| igorsk | 0:12b53511e212 | 326 | #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ |
| igorsk | 0:12b53511e212 | 327 | #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ |
| igorsk | 0:12b53511e212 | 328 | #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ |
| igorsk | 0:12b53511e212 | 329 | #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ |
| igorsk | 0:12b53511e212 | 330 | #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ |
| igorsk | 0:12b53511e212 | 331 | #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ |
| igorsk | 0:12b53511e212 | 332 | #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ |
| igorsk | 0:12b53511e212 | 333 | #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ |
| igorsk | 0:12b53511e212 | 334 | #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ |
| igorsk | 0:12b53511e212 | 335 | |
| igorsk | 0:12b53511e212 | 336 | /* Back-to-Back Inter-Packet-Gap Register */ |
| igorsk | 0:12b53511e212 | 337 | #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ |
| igorsk | 0:12b53511e212 | 338 | #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ |
| igorsk | 0:12b53511e212 | 339 | |
| igorsk | 0:12b53511e212 | 340 | /* Non Back-to-Back Inter-Packet-Gap Register */ |
| igorsk | 0:12b53511e212 | 341 | #define IPGR_DEF 0x00000012 /* Recommended value */ |
| igorsk | 0:12b53511e212 | 342 | |
| igorsk | 0:12b53511e212 | 343 | /* Collision Window/Retry Register */ |
| igorsk | 0:12b53511e212 | 344 | #define CLRT_DEF 0x0000370F /* Default value */ |
| igorsk | 0:12b53511e212 | 345 | |
| igorsk | 0:12b53511e212 | 346 | /* PHY Support Register */ |
| igorsk | 0:12b53511e212 | 347 | #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ |
| igorsk | 0:12b53511e212 | 348 | |
| igorsk | 0:12b53511e212 | 349 | /* Test Register */ |
| igorsk | 0:12b53511e212 | 350 | #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ |
| igorsk | 0:12b53511e212 | 351 | #define TEST_TST_PAUSE 0x00000002 /* Test Pause */ |
| igorsk | 0:12b53511e212 | 352 | #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ |
| igorsk | 0:12b53511e212 | 353 | |
| igorsk | 0:12b53511e212 | 354 | /* MII Management Configuration Register */ |
| igorsk | 0:12b53511e212 | 355 | #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ |
| igorsk | 0:12b53511e212 | 356 | #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ |
| igorsk | 0:12b53511e212 | 357 | #define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */ |
| igorsk | 0:12b53511e212 | 358 | #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ |
| igorsk | 0:12b53511e212 | 359 | |
| igorsk | 0:12b53511e212 | 360 | /* MII Management Command Register */ |
| igorsk | 0:12b53511e212 | 361 | #define MCMD_READ 0x00000001 /* MII Read */ |
| igorsk | 0:12b53511e212 | 362 | #define MCMD_SCAN 0x00000002 /* MII Scan continuously */ |
| igorsk | 0:12b53511e212 | 363 | |
| igorsk | 0:12b53511e212 | 364 | #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ |
| igorsk | 0:12b53511e212 | 365 | #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ |
| igorsk | 0:12b53511e212 | 366 | |
| igorsk | 0:12b53511e212 | 367 | /* MII Management Address Register */ |
| igorsk | 0:12b53511e212 | 368 | #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ |
| igorsk | 0:12b53511e212 | 369 | #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ |
| igorsk | 0:12b53511e212 | 370 | |
| igorsk | 0:12b53511e212 | 371 | /* MII Management Indicators Register */ |
| igorsk | 0:12b53511e212 | 372 | #define MIND_BUSY 0x00000001 /* MII is Busy */ |
| igorsk | 0:12b53511e212 | 373 | #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ |
| igorsk | 0:12b53511e212 | 374 | #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ |
| igorsk | 0:12b53511e212 | 375 | #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ |
| igorsk | 0:12b53511e212 | 376 | |
| igorsk | 0:12b53511e212 | 377 | /* Command Register */ |
| igorsk | 0:12b53511e212 | 378 | #define CR_RX_EN 0x00000001 /* Enable Receive */ |
| igorsk | 0:12b53511e212 | 379 | #define CR_TX_EN 0x00000002 /* Enable Transmit */ |
| igorsk | 0:12b53511e212 | 380 | #define CR_REG_RES 0x00000008 /* Reset Host Registers */ |
| igorsk | 0:12b53511e212 | 381 | #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ |
| igorsk | 0:12b53511e212 | 382 | #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ |
| igorsk | 0:12b53511e212 | 383 | #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ |
| igorsk | 0:12b53511e212 | 384 | #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ |
| igorsk | 0:12b53511e212 | 385 | #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ |
| igorsk | 0:12b53511e212 | 386 | #define CR_RMII 0x00000200 /* Reduced MII Interface */ |
| igorsk | 0:12b53511e212 | 387 | #define CR_FULL_DUP 0x00000400 /* Full Duplex */ |
| igorsk | 0:12b53511e212 | 388 | |
| igorsk | 0:12b53511e212 | 389 | /* Status Register */ |
| igorsk | 0:12b53511e212 | 390 | #define SR_RX_EN 0x00000001 /* Enable Receive */ |
| igorsk | 0:12b53511e212 | 391 | #define SR_TX_EN 0x00000002 /* Enable Transmit */ |
| igorsk | 0:12b53511e212 | 392 | |
| igorsk | 0:12b53511e212 | 393 | /* Transmit Status Vector 0 Register */ |
| igorsk | 0:12b53511e212 | 394 | #define TSV0_CRC_ERR 0x00000001 /* CRC error */ |
| igorsk | 0:12b53511e212 | 395 | #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ |
| igorsk | 0:12b53511e212 | 396 | #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ |
| igorsk | 0:12b53511e212 | 397 | #define TSV0_DONE 0x00000008 /* Tramsmission Completed */ |
| igorsk | 0:12b53511e212 | 398 | #define TSV0_MCAST 0x00000010 /* Multicast Destination */ |
| igorsk | 0:12b53511e212 | 399 | #define TSV0_BCAST 0x00000020 /* Broadcast Destination */ |
| igorsk | 0:12b53511e212 | 400 | #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ |
| igorsk | 0:12b53511e212 | 401 | #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ |
| igorsk | 0:12b53511e212 | 402 | #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ |
| igorsk | 0:12b53511e212 | 403 | #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ |
| igorsk | 0:12b53511e212 | 404 | #define TSV0_GIANT 0x00000400 /* Giant Frame */ |
| igorsk | 0:12b53511e212 | 405 | #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ |
| igorsk | 0:12b53511e212 | 406 | #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ |
| igorsk | 0:12b53511e212 | 407 | #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ |
| igorsk | 0:12b53511e212 | 408 | #define TSV0_PAUSE 0x20000000 /* Pause Frame */ |
| igorsk | 0:12b53511e212 | 409 | #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ |
| igorsk | 0:12b53511e212 | 410 | #define TSV0_VLAN 0x80000000 /* VLAN Frame */ |
| igorsk | 0:12b53511e212 | 411 | |
| igorsk | 0:12b53511e212 | 412 | /* Transmit Status Vector 1 Register */ |
| igorsk | 0:12b53511e212 | 413 | #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ |
| igorsk | 0:12b53511e212 | 414 | #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ |
| igorsk | 0:12b53511e212 | 415 | |
| igorsk | 0:12b53511e212 | 416 | /* Receive Status Vector Register */ |
| igorsk | 0:12b53511e212 | 417 | #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ |
| igorsk | 0:12b53511e212 | 418 | #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ |
| igorsk | 0:12b53511e212 | 419 | #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ |
| igorsk | 0:12b53511e212 | 420 | #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ |
| igorsk | 0:12b53511e212 | 421 | #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ |
| igorsk | 0:12b53511e212 | 422 | #define RSV_CRC_ERR 0x00100000 /* CRC Error */ |
| igorsk | 0:12b53511e212 | 423 | #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ |
| igorsk | 0:12b53511e212 | 424 | #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ |
| igorsk | 0:12b53511e212 | 425 | #define RSV_REC_OK 0x00800000 /* Frame Received OK */ |
| igorsk | 0:12b53511e212 | 426 | #define RSV_MCAST 0x01000000 /* Multicast Frame */ |
| igorsk | 0:12b53511e212 | 427 | #define RSV_BCAST 0x02000000 /* Broadcast Frame */ |
| igorsk | 0:12b53511e212 | 428 | #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ |
| igorsk | 0:12b53511e212 | 429 | #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ |
| igorsk | 0:12b53511e212 | 430 | #define RSV_PAUSE 0x10000000 /* Pause Frame */ |
| igorsk | 0:12b53511e212 | 431 | #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ |
| igorsk | 0:12b53511e212 | 432 | #define RSV_VLAN 0x40000000 /* VLAN Frame */ |
| igorsk | 0:12b53511e212 | 433 | |
| igorsk | 0:12b53511e212 | 434 | /* Flow Control Counter Register */ |
| igorsk | 0:12b53511e212 | 435 | #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ |
| igorsk | 0:12b53511e212 | 436 | #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ |
| igorsk | 0:12b53511e212 | 437 | |
| igorsk | 0:12b53511e212 | 438 | /* Flow Control Status Register */ |
| igorsk | 0:12b53511e212 | 439 | #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ |
| igorsk | 0:12b53511e212 | 440 | |
| igorsk | 0:12b53511e212 | 441 | /* Receive Filter Control Register */ |
| igorsk | 0:12b53511e212 | 442 | #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ |
| igorsk | 0:12b53511e212 | 443 | #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ |
| igorsk | 0:12b53511e212 | 444 | #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ |
| igorsk | 0:12b53511e212 | 445 | #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ |
| igorsk | 0:12b53511e212 | 446 | #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ |
| igorsk | 0:12b53511e212 | 447 | #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ |
| igorsk | 0:12b53511e212 | 448 | #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ |
| igorsk | 0:12b53511e212 | 449 | #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ |
| igorsk | 0:12b53511e212 | 450 | |
| igorsk | 0:12b53511e212 | 451 | /* Receive Filter WoL Status/Clear Registers */ |
| igorsk | 0:12b53511e212 | 452 | #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ |
| igorsk | 0:12b53511e212 | 453 | #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ |
| igorsk | 0:12b53511e212 | 454 | #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ |
| igorsk | 0:12b53511e212 | 455 | #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ |
| igorsk | 0:12b53511e212 | 456 | #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ |
| igorsk | 0:12b53511e212 | 457 | #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ |
| igorsk | 0:12b53511e212 | 458 | #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ |
| igorsk | 0:12b53511e212 | 459 | #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ |
| igorsk | 0:12b53511e212 | 460 | |
| igorsk | 0:12b53511e212 | 461 | /* Interrupt Status/Enable/Clear/Set Registers */ |
| igorsk | 0:12b53511e212 | 462 | #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ |
| igorsk | 0:12b53511e212 | 463 | #define INT_RX_ERR 0x00000002 /* Receive Error */ |
| igorsk | 0:12b53511e212 | 464 | #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ |
| igorsk | 0:12b53511e212 | 465 | #define INT_RX_DONE 0x00000008 /* Receive Done */ |
| igorsk | 0:12b53511e212 | 466 | #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ |
| igorsk | 0:12b53511e212 | 467 | #define INT_TX_ERR 0x00000020 /* Transmit Error */ |
| igorsk | 0:12b53511e212 | 468 | #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ |
| igorsk | 0:12b53511e212 | 469 | #define INT_TX_DONE 0x00000080 /* Transmit Done */ |
| igorsk | 0:12b53511e212 | 470 | #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ |
| igorsk | 0:12b53511e212 | 471 | #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ |
| igorsk | 0:12b53511e212 | 472 | |
| igorsk | 0:12b53511e212 | 473 | /* Power Down Register */ |
| igorsk | 0:12b53511e212 | 474 | #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ |
| igorsk | 0:12b53511e212 | 475 | |
| igorsk | 0:12b53511e212 | 476 | /* RX Descriptor Control Word */ |
| igorsk | 0:12b53511e212 | 477 | #define RCTRL_SIZE 0x000007FF /* Buffer size mask */ |
| igorsk | 0:12b53511e212 | 478 | #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ |
| igorsk | 0:12b53511e212 | 479 | |
| igorsk | 0:12b53511e212 | 480 | /* RX Status Hash CRC Word */ |
| igorsk | 0:12b53511e212 | 481 | #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ |
| igorsk | 0:12b53511e212 | 482 | #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ |
| igorsk | 0:12b53511e212 | 483 | |
| igorsk | 0:12b53511e212 | 484 | /* RX Status Information Word */ |
| igorsk | 0:12b53511e212 | 485 | #define RINFO_SIZE 0x000007FF /* Data size in bytes */ |
| igorsk | 0:12b53511e212 | 486 | #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ |
| igorsk | 0:12b53511e212 | 487 | #define RINFO_VLAN 0x00080000 /* VLAN Frame */ |
| igorsk | 0:12b53511e212 | 488 | #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ |
| igorsk | 0:12b53511e212 | 489 | #define RINFO_MCAST 0x00200000 /* Multicast Frame */ |
| igorsk | 0:12b53511e212 | 490 | #define RINFO_BCAST 0x00400000 /* Broadcast Frame */ |
| igorsk | 0:12b53511e212 | 491 | #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ |
| igorsk | 0:12b53511e212 | 492 | #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ |
| igorsk | 0:12b53511e212 | 493 | #define RINFO_LEN_ERR 0x02000000 /* Length Error */ |
| igorsk | 0:12b53511e212 | 494 | #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ |
| igorsk | 0:12b53511e212 | 495 | #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ |
| igorsk | 0:12b53511e212 | 496 | #define RINFO_OVERRUN 0x10000000 /* Receive overrun */ |
| igorsk | 0:12b53511e212 | 497 | #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ |
| igorsk | 0:12b53511e212 | 498 | #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ |
| igorsk | 0:12b53511e212 | 499 | #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ |
| igorsk | 0:12b53511e212 | 500 | |
| igorsk | 0:12b53511e212 | 501 | #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \ |
| igorsk | 0:12b53511e212 | 502 | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) |
| igorsk | 0:12b53511e212 | 503 | |
| igorsk | 0:12b53511e212 | 504 | /* TX Descriptor Control Word */ |
| igorsk | 0:12b53511e212 | 505 | #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ |
| igorsk | 0:12b53511e212 | 506 | #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ |
| igorsk | 0:12b53511e212 | 507 | #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ |
| igorsk | 0:12b53511e212 | 508 | #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ |
| igorsk | 0:12b53511e212 | 509 | #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ |
| igorsk | 0:12b53511e212 | 510 | #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ |
| igorsk | 0:12b53511e212 | 511 | #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ |
| igorsk | 0:12b53511e212 | 512 | |
| igorsk | 0:12b53511e212 | 513 | /* TX Status Information Word */ |
| igorsk | 0:12b53511e212 | 514 | #define TINFO_COL_CNT 0x01E00000 /* Collision Count */ |
| igorsk | 0:12b53511e212 | 515 | #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ |
| igorsk | 0:12b53511e212 | 516 | #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ |
| igorsk | 0:12b53511e212 | 517 | #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ |
| igorsk | 0:12b53511e212 | 518 | #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ |
| igorsk | 0:12b53511e212 | 519 | #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ |
| igorsk | 0:12b53511e212 | 520 | #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ |
| igorsk | 0:12b53511e212 | 521 | #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ |
| igorsk | 0:12b53511e212 | 522 | |
| igorsk | 0:12b53511e212 | 523 | /* ENET Device Revision ID */ |
| igorsk | 0:12b53511e212 | 524 | #define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */ |
| igorsk | 0:12b53511e212 | 525 | |
| igorsk | 0:12b53511e212 | 526 | /* DP83848C PHY Registers */ |
| igorsk | 0:12b53511e212 | 527 | #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ |
| igorsk | 0:12b53511e212 | 528 | #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ |
| igorsk | 0:12b53511e212 | 529 | #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ |
| igorsk | 0:12b53511e212 | 530 | #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ |
| igorsk | 0:12b53511e212 | 531 | #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ |
| igorsk | 0:12b53511e212 | 532 | #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ |
| igorsk | 0:12b53511e212 | 533 | #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ |
| igorsk | 0:12b53511e212 | 534 | #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ |
| igorsk | 0:12b53511e212 | 535 | |
| igorsk | 0:12b53511e212 | 536 | /* PHY Extended Registers */ |
| igorsk | 0:12b53511e212 | 537 | #define PHY_REG_STS 0x10 /* Status Register */ |
| igorsk | 0:12b53511e212 | 538 | #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ |
| igorsk | 0:12b53511e212 | 539 | #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ |
| igorsk | 0:12b53511e212 | 540 | #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ |
| igorsk | 0:12b53511e212 | 541 | #define PHY_REG_RECR 0x15 /* Receive Error Counter */ |
| igorsk | 0:12b53511e212 | 542 | #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ |
| igorsk | 0:12b53511e212 | 543 | #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ |
| igorsk | 0:12b53511e212 | 544 | #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ |
| igorsk | 0:12b53511e212 | 545 | #define PHY_REG_PHYCR 0x19 /* PHY Control Register */ |
| igorsk | 0:12b53511e212 | 546 | #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ |
| igorsk | 0:12b53511e212 | 547 | #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ |
| igorsk | 0:12b53511e212 | 548 | #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ |
| igorsk | 0:12b53511e212 | 549 | |
| igorsk | 0:12b53511e212 | 550 | #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ |
| igorsk | 0:12b53511e212 | 551 | #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ |
| igorsk | 0:12b53511e212 | 552 | #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ |
| igorsk | 0:12b53511e212 | 553 | #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ |
| igorsk | 0:12b53511e212 | 554 | #define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ |
| igorsk | 0:12b53511e212 | 555 | |
| igorsk | 0:12b53511e212 | 556 | #define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */ |
| igorsk | 0:12b53511e212 | 557 | #define DP83848C_ID 0x20005C90 /* PHY Identifier */ |
| igorsk | 0:12b53511e212 | 558 | |
| igorsk | 0:12b53511e212 | 559 | |
| igorsk | 0:12b53511e212 | 560 | /************************************************* |
| igorsk | 0:12b53511e212 | 561 | * CodeRed - PHY definitions for RDB1768 rev 2 |
| igorsk | 0:12b53511e212 | 562 | * which uses SMSC LAN8720 PHY instead of DP83848C |
| igorsk | 0:12b53511e212 | 563 | *************************************************/ |
| igorsk | 0:12b53511e212 | 564 | #define LAN8720_ID 0x000730F0 /* PHY Identifier */ |
| igorsk | 0:12b53511e212 | 565 | |
| igorsk | 0:12b53511e212 | 566 | |
| igorsk | 0:12b53511e212 | 567 | |
| igorsk | 0:12b53511e212 | 568 | |
| igorsk | 0:12b53511e212 | 569 | // Code Red - not required for RDB1768 port |
| igorsk | 0:12b53511e212 | 570 | /* |
| igorsk | 0:12b53511e212 | 571 | // typedefs |
| igorsk | 0:12b53511e212 | 572 | typedef struct { // struct to store CS8900's |
| igorsk | 0:12b53511e212 | 573 | unsigned int Addr; // init-sequence |
| igorsk | 0:12b53511e212 | 574 | unsigned int Data; |
| igorsk | 0:12b53511e212 | 575 | } TInitSeq; |
| igorsk | 0:12b53511e212 | 576 | */ |
| igorsk | 0:12b53511e212 | 577 | |
| igorsk | 0:12b53511e212 | 578 | // Code Red - moved into tcpip.c |
| igorsk | 0:12b53511e212 | 579 | /* |
| igorsk | 0:12b53511e212 | 580 | // constants |
| igorsk | 0:12b53511e212 | 581 | const unsigned char MyMAC[] = // "M1-M2-M3-M4-M5-M6" |
| igorsk | 0:12b53511e212 | 582 | { |
| igorsk | 0:12b53511e212 | 583 | MYMAC_1, MYMAC_2, MYMAC_3, |
| igorsk | 0:12b53511e212 | 584 | MYMAC_4, MYMAC_5, MYMAC_6 |
| igorsk | 0:12b53511e212 | 585 | }; |
| igorsk | 0:12b53511e212 | 586 | */ |
| igorsk | 0:12b53511e212 | 587 | |
| igorsk | 0:12b53511e212 | 588 | // Code Red - not required for RDB1768 port |
| igorsk | 0:12b53511e212 | 589 | /* |
| igorsk | 0:12b53511e212 | 590 | const TInitSeq InitSeq[] = |
| igorsk | 0:12b53511e212 | 591 | { |
| igorsk | 0:12b53511e212 | 592 | PP_IA, MYMAC_1 + (MYMAC_2 << 8), // set our MAC as Individual Address |
| igorsk | 0:12b53511e212 | 593 | PP_IA + 2, MYMAC_3 + (MYMAC_4 << 8), |
| igorsk | 0:12b53511e212 | 594 | PP_IA + 4, MYMAC_5 + (MYMAC_6 << 8), |
| igorsk | 0:12b53511e212 | 595 | PP_LineCTL, SERIAL_RX_ON | SERIAL_TX_ON, // configure the Physical Interface |
| igorsk | 0:12b53511e212 | 596 | PP_RxCTL, RX_OK_ACCEPT | RX_IA_ACCEPT | RX_BROADCAST_ACCEPT |
| igorsk | 0:12b53511e212 | 597 | }; |
| igorsk | 0:12b53511e212 | 598 | */ |
| igorsk | 0:12b53511e212 | 599 | |
| igorsk | 0:12b53511e212 | 600 | // prototypes |
| igorsk | 0:12b53511e212 | 601 | |
| igorsk | 0:12b53511e212 | 602 | // CodeRed - updated for LPC1768 port |
| igorsk | 0:12b53511e212 | 603 | /* |
| igorsk | 0:12b53511e212 | 604 | void Init8900(void); |
| igorsk | 0:12b53511e212 | 605 | void Write8900(unsigned char Address, unsigned int Data); |
| igorsk | 0:12b53511e212 | 606 | void WriteFrame8900(unsigned int Data); |
| igorsk | 0:12b53511e212 | 607 | unsigned int Read8900(unsigned char Address); |
| igorsk | 0:12b53511e212 | 608 | unsigned int ReadFrame8900(void); |
| igorsk | 0:12b53511e212 | 609 | unsigned int ReadHB1ST8900(unsigned char Address); |
| igorsk | 0:12b53511e212 | 610 | unsigned int ReadFrameBE8900(void); |
| igorsk | 0:12b53511e212 | 611 | void CopyToFrame8900(void *Source, unsigned int Size); |
| igorsk | 0:12b53511e212 | 612 | void CopyFromFrame8900(void *Dest, unsigned int Size); |
| igorsk | 0:12b53511e212 | 613 | void DummyReadFrame8900(unsigned int Size); |
| igorsk | 0:12b53511e212 | 614 | void RequestSend(unsigned int FrameSize); |
| igorsk | 0:12b53511e212 | 615 | unsigned int Rdy4Tx(void); |
| igorsk | 0:12b53511e212 | 616 | */ |
| igorsk | 0:12b53511e212 | 617 | |
| igorsk | 0:12b53511e212 | 618 | void Init_EthMAC(void); |
| igorsk | 0:12b53511e212 | 619 | unsigned short ReadFrameBE_EthMAC(void); |
| igorsk | 0:12b53511e212 | 620 | void CopyToFrame_EthMAC(void *Source, unsigned int Size); |
| igorsk | 0:12b53511e212 | 621 | void CopyFromFrame_EthMAC(void *Dest, unsigned short Size); |
| igorsk | 0:12b53511e212 | 622 | void DummyReadFrame_EthMAC(unsigned short Size); |
| igorsk | 0:12b53511e212 | 623 | void RequestSend(unsigned short FrameSize); |
| igorsk | 0:12b53511e212 | 624 | unsigned int Rdy4Tx(void); |
| igorsk | 0:12b53511e212 | 625 | unsigned short StartReadingFrame(void); |
| igorsk | 0:12b53511e212 | 626 | void StopReadingFrame(void); |
| igorsk | 0:12b53511e212 | 627 | unsigned int CheckIfFrameReceived(void); |
| igorsk | 0:12b53511e212 | 628 | |
| igorsk | 0:12b53511e212 | 629 | #endif |
| igorsk | 0:12b53511e212 | 630 |