EL4121 Embedded System / mbed-os

mbed-os

Dependents:   cobaLCDJoyMotor_Thread odometry_omni_3roda_v3 odometry_omni_3roda_v1 odometry_omni_3roda_v2 ... more

targets/TARGET_Freescale/TARGET_K20XX/sleep.c@0:b74591d5ab33, 2017-12-11 (annotated)

Committer:
be_bryan
Date:
Mon Dec 11 17:54:04 2017 +0000
Revision:
0:b74591d5ab33
motor ++

Who changed what in which revision?

UserRevisionLine numberNew contents of line
be_bryan 0:b74591d5ab33 1 /* mbed Microcontroller Library
be_bryan 0:b74591d5ab33 2 * Copyright (c) 2006-2015 ARM Limited
be_bryan 0:b74591d5ab33 3 *
be_bryan 0:b74591d5ab33 4 * Licensed under the Apache License, Version 2.0 (the "License");
be_bryan 0:b74591d5ab33 5 * you may not use this file except in compliance with the License.
be_bryan 0:b74591d5ab33 6 * You may obtain a copy of the License at
be_bryan 0:b74591d5ab33 7 *
be_bryan 0:b74591d5ab33 8 * http://www.apache.org/licenses/LICENSE-2.0
be_bryan 0:b74591d5ab33 9 *
be_bryan 0:b74591d5ab33 10 * Unless required by applicable law or agreed to in writing, software
be_bryan 0:b74591d5ab33 11 * distributed under the License is distributed on an "AS IS" BASIS,
be_bryan 0:b74591d5ab33 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
be_bryan 0:b74591d5ab33 13 * See the License for the specific language governing permissions and
be_bryan 0:b74591d5ab33 14 * limitations under the License.
be_bryan 0:b74591d5ab33 15 */
be_bryan 0:b74591d5ab33 16 #include "sleep_api.h"
be_bryan 0:b74591d5ab33 17 #include "cmsis.h"
be_bryan 0:b74591d5ab33 18
be_bryan 0:b74591d5ab33 19 //Normal wait mode
be_bryan 0:b74591d5ab33 20 void hal_sleep(void)
be_bryan 0:b74591d5ab33 21 {
be_bryan 0:b74591d5ab33 22 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
be_bryan 0:b74591d5ab33 23
be_bryan 0:b74591d5ab33 24 //Normal sleep mode for ARM core:
be_bryan 0:b74591d5ab33 25 SCB->SCR = 0;
be_bryan 0:b74591d5ab33 26 __WFI();
be_bryan 0:b74591d5ab33 27 }
be_bryan 0:b74591d5ab33 28
be_bryan 0:b74591d5ab33 29 //Very low-power stop mode
be_bryan 0:b74591d5ab33 30 void hal_deepsleep(void)
be_bryan 0:b74591d5ab33 31 {
be_bryan 0:b74591d5ab33 32 //Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA)
be_bryan 0:b74591d5ab33 33 uint8_t ADC_HSC = 0;
be_bryan 0:b74591d5ab33 34 if (SIM->SCGC6 & SIM_SCGC6_ADC0_MASK) {
be_bryan 0:b74591d5ab33 35 if (ADC0->CFG2 & ADC_CFG2_ADHSC_MASK) {
be_bryan 0:b74591d5ab33 36 ADC_HSC = 1;
be_bryan 0:b74591d5ab33 37 ADC0->CFG2 &= ~(ADC_CFG2_ADHSC_MASK);
be_bryan 0:b74591d5ab33 38 }
be_bryan 0:b74591d5ab33 39 }
be_bryan 0:b74591d5ab33 40
be_bryan 0:b74591d5ab33 41 //Check if PLL/FLL is enabled:
be_bryan 0:b74591d5ab33 42 uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0);
be_bryan 0:b74591d5ab33 43
be_bryan 0:b74591d5ab33 44 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
be_bryan 0:b74591d5ab33 45 SMC->PMCTRL = SMC_PMCTRL_STOPM(2);
be_bryan 0:b74591d5ab33 46
be_bryan 0:b74591d5ab33 47 //Deep sleep for ARM core:
be_bryan 0:b74591d5ab33 48 SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos;
be_bryan 0:b74591d5ab33 49
be_bryan 0:b74591d5ab33 50 __WFI();
be_bryan 0:b74591d5ab33 51 //Switch back to PLL as clock source if needed
be_bryan 0:b74591d5ab33 52 //The interrupt that woke up the device will run at reduced speed
be_bryan 0:b74591d5ab33 53 if (PLL_FLL_en) {
be_bryan 0:b74591d5ab33 54
be_bryan 0:b74591d5ab33 55 #if defined (TARGET_K20D50M)
be_bryan 0:b74591d5ab33 56 if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */
be_bryan 0:b74591d5ab33 57 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */
be_bryan 0:b74591d5ab33 58 MCG->C1 &= ~MCG_C1_CLKS_MASK;
be_bryan 0:b74591d5ab33 59 #else
be_bryan 0:b74591d5ab33 60 // MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0
be_bryan 0:b74591d5ab33 61 MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
be_bryan 0:b74591d5ab33 62 // MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0
be_bryan 0:b74591d5ab33 63 MCG->C6 = MCG_C6_VDIV0(0);
be_bryan 0:b74591d5ab33 64 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } // Check that the oscillator is running
be_bryan 0:b74591d5ab33 65 while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output
be_bryan 0:b74591d5ab33 66 // MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3
be_bryan 0:b74591d5ab33 67 MCG->C5 = MCG_C5_PRDIV0(5);
be_bryan 0:b74591d5ab33 68 // MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3
be_bryan 0:b74591d5ab33 69 MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3);
be_bryan 0:b74591d5ab33 70 while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output
be_bryan 0:b74591d5ab33 71 while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } // Wait until the source of the PLLS clock has switched to the PLL
be_bryan 0:b74591d5ab33 72 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked
be_bryan 0:b74591d5ab33 73 // MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0
be_bryan 0:b74591d5ab33 74 MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;;
be_bryan 0:b74591d5ab33 75 while((MCG->S & 0x0Cu) != 0x0Cu) { } // Wait until output of the PLL is selected
be_bryan 0:b74591d5ab33 76 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked
be_bryan 0:b74591d5ab33 77 #endif
be_bryan 0:b74591d5ab33 78 }
be_bryan 0:b74591d5ab33 79
be_bryan 0:b74591d5ab33 80 if (ADC_HSC) {
be_bryan 0:b74591d5ab33 81 ADC0->CFG2 |= (ADC_CFG2_ADHSC_MASK);
be_bryan 0:b74591d5ab33 82 }
be_bryan 0:b74591d5ab33 83 }