Release 1.01
SPI_MX25R.h@2:1d5204d29bc5, 2019-09-17 (annotated)
- Committer:
- foxbrianr
- Date:
- Tue Sep 17 13:48:28 2019 +0000
- Revision:
- 2:1d5204d29bc5
- Parent:
- 1:86f6ebbe4fd1
Beta 2
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
foxbrianr | 2:1d5204d29bc5 | 1 | /**************************************************************************//** |
foxbrianr | 2:1d5204d29bc5 | 2 | * @file SPI_MX25R.cpp |
foxbrianr | 2:1d5204d29bc5 | 3 | * @brief Base class for wrapping the interface with the SPI NOR Flash. |
foxbrianr | 2:1d5204d29bc5 | 4 | * @version: V1.0 |
foxbrianr | 2:1d5204d29bc5 | 5 | * @date: 9/17/2019 |
foxbrianr | 2:1d5204d29bc5 | 6 | * |
foxbrianr | 2:1d5204d29bc5 | 7 | * @note |
foxbrianr | 2:1d5204d29bc5 | 8 | * SPI_MX25R Series SPI-Flash Memory |
foxbrianr | 2:1d5204d29bc5 | 9 | * Macronix Low Power Serial NOR Flash |
foxbrianr | 2:1d5204d29bc5 | 10 | * (x2, and x4 I/O modes not implemented) |
foxbrianr | 2:1d5204d29bc5 | 11 | * |
foxbrianr | 2:1d5204d29bc5 | 12 | * |
foxbrianr | 2:1d5204d29bc5 | 13 | * @note |
foxbrianr | 2:1d5204d29bc5 | 14 | * Copyright (C) 2019 E3 Design. All rights reserved. |
foxbrianr | 2:1d5204d29bc5 | 15 | * |
foxbrianr | 2:1d5204d29bc5 | 16 | * @par |
foxbrianr | 2:1d5204d29bc5 | 17 | * E3 Designers LLC is supplying this software for use with Cortex-M3 LPC1768 |
foxbrianr | 2:1d5204d29bc5 | 18 | * processor based microcontroller for the ESCM 2000 Monitor and Display. |
foxbrianr | 2:1d5204d29bc5 | 19 | * * |
foxbrianr | 2:1d5204d29bc5 | 20 | * @par |
foxbrianr | 2:1d5204d29bc5 | 21 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
foxbrianr | 2:1d5204d29bc5 | 22 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
foxbrianr | 2:1d5204d29bc5 | 23 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
foxbrianr | 2:1d5204d29bc5 | 24 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
foxbrianr | 2:1d5204d29bc5 | 25 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
foxbrianr | 2:1d5204d29bc5 | 26 | * |
foxbrianr | 2:1d5204d29bc5 | 27 | ******************************************************************************/ |
foxbrianr | 1:86f6ebbe4fd1 | 28 | #ifndef _SPI_MX25R_H_ |
foxbrianr | 1:86f6ebbe4fd1 | 29 | #define _SPI_MX25R_H_ |
foxbrianr | 1:86f6ebbe4fd1 | 30 | |
foxbrianr | 1:86f6ebbe4fd1 | 31 | #include "mbed.h" |
foxbrianr | 1:86f6ebbe4fd1 | 32 | |
foxbrianr | 1:86f6ebbe4fd1 | 33 | /** |
foxbrianr | 1:86f6ebbe4fd1 | 34 | * Macronix Serial Flash Low Power Memories |
foxbrianr | 1:86f6ebbe4fd1 | 35 | * SPI_MX25R Series SPI-Flash Memory |
foxbrianr | 1:86f6ebbe4fd1 | 36 | */ |
foxbrianr | 1:86f6ebbe4fd1 | 37 | #define CS_LOW 0 // SPI CS# (Chip Select) Setting |
foxbrianr | 1:86f6ebbe4fd1 | 38 | #define CS_HIGH 1 // SPI CS# (Chip Select) Setting |
foxbrianr | 1:86f6ebbe4fd1 | 39 | #define DUMMY 0x00 // Dummy byte which can be changed to any value |
foxbrianr | 1:86f6ebbe4fd1 | 40 | /** |
foxbrianr | 1:86f6ebbe4fd1 | 41 | * MX25R Series Register Command Table. |
foxbrianr | 1:86f6ebbe4fd1 | 42 | * x2 and x4 commands not currently supported with FRDM K64F platform |
foxbrianr | 1:86f6ebbe4fd1 | 43 | */ |
foxbrianr | 1:86f6ebbe4fd1 | 44 | #define CMD_READ 0x03 // x1 Normal Read Data Byte |
foxbrianr | 1:86f6ebbe4fd1 | 45 | #define CMD_FREAD 0x0B // x1 Fast Read Data Byte |
foxbrianr | 1:86f6ebbe4fd1 | 46 | #define CMD_2READ 0xBB // x2 2READ |
foxbrianr | 1:86f6ebbe4fd1 | 47 | #define CMD_DREAD 0x3B // x2 DREAD |
foxbrianr | 1:86f6ebbe4fd1 | 48 | #define CMD_4READ 0xEB // x4 4READ |
foxbrianr | 1:86f6ebbe4fd1 | 49 | #define CMD_QREAD 0x6B // x4 QREAD |
foxbrianr | 1:86f6ebbe4fd1 | 50 | #define CMD_PP 0x02 // Page Program |
foxbrianr | 1:86f6ebbe4fd1 | 51 | #define CMD_4PP 0x38 // x4 PP |
foxbrianr | 1:86f6ebbe4fd1 | 52 | #define CMD_SE 0x20 // 4KB Sector Erase |
foxbrianr | 1:86f6ebbe4fd1 | 53 | #define CMD_32KBE 0x52 // 32KB Block Erase |
foxbrianr | 1:86f6ebbe4fd1 | 54 | #define CMD_BE 0xD8 // 64KB Block Erase |
foxbrianr | 1:86f6ebbe4fd1 | 55 | #define CMD_CE 0xC7 // Chip Erase |
foxbrianr | 1:86f6ebbe4fd1 | 56 | #define CMD_RDSFDP 0x5A // Read SFDP |
foxbrianr | 1:86f6ebbe4fd1 | 57 | #define CMD_WREN 0x06 // Write Enable |
foxbrianr | 1:86f6ebbe4fd1 | 58 | #define CMD_WRDI 0x04 // Write Disable |
foxbrianr | 1:86f6ebbe4fd1 | 59 | #define CMD_RDSR 0x05 // Read Status Register |
foxbrianr | 1:86f6ebbe4fd1 | 60 | #define CMD_RDCR 0x15 // Read Configuration Register |
foxbrianr | 1:86f6ebbe4fd1 | 61 | #define CMD_WRSR 0x01 // Write Status Register |
foxbrianr | 1:86f6ebbe4fd1 | 62 | #define CMD_PESUS 0xB0 // Program/Erase Suspend |
foxbrianr | 1:86f6ebbe4fd1 | 63 | #define CMD_PERES 0x30 // Program/Erase Resume |
foxbrianr | 1:86f6ebbe4fd1 | 64 | #define CMD_DP 0xB9 // Enter Deep Power Down |
foxbrianr | 1:86f6ebbe4fd1 | 65 | #define CMD_SBL 0xC0 // Set Burst Length |
foxbrianr | 1:86f6ebbe4fd1 | 66 | #define CMD_RDID 0x9F // Read Manufacturer and JDEC Device ID |
foxbrianr | 1:86f6ebbe4fd1 | 67 | #define CMD_REMS 0x90 // Read Electronic Manufacturer and Device ID |
foxbrianr | 1:86f6ebbe4fd1 | 68 | #define CMD_RES 0xAB // Read Electronic ID |
foxbrianr | 1:86f6ebbe4fd1 | 69 | #define CMD_ENSO 0xB1 // Enter Secure OTP |
foxbrianr | 1:86f6ebbe4fd1 | 70 | #define CMD_EXSO 0xC1 // Exit Secure OTP |
foxbrianr | 1:86f6ebbe4fd1 | 71 | #define CMD_RDSCUR 0x2B // Read Security Register |
foxbrianr | 1:86f6ebbe4fd1 | 72 | #define CMD_WRSCUR 0x2F // Write Security Register |
foxbrianr | 1:86f6ebbe4fd1 | 73 | #define CMD_NOP 0x00 // No Operation |
foxbrianr | 1:86f6ebbe4fd1 | 74 | #define CMD_RSTEN 0x66 // Reset Enable |
foxbrianr | 1:86f6ebbe4fd1 | 75 | #define CMD_RST 0x99 // Reset |
foxbrianr | 1:86f6ebbe4fd1 | 76 | #define CMD_RRE 0xFF // Release Read Enhanced Mode |
foxbrianr | 1:86f6ebbe4fd1 | 77 | |
foxbrianr | 1:86f6ebbe4fd1 | 78 | |
foxbrianr | 1:86f6ebbe4fd1 | 79 | class SPI_MX25R |
foxbrianr | 1:86f6ebbe4fd1 | 80 | { |
foxbrianr | 1:86f6ebbe4fd1 | 81 | public: |
foxbrianr | 1:86f6ebbe4fd1 | 82 | /** |
foxbrianr | 1:86f6ebbe4fd1 | 83 | * Macronix MX25R Low Power and Wide Vcc SPI-Flash Memory Family |
foxbrianr | 1:86f6ebbe4fd1 | 84 | * |
foxbrianr | 1:86f6ebbe4fd1 | 85 | * @param SI/SIO0 SPI_MOSI pin |
foxbrianr | 1:86f6ebbe4fd1 | 86 | * @param SO/SI01 SPI_MISO pin |
foxbrianr | 1:86f6ebbe4fd1 | 87 | * @param SCLK SPI_CLK pin |
foxbrianr | 1:86f6ebbe4fd1 | 88 | * @param CSb SPI_CS pin |
foxbrianr | 1:86f6ebbe4fd1 | 89 | */ |
foxbrianr | 1:86f6ebbe4fd1 | 90 | SPI_MX25R(PinName mosi, PinName miso, PinName sclk, PinName cs) ; |
foxbrianr | 1:86f6ebbe4fd1 | 91 | |
foxbrianr | 1:86f6ebbe4fd1 | 92 | ~SPI_MX25R() ; |
foxbrianr | 1:86f6ebbe4fd1 | 93 | |
foxbrianr | 1:86f6ebbe4fd1 | 94 | SPI m_spi; |
foxbrianr | 1:86f6ebbe4fd1 | 95 | DigitalOut m_cs ; |
foxbrianr | 1:86f6ebbe4fd1 | 96 | int _mode ; |
foxbrianr | 1:86f6ebbe4fd1 | 97 | |
foxbrianr | 1:86f6ebbe4fd1 | 98 | /// Write Enable |
foxbrianr | 1:86f6ebbe4fd1 | 99 | void writeEnable(void) ; |
foxbrianr | 1:86f6ebbe4fd1 | 100 | |
foxbrianr | 1:86f6ebbe4fd1 | 101 | /// Write Disable |
foxbrianr | 1:86f6ebbe4fd1 | 102 | void writeDisable(void) ; |
foxbrianr | 1:86f6ebbe4fd1 | 103 | |
foxbrianr | 1:86f6ebbe4fd1 | 104 | /// Reset Enable |
foxbrianr | 1:86f6ebbe4fd1 | 105 | void resetEnable(void) ; |
foxbrianr | 1:86f6ebbe4fd1 | 106 | |
foxbrianr | 1:86f6ebbe4fd1 | 107 | /// Reset |
foxbrianr | 1:86f6ebbe4fd1 | 108 | void reset(void) ; |
foxbrianr | 1:86f6ebbe4fd1 | 109 | |
foxbrianr | 1:86f6ebbe4fd1 | 110 | /// Program or Erase Suspend |
foxbrianr | 1:86f6ebbe4fd1 | 111 | void pgmersSuspend(void) ; |
foxbrianr | 1:86f6ebbe4fd1 | 112 | |
foxbrianr | 1:86f6ebbe4fd1 | 113 | /// Program or Erase Resume |
foxbrianr | 1:86f6ebbe4fd1 | 114 | void pgmersResume(void) ; |
foxbrianr | 1:86f6ebbe4fd1 | 115 | |
foxbrianr | 1:86f6ebbe4fd1 | 116 | /// Enter Deep Power Down |
foxbrianr | 1:86f6ebbe4fd1 | 117 | void deepPowerdown(void) ; |
foxbrianr | 1:86f6ebbe4fd1 | 118 | |
foxbrianr | 1:86f6ebbe4fd1 | 119 | /// Set Burst Length |
foxbrianr | 1:86f6ebbe4fd1 | 120 | void setBurstlength(void) ; |
foxbrianr | 1:86f6ebbe4fd1 | 121 | |
foxbrianr | 1:86f6ebbe4fd1 | 122 | /// Release from Read Enhanced Mode |
foxbrianr | 1:86f6ebbe4fd1 | 123 | void releaseReadenhaced(void) ; |
foxbrianr | 1:86f6ebbe4fd1 | 124 | |
foxbrianr | 1:86f6ebbe4fd1 | 125 | /// No Operation |
foxbrianr | 1:86f6ebbe4fd1 | 126 | void noOperation(void) ; |
foxbrianr | 1:86f6ebbe4fd1 | 127 | |
foxbrianr | 1:86f6ebbe4fd1 | 128 | /// Enter OTP Area |
foxbrianr | 1:86f6ebbe4fd1 | 129 | void enterSecureOTP(void) ; |
foxbrianr | 1:86f6ebbe4fd1 | 130 | |
foxbrianr | 1:86f6ebbe4fd1 | 131 | /// Exit OTP Area |
foxbrianr | 1:86f6ebbe4fd1 | 132 | void exitSecureOTP(void) ; |
foxbrianr | 1:86f6ebbe4fd1 | 133 | |
foxbrianr | 1:86f6ebbe4fd1 | 134 | /// Chip Erase |
foxbrianr | 1:86f6ebbe4fd1 | 135 | void chipErase(void) ; |
foxbrianr | 1:86f6ebbe4fd1 | 136 | |
foxbrianr | 1:86f6ebbe4fd1 | 137 | /// Write Status and Configuration Reg 1 and 2 |
foxbrianr | 1:86f6ebbe4fd1 | 138 | void writeStatusreg(int addr) ; |
foxbrianr | 1:86f6ebbe4fd1 | 139 | |
foxbrianr | 1:86f6ebbe4fd1 | 140 | /// Write Security Reg |
foxbrianr | 1:86f6ebbe4fd1 | 141 | void writeSecurityreg(int addr) ; |
foxbrianr | 1:86f6ebbe4fd1 | 142 | |
foxbrianr | 1:86f6ebbe4fd1 | 143 | /** Page Program |
foxbrianr | 1:86f6ebbe4fd1 | 144 | * |
foxbrianr | 1:86f6ebbe4fd1 | 145 | * @param int addr start address |
foxbrianr | 1:86f6ebbe4fd1 | 146 | * @param uint8_t *data data buffer |
foxbrianr | 1:86f6ebbe4fd1 | 147 | * @param int numData the number of data to be written |
foxbrianr | 1:86f6ebbe4fd1 | 148 | */ |
foxbrianr | 1:86f6ebbe4fd1 | 149 | void programPage(int addr, uint8_t *data, int numData) ; |
foxbrianr | 1:86f6ebbe4fd1 | 150 | |
foxbrianr | 1:86f6ebbe4fd1 | 151 | /** Sector Erase |
foxbrianr | 1:86f6ebbe4fd1 | 152 | * |
foxbrianr | 1:86f6ebbe4fd1 | 153 | * @param int addr specify the sector to be erased |
foxbrianr | 1:86f6ebbe4fd1 | 154 | */ |
foxbrianr | 1:86f6ebbe4fd1 | 155 | void sectorErase(int addr) ; |
foxbrianr | 1:86f6ebbe4fd1 | 156 | |
foxbrianr | 1:86f6ebbe4fd1 | 157 | /** Block Erase |
foxbrianr | 1:86f6ebbe4fd1 | 158 | * |
foxbrianr | 1:86f6ebbe4fd1 | 159 | * @param int addr specify the sector to be erased |
foxbrianr | 1:86f6ebbe4fd1 | 160 | */ |
foxbrianr | 1:86f6ebbe4fd1 | 161 | void blockErase(int addr) ; |
foxbrianr | 1:86f6ebbe4fd1 | 162 | |
foxbrianr | 1:86f6ebbe4fd1 | 163 | /** 32KB Block Erase |
foxbrianr | 1:86f6ebbe4fd1 | 164 | * |
foxbrianr | 1:86f6ebbe4fd1 | 165 | * @param int addr specify the sector to be erased |
foxbrianr | 1:86f6ebbe4fd1 | 166 | */ |
foxbrianr | 1:86f6ebbe4fd1 | 167 | void blockErase32KB(int addr) ; |
foxbrianr | 1:86f6ebbe4fd1 | 168 | |
foxbrianr | 1:86f6ebbe4fd1 | 169 | /** Read Status Register |
foxbrianr | 1:86f6ebbe4fd1 | 170 | * |
foxbrianr | 1:86f6ebbe4fd1 | 171 | * @returns uint8_t status register value |
foxbrianr | 1:86f6ebbe4fd1 | 172 | */ |
foxbrianr | 1:86f6ebbe4fd1 | 173 | uint8_t readStatus(void) ; |
foxbrianr | 1:86f6ebbe4fd1 | 174 | |
foxbrianr | 1:86f6ebbe4fd1 | 175 | /** Read Security Register |
foxbrianr | 1:86f6ebbe4fd1 | 176 | * |
foxbrianr | 1:86f6ebbe4fd1 | 177 | * @returns uint8_t security register value |
foxbrianr | 1:86f6ebbe4fd1 | 178 | */ |
foxbrianr | 1:86f6ebbe4fd1 | 179 | uint8_t readSecurity(void) ; |
foxbrianr | 1:86f6ebbe4fd1 | 180 | |
foxbrianr | 1:86f6ebbe4fd1 | 181 | /** Read Manufacturer and JEDEC Device ID |
foxbrianr | 1:86f6ebbe4fd1 | 182 | * |
foxbrianr | 1:86f6ebbe4fd1 | 183 | * @returns uint32_t Manufacturer ID, Mem Type, Device ID |
foxbrianr | 1:86f6ebbe4fd1 | 184 | */ |
foxbrianr | 1:86f6ebbe4fd1 | 185 | uint32_t readID(void) ; |
foxbrianr | 1:86f6ebbe4fd1 | 186 | |
foxbrianr | 1:86f6ebbe4fd1 | 187 | /** Read Electronic Manufacturer and Device ID |
foxbrianr | 1:86f6ebbe4fd1 | 188 | * |
foxbrianr | 1:86f6ebbe4fd1 | 189 | * @returns uint32_t Manufacturer ID, Device ID |
foxbrianr | 1:86f6ebbe4fd1 | 190 | */ |
foxbrianr | 1:86f6ebbe4fd1 | 191 | uint32_t readREMS(void) ; |
foxbrianr | 1:86f6ebbe4fd1 | 192 | |
foxbrianr | 1:86f6ebbe4fd1 | 193 | /** Read Electronic ID |
foxbrianr | 1:86f6ebbe4fd1 | 194 | * |
foxbrianr | 1:86f6ebbe4fd1 | 195 | * @returns uint8_t Device ID |
foxbrianr | 1:86f6ebbe4fd1 | 196 | */ |
foxbrianr | 1:86f6ebbe4fd1 | 197 | uint8_t readRES(void) ; |
foxbrianr | 1:86f6ebbe4fd1 | 198 | |
foxbrianr | 1:86f6ebbe4fd1 | 199 | /** Read Configuration Register |
foxbrianr | 1:86f6ebbe4fd1 | 200 | * |
foxbrianr | 1:86f6ebbe4fd1 | 201 | * @returns uint32_t configuration register value |
foxbrianr | 1:86f6ebbe4fd1 | 202 | */ |
foxbrianr | 1:86f6ebbe4fd1 | 203 | uint32_t readConfig(void) ; |
foxbrianr | 1:86f6ebbe4fd1 | 204 | uint8_t readSFDP(int addr) ; |
foxbrianr | 1:86f6ebbe4fd1 | 205 | uint8_t readFREAD(int addr) ; |
foxbrianr | 1:86f6ebbe4fd1 | 206 | uint8_t read8(int addr) ; |
foxbrianr | 1:86f6ebbe4fd1 | 207 | void write8(int addr, uint8_t data) ; |
foxbrianr | 1:86f6ebbe4fd1 | 208 | private: |
foxbrianr | 1:86f6ebbe4fd1 | 209 | |
foxbrianr | 1:86f6ebbe4fd1 | 210 | } ; |
foxbrianr | 1:86f6ebbe4fd1 | 211 | #endif // _SPI_MX25R_H_ |