MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC2460/gpio_irq_api.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2015 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include "gpio_irq_api.h"
sahilmgandhi 18:6a4db94011d3 17 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 18 #include <stddef.h>
sahilmgandhi 18:6a4db94011d3 19 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 #define CHANNEL_NUM 48
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 static uint32_t channel_ids[CHANNEL_NUM] = {0};
sahilmgandhi 18:6a4db94011d3 24 static gpio_irq_handler irq_handler;
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 static void handle_interrupt_in(void) {
sahilmgandhi 18:6a4db94011d3 27 // Read in all current interrupt registers. We do this once as the
sahilmgandhi 18:6a4db94011d3 28 // GPIO interrupt registers are on the APB bus, and this is slow.
sahilmgandhi 18:6a4db94011d3 29 uint32_t rise0 = LPC_GPIOINT->IO0IntStatR;
sahilmgandhi 18:6a4db94011d3 30 uint32_t fall0 = LPC_GPIOINT->IO0IntStatF;
sahilmgandhi 18:6a4db94011d3 31 uint32_t rise2 = LPC_GPIOINT->IO2IntStatR;
sahilmgandhi 18:6a4db94011d3 32 uint32_t fall2 = LPC_GPIOINT->IO2IntStatF;
sahilmgandhi 18:6a4db94011d3 33 uint32_t mask0 = 0;
sahilmgandhi 18:6a4db94011d3 34 uint32_t mask2 = 0;
sahilmgandhi 18:6a4db94011d3 35 int i;
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 // P0.0-0.31
sahilmgandhi 18:6a4db94011d3 38 for (i = 0; i < 32; i++) {
sahilmgandhi 18:6a4db94011d3 39 uint32_t pmask = (1 << i);
sahilmgandhi 18:6a4db94011d3 40 if (rise0 & pmask) {
sahilmgandhi 18:6a4db94011d3 41 mask0 |= pmask;
sahilmgandhi 18:6a4db94011d3 42 if (channel_ids[i] != 0)
sahilmgandhi 18:6a4db94011d3 43 irq_handler(channel_ids[i], IRQ_RISE);
sahilmgandhi 18:6a4db94011d3 44 }
sahilmgandhi 18:6a4db94011d3 45 if (fall0 & pmask) {
sahilmgandhi 18:6a4db94011d3 46 mask0 |= pmask;
sahilmgandhi 18:6a4db94011d3 47 if (channel_ids[i] != 0)
sahilmgandhi 18:6a4db94011d3 48 irq_handler(channel_ids[i], IRQ_FALL);
sahilmgandhi 18:6a4db94011d3 49 }
sahilmgandhi 18:6a4db94011d3 50 }
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 // P2.0-2.15
sahilmgandhi 18:6a4db94011d3 53 for (i = 0; i < 16; i++) {
sahilmgandhi 18:6a4db94011d3 54 uint32_t pmask = (1 << i);
sahilmgandhi 18:6a4db94011d3 55 int channel_index = i + 32;
sahilmgandhi 18:6a4db94011d3 56 if (rise2 & pmask) {
sahilmgandhi 18:6a4db94011d3 57 mask2 |= pmask;
sahilmgandhi 18:6a4db94011d3 58 if (channel_ids[channel_index] != 0)
sahilmgandhi 18:6a4db94011d3 59 irq_handler(channel_ids[channel_index], IRQ_RISE);
sahilmgandhi 18:6a4db94011d3 60 }
sahilmgandhi 18:6a4db94011d3 61 if (fall2 & pmask) {
sahilmgandhi 18:6a4db94011d3 62 mask2 |= pmask;
sahilmgandhi 18:6a4db94011d3 63 if (channel_ids[channel_index] != 0)
sahilmgandhi 18:6a4db94011d3 64 irq_handler(channel_ids[channel_index], IRQ_FALL);
sahilmgandhi 18:6a4db94011d3 65 }
sahilmgandhi 18:6a4db94011d3 66 }
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68 // Clear the interrupts we just handled
sahilmgandhi 18:6a4db94011d3 69 LPC_GPIOINT->IO0IntClr = mask0;
sahilmgandhi 18:6a4db94011d3 70 LPC_GPIOINT->IO2IntClr = mask2;
sahilmgandhi 18:6a4db94011d3 71 }
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
sahilmgandhi 18:6a4db94011d3 74 if (pin == NC) return -1;
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 irq_handler = handler;
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78 obj->port = (int)pin & ~0x1F;
sahilmgandhi 18:6a4db94011d3 79 obj->pin = (int)pin & 0x1F;
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 // Interrupts available only on GPIO0 and GPIO2
sahilmgandhi 18:6a4db94011d3 82 if (obj->port != LPC_GPIO0_BASE && obj->port != LPC_GPIO2_BASE) {
sahilmgandhi 18:6a4db94011d3 83 error("pins on this port cannot generate interrupts");
sahilmgandhi 18:6a4db94011d3 84 }
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 // put us in the interrupt table
sahilmgandhi 18:6a4db94011d3 87 int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32;
sahilmgandhi 18:6a4db94011d3 88 channel_ids[index] = id;
sahilmgandhi 18:6a4db94011d3 89 obj->ch = index;
sahilmgandhi 18:6a4db94011d3 90
sahilmgandhi 18:6a4db94011d3 91 NVIC_SetVector(EINT3_IRQn, (uint32_t)handle_interrupt_in);
sahilmgandhi 18:6a4db94011d3 92 NVIC_EnableIRQ(EINT3_IRQn);
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 return 0;
sahilmgandhi 18:6a4db94011d3 95 }
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 void gpio_irq_free(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 98 channel_ids[obj->ch] = 0;
sahilmgandhi 18:6a4db94011d3 99 }
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
sahilmgandhi 18:6a4db94011d3 102 // ensure nothing is pending
sahilmgandhi 18:6a4db94011d3 103 switch (obj->port) {
sahilmgandhi 18:6a4db94011d3 104 case LPC_GPIO0_BASE: LPC_GPIOINT->IO0IntClr = 1 << obj->pin; break;
sahilmgandhi 18:6a4db94011d3 105 case LPC_GPIO2_BASE: LPC_GPIOINT->IO2IntClr = 1 << obj->pin; break;
sahilmgandhi 18:6a4db94011d3 106 }
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 // enable the pin interrupt
sahilmgandhi 18:6a4db94011d3 109 if (event == IRQ_RISE) {
sahilmgandhi 18:6a4db94011d3 110 switch (obj->port) {
sahilmgandhi 18:6a4db94011d3 111 case LPC_GPIO0_BASE:
sahilmgandhi 18:6a4db94011d3 112 if (enable) {
sahilmgandhi 18:6a4db94011d3 113 LPC_GPIOINT->IO0IntEnR |= 1 << obj->pin;
sahilmgandhi 18:6a4db94011d3 114 } else {
sahilmgandhi 18:6a4db94011d3 115 LPC_GPIOINT->IO0IntEnR &= ~(1 << obj->pin);
sahilmgandhi 18:6a4db94011d3 116 }
sahilmgandhi 18:6a4db94011d3 117 break;
sahilmgandhi 18:6a4db94011d3 118 case LPC_GPIO2_BASE:
sahilmgandhi 18:6a4db94011d3 119 if (enable) {
sahilmgandhi 18:6a4db94011d3 120 LPC_GPIOINT->IO2IntEnR |= 1 << obj->pin;
sahilmgandhi 18:6a4db94011d3 121 } else {
sahilmgandhi 18:6a4db94011d3 122 LPC_GPIOINT->IO2IntEnR &= ~(1 << obj->pin);
sahilmgandhi 18:6a4db94011d3 123 }
sahilmgandhi 18:6a4db94011d3 124 break;
sahilmgandhi 18:6a4db94011d3 125 }
sahilmgandhi 18:6a4db94011d3 126 } else {
sahilmgandhi 18:6a4db94011d3 127 switch (obj->port) {
sahilmgandhi 18:6a4db94011d3 128 case LPC_GPIO0_BASE:
sahilmgandhi 18:6a4db94011d3 129 if (enable) {
sahilmgandhi 18:6a4db94011d3 130 LPC_GPIOINT->IO0IntEnF |= 1 << obj->pin;
sahilmgandhi 18:6a4db94011d3 131 } else {
sahilmgandhi 18:6a4db94011d3 132 LPC_GPIOINT->IO0IntEnF &= ~(1 << obj->pin);
sahilmgandhi 18:6a4db94011d3 133 }
sahilmgandhi 18:6a4db94011d3 134 break;
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 case LPC_GPIO2_BASE:
sahilmgandhi 18:6a4db94011d3 137 if (enable) {
sahilmgandhi 18:6a4db94011d3 138 LPC_GPIOINT->IO2IntEnF |= 1 << obj->pin;
sahilmgandhi 18:6a4db94011d3 139 } else {
sahilmgandhi 18:6a4db94011d3 140 LPC_GPIOINT->IO2IntEnF &= ~(1 << obj->pin);
sahilmgandhi 18:6a4db94011d3 141 }
sahilmgandhi 18:6a4db94011d3 142 break;
sahilmgandhi 18:6a4db94011d3 143 }
sahilmgandhi 18:6a4db94011d3 144 }
sahilmgandhi 18:6a4db94011d3 145 }
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 void gpio_irq_enable(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 148 NVIC_EnableIRQ(EINT3_IRQn);
sahilmgandhi 18:6a4db94011d3 149 }
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 void gpio_irq_disable(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 152 NVIC_DisableIRQ(EINT3_IRQn);
sahilmgandhi 18:6a4db94011d3 153 }
sahilmgandhi 18:6a4db94011d3 154