MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f4xx_hal_spi.h
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 06-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief Header file of SPI HAL module.
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 * @attention
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 14 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 18 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 19 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 21 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 22 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 34 *
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 36 */
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 /* Define to prevent recursive inclusion -------------------------------------*/
sahilmgandhi 18:6a4db94011d3 39 #ifndef __STM32F4xx_HAL_SPI_H
sahilmgandhi 18:6a4db94011d3 40 #define __STM32F4xx_HAL_SPI_H
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 43 extern "C" {
sahilmgandhi 18:6a4db94011d3 44 #endif
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 47 #include "stm32f4xx_hal_def.h"
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 50 * @{
sahilmgandhi 18:6a4db94011d3 51 */
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 /** @addtogroup SPI
sahilmgandhi 18:6a4db94011d3 54 * @{
sahilmgandhi 18:6a4db94011d3 55 */
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 /* Exported types ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 58 /** @defgroup SPI_Exported_Types SPI Exported Types
sahilmgandhi 18:6a4db94011d3 59 * @{
sahilmgandhi 18:6a4db94011d3 60 */
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 /**
sahilmgandhi 18:6a4db94011d3 63 * @brief SPI Configuration Structure definition
sahilmgandhi 18:6a4db94011d3 64 */
sahilmgandhi 18:6a4db94011d3 65 typedef struct
sahilmgandhi 18:6a4db94011d3 66 {
sahilmgandhi 18:6a4db94011d3 67 uint32_t Mode; /*!< Specifies the SPI operating mode.
sahilmgandhi 18:6a4db94011d3 68 This parameter can be a value of @ref SPI_Mode */
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70 uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
sahilmgandhi 18:6a4db94011d3 71 This parameter can be a value of @ref SPI_Direction */
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 uint32_t DataSize; /*!< Specifies the SPI data size.
sahilmgandhi 18:6a4db94011d3 74 This parameter can be a value of @ref SPI_Data_Size */
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
sahilmgandhi 18:6a4db94011d3 77 This parameter can be a value of @ref SPI_Clock_Polarity */
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
sahilmgandhi 18:6a4db94011d3 80 This parameter can be a value of @ref SPI_Clock_Phase */
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
sahilmgandhi 18:6a4db94011d3 83 hardware (NSS pin) or by software using the SSI bit.
sahilmgandhi 18:6a4db94011d3 84 This parameter can be a value of @ref SPI_Slave_Select_management */
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
sahilmgandhi 18:6a4db94011d3 87 used to configure the transmit and receive SCK clock.
sahilmgandhi 18:6a4db94011d3 88 This parameter can be a value of @ref SPI_BaudRate_Prescaler
sahilmgandhi 18:6a4db94011d3 89 @note The communication clock is derived from the master
sahilmgandhi 18:6a4db94011d3 90 clock. The slave clock does not need to be set. */
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
sahilmgandhi 18:6a4db94011d3 93 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
sahilmgandhi 18:6a4db94011d3 96 This parameter can be a value of @ref SPI_TI_mode */
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
sahilmgandhi 18:6a4db94011d3 99 This parameter can be a value of @ref SPI_CRC_Calculation */
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
sahilmgandhi 18:6a4db94011d3 102 This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
sahilmgandhi 18:6a4db94011d3 103 }SPI_InitTypeDef;
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 /**
sahilmgandhi 18:6a4db94011d3 106 * @brief HAL SPI State structure definition
sahilmgandhi 18:6a4db94011d3 107 */
sahilmgandhi 18:6a4db94011d3 108 typedef enum
sahilmgandhi 18:6a4db94011d3 109 {
sahilmgandhi 18:6a4db94011d3 110 HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
sahilmgandhi 18:6a4db94011d3 111 HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
sahilmgandhi 18:6a4db94011d3 112 HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
sahilmgandhi 18:6a4db94011d3 113 HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
sahilmgandhi 18:6a4db94011d3 114 HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
sahilmgandhi 18:6a4db94011d3 115 HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
sahilmgandhi 18:6a4db94011d3 116 HAL_SPI_STATE_ERROR = 0x06U /*!< SPI error state */
sahilmgandhi 18:6a4db94011d3 117 }HAL_SPI_StateTypeDef;
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 /**
sahilmgandhi 18:6a4db94011d3 120 * @brief SPI handle Structure definition
sahilmgandhi 18:6a4db94011d3 121 */
sahilmgandhi 18:6a4db94011d3 122 typedef struct __SPI_HandleTypeDef
sahilmgandhi 18:6a4db94011d3 123 {
sahilmgandhi 18:6a4db94011d3 124 SPI_TypeDef *Instance; /* SPI registers base address */
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 SPI_InitTypeDef Init; /* SPI communication parameters */
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 uint16_t TxXferSize; /* SPI Tx Transfer size */
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132 __IO uint16_t TxXferCount; /* SPI Tx Transfer Counter */
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 uint16_t RxXferSize; /* SPI Rx Transfer size */
sahilmgandhi 18:6a4db94011d3 137
sahilmgandhi 18:6a4db94011d3 138 __IO uint16_t RxXferCount; /* SPI Rx Transfer Counter */
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148 HAL_LockTypeDef Lock; /* Locking object */
sahilmgandhi 18:6a4db94011d3 149
sahilmgandhi 18:6a4db94011d3 150 __IO HAL_SPI_StateTypeDef State; /* SPI communication state */
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152 __IO uint32_t ErrorCode; /* SPI Error code */
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 }SPI_HandleTypeDef;
sahilmgandhi 18:6a4db94011d3 155
sahilmgandhi 18:6a4db94011d3 156 /**
sahilmgandhi 18:6a4db94011d3 157 * @}
sahilmgandhi 18:6a4db94011d3 158 */
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 /* Exported constants --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 161 /** @defgroup SPI_Exported_Constants SPI Exported Constants
sahilmgandhi 18:6a4db94011d3 162 * @{
sahilmgandhi 18:6a4db94011d3 163 */
sahilmgandhi 18:6a4db94011d3 164
sahilmgandhi 18:6a4db94011d3 165 /** @defgroup SPI_Error_Code SPI Error Code
sahilmgandhi 18:6a4db94011d3 166 * @{
sahilmgandhi 18:6a4db94011d3 167 */
sahilmgandhi 18:6a4db94011d3 168 #define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
sahilmgandhi 18:6a4db94011d3 169 #define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001U) /*!< MODF error */
sahilmgandhi 18:6a4db94011d3 170 #define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002U) /*!< CRC error */
sahilmgandhi 18:6a4db94011d3 171 #define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004U) /*!< OVR error */
sahilmgandhi 18:6a4db94011d3 172 #define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008U) /*!< FRE error */
sahilmgandhi 18:6a4db94011d3 173 #define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
sahilmgandhi 18:6a4db94011d3 174 #define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020U) /*!< Flag: RXNE,TXE, BSY */
sahilmgandhi 18:6a4db94011d3 175 /**
sahilmgandhi 18:6a4db94011d3 176 * @}
sahilmgandhi 18:6a4db94011d3 177 */
sahilmgandhi 18:6a4db94011d3 178
sahilmgandhi 18:6a4db94011d3 179 /** @defgroup SPI_Mode SPI Mode
sahilmgandhi 18:6a4db94011d3 180 * @{
sahilmgandhi 18:6a4db94011d3 181 */
sahilmgandhi 18:6a4db94011d3 182 #define SPI_MODE_SLAVE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 183 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
sahilmgandhi 18:6a4db94011d3 184 /**
sahilmgandhi 18:6a4db94011d3 185 * @}
sahilmgandhi 18:6a4db94011d3 186 */
sahilmgandhi 18:6a4db94011d3 187
sahilmgandhi 18:6a4db94011d3 188 /** @defgroup SPI_Direction SPI Direction Mode
sahilmgandhi 18:6a4db94011d3 189 * @{
sahilmgandhi 18:6a4db94011d3 190 */
sahilmgandhi 18:6a4db94011d3 191 #define SPI_DIRECTION_2LINES ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 192 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
sahilmgandhi 18:6a4db94011d3 193 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
sahilmgandhi 18:6a4db94011d3 194 /**
sahilmgandhi 18:6a4db94011d3 195 * @}
sahilmgandhi 18:6a4db94011d3 196 */
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 /** @defgroup SPI_Data_Size SPI Data Size
sahilmgandhi 18:6a4db94011d3 199 * @{
sahilmgandhi 18:6a4db94011d3 200 */
sahilmgandhi 18:6a4db94011d3 201 #define SPI_DATASIZE_8BIT ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 202 #define SPI_DATASIZE_16BIT SPI_CR1_DFF
sahilmgandhi 18:6a4db94011d3 203 /**
sahilmgandhi 18:6a4db94011d3 204 * @}
sahilmgandhi 18:6a4db94011d3 205 */
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
sahilmgandhi 18:6a4db94011d3 208 * @{
sahilmgandhi 18:6a4db94011d3 209 */
sahilmgandhi 18:6a4db94011d3 210 #define SPI_POLARITY_LOW ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 211 #define SPI_POLARITY_HIGH SPI_CR1_CPOL
sahilmgandhi 18:6a4db94011d3 212 /**
sahilmgandhi 18:6a4db94011d3 213 * @}
sahilmgandhi 18:6a4db94011d3 214 */
sahilmgandhi 18:6a4db94011d3 215
sahilmgandhi 18:6a4db94011d3 216 /** @defgroup SPI_Clock_Phase SPI Clock Phase
sahilmgandhi 18:6a4db94011d3 217 * @{
sahilmgandhi 18:6a4db94011d3 218 */
sahilmgandhi 18:6a4db94011d3 219 #define SPI_PHASE_1EDGE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 220 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
sahilmgandhi 18:6a4db94011d3 221 /**
sahilmgandhi 18:6a4db94011d3 222 * @}
sahilmgandhi 18:6a4db94011d3 223 */
sahilmgandhi 18:6a4db94011d3 224
sahilmgandhi 18:6a4db94011d3 225 /** @defgroup SPI_Slave_Select_management SPI Slave Select Management
sahilmgandhi 18:6a4db94011d3 226 * @{
sahilmgandhi 18:6a4db94011d3 227 */
sahilmgandhi 18:6a4db94011d3 228 #define SPI_NSS_SOFT SPI_CR1_SSM
sahilmgandhi 18:6a4db94011d3 229 #define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 230 #define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000U)
sahilmgandhi 18:6a4db94011d3 231 /**
sahilmgandhi 18:6a4db94011d3 232 * @}
sahilmgandhi 18:6a4db94011d3 233 */
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
sahilmgandhi 18:6a4db94011d3 236 * @{
sahilmgandhi 18:6a4db94011d3 237 */
sahilmgandhi 18:6a4db94011d3 238 #define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 239 #define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008U)
sahilmgandhi 18:6a4db94011d3 240 #define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010U)
sahilmgandhi 18:6a4db94011d3 241 #define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018U)
sahilmgandhi 18:6a4db94011d3 242 #define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020U)
sahilmgandhi 18:6a4db94011d3 243 #define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028U)
sahilmgandhi 18:6a4db94011d3 244 #define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030U)
sahilmgandhi 18:6a4db94011d3 245 #define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038U)
sahilmgandhi 18:6a4db94011d3 246 /**
sahilmgandhi 18:6a4db94011d3 247 * @}
sahilmgandhi 18:6a4db94011d3 248 */
sahilmgandhi 18:6a4db94011d3 249
sahilmgandhi 18:6a4db94011d3 250 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
sahilmgandhi 18:6a4db94011d3 251 * @{
sahilmgandhi 18:6a4db94011d3 252 */
sahilmgandhi 18:6a4db94011d3 253 #define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 254 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
sahilmgandhi 18:6a4db94011d3 255 /**
sahilmgandhi 18:6a4db94011d3 256 * @}
sahilmgandhi 18:6a4db94011d3 257 */
sahilmgandhi 18:6a4db94011d3 258
sahilmgandhi 18:6a4db94011d3 259 /** @defgroup SPI_TI_mode SPI TI Mode
sahilmgandhi 18:6a4db94011d3 260 * @{
sahilmgandhi 18:6a4db94011d3 261 */
sahilmgandhi 18:6a4db94011d3 262 #define SPI_TIMODE_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 263 #define SPI_TIMODE_ENABLE SPI_CR2_FRF
sahilmgandhi 18:6a4db94011d3 264 /**
sahilmgandhi 18:6a4db94011d3 265 * @}
sahilmgandhi 18:6a4db94011d3 266 */
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
sahilmgandhi 18:6a4db94011d3 269 * @{
sahilmgandhi 18:6a4db94011d3 270 */
sahilmgandhi 18:6a4db94011d3 271 #define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 272 #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
sahilmgandhi 18:6a4db94011d3 273 /**
sahilmgandhi 18:6a4db94011d3 274 * @}
sahilmgandhi 18:6a4db94011d3 275 */
sahilmgandhi 18:6a4db94011d3 276
sahilmgandhi 18:6a4db94011d3 277 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
sahilmgandhi 18:6a4db94011d3 278 * @{
sahilmgandhi 18:6a4db94011d3 279 */
sahilmgandhi 18:6a4db94011d3 280 #define SPI_IT_TXE SPI_CR2_TXEIE
sahilmgandhi 18:6a4db94011d3 281 #define SPI_IT_RXNE SPI_CR2_RXNEIE
sahilmgandhi 18:6a4db94011d3 282 #define SPI_IT_ERR SPI_CR2_ERRIE
sahilmgandhi 18:6a4db94011d3 283 /**
sahilmgandhi 18:6a4db94011d3 284 * @}
sahilmgandhi 18:6a4db94011d3 285 */
sahilmgandhi 18:6a4db94011d3 286
sahilmgandhi 18:6a4db94011d3 287 /** @defgroup SPI_Flags_definition SPI Flags Definition
sahilmgandhi 18:6a4db94011d3 288 * @{
sahilmgandhi 18:6a4db94011d3 289 */
sahilmgandhi 18:6a4db94011d3 290 #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
sahilmgandhi 18:6a4db94011d3 291 #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
sahilmgandhi 18:6a4db94011d3 292 #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
sahilmgandhi 18:6a4db94011d3 293 #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
sahilmgandhi 18:6a4db94011d3 294 #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
sahilmgandhi 18:6a4db94011d3 295 #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
sahilmgandhi 18:6a4db94011d3 296 #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
sahilmgandhi 18:6a4db94011d3 297 /**
sahilmgandhi 18:6a4db94011d3 298 * @}
sahilmgandhi 18:6a4db94011d3 299 */
sahilmgandhi 18:6a4db94011d3 300
sahilmgandhi 18:6a4db94011d3 301 /**
sahilmgandhi 18:6a4db94011d3 302 * @}
sahilmgandhi 18:6a4db94011d3 303 */
sahilmgandhi 18:6a4db94011d3 304
sahilmgandhi 18:6a4db94011d3 305 /* Exported macro ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 306 /** @defgroup SPI_Exported_Macros SPI Exported Macros
sahilmgandhi 18:6a4db94011d3 307 * @{
sahilmgandhi 18:6a4db94011d3 308 */
sahilmgandhi 18:6a4db94011d3 309
sahilmgandhi 18:6a4db94011d3 310 /** @brief Reset SPI handle state.
sahilmgandhi 18:6a4db94011d3 311 * @param __HANDLE__: specifies the SPI Handle.
sahilmgandhi 18:6a4db94011d3 312 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
sahilmgandhi 18:6a4db94011d3 313 * @retval None
sahilmgandhi 18:6a4db94011d3 314 */
sahilmgandhi 18:6a4db94011d3 315 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
sahilmgandhi 18:6a4db94011d3 316
sahilmgandhi 18:6a4db94011d3 317 /** @brief Enable or disable the specified SPI interrupts.
sahilmgandhi 18:6a4db94011d3 318 * @param __HANDLE__: specifies the SPI Handle.
sahilmgandhi 18:6a4db94011d3 319 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
sahilmgandhi 18:6a4db94011d3 320 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
sahilmgandhi 18:6a4db94011d3 321 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 322 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
sahilmgandhi 18:6a4db94011d3 323 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
sahilmgandhi 18:6a4db94011d3 324 * @arg SPI_IT_ERR: Error interrupt enable
sahilmgandhi 18:6a4db94011d3 325 * @retval None
sahilmgandhi 18:6a4db94011d3 326 */
sahilmgandhi 18:6a4db94011d3 327 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
sahilmgandhi 18:6a4db94011d3 328 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
sahilmgandhi 18:6a4db94011d3 329
sahilmgandhi 18:6a4db94011d3 330 /** @brief Check whether the specified SPI interrupt source is enabled or not.
sahilmgandhi 18:6a4db94011d3 331 * @param __HANDLE__: specifies the SPI Handle.
sahilmgandhi 18:6a4db94011d3 332 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
sahilmgandhi 18:6a4db94011d3 333 * @param __INTERRUPT__: specifies the SPI interrupt source to check.
sahilmgandhi 18:6a4db94011d3 334 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 335 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
sahilmgandhi 18:6a4db94011d3 336 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
sahilmgandhi 18:6a4db94011d3 337 * @arg SPI_IT_ERR: Error interrupt enable
sahilmgandhi 18:6a4db94011d3 338 * @retval The new state of __IT__ (TRUE or FALSE).
sahilmgandhi 18:6a4db94011d3 339 */
sahilmgandhi 18:6a4db94011d3 340 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
sahilmgandhi 18:6a4db94011d3 341
sahilmgandhi 18:6a4db94011d3 342 /** @brief Check whether the specified SPI flag is set or not.
sahilmgandhi 18:6a4db94011d3 343 * @param __HANDLE__: specifies the SPI Handle.
sahilmgandhi 18:6a4db94011d3 344 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
sahilmgandhi 18:6a4db94011d3 345 * @param __FLAG__: specifies the flag to check.
sahilmgandhi 18:6a4db94011d3 346 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 347 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
sahilmgandhi 18:6a4db94011d3 348 * @arg SPI_FLAG_TXE: Transmit buffer empty flag
sahilmgandhi 18:6a4db94011d3 349 * @arg SPI_FLAG_CRCERR: CRC error flag
sahilmgandhi 18:6a4db94011d3 350 * @arg SPI_FLAG_MODF: Mode fault flag
sahilmgandhi 18:6a4db94011d3 351 * @arg SPI_FLAG_OVR: Overrun flag
sahilmgandhi 18:6a4db94011d3 352 * @arg SPI_FLAG_BSY: Busy flag
sahilmgandhi 18:6a4db94011d3 353 * @arg SPI_FLAG_FRE: Frame format error flag
sahilmgandhi 18:6a4db94011d3 354 * @retval The new state of __FLAG__ (TRUE or FALSE).
sahilmgandhi 18:6a4db94011d3 355 */
sahilmgandhi 18:6a4db94011d3 356 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
sahilmgandhi 18:6a4db94011d3 357
sahilmgandhi 18:6a4db94011d3 358 /** @brief Clear the SPI CRCERR pending flag.
sahilmgandhi 18:6a4db94011d3 359 * @param __HANDLE__: specifies the SPI Handle.
sahilmgandhi 18:6a4db94011d3 360 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
sahilmgandhi 18:6a4db94011d3 361 * @retval None
sahilmgandhi 18:6a4db94011d3 362 */
sahilmgandhi 18:6a4db94011d3 363 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
sahilmgandhi 18:6a4db94011d3 364
sahilmgandhi 18:6a4db94011d3 365 /** @brief Clear the SPI MODF pending flag.
sahilmgandhi 18:6a4db94011d3 366 * @param __HANDLE__: specifies the SPI Handle.
sahilmgandhi 18:6a4db94011d3 367 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
sahilmgandhi 18:6a4db94011d3 368 * @retval None
sahilmgandhi 18:6a4db94011d3 369 */
sahilmgandhi 18:6a4db94011d3 370 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
sahilmgandhi 18:6a4db94011d3 371 do{ \
sahilmgandhi 18:6a4db94011d3 372 __IO uint32_t tmpreg_modf = 0x00U; \
sahilmgandhi 18:6a4db94011d3 373 tmpreg_modf = (__HANDLE__)->Instance->SR; \
sahilmgandhi 18:6a4db94011d3 374 (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
sahilmgandhi 18:6a4db94011d3 375 UNUSED(tmpreg_modf); \
sahilmgandhi 18:6a4db94011d3 376 } while(0)
sahilmgandhi 18:6a4db94011d3 377
sahilmgandhi 18:6a4db94011d3 378 /** @brief Clear the SPI OVR pending flag.
sahilmgandhi 18:6a4db94011d3 379 * @param __HANDLE__: specifies the SPI Handle.
sahilmgandhi 18:6a4db94011d3 380 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
sahilmgandhi 18:6a4db94011d3 381 * @retval None
sahilmgandhi 18:6a4db94011d3 382 */
sahilmgandhi 18:6a4db94011d3 383 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
sahilmgandhi 18:6a4db94011d3 384 do{ \
sahilmgandhi 18:6a4db94011d3 385 __IO uint32_t tmpreg_ovr = 0x00U; \
sahilmgandhi 18:6a4db94011d3 386 tmpreg_ovr = (__HANDLE__)->Instance->DR; \
sahilmgandhi 18:6a4db94011d3 387 tmpreg_ovr = (__HANDLE__)->Instance->SR; \
sahilmgandhi 18:6a4db94011d3 388 UNUSED(tmpreg_ovr); \
sahilmgandhi 18:6a4db94011d3 389 } while(0)
sahilmgandhi 18:6a4db94011d3 390
sahilmgandhi 18:6a4db94011d3 391 /** @brief Clear the SPI FRE pending flag.
sahilmgandhi 18:6a4db94011d3 392 * @param __HANDLE__: specifies the SPI Handle.
sahilmgandhi 18:6a4db94011d3 393 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
sahilmgandhi 18:6a4db94011d3 394 * @retval None
sahilmgandhi 18:6a4db94011d3 395 */
sahilmgandhi 18:6a4db94011d3 396 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
sahilmgandhi 18:6a4db94011d3 397 do{ \
sahilmgandhi 18:6a4db94011d3 398 __IO uint32_t tmpreg_fre = 0x00U; \
sahilmgandhi 18:6a4db94011d3 399 tmpreg_fre = (__HANDLE__)->Instance->SR; \
sahilmgandhi 18:6a4db94011d3 400 UNUSED(tmpreg_fre); \
sahilmgandhi 18:6a4db94011d3 401 }while(0)
sahilmgandhi 18:6a4db94011d3 402
sahilmgandhi 18:6a4db94011d3 403 /** @brief Enable the SPI peripheral.
sahilmgandhi 18:6a4db94011d3 404 * @param __HANDLE__: specifies the SPI Handle.
sahilmgandhi 18:6a4db94011d3 405 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
sahilmgandhi 18:6a4db94011d3 406 * @retval None
sahilmgandhi 18:6a4db94011d3 407 */
sahilmgandhi 18:6a4db94011d3 408 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
sahilmgandhi 18:6a4db94011d3 409
sahilmgandhi 18:6a4db94011d3 410 /** @brief Disable the SPI peripheral.
sahilmgandhi 18:6a4db94011d3 411 * @param __HANDLE__: specifies the SPI Handle.
sahilmgandhi 18:6a4db94011d3 412 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
sahilmgandhi 18:6a4db94011d3 413 * @retval None
sahilmgandhi 18:6a4db94011d3 414 */
sahilmgandhi 18:6a4db94011d3 415 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
sahilmgandhi 18:6a4db94011d3 416 /**
sahilmgandhi 18:6a4db94011d3 417 * @}
sahilmgandhi 18:6a4db94011d3 418 */
sahilmgandhi 18:6a4db94011d3 419
sahilmgandhi 18:6a4db94011d3 420 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 421 /** @addtogroup SPI_Exported_Functions
sahilmgandhi 18:6a4db94011d3 422 * @{
sahilmgandhi 18:6a4db94011d3 423 */
sahilmgandhi 18:6a4db94011d3 424
sahilmgandhi 18:6a4db94011d3 425 /** @addtogroup SPI_Exported_Functions_Group1
sahilmgandhi 18:6a4db94011d3 426 * @{
sahilmgandhi 18:6a4db94011d3 427 */
sahilmgandhi 18:6a4db94011d3 428 /* Initialization/de-initialization functions **********************************/
sahilmgandhi 18:6a4db94011d3 429 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 430 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 431 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 432 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 433 /**
sahilmgandhi 18:6a4db94011d3 434 * @}
sahilmgandhi 18:6a4db94011d3 435 */
sahilmgandhi 18:6a4db94011d3 436
sahilmgandhi 18:6a4db94011d3 437 /** @addtogroup SPI_Exported_Functions_Group2
sahilmgandhi 18:6a4db94011d3 438 * @{
sahilmgandhi 18:6a4db94011d3 439 */
sahilmgandhi 18:6a4db94011d3 440 /* I/O operation functions *****************************************************/
sahilmgandhi 18:6a4db94011d3 441 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
sahilmgandhi 18:6a4db94011d3 442 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
sahilmgandhi 18:6a4db94011d3 443 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
sahilmgandhi 18:6a4db94011d3 444 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
sahilmgandhi 18:6a4db94011d3 445 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
sahilmgandhi 18:6a4db94011d3 446 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
sahilmgandhi 18:6a4db94011d3 447 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
sahilmgandhi 18:6a4db94011d3 448 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
sahilmgandhi 18:6a4db94011d3 449 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
sahilmgandhi 18:6a4db94011d3 450 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 451 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 452 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 453
sahilmgandhi 18:6a4db94011d3 454 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 455 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 456 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 457 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 458 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 459 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 460 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 461 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 462 /**
sahilmgandhi 18:6a4db94011d3 463 * @}
sahilmgandhi 18:6a4db94011d3 464 */
sahilmgandhi 18:6a4db94011d3 465
sahilmgandhi 18:6a4db94011d3 466 /** @addtogroup SPI_Exported_Functions_Group3
sahilmgandhi 18:6a4db94011d3 467 * @{
sahilmgandhi 18:6a4db94011d3 468 */
sahilmgandhi 18:6a4db94011d3 469 /* Peripheral State and Error functions ***************************************/
sahilmgandhi 18:6a4db94011d3 470 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 471 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 472 /**
sahilmgandhi 18:6a4db94011d3 473 * @}
sahilmgandhi 18:6a4db94011d3 474 */
sahilmgandhi 18:6a4db94011d3 475
sahilmgandhi 18:6a4db94011d3 476 /**
sahilmgandhi 18:6a4db94011d3 477 * @}
sahilmgandhi 18:6a4db94011d3 478 */
sahilmgandhi 18:6a4db94011d3 479
sahilmgandhi 18:6a4db94011d3 480 /* Private types -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 481 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 482 /* Private constants ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 483
sahilmgandhi 18:6a4db94011d3 484 /* Private macros ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 485 /** @defgroup SPI_Private_Macros SPI Private Macros
sahilmgandhi 18:6a4db94011d3 486 * @{
sahilmgandhi 18:6a4db94011d3 487 */
sahilmgandhi 18:6a4db94011d3 488
sahilmgandhi 18:6a4db94011d3 489 /** @brief Set the SPI transmit-only mode.
sahilmgandhi 18:6a4db94011d3 490 * @param __HANDLE__: specifies the SPI Handle.
sahilmgandhi 18:6a4db94011d3 491 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
sahilmgandhi 18:6a4db94011d3 492 * @retval None
sahilmgandhi 18:6a4db94011d3 493 */
sahilmgandhi 18:6a4db94011d3 494 #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
sahilmgandhi 18:6a4db94011d3 495
sahilmgandhi 18:6a4db94011d3 496 /** @brief Set the SPI receive-only mode.
sahilmgandhi 18:6a4db94011d3 497 * @param __HANDLE__: specifies the SPI Handle.
sahilmgandhi 18:6a4db94011d3 498 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
sahilmgandhi 18:6a4db94011d3 499 * @retval None
sahilmgandhi 18:6a4db94011d3 500 */
sahilmgandhi 18:6a4db94011d3 501 #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
sahilmgandhi 18:6a4db94011d3 502
sahilmgandhi 18:6a4db94011d3 503 /** @brief Reset the CRC calculation of the SPI.
sahilmgandhi 18:6a4db94011d3 504 * @param __HANDLE__: specifies the SPI Handle.
sahilmgandhi 18:6a4db94011d3 505 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
sahilmgandhi 18:6a4db94011d3 506 * @retval None
sahilmgandhi 18:6a4db94011d3 507 */
sahilmgandhi 18:6a4db94011d3 508 #define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
sahilmgandhi 18:6a4db94011d3 509 (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
sahilmgandhi 18:6a4db94011d3 510
sahilmgandhi 18:6a4db94011d3 511 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
sahilmgandhi 18:6a4db94011d3 512 ((MODE) == SPI_MODE_MASTER))
sahilmgandhi 18:6a4db94011d3 513
sahilmgandhi 18:6a4db94011d3 514 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
sahilmgandhi 18:6a4db94011d3 515 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
sahilmgandhi 18:6a4db94011d3 516 ((MODE) == SPI_DIRECTION_1LINE))
sahilmgandhi 18:6a4db94011d3 517
sahilmgandhi 18:6a4db94011d3 518 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
sahilmgandhi 18:6a4db94011d3 519
sahilmgandhi 18:6a4db94011d3 520 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
sahilmgandhi 18:6a4db94011d3 521 ((MODE) == SPI_DIRECTION_1LINE))
sahilmgandhi 18:6a4db94011d3 522
sahilmgandhi 18:6a4db94011d3 523 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
sahilmgandhi 18:6a4db94011d3 524 ((DATASIZE) == SPI_DATASIZE_8BIT))
sahilmgandhi 18:6a4db94011d3 525
sahilmgandhi 18:6a4db94011d3 526 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
sahilmgandhi 18:6a4db94011d3 527 ((CPOL) == SPI_POLARITY_HIGH))
sahilmgandhi 18:6a4db94011d3 528
sahilmgandhi 18:6a4db94011d3 529 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
sahilmgandhi 18:6a4db94011d3 530 ((CPHA) == SPI_PHASE_2EDGE))
sahilmgandhi 18:6a4db94011d3 531
sahilmgandhi 18:6a4db94011d3 532 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
sahilmgandhi 18:6a4db94011d3 533 ((NSS) == SPI_NSS_HARD_INPUT) || \
sahilmgandhi 18:6a4db94011d3 534 ((NSS) == SPI_NSS_HARD_OUTPUT))
sahilmgandhi 18:6a4db94011d3 535
sahilmgandhi 18:6a4db94011d3 536 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
sahilmgandhi 18:6a4db94011d3 537 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
sahilmgandhi 18:6a4db94011d3 538 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
sahilmgandhi 18:6a4db94011d3 539 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
sahilmgandhi 18:6a4db94011d3 540 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
sahilmgandhi 18:6a4db94011d3 541 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
sahilmgandhi 18:6a4db94011d3 542 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
sahilmgandhi 18:6a4db94011d3 543 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
sahilmgandhi 18:6a4db94011d3 544
sahilmgandhi 18:6a4db94011d3 545 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
sahilmgandhi 18:6a4db94011d3 546 ((BIT) == SPI_FIRSTBIT_LSB))
sahilmgandhi 18:6a4db94011d3 547
sahilmgandhi 18:6a4db94011d3 548 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
sahilmgandhi 18:6a4db94011d3 549 ((MODE) == SPI_TIMODE_ENABLE))
sahilmgandhi 18:6a4db94011d3 550
sahilmgandhi 18:6a4db94011d3 551 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
sahilmgandhi 18:6a4db94011d3 552 ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
sahilmgandhi 18:6a4db94011d3 553
sahilmgandhi 18:6a4db94011d3 554 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU))
sahilmgandhi 18:6a4db94011d3 555
sahilmgandhi 18:6a4db94011d3 556 /**
sahilmgandhi 18:6a4db94011d3 557 * @}
sahilmgandhi 18:6a4db94011d3 558 */
sahilmgandhi 18:6a4db94011d3 559
sahilmgandhi 18:6a4db94011d3 560 /* Private functions ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 561 /** @defgroup SPI_Private_Functions SPI Private Functions
sahilmgandhi 18:6a4db94011d3 562 * @{
sahilmgandhi 18:6a4db94011d3 563 */
sahilmgandhi 18:6a4db94011d3 564
sahilmgandhi 18:6a4db94011d3 565 /**
sahilmgandhi 18:6a4db94011d3 566 * @}
sahilmgandhi 18:6a4db94011d3 567 */
sahilmgandhi 18:6a4db94011d3 568
sahilmgandhi 18:6a4db94011d3 569 /**
sahilmgandhi 18:6a4db94011d3 570 * @}
sahilmgandhi 18:6a4db94011d3 571 */
sahilmgandhi 18:6a4db94011d3 572
sahilmgandhi 18:6a4db94011d3 573 /**
sahilmgandhi 18:6a4db94011d3 574 * @}
sahilmgandhi 18:6a4db94011d3 575 */
sahilmgandhi 18:6a4db94011d3 576
sahilmgandhi 18:6a4db94011d3 577 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 578 }
sahilmgandhi 18:6a4db94011d3 579 #endif
sahilmgandhi 18:6a4db94011d3 580
sahilmgandhi 18:6a4db94011d3 581 #endif /* __STM32F4xx_HAL_SPI_H */
sahilmgandhi 18:6a4db94011d3 582
sahilmgandhi 18:6a4db94011d3 583 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/