MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_GCC_ARM/startup_LPC824.S@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* File: startup_ARMCM0.S
sahilmgandhi 18:6a4db94011d3 2 * Purpose: startup file for Cortex-M0 devices. Should use with
sahilmgandhi 18:6a4db94011d3 3 * GCC for ARM Embedded Processors
sahilmgandhi 18:6a4db94011d3 4 * Version: V1.2
sahilmgandhi 18:6a4db94011d3 5 * Date: 15 Nov 2011
sahilmgandhi 18:6a4db94011d3 6 *
sahilmgandhi 18:6a4db94011d3 7 * Copyright (c) 2011, ARM Limited
sahilmgandhi 18:6a4db94011d3 8 * All rights reserved.
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 11 * modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 12 * Redistributions of source code must retain the above copyright
sahilmgandhi 18:6a4db94011d3 13 notice, this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 14 * Redistributions in binary form must reproduce the above copyright
sahilmgandhi 18:6a4db94011d3 15 notice, this list of conditions and the following disclaimer in the
sahilmgandhi 18:6a4db94011d3 16 documentation and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 17 * Neither the name of the ARM Limited nor the
sahilmgandhi 18:6a4db94011d3 18 names of its contributors may be used to endorse or promote products
sahilmgandhi 18:6a4db94011d3 19 derived from this software without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 20 *
sahilmgandhi 18:6a4db94011d3 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
sahilmgandhi 18:6a4db94011d3 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
sahilmgandhi 18:6a4db94011d3 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 24 * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
sahilmgandhi 18:6a4db94011d3 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
sahilmgandhi 18:6a4db94011d3 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
sahilmgandhi 18:6a4db94011d3 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
sahilmgandhi 18:6a4db94011d3 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
sahilmgandhi 18:6a4db94011d3 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
sahilmgandhi 18:6a4db94011d3 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 31 */
sahilmgandhi 18:6a4db94011d3 32 .syntax unified
sahilmgandhi 18:6a4db94011d3 33 .arch armv6-m
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 /* Memory Model
sahilmgandhi 18:6a4db94011d3 36 The HEAP starts at the end of the DATA section and grows upward.
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 The STACK starts at the end of the RAM and grows downward.
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 The HEAP and stack STACK are only checked at compile time:
sahilmgandhi 18:6a4db94011d3 41 (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 This is just a check for the bare minimum for the Heap+Stack area before
sahilmgandhi 18:6a4db94011d3 44 aborting compilation, it is not the run time limit:
sahilmgandhi 18:6a4db94011d3 45 Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
sahilmgandhi 18:6a4db94011d3 46 */
sahilmgandhi 18:6a4db94011d3 47 .section .stack
sahilmgandhi 18:6a4db94011d3 48 .align 3
sahilmgandhi 18:6a4db94011d3 49 #ifdef __STACK_SIZE
sahilmgandhi 18:6a4db94011d3 50 .equ Stack_Size, __STACK_SIZE
sahilmgandhi 18:6a4db94011d3 51 #else
sahilmgandhi 18:6a4db94011d3 52 .equ Stack_Size, 0x80
sahilmgandhi 18:6a4db94011d3 53 #endif
sahilmgandhi 18:6a4db94011d3 54 .globl __StackTop
sahilmgandhi 18:6a4db94011d3 55 .globl __StackLimit
sahilmgandhi 18:6a4db94011d3 56 __StackLimit:
sahilmgandhi 18:6a4db94011d3 57 .space Stack_Size
sahilmgandhi 18:6a4db94011d3 58 .size __StackLimit, . - __StackLimit
sahilmgandhi 18:6a4db94011d3 59 __StackTop:
sahilmgandhi 18:6a4db94011d3 60 .size __StackTop, . - __StackTop
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 .section .heap
sahilmgandhi 18:6a4db94011d3 63 .align 3
sahilmgandhi 18:6a4db94011d3 64 #ifdef __HEAP_SIZE
sahilmgandhi 18:6a4db94011d3 65 .equ Heap_Size, __HEAP_SIZE
sahilmgandhi 18:6a4db94011d3 66 #else
sahilmgandhi 18:6a4db94011d3 67 .equ Heap_Size, 0x80
sahilmgandhi 18:6a4db94011d3 68 #endif
sahilmgandhi 18:6a4db94011d3 69 .globl __HeapBase
sahilmgandhi 18:6a4db94011d3 70 .globl __HeapLimit
sahilmgandhi 18:6a4db94011d3 71 __HeapBase:
sahilmgandhi 18:6a4db94011d3 72 .space Heap_Size
sahilmgandhi 18:6a4db94011d3 73 .size __HeapBase, . - __HeapBase
sahilmgandhi 18:6a4db94011d3 74 __HeapLimit:
sahilmgandhi 18:6a4db94011d3 75 .size __HeapLimit, . - __HeapLimit
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 .section .isr_vector
sahilmgandhi 18:6a4db94011d3 78 .align 2
sahilmgandhi 18:6a4db94011d3 79 .globl __isr_vector
sahilmgandhi 18:6a4db94011d3 80 __isr_vector:
sahilmgandhi 18:6a4db94011d3 81 .long __StackTop /* Top of Stack */
sahilmgandhi 18:6a4db94011d3 82 .long Reset_Handler /* Reset Handler */
sahilmgandhi 18:6a4db94011d3 83 .long NMI_Handler /* NMI Handler */
sahilmgandhi 18:6a4db94011d3 84 .long HardFault_Handler /* Hard Fault Handler */
sahilmgandhi 18:6a4db94011d3 85 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 86 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 87 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 88 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 89 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 90 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 91 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 92 .long SVC_Handler /* SVCall Handler */
sahilmgandhi 18:6a4db94011d3 93 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 94 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 95 .long PendSV_Handler /* PendSV Handler */
sahilmgandhi 18:6a4db94011d3 96 .long SysTick_Handler /* SysTick Handler */
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 /* LPC824 interrupts */
sahilmgandhi 18:6a4db94011d3 99 .long SPI0_IRQHandler // SPI0 controller
sahilmgandhi 18:6a4db94011d3 100 .long SPI1_IRQHandler // SPI1 controller
sahilmgandhi 18:6a4db94011d3 101 .long 0 // Reserved
sahilmgandhi 18:6a4db94011d3 102 .long UART0_IRQHandler // UART0
sahilmgandhi 18:6a4db94011d3 103 .long UART1_IRQHandler // UART1
sahilmgandhi 18:6a4db94011d3 104 .long UART2_IRQHandler // UART2
sahilmgandhi 18:6a4db94011d3 105 .long 0 // Reserved
sahilmgandhi 18:6a4db94011d3 106 .long I2C1_IRQHandler // I2C ch1 controller
sahilmgandhi 18:6a4db94011d3 107 .long I2C0_IRQHandler // I2C ch0 controller
sahilmgandhi 18:6a4db94011d3 108 .long SCT_IRQHandler // Smart Counter Timer
sahilmgandhi 18:6a4db94011d3 109 .long MRT_IRQHandler // Multi-Rate Timer
sahilmgandhi 18:6a4db94011d3 110 .long CMP_IRQHandler // Comparator
sahilmgandhi 18:6a4db94011d3 111 .long WDT_IRQHandler // PIO1 (0:11)
sahilmgandhi 18:6a4db94011d3 112 .long BOD_IRQHandler // Brown Out Detect
sahilmgandhi 18:6a4db94011d3 113 .long Flash_IRQHandler // Flash interrupt
sahilmgandhi 18:6a4db94011d3 114 .long WKT_IRQHandler // Wakeup timer
sahilmgandhi 18:6a4db94011d3 115 .long ADC_SEQA_IRQHandler // ADC sequence A completion
sahilmgandhi 18:6a4db94011d3 116 .long ADC_SEQB_IRQHandler // ADC sequence B completion
sahilmgandhi 18:6a4db94011d3 117 .long ADC_THCMP_IRQHandler // ADC threshold compare
sahilmgandhi 18:6a4db94011d3 118 .long ADC_OVR_IRQHandler // ADC overrun
sahilmgandhi 18:6a4db94011d3 119 .long DMA_IRQHandler // DMA interrupt
sahilmgandhi 18:6a4db94011d3 120 .long I2C2_IRQHandler // I2C2 controller
sahilmgandhi 18:6a4db94011d3 121 .long I2C3_IRQHandler // I2C3 controller
sahilmgandhi 18:6a4db94011d3 122 .long 0 // Reserved
sahilmgandhi 18:6a4db94011d3 123 .long PININT0_IRQHandler // PIO INT0
sahilmgandhi 18:6a4db94011d3 124 .long PININT1_IRQHandler // PIO INT1
sahilmgandhi 18:6a4db94011d3 125 .long PININT2_IRQHandler // PIO INT2
sahilmgandhi 18:6a4db94011d3 126 .long PININT3_IRQHandler // PIO INT3
sahilmgandhi 18:6a4db94011d3 127 .long PININT4_IRQHandler // PIO INT4
sahilmgandhi 18:6a4db94011d3 128 .long PININT5_IRQHandler // PIO INT5
sahilmgandhi 18:6a4db94011d3 129 .long PININT6_IRQHandler // PIO INT6
sahilmgandhi 18:6a4db94011d3 130 .long PININT7_IRQHandler // PIO INT7
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132 .size __isr_vector, . - __isr_vector
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 .section .text.Reset_Handler
sahilmgandhi 18:6a4db94011d3 135 .thumb
sahilmgandhi 18:6a4db94011d3 136 .thumb_func
sahilmgandhi 18:6a4db94011d3 137 .align 2
sahilmgandhi 18:6a4db94011d3 138 .globl Reset_Handler
sahilmgandhi 18:6a4db94011d3 139 .type Reset_Handler, %function
sahilmgandhi 18:6a4db94011d3 140 Reset_Handler:
sahilmgandhi 18:6a4db94011d3 141 /* Loop to copy data from read only memory to RAM. The ranges
sahilmgandhi 18:6a4db94011d3 142 * of copy from/to are specified by following symbols evaluated in
sahilmgandhi 18:6a4db94011d3 143 * linker script.
sahilmgandhi 18:6a4db94011d3 144 * __etext: End of code section, i.e., begin of data sections to copy from.
sahilmgandhi 18:6a4db94011d3 145 * __data_start__/__data_end__: RAM address range that data should be
sahilmgandhi 18:6a4db94011d3 146 * copied to. Both must be aligned to 4 bytes boundary. */
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148 ldr r1, =__etext
sahilmgandhi 18:6a4db94011d3 149 ldr r2, =__data_start__
sahilmgandhi 18:6a4db94011d3 150 ldr r3, =__data_end__
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152 subs r3, r2
sahilmgandhi 18:6a4db94011d3 153 ble .Lflash_to_ram_loop_end
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 movs r4, 0
sahilmgandhi 18:6a4db94011d3 156 .Lflash_to_ram_loop:
sahilmgandhi 18:6a4db94011d3 157 ldr r0, [r1,r4]
sahilmgandhi 18:6a4db94011d3 158 str r0, [r2,r4]
sahilmgandhi 18:6a4db94011d3 159 adds r4, 4
sahilmgandhi 18:6a4db94011d3 160 cmp r4, r3
sahilmgandhi 18:6a4db94011d3 161 blt .Lflash_to_ram_loop
sahilmgandhi 18:6a4db94011d3 162 .Lflash_to_ram_loop_end:
sahilmgandhi 18:6a4db94011d3 163
sahilmgandhi 18:6a4db94011d3 164 ldr r0, =SystemInit
sahilmgandhi 18:6a4db94011d3 165 blx r0
sahilmgandhi 18:6a4db94011d3 166 ldr r0, =_start
sahilmgandhi 18:6a4db94011d3 167 bx r0
sahilmgandhi 18:6a4db94011d3 168 .pool
sahilmgandhi 18:6a4db94011d3 169 .size Reset_Handler, . - Reset_Handler
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 .text
sahilmgandhi 18:6a4db94011d3 172 /* Macro to define default handlers. Default handler
sahilmgandhi 18:6a4db94011d3 173 * will be weak symbol and just dead loops. They can be
sahilmgandhi 18:6a4db94011d3 174 * overwritten by other handlers */
sahilmgandhi 18:6a4db94011d3 175 .macro def_default_handler handler_name
sahilmgandhi 18:6a4db94011d3 176 .align 1
sahilmgandhi 18:6a4db94011d3 177 .thumb_func
sahilmgandhi 18:6a4db94011d3 178 .weak \handler_name
sahilmgandhi 18:6a4db94011d3 179 .type \handler_name, %function
sahilmgandhi 18:6a4db94011d3 180 \handler_name :
sahilmgandhi 18:6a4db94011d3 181 b .
sahilmgandhi 18:6a4db94011d3 182 .size \handler_name, . - \handler_name
sahilmgandhi 18:6a4db94011d3 183 .endm
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 def_default_handler NMI_Handler
sahilmgandhi 18:6a4db94011d3 186 def_default_handler HardFault_Handler
sahilmgandhi 18:6a4db94011d3 187 def_default_handler SVC_Handler
sahilmgandhi 18:6a4db94011d3 188 def_default_handler PendSV_Handler
sahilmgandhi 18:6a4db94011d3 189 def_default_handler SysTick_Handler
sahilmgandhi 18:6a4db94011d3 190 def_default_handler Default_Handler
sahilmgandhi 18:6a4db94011d3 191
sahilmgandhi 18:6a4db94011d3 192 .macro def_irq_default_handler handler_name
sahilmgandhi 18:6a4db94011d3 193 .weak \handler_name
sahilmgandhi 18:6a4db94011d3 194 .set \handler_name, Default_Handler
sahilmgandhi 18:6a4db94011d3 195 .endm
sahilmgandhi 18:6a4db94011d3 196
sahilmgandhi 18:6a4db94011d3 197 def_irq_default_handler SPI0_IRQHandler
sahilmgandhi 18:6a4db94011d3 198 def_irq_default_handler SPI1_IRQHandler
sahilmgandhi 18:6a4db94011d3 199 def_irq_default_handler UART0_IRQHandler
sahilmgandhi 18:6a4db94011d3 200 def_irq_default_handler UART1_IRQHandler
sahilmgandhi 18:6a4db94011d3 201 def_irq_default_handler UART2_IRQHandler
sahilmgandhi 18:6a4db94011d3 202 def_irq_default_handler I2C0_IRQHandler
sahilmgandhi 18:6a4db94011d3 203 def_irq_default_handler I2C1_IRQHandler
sahilmgandhi 18:6a4db94011d3 204 def_irq_default_handler I2C2_IRQHandler
sahilmgandhi 18:6a4db94011d3 205 def_irq_default_handler I2C3_IRQHandler
sahilmgandhi 18:6a4db94011d3 206 def_irq_default_handler SCT_IRQHandler
sahilmgandhi 18:6a4db94011d3 207 def_irq_default_handler MRT_IRQHandler
sahilmgandhi 18:6a4db94011d3 208 def_irq_default_handler CMP_IRQHandler
sahilmgandhi 18:6a4db94011d3 209 def_irq_default_handler WDT_IRQHandler
sahilmgandhi 18:6a4db94011d3 210 def_irq_default_handler BOD_IRQHandler
sahilmgandhi 18:6a4db94011d3 211 def_irq_default_handler Flash_IRQHandler
sahilmgandhi 18:6a4db94011d3 212 def_irq_default_handler WKT_IRQHandler
sahilmgandhi 18:6a4db94011d3 213 def_irq_default_handler ADC_SEQA_IRQHandler
sahilmgandhi 18:6a4db94011d3 214 def_irq_default_handler ADC_SEQB_IRQHandler
sahilmgandhi 18:6a4db94011d3 215 def_irq_default_handler ADC_THCMP_IRQHandler
sahilmgandhi 18:6a4db94011d3 216 def_irq_default_handler ADC_OVR_IRQHandler
sahilmgandhi 18:6a4db94011d3 217 def_irq_default_handler DMA_IRQHandler
sahilmgandhi 18:6a4db94011d3 218 def_irq_default_handler PININT0_IRQHandler
sahilmgandhi 18:6a4db94011d3 219 def_irq_default_handler PININT1_IRQHandler
sahilmgandhi 18:6a4db94011d3 220 def_irq_default_handler PININT2_IRQHandler
sahilmgandhi 18:6a4db94011d3 221 def_irq_default_handler PININT3_IRQHandler
sahilmgandhi 18:6a4db94011d3 222 def_irq_default_handler PININT4_IRQHandler
sahilmgandhi 18:6a4db94011d3 223 def_irq_default_handler PININT5_IRQHandler
sahilmgandhi 18:6a4db94011d3 224 def_irq_default_handler PININT6_IRQHandler
sahilmgandhi 18:6a4db94011d3 225 def_irq_default_handler PININT7_IRQHandler
sahilmgandhi 18:6a4db94011d3 226
sahilmgandhi 18:6a4db94011d3 227 .end
sahilmgandhi 18:6a4db94011d3 228