MouseCode - Mouse code for the MacroRat

MacroRat » Code » MouseCode

Mouse code for the MacroRat

Dependencies: ITG3200 QEI

mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/usart/usart.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:: sahilmgandhi
Date:: Sat Jun 03 00:22:44 2017 +0000
Revision:: 46:b156ef445742
Parent:: 18:6a4db94011d3

Final code for internal battlebot competition.

Who changed what in which revision?

User	Revision	Line number	New contents of line
sahilmgandhi	18:6a4db94011d3	1	/**
sahilmgandhi	18:6a4db94011d3	2	* \file
sahilmgandhi	18:6a4db94011d3	3	*
sahilmgandhi	18:6a4db94011d3	4	* \brief Universal Synchronous Asynchronous Receiver Transmitter (USART) driver
sahilmgandhi	18:6a4db94011d3	5	* for SAM.
sahilmgandhi	18:6a4db94011d3	6	*
sahilmgandhi	18:6a4db94011d3	7	* Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
sahilmgandhi	18:6a4db94011d3	8	*
sahilmgandhi	18:6a4db94011d3	9	* \asf_license_start
sahilmgandhi	18:6a4db94011d3	10	*
sahilmgandhi	18:6a4db94011d3	11	* \page License
sahilmgandhi	18:6a4db94011d3	12	*
sahilmgandhi	18:6a4db94011d3	13	* Redistribution and use in source and binary forms, with or without
sahilmgandhi	18:6a4db94011d3	14	* modification, are permitted provided that the following conditions are met:
sahilmgandhi	18:6a4db94011d3	15	*
sahilmgandhi	18:6a4db94011d3	16	* 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi	18:6a4db94011d3	17	* this list of conditions and the following disclaimer.
sahilmgandhi	18:6a4db94011d3	18	*
sahilmgandhi	18:6a4db94011d3	19	* 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi	18:6a4db94011d3	20	* this list of conditions and the following disclaimer in the documentation
sahilmgandhi	18:6a4db94011d3	21	* and/or other materials provided with the distribution.
sahilmgandhi	18:6a4db94011d3	22	*
sahilmgandhi	18:6a4db94011d3	23	* 3. The name of Atmel may not be used to endorse or promote products derived
sahilmgandhi	18:6a4db94011d3	24	* from this software without specific prior written permission.
sahilmgandhi	18:6a4db94011d3	25	*
sahilmgandhi	18:6a4db94011d3	26	* 4. This software may only be redistributed and used in connection with an
sahilmgandhi	18:6a4db94011d3	27	* Atmel microcontroller product.
sahilmgandhi	18:6a4db94011d3	28	*
sahilmgandhi	18:6a4db94011d3	29	* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
sahilmgandhi	18:6a4db94011d3	30	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
sahilmgandhi	18:6a4db94011d3	31	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
sahilmgandhi	18:6a4db94011d3	32	* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
sahilmgandhi	18:6a4db94011d3	33	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi	18:6a4db94011d3	34	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
sahilmgandhi	18:6a4db94011d3	35	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
sahilmgandhi	18:6a4db94011d3	36	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
sahilmgandhi	18:6a4db94011d3	37	* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
sahilmgandhi	18:6a4db94011d3	38	* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi	18:6a4db94011d3	39	* POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi	18:6a4db94011d3	40	*
sahilmgandhi	18:6a4db94011d3	41	* \asf_license_stop
sahilmgandhi	18:6a4db94011d3	42	*
sahilmgandhi	18:6a4db94011d3	43	*/
sahilmgandhi	18:6a4db94011d3	44	/*
sahilmgandhi	18:6a4db94011d3	45	* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
sahilmgandhi	18:6a4db94011d3	46	*/
sahilmgandhi	18:6a4db94011d3	47
sahilmgandhi	18:6a4db94011d3	48	#include "usart.h"
sahilmgandhi	18:6a4db94011d3	49
sahilmgandhi	18:6a4db94011d3	50	/// @cond 0
sahilmgandhi	18:6a4db94011d3	51	/INDENT-OFF/
sahilmgandhi	18:6a4db94011d3	52	#ifdef __cplusplus
sahilmgandhi	18:6a4db94011d3	53	extern "C" {
sahilmgandhi	18:6a4db94011d3	54	#endif
sahilmgandhi	18:6a4db94011d3	55	/INDENT-ON/
sahilmgandhi	18:6a4db94011d3	56	/// @endcond
sahilmgandhi	18:6a4db94011d3	57
sahilmgandhi	18:6a4db94011d3	58	/**
sahilmgandhi	18:6a4db94011d3	59	* \defgroup sam_drivers_usart_group Universal Synchronous Asynchronous
sahilmgandhi	18:6a4db94011d3	60	* Receiver Transmitter (USART)
sahilmgandhi	18:6a4db94011d3	61	*
sahilmgandhi	18:6a4db94011d3	62	* The Universal Synchronous Asynchronous Receiver Transceiver (USART)
sahilmgandhi	18:6a4db94011d3	63	* provides one full duplex universal synchronous asynchronous serial link.
sahilmgandhi	18:6a4db94011d3	64	* Data frame format is widely programmable (data length, parity, number of
sahilmgandhi	18:6a4db94011d3	65	* stop bits) to support a maximum of standards. The receiver implements
sahilmgandhi	18:6a4db94011d3	66	* parity error, framing error and overrun error detection. The receiver
sahilmgandhi	18:6a4db94011d3	67	* time-out enables handling variable-length frames and the transmitter
sahilmgandhi	18:6a4db94011d3	68	* timeguard facilitates communications with slow remote devices. Multidrop
sahilmgandhi	18:6a4db94011d3	69	* communications are also supported through address bit handling in reception
sahilmgandhi	18:6a4db94011d3	70	* and transmission. The driver supports the following modes:
sahilmgandhi	18:6a4db94011d3	71	* RS232, RS485, SPI, IrDA, ISO7816, MODEM, Hardware handshaking and LIN.
sahilmgandhi	18:6a4db94011d3	72	*
sahilmgandhi	18:6a4db94011d3	73	* @{
sahilmgandhi	18:6a4db94011d3	74	*/
sahilmgandhi	18:6a4db94011d3	75
sahilmgandhi	18:6a4db94011d3	76	/* The write protect key value. */
sahilmgandhi	18:6a4db94011d3	77	#ifndef US_WPMR_WPKEY_PASSWD
sahilmgandhi	18:6a4db94011d3	78	#define US_WPMR_WPKEY_PASSWD US_WPMR_WPKEY(0x555341U)
sahilmgandhi	18:6a4db94011d3	79	#endif
sahilmgandhi	18:6a4db94011d3	80
sahilmgandhi	18:6a4db94011d3	81	#ifndef US_WPMR_WPKEY_PASSWD
sahilmgandhi	18:6a4db94011d3	82	# define US_WPMR_WPKEY_PASSWD US_WPMR_WPKEY(US_WPKEY_VALUE)
sahilmgandhi	18:6a4db94011d3	83	#endif
sahilmgandhi	18:6a4db94011d3	84
sahilmgandhi	18:6a4db94011d3	85	/* The CD value scope programmed in MR register. */
sahilmgandhi	18:6a4db94011d3	86	#define MIN_CD_VALUE 0x01
sahilmgandhi	18:6a4db94011d3	87	#define MIN_CD_VALUE_SPI 0x04
sahilmgandhi	18:6a4db94011d3	88	#define MAX_CD_VALUE US_BRGR_CD_Msk
sahilmgandhi	18:6a4db94011d3	89
sahilmgandhi	18:6a4db94011d3	90	/* The receiver sampling divide of baudrate clock. */
sahilmgandhi	18:6a4db94011d3	91	#define HIGH_FRQ_SAMPLE_DIV 16
sahilmgandhi	18:6a4db94011d3	92	#define LOW_FRQ_SAMPLE_DIV 8
sahilmgandhi	18:6a4db94011d3	93
sahilmgandhi	18:6a4db94011d3	94	/* Max transmitter timeguard. */
sahilmgandhi	18:6a4db94011d3	95	#define MAX_TRAN_GUARD_TIME US_TTGR_TG_Msk
sahilmgandhi	18:6a4db94011d3	96
sahilmgandhi	18:6a4db94011d3	97	/* The non-existent parity error number. */
sahilmgandhi	18:6a4db94011d3	98	#define USART_PARITY_ERROR 5
sahilmgandhi	18:6a4db94011d3	99
sahilmgandhi	18:6a4db94011d3	100	/* ISO7816 protocol type. */
sahilmgandhi	18:6a4db94011d3	101	#define ISO7816_T_0 0
sahilmgandhi	18:6a4db94011d3	102	#define ISO7816_T_1 1
sahilmgandhi	18:6a4db94011d3	103
sahilmgandhi	18:6a4db94011d3	104	/**
sahilmgandhi	18:6a4db94011d3	105	* \brief Calculate a clock divider(CD) and a fractional part (FP) for the
sahilmgandhi	18:6a4db94011d3	106	* USART asynchronous modes to generate a baudrate as close as possible to
sahilmgandhi	18:6a4db94011d3	107	* the baudrate set point.
sahilmgandhi	18:6a4db94011d3	108	*
sahilmgandhi	18:6a4db94011d3	109	* \note Baud rate calculation: Baudrate = ul_mck/(Over * (CD + FP/8))
sahilmgandhi	18:6a4db94011d3	110	* (Over being 16 or 8). The maximal oversampling is selected if it allows to
sahilmgandhi	18:6a4db94011d3	111	* generate a baudrate close to the set point.
sahilmgandhi	18:6a4db94011d3	112	*
sahilmgandhi	18:6a4db94011d3	113	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	114	* \param baudrate Baud rate set point.
sahilmgandhi	18:6a4db94011d3	115	* \param ul_mck USART module input clock frequency.
sahilmgandhi	18:6a4db94011d3	116	*
sahilmgandhi	18:6a4db94011d3	117	* \retval 0 Baud rate is successfully initialized.
sahilmgandhi	18:6a4db94011d3	118	* \retval 1 Baud rate set point is out of range for the given input clock
sahilmgandhi	18:6a4db94011d3	119	* frequency.
sahilmgandhi	18:6a4db94011d3	120	*/
sahilmgandhi	18:6a4db94011d3	121	uint32_t usart_set_async_baudrate(Usart *p_usart,
sahilmgandhi	18:6a4db94011d3	122	uint32_t baudrate, uint32_t ul_mck)
sahilmgandhi	18:6a4db94011d3	123	{
sahilmgandhi	18:6a4db94011d3	124	uint32_t over;
sahilmgandhi	18:6a4db94011d3	125	uint32_t cd_fp;
sahilmgandhi	18:6a4db94011d3	126	uint32_t cd;
sahilmgandhi	18:6a4db94011d3	127	uint32_t fp;
sahilmgandhi	18:6a4db94011d3	128
sahilmgandhi	18:6a4db94011d3	129	/* Calculate the receiver sampling divide of baudrate clock. */
sahilmgandhi	18:6a4db94011d3	130	if (ul_mck >= HIGH_FRQ_SAMPLE_DIV * baudrate) {
sahilmgandhi	18:6a4db94011d3	131	over = HIGH_FRQ_SAMPLE_DIV;
sahilmgandhi	18:6a4db94011d3	132	} else {
sahilmgandhi	18:6a4db94011d3	133	over = LOW_FRQ_SAMPLE_DIV;
sahilmgandhi	18:6a4db94011d3	134	}
sahilmgandhi	18:6a4db94011d3	135
sahilmgandhi	18:6a4db94011d3	136	/* Calculate clock divider according to the fraction calculated formula. */
sahilmgandhi	18:6a4db94011d3	137	cd_fp = (8 * ul_mck + (over * baudrate) / 2) / (over * baudrate);
sahilmgandhi	18:6a4db94011d3	138	cd = cd_fp >> 3;
sahilmgandhi	18:6a4db94011d3	139	fp = cd_fp & 0x07;
sahilmgandhi	18:6a4db94011d3	140	if (cd < MIN_CD_VALUE \|\| cd > MAX_CD_VALUE) {
sahilmgandhi	18:6a4db94011d3	141	return 1;
sahilmgandhi	18:6a4db94011d3	142	}
sahilmgandhi	18:6a4db94011d3	143
sahilmgandhi	18:6a4db94011d3	144	/* Configure the OVER bit in MR register. */
sahilmgandhi	18:6a4db94011d3	145	if (over == 8) {
sahilmgandhi	18:6a4db94011d3	146	p_usart->US_MR \|= US_MR_OVER;
sahilmgandhi	18:6a4db94011d3	147	}
sahilmgandhi	18:6a4db94011d3	148
sahilmgandhi	18:6a4db94011d3	149	/* Configure the baudrate generate register. */
sahilmgandhi	18:6a4db94011d3	150	p_usart->US_BRGR = (cd << US_BRGR_CD_Pos) \| (fp << US_BRGR_FP_Pos);
sahilmgandhi	18:6a4db94011d3	151
sahilmgandhi	18:6a4db94011d3	152	return 0;
sahilmgandhi	18:6a4db94011d3	153	}
sahilmgandhi	18:6a4db94011d3	154
sahilmgandhi	18:6a4db94011d3	155	/**
sahilmgandhi	18:6a4db94011d3	156	* \brief Calculate a clock divider for the USART synchronous master modes
sahilmgandhi	18:6a4db94011d3	157	* to generate a baudrate as close as possible to the baudrate set point.
sahilmgandhi	18:6a4db94011d3	158	*
sahilmgandhi	18:6a4db94011d3	159	* \note Synchronous baudrate calculation: baudrate = ul_mck / cd
sahilmgandhi	18:6a4db94011d3	160	*
sahilmgandhi	18:6a4db94011d3	161	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	162	* \param baudrate Baud rate set point.
sahilmgandhi	18:6a4db94011d3	163	* \param ul_mck USART module input clock frequency.
sahilmgandhi	18:6a4db94011d3	164	*
sahilmgandhi	18:6a4db94011d3	165	* \retval 0 Baud rate is successfully initialized.
sahilmgandhi	18:6a4db94011d3	166	* \retval 1 Baud rate set point is out of range for the given input clock
sahilmgandhi	18:6a4db94011d3	167	* frequency.
sahilmgandhi	18:6a4db94011d3	168	*/
sahilmgandhi	18:6a4db94011d3	169	static uint32_t usart_set_sync_master_baudrate(Usart *p_usart,
sahilmgandhi	18:6a4db94011d3	170	uint32_t baudrate, uint32_t ul_mck)
sahilmgandhi	18:6a4db94011d3	171	{
sahilmgandhi	18:6a4db94011d3	172	uint32_t cd;
sahilmgandhi	18:6a4db94011d3	173
sahilmgandhi	18:6a4db94011d3	174	/* Calculate clock divider according to the formula in synchronous mode. */
sahilmgandhi	18:6a4db94011d3	175	cd = (ul_mck + baudrate / 2) / baudrate;
sahilmgandhi	18:6a4db94011d3	176
sahilmgandhi	18:6a4db94011d3	177	if (cd < MIN_CD_VALUE \|\| cd > MAX_CD_VALUE) {
sahilmgandhi	18:6a4db94011d3	178	return 1;
sahilmgandhi	18:6a4db94011d3	179	}
sahilmgandhi	18:6a4db94011d3	180
sahilmgandhi	18:6a4db94011d3	181	/* Configure the baudrate generate register. */
sahilmgandhi	18:6a4db94011d3	182	p_usart->US_BRGR = cd << US_BRGR_CD_Pos;
sahilmgandhi	18:6a4db94011d3	183
sahilmgandhi	18:6a4db94011d3	184	p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) \|
sahilmgandhi	18:6a4db94011d3	185	US_MR_USCLKS_MCK \| US_MR_SYNC;
sahilmgandhi	18:6a4db94011d3	186	return 0;
sahilmgandhi	18:6a4db94011d3	187	}
sahilmgandhi	18:6a4db94011d3	188
sahilmgandhi	18:6a4db94011d3	189	/**
sahilmgandhi	18:6a4db94011d3	190	* \brief Select the SCK pin as the source of baud rate for the USART
sahilmgandhi	18:6a4db94011d3	191	* synchronous slave modes.
sahilmgandhi	18:6a4db94011d3	192	*
sahilmgandhi	18:6a4db94011d3	193	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	194	*/
sahilmgandhi	18:6a4db94011d3	195	static void usart_set_sync_slave_baudrate(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	196	{
sahilmgandhi	18:6a4db94011d3	197	p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) \|
sahilmgandhi	18:6a4db94011d3	198	US_MR_USCLKS_SCK \| US_MR_SYNC;
sahilmgandhi	18:6a4db94011d3	199	}
sahilmgandhi	18:6a4db94011d3	200
sahilmgandhi	18:6a4db94011d3	201	/**
sahilmgandhi	18:6a4db94011d3	202	* \brief Calculate a clock divider (\e CD) for the USART SPI master mode to
sahilmgandhi	18:6a4db94011d3	203	* generate a baud rate as close as possible to the baud rate set point.
sahilmgandhi	18:6a4db94011d3	204	*
sahilmgandhi	18:6a4db94011d3	205	* \note Baud rate calculation:
sahilmgandhi	18:6a4db94011d3	206	* \f$ Baudrate = \frac{SelectedClock}{CD} \f$.
sahilmgandhi	18:6a4db94011d3	207	*
sahilmgandhi	18:6a4db94011d3	208	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	209	* \param baudrate Baud rate set point.
sahilmgandhi	18:6a4db94011d3	210	* \param ul_mck USART module input clock frequency.
sahilmgandhi	18:6a4db94011d3	211	*
sahilmgandhi	18:6a4db94011d3	212	* \retval 0 Baud rate is successfully initialized.
sahilmgandhi	18:6a4db94011d3	213	* \retval 1 Baud rate set point is out of range for the given input clock
sahilmgandhi	18:6a4db94011d3	214	* frequency.
sahilmgandhi	18:6a4db94011d3	215	*/
sahilmgandhi	18:6a4db94011d3	216	static uint32_t usart_set_spi_master_baudrate(Usart *p_usart,
sahilmgandhi	18:6a4db94011d3	217	uint32_t baudrate, uint32_t ul_mck)
sahilmgandhi	18:6a4db94011d3	218	{
sahilmgandhi	18:6a4db94011d3	219	uint32_t cd;
sahilmgandhi	18:6a4db94011d3	220
sahilmgandhi	18:6a4db94011d3	221	/* Calculate the clock divider according to the formula in SPI mode. */
sahilmgandhi	18:6a4db94011d3	222	cd = (ul_mck + baudrate / 2) / baudrate;
sahilmgandhi	18:6a4db94011d3	223
sahilmgandhi	18:6a4db94011d3	224	if (cd < MIN_CD_VALUE_SPI \|\| cd > MAX_CD_VALUE) {
sahilmgandhi	18:6a4db94011d3	225	return 1;
sahilmgandhi	18:6a4db94011d3	226	}
sahilmgandhi	18:6a4db94011d3	227
sahilmgandhi	18:6a4db94011d3	228	p_usart->US_BRGR = cd << US_BRGR_CD_Pos;
sahilmgandhi	18:6a4db94011d3	229
sahilmgandhi	18:6a4db94011d3	230	return 0;
sahilmgandhi	18:6a4db94011d3	231	}
sahilmgandhi	18:6a4db94011d3	232
sahilmgandhi	18:6a4db94011d3	233	/**
sahilmgandhi	18:6a4db94011d3	234	* \brief Select the SCK pin as the source of baudrate for the USART SPI slave
sahilmgandhi	18:6a4db94011d3	235	* mode.
sahilmgandhi	18:6a4db94011d3	236	*
sahilmgandhi	18:6a4db94011d3	237	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	238	*/
sahilmgandhi	18:6a4db94011d3	239	static void usart_set_spi_slave_baudrate(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	240	{
sahilmgandhi	18:6a4db94011d3	241	p_usart->US_MR &= ~US_MR_USCLKS_Msk;
sahilmgandhi	18:6a4db94011d3	242	p_usart->US_MR \|= US_MR_USCLKS_SCK;
sahilmgandhi	18:6a4db94011d3	243	}
sahilmgandhi	18:6a4db94011d3	244
sahilmgandhi	18:6a4db94011d3	245	/**
sahilmgandhi	18:6a4db94011d3	246	* \brief Reset the USART and disable TX and RX.
sahilmgandhi	18:6a4db94011d3	247	*
sahilmgandhi	18:6a4db94011d3	248	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	249	*/
sahilmgandhi	18:6a4db94011d3	250	void usart_reset(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	251	{
sahilmgandhi	18:6a4db94011d3	252	/* Disable the Write Protect. */
sahilmgandhi	18:6a4db94011d3	253	usart_disable_writeprotect(p_usart);
sahilmgandhi	18:6a4db94011d3	254
sahilmgandhi	18:6a4db94011d3	255	/* Reset registers that could cause unpredictable behavior after reset. */
sahilmgandhi	18:6a4db94011d3	256	p_usart->US_MR = 0;
sahilmgandhi	18:6a4db94011d3	257	p_usart->US_RTOR = 0;
sahilmgandhi	18:6a4db94011d3	258	p_usart->US_TTGR = 0;
sahilmgandhi	18:6a4db94011d3	259
sahilmgandhi	18:6a4db94011d3	260	/* Disable TX and RX. */
sahilmgandhi	18:6a4db94011d3	261	usart_reset_tx(p_usart);
sahilmgandhi	18:6a4db94011d3	262	usart_reset_rx(p_usart);
sahilmgandhi	18:6a4db94011d3	263	/* Reset status bits. */
sahilmgandhi	18:6a4db94011d3	264	usart_reset_status(p_usart);
sahilmgandhi	18:6a4db94011d3	265	/* Turn off RTS and DTR if exist. */
sahilmgandhi	18:6a4db94011d3	266	usart_drive_RTS_pin_high(p_usart);
sahilmgandhi	18:6a4db94011d3	267	#if (SAM3S \|\| SAM4S \|\| SAM3U \|\| SAM4L \|\| SAM4E)
sahilmgandhi	18:6a4db94011d3	268	usart_drive_DTR_pin_high(p_usart);
sahilmgandhi	18:6a4db94011d3	269	#endif
sahilmgandhi	18:6a4db94011d3	270	}
sahilmgandhi	18:6a4db94011d3	271
sahilmgandhi	18:6a4db94011d3	272	/**
sahilmgandhi	18:6a4db94011d3	273	* \brief Configure USART to work in RS232 mode.
sahilmgandhi	18:6a4db94011d3	274	*
sahilmgandhi	18:6a4db94011d3	275	* \note By default, the transmitter and receiver aren't enabled.
sahilmgandhi	18:6a4db94011d3	276	*
sahilmgandhi	18:6a4db94011d3	277	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	278	* \param p_usart_opt Pointer to sam_usart_opt_t instance.
sahilmgandhi	18:6a4db94011d3	279	* \param ul_mck USART module input clock frequency.
sahilmgandhi	18:6a4db94011d3	280	*
sahilmgandhi	18:6a4db94011d3	281	* \retval 0 on success.
sahilmgandhi	18:6a4db94011d3	282	* \retval 1 on failure.
sahilmgandhi	18:6a4db94011d3	283	*/
sahilmgandhi	18:6a4db94011d3	284	uint32_t usart_init_rs232(Usart *p_usart,
sahilmgandhi	18:6a4db94011d3	285	const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
sahilmgandhi	18:6a4db94011d3	286	{
sahilmgandhi	18:6a4db94011d3	287	static uint32_t ul_reg_val;
sahilmgandhi	18:6a4db94011d3	288
sahilmgandhi	18:6a4db94011d3	289	/* Reset the USART and shut down TX and RX. */
sahilmgandhi	18:6a4db94011d3	290	usart_reset(p_usart);
sahilmgandhi	18:6a4db94011d3	291
sahilmgandhi	18:6a4db94011d3	292	ul_reg_val = 0;
sahilmgandhi	18:6a4db94011d3	293	/* Check whether the input values are legal. */
sahilmgandhi	18:6a4db94011d3	294	if (!p_usart_opt \|\| usart_set_async_baudrate(p_usart,
sahilmgandhi	18:6a4db94011d3	295	p_usart_opt->baudrate, ul_mck)) {
sahilmgandhi	18:6a4db94011d3	296	return 1;
sahilmgandhi	18:6a4db94011d3	297	}
sahilmgandhi	18:6a4db94011d3	298
sahilmgandhi	18:6a4db94011d3	299	/* Configure the USART option. */
sahilmgandhi	18:6a4db94011d3	300	ul_reg_val \|= p_usart_opt->char_length \| p_usart_opt->parity_type \|
sahilmgandhi	18:6a4db94011d3	301	p_usart_opt->channel_mode \| p_usart_opt->stop_bits;
sahilmgandhi	18:6a4db94011d3	302
sahilmgandhi	18:6a4db94011d3	303	/* Configure the USART mode as normal mode. */
sahilmgandhi	18:6a4db94011d3	304	ul_reg_val \|= US_MR_USART_MODE_NORMAL;
sahilmgandhi	18:6a4db94011d3	305
sahilmgandhi	18:6a4db94011d3	306	p_usart->US_MR \|= ul_reg_val;
sahilmgandhi	18:6a4db94011d3	307
sahilmgandhi	18:6a4db94011d3	308	return 0;
sahilmgandhi	18:6a4db94011d3	309	}
sahilmgandhi	18:6a4db94011d3	310
sahilmgandhi	18:6a4db94011d3	311	/**
sahilmgandhi	18:6a4db94011d3	312	* \brief Configure USART to work in hardware handshaking mode.
sahilmgandhi	18:6a4db94011d3	313	*
sahilmgandhi	18:6a4db94011d3	314	* \note By default, the transmitter and receiver aren't enabled.
sahilmgandhi	18:6a4db94011d3	315	*
sahilmgandhi	18:6a4db94011d3	316	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	317	* \param p_usart_opt Pointer to sam_usart_opt_t instance.
sahilmgandhi	18:6a4db94011d3	318	* \param ul_mck USART module input clock frequency.
sahilmgandhi	18:6a4db94011d3	319	*
sahilmgandhi	18:6a4db94011d3	320	* \retval 0 on success.
sahilmgandhi	18:6a4db94011d3	321	* \retval 1 on failure.
sahilmgandhi	18:6a4db94011d3	322	*/
sahilmgandhi	18:6a4db94011d3	323	uint32_t usart_init_hw_handshaking(Usart *p_usart,
sahilmgandhi	18:6a4db94011d3	324	const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
sahilmgandhi	18:6a4db94011d3	325	{
sahilmgandhi	18:6a4db94011d3	326	/* Initialize the USART as standard RS232. */
sahilmgandhi	18:6a4db94011d3	327	if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {
sahilmgandhi	18:6a4db94011d3	328	return 1;
sahilmgandhi	18:6a4db94011d3	329	}
sahilmgandhi	18:6a4db94011d3	330
sahilmgandhi	18:6a4db94011d3	331	/* Set hardware handshaking mode. */
sahilmgandhi	18:6a4db94011d3	332	p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) \|
sahilmgandhi	18:6a4db94011d3	333	US_MR_USART_MODE_HW_HANDSHAKING;
sahilmgandhi	18:6a4db94011d3	334
sahilmgandhi	18:6a4db94011d3	335	return 0;
sahilmgandhi	18:6a4db94011d3	336	}
sahilmgandhi	18:6a4db94011d3	337
sahilmgandhi	18:6a4db94011d3	338	#if (SAM3S \|\| SAM4S \|\| SAM3U \|\| SAM4L \|\| SAM4E)
sahilmgandhi	18:6a4db94011d3	339
sahilmgandhi	18:6a4db94011d3	340	/**
sahilmgandhi	18:6a4db94011d3	341	* \brief Configure USART to work in modem mode.
sahilmgandhi	18:6a4db94011d3	342	*
sahilmgandhi	18:6a4db94011d3	343	* \note By default, the transmitter and receiver aren't enabled.
sahilmgandhi	18:6a4db94011d3	344	*
sahilmgandhi	18:6a4db94011d3	345	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	346	* \param p_usart_opt Pointer to sam_usart_opt_t instance.
sahilmgandhi	18:6a4db94011d3	347	* \param ul_mck USART module input clock frequency.
sahilmgandhi	18:6a4db94011d3	348	*
sahilmgandhi	18:6a4db94011d3	349	* \retval 0 on success.
sahilmgandhi	18:6a4db94011d3	350	* \retval 1 on failure.
sahilmgandhi	18:6a4db94011d3	351	*/
sahilmgandhi	18:6a4db94011d3	352	uint32_t usart_init_modem(Usart *p_usart,
sahilmgandhi	18:6a4db94011d3	353	const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
sahilmgandhi	18:6a4db94011d3	354	{
sahilmgandhi	18:6a4db94011d3	355	/*
sahilmgandhi	18:6a4db94011d3	356	* SAM3S, SAM4S and SAM4E series support MODEM mode only on USART1,
sahilmgandhi	18:6a4db94011d3	357	* SAM3U and SAM4L series support MODEM mode only on USART0.
sahilmgandhi	18:6a4db94011d3	358	*/
sahilmgandhi	18:6a4db94011d3	359	#if (SAM3S \|\| SAM4S \|\| SAM4E)
sahilmgandhi	18:6a4db94011d3	360	#ifdef USART1
sahilmgandhi	18:6a4db94011d3	361	if (p_usart != USART1) {
sahilmgandhi	18:6a4db94011d3	362	return 1;
sahilmgandhi	18:6a4db94011d3	363	}
sahilmgandhi	18:6a4db94011d3	364	#endif
sahilmgandhi	18:6a4db94011d3	365	#elif (SAM3U \|\| SAM4L)
sahilmgandhi	18:6a4db94011d3	366	if (p_usart != USART0) {
sahilmgandhi	18:6a4db94011d3	367	return 1;
sahilmgandhi	18:6a4db94011d3	368	}
sahilmgandhi	18:6a4db94011d3	369	#endif
sahilmgandhi	18:6a4db94011d3	370
sahilmgandhi	18:6a4db94011d3	371	/* Initialize the USART as standard RS232. */
sahilmgandhi	18:6a4db94011d3	372	if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {
sahilmgandhi	18:6a4db94011d3	373	return 1;
sahilmgandhi	18:6a4db94011d3	374	}
sahilmgandhi	18:6a4db94011d3	375
sahilmgandhi	18:6a4db94011d3	376	/* Set MODEM mode. */
sahilmgandhi	18:6a4db94011d3	377	p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) \|
sahilmgandhi	18:6a4db94011d3	378	US_MR_USART_MODE_MODEM;
sahilmgandhi	18:6a4db94011d3	379
sahilmgandhi	18:6a4db94011d3	380	return 0;
sahilmgandhi	18:6a4db94011d3	381	}
sahilmgandhi	18:6a4db94011d3	382	#endif
sahilmgandhi	18:6a4db94011d3	383
sahilmgandhi	18:6a4db94011d3	384	/**
sahilmgandhi	18:6a4db94011d3	385	* \brief Configure USART to work in SYNC mode and act as a master.
sahilmgandhi	18:6a4db94011d3	386	*
sahilmgandhi	18:6a4db94011d3	387	* \note By default, the transmitter and receiver aren't enabled.
sahilmgandhi	18:6a4db94011d3	388	*
sahilmgandhi	18:6a4db94011d3	389	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	390	* \param p_usart_opt Pointer to sam_usart_opt_t instance.
sahilmgandhi	18:6a4db94011d3	391	* \param ul_mck USART module input clock frequency.
sahilmgandhi	18:6a4db94011d3	392	*
sahilmgandhi	18:6a4db94011d3	393	* \retval 0 on success.
sahilmgandhi	18:6a4db94011d3	394	* \retval 1 on failure.
sahilmgandhi	18:6a4db94011d3	395	*/
sahilmgandhi	18:6a4db94011d3	396	uint32_t usart_init_sync_master(Usart *p_usart,
sahilmgandhi	18:6a4db94011d3	397	const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
sahilmgandhi	18:6a4db94011d3	398	{
sahilmgandhi	18:6a4db94011d3	399	static uint32_t ul_reg_val;
sahilmgandhi	18:6a4db94011d3	400
sahilmgandhi	18:6a4db94011d3	401	/* Reset the USART and shut down TX and RX. */
sahilmgandhi	18:6a4db94011d3	402	usart_reset(p_usart);
sahilmgandhi	18:6a4db94011d3	403
sahilmgandhi	18:6a4db94011d3	404	ul_reg_val = 0;
sahilmgandhi	18:6a4db94011d3	405	/* Check whether the input values are legal. */
sahilmgandhi	18:6a4db94011d3	406	if (!p_usart_opt \|\| usart_set_sync_master_baudrate(p_usart,
sahilmgandhi	18:6a4db94011d3	407	p_usart_opt->baudrate, ul_mck)) {
sahilmgandhi	18:6a4db94011d3	408	return 1;
sahilmgandhi	18:6a4db94011d3	409	}
sahilmgandhi	18:6a4db94011d3	410
sahilmgandhi	18:6a4db94011d3	411	/* Configure the USART option. */
sahilmgandhi	18:6a4db94011d3	412	ul_reg_val \|= p_usart_opt->char_length \| p_usart_opt->parity_type \|
sahilmgandhi	18:6a4db94011d3	413	p_usart_opt->channel_mode \| p_usart_opt->stop_bits;
sahilmgandhi	18:6a4db94011d3	414
sahilmgandhi	18:6a4db94011d3	415	/* Set normal mode and output clock as synchronous master. */
sahilmgandhi	18:6a4db94011d3	416	ul_reg_val \|= US_MR_USART_MODE_NORMAL \| US_MR_CLKO;
sahilmgandhi	18:6a4db94011d3	417	p_usart->US_MR \|= ul_reg_val;
sahilmgandhi	18:6a4db94011d3	418
sahilmgandhi	18:6a4db94011d3	419	return 0;
sahilmgandhi	18:6a4db94011d3	420	}
sahilmgandhi	18:6a4db94011d3	421
sahilmgandhi	18:6a4db94011d3	422	/**
sahilmgandhi	18:6a4db94011d3	423	* \brief Configure USART to work in SYNC mode and act as a slave.
sahilmgandhi	18:6a4db94011d3	424	*
sahilmgandhi	18:6a4db94011d3	425	* \note By default, the transmitter and receiver aren't enabled.
sahilmgandhi	18:6a4db94011d3	426	*
sahilmgandhi	18:6a4db94011d3	427	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	428	* \param p_usart_opt Pointer to sam_usart_opt_t instance.
sahilmgandhi	18:6a4db94011d3	429	*
sahilmgandhi	18:6a4db94011d3	430	* \retval 0 on success.
sahilmgandhi	18:6a4db94011d3	431	* \retval 1 on failure.
sahilmgandhi	18:6a4db94011d3	432	*/
sahilmgandhi	18:6a4db94011d3	433	uint32_t usart_init_sync_slave(Usart *p_usart,
sahilmgandhi	18:6a4db94011d3	434	const sam_usart_opt_t *p_usart_opt)
sahilmgandhi	18:6a4db94011d3	435	{
sahilmgandhi	18:6a4db94011d3	436	static uint32_t ul_reg_val;
sahilmgandhi	18:6a4db94011d3	437
sahilmgandhi	18:6a4db94011d3	438	/* Reset the USART and shut down TX and RX. */
sahilmgandhi	18:6a4db94011d3	439	usart_reset(p_usart);
sahilmgandhi	18:6a4db94011d3	440
sahilmgandhi	18:6a4db94011d3	441	ul_reg_val = 0;
sahilmgandhi	18:6a4db94011d3	442	usart_set_sync_slave_baudrate(p_usart);
sahilmgandhi	18:6a4db94011d3	443
sahilmgandhi	18:6a4db94011d3	444	/* Check whether the input values are legal. */
sahilmgandhi	18:6a4db94011d3	445	if (!p_usart_opt) {
sahilmgandhi	18:6a4db94011d3	446	return 1;
sahilmgandhi	18:6a4db94011d3	447	}
sahilmgandhi	18:6a4db94011d3	448
sahilmgandhi	18:6a4db94011d3	449	/* Configure the USART option. */
sahilmgandhi	18:6a4db94011d3	450	ul_reg_val \|= p_usart_opt->char_length \| p_usart_opt->parity_type \|
sahilmgandhi	18:6a4db94011d3	451	p_usart_opt->channel_mode \| p_usart_opt->stop_bits;
sahilmgandhi	18:6a4db94011d3	452
sahilmgandhi	18:6a4db94011d3	453	/* Set normal mode. */
sahilmgandhi	18:6a4db94011d3	454	ul_reg_val \|= US_MR_USART_MODE_NORMAL;
sahilmgandhi	18:6a4db94011d3	455	p_usart->US_MR \|= ul_reg_val;
sahilmgandhi	18:6a4db94011d3	456
sahilmgandhi	18:6a4db94011d3	457	return 0;
sahilmgandhi	18:6a4db94011d3	458	}
sahilmgandhi	18:6a4db94011d3	459
sahilmgandhi	18:6a4db94011d3	460	/**
sahilmgandhi	18:6a4db94011d3	461	* \brief Configure USART to work in RS485 mode.
sahilmgandhi	18:6a4db94011d3	462	*
sahilmgandhi	18:6a4db94011d3	463	* \note By default, the transmitter and receiver aren't enabled.
sahilmgandhi	18:6a4db94011d3	464	*
sahilmgandhi	18:6a4db94011d3	465	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	466	* \param p_usart_opt Pointer to sam_usart_opt_t instance.
sahilmgandhi	18:6a4db94011d3	467	* \param ul_mck USART module input clock frequency.
sahilmgandhi	18:6a4db94011d3	468	*
sahilmgandhi	18:6a4db94011d3	469	* \retval 0 on success.
sahilmgandhi	18:6a4db94011d3	470	* \retval 1 on failure.
sahilmgandhi	18:6a4db94011d3	471	*/
sahilmgandhi	18:6a4db94011d3	472	uint32_t usart_init_rs485(Usart *p_usart,
sahilmgandhi	18:6a4db94011d3	473	const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
sahilmgandhi	18:6a4db94011d3	474	{
sahilmgandhi	18:6a4db94011d3	475	/* Initialize the USART as standard RS232. */
sahilmgandhi	18:6a4db94011d3	476	if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {
sahilmgandhi	18:6a4db94011d3	477	return 1;
sahilmgandhi	18:6a4db94011d3	478	}
sahilmgandhi	18:6a4db94011d3	479
sahilmgandhi	18:6a4db94011d3	480	/* Set RS485 mode. */
sahilmgandhi	18:6a4db94011d3	481	p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) \|
sahilmgandhi	18:6a4db94011d3	482	US_MR_USART_MODE_RS485;
sahilmgandhi	18:6a4db94011d3	483
sahilmgandhi	18:6a4db94011d3	484	return 0;
sahilmgandhi	18:6a4db94011d3	485	}
sahilmgandhi	18:6a4db94011d3	486
sahilmgandhi	18:6a4db94011d3	487	#if (!SAMG55 && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70)
sahilmgandhi	18:6a4db94011d3	488	/**
sahilmgandhi	18:6a4db94011d3	489	* \brief Configure USART to work in IrDA mode.
sahilmgandhi	18:6a4db94011d3	490	*
sahilmgandhi	18:6a4db94011d3	491	* \note By default, the transmitter and receiver aren't enabled.
sahilmgandhi	18:6a4db94011d3	492	*
sahilmgandhi	18:6a4db94011d3	493	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	494	* \param p_usart_opt Pointer to sam_usart_opt_t instance.
sahilmgandhi	18:6a4db94011d3	495	* \param ul_mck USART module input clock frequency.
sahilmgandhi	18:6a4db94011d3	496	*
sahilmgandhi	18:6a4db94011d3	497	* \retval 0 on success.
sahilmgandhi	18:6a4db94011d3	498	* \retval 1 on failure.
sahilmgandhi	18:6a4db94011d3	499	*/
sahilmgandhi	18:6a4db94011d3	500	uint32_t usart_init_irda(Usart *p_usart,
sahilmgandhi	18:6a4db94011d3	501	const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
sahilmgandhi	18:6a4db94011d3	502	{
sahilmgandhi	18:6a4db94011d3	503	/* Initialize the USART as standard RS232. */
sahilmgandhi	18:6a4db94011d3	504	if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {
sahilmgandhi	18:6a4db94011d3	505	return 1;
sahilmgandhi	18:6a4db94011d3	506	}
sahilmgandhi	18:6a4db94011d3	507
sahilmgandhi	18:6a4db94011d3	508	/* Set IrDA filter. */
sahilmgandhi	18:6a4db94011d3	509	p_usart->US_IF = p_usart_opt->irda_filter;
sahilmgandhi	18:6a4db94011d3	510
sahilmgandhi	18:6a4db94011d3	511	/* Set IrDA mode. */
sahilmgandhi	18:6a4db94011d3	512	p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) \|
sahilmgandhi	18:6a4db94011d3	513	US_MR_USART_MODE_IRDA;
sahilmgandhi	18:6a4db94011d3	514
sahilmgandhi	18:6a4db94011d3	515	return 0;
sahilmgandhi	18:6a4db94011d3	516	}
sahilmgandhi	18:6a4db94011d3	517	#endif
sahilmgandhi	18:6a4db94011d3	518
sahilmgandhi	18:6a4db94011d3	519	#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70)
sahilmgandhi	18:6a4db94011d3	520	/**
sahilmgandhi	18:6a4db94011d3	521	* \brief Calculate a clock divider (\e CD) for the USART ISO7816 mode to
sahilmgandhi	18:6a4db94011d3	522	* generate an ISO7816 clock as close as possible to the clock set point.
sahilmgandhi	18:6a4db94011d3	523	*
sahilmgandhi	18:6a4db94011d3	524	* \note ISO7816 clock calculation: Clock = ul_mck / cd
sahilmgandhi	18:6a4db94011d3	525	*
sahilmgandhi	18:6a4db94011d3	526	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	527	* \param clock ISO7816 clock set point.
sahilmgandhi	18:6a4db94011d3	528	* \param ul_mck USART module input clock frequency.
sahilmgandhi	18:6a4db94011d3	529	*
sahilmgandhi	18:6a4db94011d3	530	* \retval 0 ISO7816 clock is successfully initialized.
sahilmgandhi	18:6a4db94011d3	531	* \retval 1 ISO7816 clock set point is out of range for the given input clock
sahilmgandhi	18:6a4db94011d3	532	* frequency.
sahilmgandhi	18:6a4db94011d3	533	*/
sahilmgandhi	18:6a4db94011d3	534	static uint32_t usart_set_iso7816_clock(Usart *p_usart,
sahilmgandhi	18:6a4db94011d3	535	uint32_t clock, uint32_t ul_mck)
sahilmgandhi	18:6a4db94011d3	536	{
sahilmgandhi	18:6a4db94011d3	537	uint32_t cd;
sahilmgandhi	18:6a4db94011d3	538
sahilmgandhi	18:6a4db94011d3	539	/* Calculate clock divider according to the formula in ISO7816 mode. */
sahilmgandhi	18:6a4db94011d3	540	cd = (ul_mck + clock / 2) / clock;
sahilmgandhi	18:6a4db94011d3	541
sahilmgandhi	18:6a4db94011d3	542	if (cd < MIN_CD_VALUE \|\| cd > MAX_CD_VALUE) {
sahilmgandhi	18:6a4db94011d3	543	return 1;
sahilmgandhi	18:6a4db94011d3	544	}
sahilmgandhi	18:6a4db94011d3	545
sahilmgandhi	18:6a4db94011d3	546	p_usart->US_MR = (p_usart->US_MR & ~(US_MR_USCLKS_Msk \| US_MR_SYNC \|
sahilmgandhi	18:6a4db94011d3	547	US_MR_OVER)) \| US_MR_USCLKS_MCK \| US_MR_CLKO;
sahilmgandhi	18:6a4db94011d3	548
sahilmgandhi	18:6a4db94011d3	549	/* Configure the baudrate generate register. */
sahilmgandhi	18:6a4db94011d3	550	p_usart->US_BRGR = cd << US_BRGR_CD_Pos;
sahilmgandhi	18:6a4db94011d3	551
sahilmgandhi	18:6a4db94011d3	552	return 0;
sahilmgandhi	18:6a4db94011d3	553	}
sahilmgandhi	18:6a4db94011d3	554
sahilmgandhi	18:6a4db94011d3	555	/**
sahilmgandhi	18:6a4db94011d3	556	* \brief Configure USART to work in ISO7816 mode.
sahilmgandhi	18:6a4db94011d3	557	*
sahilmgandhi	18:6a4db94011d3	558	* \note By default, the transmitter and receiver aren't enabled.
sahilmgandhi	18:6a4db94011d3	559	*
sahilmgandhi	18:6a4db94011d3	560	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	561	* \param p_usart_opt Pointer to sam_usart_opt_t instance.
sahilmgandhi	18:6a4db94011d3	562	* \param ul_mck USART module input clock frequency.
sahilmgandhi	18:6a4db94011d3	563	*
sahilmgandhi	18:6a4db94011d3	564	* \retval 0 on success.
sahilmgandhi	18:6a4db94011d3	565	* \retval 1 on failure.
sahilmgandhi	18:6a4db94011d3	566	*/
sahilmgandhi	18:6a4db94011d3	567	uint32_t usart_init_iso7816(Usart *p_usart,
sahilmgandhi	18:6a4db94011d3	568	const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck)
sahilmgandhi	18:6a4db94011d3	569	{
sahilmgandhi	18:6a4db94011d3	570	static uint32_t ul_reg_val;
sahilmgandhi	18:6a4db94011d3	571
sahilmgandhi	18:6a4db94011d3	572	/* Reset the USART and shut down TX and RX. */
sahilmgandhi	18:6a4db94011d3	573	usart_reset(p_usart);
sahilmgandhi	18:6a4db94011d3	574
sahilmgandhi	18:6a4db94011d3	575	ul_reg_val = 0;
sahilmgandhi	18:6a4db94011d3	576
sahilmgandhi	18:6a4db94011d3	577	/* Check whether the input values are legal. */
sahilmgandhi	18:6a4db94011d3	578	if (!p_usart_opt \|\| ((p_usart_opt->parity_type != US_MR_PAR_EVEN) &&
sahilmgandhi	18:6a4db94011d3	579	(p_usart_opt->parity_type != US_MR_PAR_ODD))) {
sahilmgandhi	18:6a4db94011d3	580	return 1;
sahilmgandhi	18:6a4db94011d3	581	}
sahilmgandhi	18:6a4db94011d3	582
sahilmgandhi	18:6a4db94011d3	583	if (p_usart_opt->protocol_type == ISO7816_T_0) {
sahilmgandhi	18:6a4db94011d3	584	ul_reg_val \|= US_MR_USART_MODE_IS07816_T_0 \| US_MR_NBSTOP_2_BIT \|
sahilmgandhi	18:6a4db94011d3	585	(p_usart_opt->max_iterations << US_MR_MAX_ITERATION_Pos);
sahilmgandhi	18:6a4db94011d3	586
sahilmgandhi	18:6a4db94011d3	587	if (p_usart_opt->bit_order) {
sahilmgandhi	18:6a4db94011d3	588	ul_reg_val \|= US_MR_MSBF;
sahilmgandhi	18:6a4db94011d3	589	}
sahilmgandhi	18:6a4db94011d3	590	} else if (p_usart_opt->protocol_type == ISO7816_T_1) {
sahilmgandhi	18:6a4db94011d3	591	/*
sahilmgandhi	18:6a4db94011d3	592	* Only LSBF is used in the T=1 protocol, and max_iterations field
sahilmgandhi	18:6a4db94011d3	593	* is only used in T=0 mode.
sahilmgandhi	18:6a4db94011d3	594	*/
sahilmgandhi	18:6a4db94011d3	595	if (p_usart_opt->bit_order \|\| p_usart_opt->max_iterations) {
sahilmgandhi	18:6a4db94011d3	596	return 1;
sahilmgandhi	18:6a4db94011d3	597	}
sahilmgandhi	18:6a4db94011d3	598
sahilmgandhi	18:6a4db94011d3	599	/* Set USART mode to ISO7816, T=1, and always uses 1 stop bit. */
sahilmgandhi	18:6a4db94011d3	600	ul_reg_val \|= US_MR_USART_MODE_IS07816_T_1 \| US_MR_NBSTOP_1_BIT;
sahilmgandhi	18:6a4db94011d3	601	} else {
sahilmgandhi	18:6a4db94011d3	602	return 1;
sahilmgandhi	18:6a4db94011d3	603	}
sahilmgandhi	18:6a4db94011d3	604
sahilmgandhi	18:6a4db94011d3	605	/* Set up the baudrate. */
sahilmgandhi	18:6a4db94011d3	606	if (usart_set_iso7816_clock(p_usart, p_usart_opt->iso7816_hz, ul_mck)) {
sahilmgandhi	18:6a4db94011d3	607	return 1;
sahilmgandhi	18:6a4db94011d3	608	}
sahilmgandhi	18:6a4db94011d3	609
sahilmgandhi	18:6a4db94011d3	610	/* Set FIDI register: bit rate = iso7816_hz / fidi_ratio. */
sahilmgandhi	18:6a4db94011d3	611	p_usart->US_FIDI = p_usart_opt->fidi_ratio;
sahilmgandhi	18:6a4db94011d3	612
sahilmgandhi	18:6a4db94011d3	613	/* Set ISO7816 parity type in the MODE register. */
sahilmgandhi	18:6a4db94011d3	614	ul_reg_val \|= p_usart_opt->parity_type;
sahilmgandhi	18:6a4db94011d3	615
sahilmgandhi	18:6a4db94011d3	616	if (p_usart_opt->inhibit_nack) {
sahilmgandhi	18:6a4db94011d3	617	ul_reg_val \|= US_MR_INACK;
sahilmgandhi	18:6a4db94011d3	618	}
sahilmgandhi	18:6a4db94011d3	619	if (p_usart_opt->dis_suc_nack) {
sahilmgandhi	18:6a4db94011d3	620	ul_reg_val \|= US_MR_DSNACK;
sahilmgandhi	18:6a4db94011d3	621	}
sahilmgandhi	18:6a4db94011d3	622
sahilmgandhi	18:6a4db94011d3	623	p_usart->US_MR \|= ul_reg_val;
sahilmgandhi	18:6a4db94011d3	624
sahilmgandhi	18:6a4db94011d3	625	return 0;
sahilmgandhi	18:6a4db94011d3	626	}
sahilmgandhi	18:6a4db94011d3	627
sahilmgandhi	18:6a4db94011d3	628	/**
sahilmgandhi	18:6a4db94011d3	629	* \brief Reset the ITERATION in US_CSR when the ISO7816 mode is enabled.
sahilmgandhi	18:6a4db94011d3	630	*
sahilmgandhi	18:6a4db94011d3	631	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	632	*/
sahilmgandhi	18:6a4db94011d3	633	void usart_reset_iterations(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	634	{
sahilmgandhi	18:6a4db94011d3	635	p_usart->US_CR = US_CR_RSTIT;
sahilmgandhi	18:6a4db94011d3	636	}
sahilmgandhi	18:6a4db94011d3	637
sahilmgandhi	18:6a4db94011d3	638	/**
sahilmgandhi	18:6a4db94011d3	639	* \brief Reset NACK in US_CSR.
sahilmgandhi	18:6a4db94011d3	640	*
sahilmgandhi	18:6a4db94011d3	641	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	642	*/
sahilmgandhi	18:6a4db94011d3	643	void usart_reset_nack(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	644	{
sahilmgandhi	18:6a4db94011d3	645	p_usart->US_CR = US_CR_RSTNACK;
sahilmgandhi	18:6a4db94011d3	646	}
sahilmgandhi	18:6a4db94011d3	647
sahilmgandhi	18:6a4db94011d3	648	/**
sahilmgandhi	18:6a4db94011d3	649	* \brief Check if one receive buffer is filled.
sahilmgandhi	18:6a4db94011d3	650	*
sahilmgandhi	18:6a4db94011d3	651	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	652	*
sahilmgandhi	18:6a4db94011d3	653	* \retval 1 Receive is complete.
sahilmgandhi	18:6a4db94011d3	654	* \retval 0 Receive is still pending.
sahilmgandhi	18:6a4db94011d3	655	*/
sahilmgandhi	18:6a4db94011d3	656	uint32_t usart_is_rx_buf_end(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	657	{
sahilmgandhi	18:6a4db94011d3	658	return (p_usart->US_CSR & US_CSR_ENDRX) > 0;
sahilmgandhi	18:6a4db94011d3	659	}
sahilmgandhi	18:6a4db94011d3	660
sahilmgandhi	18:6a4db94011d3	661	/**
sahilmgandhi	18:6a4db94011d3	662	* \brief Check if one transmit buffer is empty.
sahilmgandhi	18:6a4db94011d3	663	*
sahilmgandhi	18:6a4db94011d3	664	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	665	*
sahilmgandhi	18:6a4db94011d3	666	* \retval 1 Transmit is complete.
sahilmgandhi	18:6a4db94011d3	667	* \retval 0 Transmit is still pending.
sahilmgandhi	18:6a4db94011d3	668	*/
sahilmgandhi	18:6a4db94011d3	669	uint32_t usart_is_tx_buf_end(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	670	{
sahilmgandhi	18:6a4db94011d3	671	return (p_usart->US_CSR & US_CSR_ENDTX) > 0;
sahilmgandhi	18:6a4db94011d3	672	}
sahilmgandhi	18:6a4db94011d3	673
sahilmgandhi	18:6a4db94011d3	674	/**
sahilmgandhi	18:6a4db94011d3	675	* \brief Check if both receive buffers are full.
sahilmgandhi	18:6a4db94011d3	676	*
sahilmgandhi	18:6a4db94011d3	677	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	678	*
sahilmgandhi	18:6a4db94011d3	679	* \retval 1 Receive buffers are full.
sahilmgandhi	18:6a4db94011d3	680	* \retval 0 Receive buffers are not full.
sahilmgandhi	18:6a4db94011d3	681	*/
sahilmgandhi	18:6a4db94011d3	682	uint32_t usart_is_rx_buf_full(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	683	{
sahilmgandhi	18:6a4db94011d3	684	return (p_usart->US_CSR & US_CSR_RXBUFF) > 0;
sahilmgandhi	18:6a4db94011d3	685	}
sahilmgandhi	18:6a4db94011d3	686
sahilmgandhi	18:6a4db94011d3	687	/**
sahilmgandhi	18:6a4db94011d3	688	* \brief Check if both transmit buffers are empty.
sahilmgandhi	18:6a4db94011d3	689	*
sahilmgandhi	18:6a4db94011d3	690	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	691	*
sahilmgandhi	18:6a4db94011d3	692	* \retval 1 Transmit buffers are empty.
sahilmgandhi	18:6a4db94011d3	693	* \retval 0 Transmit buffers are not empty.
sahilmgandhi	18:6a4db94011d3	694	*/
sahilmgandhi	18:6a4db94011d3	695	uint32_t usart_is_tx_buf_empty(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	696	{
sahilmgandhi	18:6a4db94011d3	697	return (p_usart->US_CSR & US_CSR_TXBUFE) > 0;
sahilmgandhi	18:6a4db94011d3	698	}
sahilmgandhi	18:6a4db94011d3	699
sahilmgandhi	18:6a4db94011d3	700	/**
sahilmgandhi	18:6a4db94011d3	701	* \brief Get the total number of errors that occur during an ISO7816 transfer.
sahilmgandhi	18:6a4db94011d3	702	*
sahilmgandhi	18:6a4db94011d3	703	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	704	*
sahilmgandhi	18:6a4db94011d3	705	* \return The number of errors that occurred.
sahilmgandhi	18:6a4db94011d3	706	*/
sahilmgandhi	18:6a4db94011d3	707	uint8_t usart_get_error_number(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	708	{
sahilmgandhi	18:6a4db94011d3	709	return (p_usart->US_NER & US_NER_NB_ERRORS_Msk);
sahilmgandhi	18:6a4db94011d3	710	}
sahilmgandhi	18:6a4db94011d3	711
sahilmgandhi	18:6a4db94011d3	712	#endif
sahilmgandhi	18:6a4db94011d3	713
sahilmgandhi	18:6a4db94011d3	714	/**
sahilmgandhi	18:6a4db94011d3	715	* \brief Configure USART to work in SPI mode and act as a master.
sahilmgandhi	18:6a4db94011d3	716	*
sahilmgandhi	18:6a4db94011d3	717	* \note By default, the transmitter and receiver aren't enabled.
sahilmgandhi	18:6a4db94011d3	718	*
sahilmgandhi	18:6a4db94011d3	719	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	720	* \param p_usart_opt Pointer to sam_usart_opt_t instance.
sahilmgandhi	18:6a4db94011d3	721	* \param ul_mck USART module input clock frequency.
sahilmgandhi	18:6a4db94011d3	722	*
sahilmgandhi	18:6a4db94011d3	723	* \retval 0 on success.
sahilmgandhi	18:6a4db94011d3	724	* \retval 1 on failure.
sahilmgandhi	18:6a4db94011d3	725	*/
sahilmgandhi	18:6a4db94011d3	726	uint32_t usart_init_spi_master(Usart *p_usart,
sahilmgandhi	18:6a4db94011d3	727	const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck)
sahilmgandhi	18:6a4db94011d3	728	{
sahilmgandhi	18:6a4db94011d3	729	static uint32_t ul_reg_val;
sahilmgandhi	18:6a4db94011d3	730
sahilmgandhi	18:6a4db94011d3	731	/* Reset the USART and shut down TX and RX. */
sahilmgandhi	18:6a4db94011d3	732	usart_reset(p_usart);
sahilmgandhi	18:6a4db94011d3	733
sahilmgandhi	18:6a4db94011d3	734	ul_reg_val = 0;
sahilmgandhi	18:6a4db94011d3	735	/* Check whether the input values are legal. */
sahilmgandhi	18:6a4db94011d3	736	if (!p_usart_opt \|\| (p_usart_opt->spi_mode > SPI_MODE_3) \|\|
sahilmgandhi	18:6a4db94011d3	737	usart_set_spi_master_baudrate(p_usart, p_usart_opt->baudrate,
sahilmgandhi	18:6a4db94011d3	738	ul_mck)) {
sahilmgandhi	18:6a4db94011d3	739	return 1;
sahilmgandhi	18:6a4db94011d3	740	}
sahilmgandhi	18:6a4db94011d3	741
sahilmgandhi	18:6a4db94011d3	742	/* Configure the character length bit in MR register. */
sahilmgandhi	18:6a4db94011d3	743	ul_reg_val \|= p_usart_opt->char_length;
sahilmgandhi	18:6a4db94011d3	744
sahilmgandhi	18:6a4db94011d3	745	/* Set SPI master mode and channel mode. */
sahilmgandhi	18:6a4db94011d3	746	ul_reg_val \|= US_MR_USART_MODE_SPI_MASTER \| US_MR_CLKO \|
sahilmgandhi	18:6a4db94011d3	747	p_usart_opt->channel_mode;
sahilmgandhi	18:6a4db94011d3	748
sahilmgandhi	18:6a4db94011d3	749	switch (p_usart_opt->spi_mode) {
sahilmgandhi	18:6a4db94011d3	750	case SPI_MODE_0:
sahilmgandhi	18:6a4db94011d3	751	ul_reg_val \|= US_MR_CPHA;
sahilmgandhi	18:6a4db94011d3	752	ul_reg_val &= ~US_MR_CPOL;
sahilmgandhi	18:6a4db94011d3	753	break;
sahilmgandhi	18:6a4db94011d3	754
sahilmgandhi	18:6a4db94011d3	755	case SPI_MODE_1:
sahilmgandhi	18:6a4db94011d3	756	ul_reg_val &= ~US_MR_CPHA;
sahilmgandhi	18:6a4db94011d3	757	ul_reg_val &= ~US_MR_CPOL;
sahilmgandhi	18:6a4db94011d3	758	break;
sahilmgandhi	18:6a4db94011d3	759
sahilmgandhi	18:6a4db94011d3	760	case SPI_MODE_2:
sahilmgandhi	18:6a4db94011d3	761	ul_reg_val \|= US_MR_CPHA;
sahilmgandhi	18:6a4db94011d3	762	ul_reg_val \|= US_MR_CPOL;
sahilmgandhi	18:6a4db94011d3	763	break;
sahilmgandhi	18:6a4db94011d3	764
sahilmgandhi	18:6a4db94011d3	765	case SPI_MODE_3:
sahilmgandhi	18:6a4db94011d3	766	ul_reg_val &= ~US_MR_CPHA;
sahilmgandhi	18:6a4db94011d3	767	ul_reg_val \|= US_MR_CPOL;
sahilmgandhi	18:6a4db94011d3	768	break;
sahilmgandhi	18:6a4db94011d3	769
sahilmgandhi	18:6a4db94011d3	770	default:
sahilmgandhi	18:6a4db94011d3	771	break;
sahilmgandhi	18:6a4db94011d3	772	}
sahilmgandhi	18:6a4db94011d3	773
sahilmgandhi	18:6a4db94011d3	774	p_usart->US_MR \|= ul_reg_val;
sahilmgandhi	18:6a4db94011d3	775
sahilmgandhi	18:6a4db94011d3	776	return 0;
sahilmgandhi	18:6a4db94011d3	777	}
sahilmgandhi	18:6a4db94011d3	778
sahilmgandhi	18:6a4db94011d3	779	/**
sahilmgandhi	18:6a4db94011d3	780	* \brief Configure USART to work in SPI mode and act as a slave.
sahilmgandhi	18:6a4db94011d3	781	*
sahilmgandhi	18:6a4db94011d3	782	* \note By default, the transmitter and receiver aren't enabled.
sahilmgandhi	18:6a4db94011d3	783	*
sahilmgandhi	18:6a4db94011d3	784	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	785	* \param p_usart_opt Pointer to sam_usart_opt_t instance.
sahilmgandhi	18:6a4db94011d3	786	*
sahilmgandhi	18:6a4db94011d3	787	* \retval 0 on success.
sahilmgandhi	18:6a4db94011d3	788	* \retval 1 on failure.
sahilmgandhi	18:6a4db94011d3	789	*/
sahilmgandhi	18:6a4db94011d3	790	uint32_t usart_init_spi_slave(Usart *p_usart,
sahilmgandhi	18:6a4db94011d3	791	const usart_spi_opt_t *p_usart_opt)
sahilmgandhi	18:6a4db94011d3	792	{
sahilmgandhi	18:6a4db94011d3	793	static uint32_t ul_reg_val;
sahilmgandhi	18:6a4db94011d3	794
sahilmgandhi	18:6a4db94011d3	795	/* Reset the USART and shut down TX and RX. */
sahilmgandhi	18:6a4db94011d3	796	usart_reset(p_usart);
sahilmgandhi	18:6a4db94011d3	797
sahilmgandhi	18:6a4db94011d3	798	ul_reg_val = 0;
sahilmgandhi	18:6a4db94011d3	799	usart_set_spi_slave_baudrate(p_usart);
sahilmgandhi	18:6a4db94011d3	800
sahilmgandhi	18:6a4db94011d3	801	/* Check whether the input values are legal. */
sahilmgandhi	18:6a4db94011d3	802	if (!p_usart_opt \|\| p_usart_opt->spi_mode > SPI_MODE_3) {
sahilmgandhi	18:6a4db94011d3	803	return 1;
sahilmgandhi	18:6a4db94011d3	804	}
sahilmgandhi	18:6a4db94011d3	805
sahilmgandhi	18:6a4db94011d3	806	/* Configure the character length bit in MR register. */
sahilmgandhi	18:6a4db94011d3	807	ul_reg_val \|= p_usart_opt->char_length;
sahilmgandhi	18:6a4db94011d3	808
sahilmgandhi	18:6a4db94011d3	809	/* Set SPI slave mode and channel mode. */
sahilmgandhi	18:6a4db94011d3	810	ul_reg_val \|= US_MR_USART_MODE_SPI_SLAVE \| p_usart_opt->channel_mode;
sahilmgandhi	18:6a4db94011d3	811
sahilmgandhi	18:6a4db94011d3	812	switch (p_usart_opt->spi_mode) {
sahilmgandhi	18:6a4db94011d3	813	case SPI_MODE_0:
sahilmgandhi	18:6a4db94011d3	814	ul_reg_val \|= US_MR_CPHA;
sahilmgandhi	18:6a4db94011d3	815	ul_reg_val &= ~US_MR_CPOL;
sahilmgandhi	18:6a4db94011d3	816	break;
sahilmgandhi	18:6a4db94011d3	817
sahilmgandhi	18:6a4db94011d3	818	case SPI_MODE_1:
sahilmgandhi	18:6a4db94011d3	819	ul_reg_val &= ~US_MR_CPHA;
sahilmgandhi	18:6a4db94011d3	820	ul_reg_val &= ~US_MR_CPOL;
sahilmgandhi	18:6a4db94011d3	821	break;
sahilmgandhi	18:6a4db94011d3	822
sahilmgandhi	18:6a4db94011d3	823	case SPI_MODE_2:
sahilmgandhi	18:6a4db94011d3	824	ul_reg_val \|= US_MR_CPHA;
sahilmgandhi	18:6a4db94011d3	825	ul_reg_val \|= US_MR_CPOL;
sahilmgandhi	18:6a4db94011d3	826	break;
sahilmgandhi	18:6a4db94011d3	827
sahilmgandhi	18:6a4db94011d3	828	case SPI_MODE_3:
sahilmgandhi	18:6a4db94011d3	829	ul_reg_val \|= US_MR_CPOL;
sahilmgandhi	18:6a4db94011d3	830	ul_reg_val &= ~US_MR_CPHA;
sahilmgandhi	18:6a4db94011d3	831	break;
sahilmgandhi	18:6a4db94011d3	832
sahilmgandhi	18:6a4db94011d3	833	default:
sahilmgandhi	18:6a4db94011d3	834	break;
sahilmgandhi	18:6a4db94011d3	835	}
sahilmgandhi	18:6a4db94011d3	836
sahilmgandhi	18:6a4db94011d3	837	p_usart->US_MR \|= ul_reg_val;
sahilmgandhi	18:6a4db94011d3	838
sahilmgandhi	18:6a4db94011d3	839	return 0;
sahilmgandhi	18:6a4db94011d3	840	}
sahilmgandhi	18:6a4db94011d3	841
sahilmgandhi	18:6a4db94011d3	842	#if (SAM3XA \|\| SAM4L \|\| SAMG55 \|\| SAMV71 \|\| SAMV70 \|\| SAME70 \|\| SAMS70)
sahilmgandhi	18:6a4db94011d3	843
sahilmgandhi	18:6a4db94011d3	844	/**
sahilmgandhi	18:6a4db94011d3	845	* \brief Configure USART to work in LIN mode and act as a LIN master.
sahilmgandhi	18:6a4db94011d3	846	*
sahilmgandhi	18:6a4db94011d3	847	* \note By default, the transmitter and receiver aren't enabled.
sahilmgandhi	18:6a4db94011d3	848	*
sahilmgandhi	18:6a4db94011d3	849	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	850	* \param ul_baudrate Baudrate to be used.
sahilmgandhi	18:6a4db94011d3	851	* \param ul_mck USART module input clock frequency.
sahilmgandhi	18:6a4db94011d3	852	*
sahilmgandhi	18:6a4db94011d3	853	* \retval 0 on success.
sahilmgandhi	18:6a4db94011d3	854	* \retval 1 on failure.
sahilmgandhi	18:6a4db94011d3	855	*/
sahilmgandhi	18:6a4db94011d3	856	uint32_t usart_init_lin_master(Usart *p_usart,uint32_t ul_baudrate,
sahilmgandhi	18:6a4db94011d3	857	uint32_t ul_mck)
sahilmgandhi	18:6a4db94011d3	858	{
sahilmgandhi	18:6a4db94011d3	859	/* Reset the USART and shut down TX and RX. */
sahilmgandhi	18:6a4db94011d3	860	usart_reset(p_usart);
sahilmgandhi	18:6a4db94011d3	861
sahilmgandhi	18:6a4db94011d3	862	/* Set up the baudrate. */
sahilmgandhi	18:6a4db94011d3	863	if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) {
sahilmgandhi	18:6a4db94011d3	864	return 1;
sahilmgandhi	18:6a4db94011d3	865	}
sahilmgandhi	18:6a4db94011d3	866
sahilmgandhi	18:6a4db94011d3	867	/* Set LIN master mode. */
sahilmgandhi	18:6a4db94011d3	868	p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) \|
sahilmgandhi	18:6a4db94011d3	869	US_MR_USART_MODE_LIN_MASTER;
sahilmgandhi	18:6a4db94011d3	870
sahilmgandhi	18:6a4db94011d3	871	usart_enable_rx(p_usart);
sahilmgandhi	18:6a4db94011d3	872	usart_enable_tx(p_usart);
sahilmgandhi	18:6a4db94011d3	873
sahilmgandhi	18:6a4db94011d3	874	return 0;
sahilmgandhi	18:6a4db94011d3	875	}
sahilmgandhi	18:6a4db94011d3	876
sahilmgandhi	18:6a4db94011d3	877	/**
sahilmgandhi	18:6a4db94011d3	878	* \brief Configure USART to work in LIN mode and act as a LIN slave.
sahilmgandhi	18:6a4db94011d3	879	*
sahilmgandhi	18:6a4db94011d3	880	* \note By default, the transmitter and receiver aren't enabled.
sahilmgandhi	18:6a4db94011d3	881	*
sahilmgandhi	18:6a4db94011d3	882	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	883	* \param ul_baudrate Baudrate to be used.
sahilmgandhi	18:6a4db94011d3	884	* \param ul_mck USART module input clock frequency.
sahilmgandhi	18:6a4db94011d3	885	*
sahilmgandhi	18:6a4db94011d3	886	* \retval 0 on success.
sahilmgandhi	18:6a4db94011d3	887	* \retval 1 on failure.
sahilmgandhi	18:6a4db94011d3	888	*/
sahilmgandhi	18:6a4db94011d3	889	uint32_t usart_init_lin_slave(Usart *p_usart, uint32_t ul_baudrate,
sahilmgandhi	18:6a4db94011d3	890	uint32_t ul_mck)
sahilmgandhi	18:6a4db94011d3	891	{
sahilmgandhi	18:6a4db94011d3	892	/* Reset the USART and shut down TX and RX. */
sahilmgandhi	18:6a4db94011d3	893	usart_reset(p_usart);
sahilmgandhi	18:6a4db94011d3	894
sahilmgandhi	18:6a4db94011d3	895	usart_enable_rx(p_usart);
sahilmgandhi	18:6a4db94011d3	896	usart_enable_tx(p_usart);
sahilmgandhi	18:6a4db94011d3	897
sahilmgandhi	18:6a4db94011d3	898	/* Set LIN slave mode. */
sahilmgandhi	18:6a4db94011d3	899	p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) \|
sahilmgandhi	18:6a4db94011d3	900	US_MR_USART_MODE_LIN_SLAVE;
sahilmgandhi	18:6a4db94011d3	901
sahilmgandhi	18:6a4db94011d3	902	/* Set up the baudrate. */
sahilmgandhi	18:6a4db94011d3	903	if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) {
sahilmgandhi	18:6a4db94011d3	904	return 1;
sahilmgandhi	18:6a4db94011d3	905	}
sahilmgandhi	18:6a4db94011d3	906
sahilmgandhi	18:6a4db94011d3	907	return 0;
sahilmgandhi	18:6a4db94011d3	908	}
sahilmgandhi	18:6a4db94011d3	909
sahilmgandhi	18:6a4db94011d3	910	/**
sahilmgandhi	18:6a4db94011d3	911	* \brief Abort the current LIN transmission.
sahilmgandhi	18:6a4db94011d3	912	*
sahilmgandhi	18:6a4db94011d3	913	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	914	*/
sahilmgandhi	18:6a4db94011d3	915	void usart_lin_abort_tx(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	916	{
sahilmgandhi	18:6a4db94011d3	917	p_usart->US_CR = US_CR_LINABT;
sahilmgandhi	18:6a4db94011d3	918	}
sahilmgandhi	18:6a4db94011d3	919
sahilmgandhi	18:6a4db94011d3	920	/**
sahilmgandhi	18:6a4db94011d3	921	* \brief Send a wakeup signal on the LIN bus.
sahilmgandhi	18:6a4db94011d3	922	*
sahilmgandhi	18:6a4db94011d3	923	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	924	*/
sahilmgandhi	18:6a4db94011d3	925	void usart_lin_send_wakeup_signal(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	926	{
sahilmgandhi	18:6a4db94011d3	927	p_usart->US_CR = US_CR_LINWKUP;
sahilmgandhi	18:6a4db94011d3	928	}
sahilmgandhi	18:6a4db94011d3	929
sahilmgandhi	18:6a4db94011d3	930	/**
sahilmgandhi	18:6a4db94011d3	931	* \brief Configure the LIN node action, which should be one of PUBLISH,
sahilmgandhi	18:6a4db94011d3	932	* SUBSCRIBE or IGNORE.
sahilmgandhi	18:6a4db94011d3	933	*
sahilmgandhi	18:6a4db94011d3	934	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	935	* \param uc_action 0 for PUBLISH, 1 for SUBSCRIBE, 2 for IGNORE.
sahilmgandhi	18:6a4db94011d3	936	*/
sahilmgandhi	18:6a4db94011d3	937	void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action)
sahilmgandhi	18:6a4db94011d3	938	{
sahilmgandhi	18:6a4db94011d3	939	p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_NACT_Msk) \|
sahilmgandhi	18:6a4db94011d3	940	(uc_action << US_LINMR_NACT_Pos);
sahilmgandhi	18:6a4db94011d3	941	}
sahilmgandhi	18:6a4db94011d3	942
sahilmgandhi	18:6a4db94011d3	943	/**
sahilmgandhi	18:6a4db94011d3	944	* \brief Disable the parity check during the LIN communication.
sahilmgandhi	18:6a4db94011d3	945	*
sahilmgandhi	18:6a4db94011d3	946	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	947	*/
sahilmgandhi	18:6a4db94011d3	948	void usart_lin_disable_parity(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	949	{
sahilmgandhi	18:6a4db94011d3	950	p_usart->US_LINMR \|= US_LINMR_PARDIS;
sahilmgandhi	18:6a4db94011d3	951	}
sahilmgandhi	18:6a4db94011d3	952
sahilmgandhi	18:6a4db94011d3	953	/**
sahilmgandhi	18:6a4db94011d3	954	* \brief Enable the parity check during the LIN communication.
sahilmgandhi	18:6a4db94011d3	955	*
sahilmgandhi	18:6a4db94011d3	956	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	957	*/
sahilmgandhi	18:6a4db94011d3	958	void usart_lin_enable_parity(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	959	{
sahilmgandhi	18:6a4db94011d3	960	p_usart->US_LINMR &= ~US_LINMR_PARDIS;
sahilmgandhi	18:6a4db94011d3	961	}
sahilmgandhi	18:6a4db94011d3	962
sahilmgandhi	18:6a4db94011d3	963	/**
sahilmgandhi	18:6a4db94011d3	964	* \brief Disable the checksum during the LIN communication.
sahilmgandhi	18:6a4db94011d3	965	*
sahilmgandhi	18:6a4db94011d3	966	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	967	*/
sahilmgandhi	18:6a4db94011d3	968	void usart_lin_disable_checksum(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	969	{
sahilmgandhi	18:6a4db94011d3	970	p_usart->US_LINMR \|= US_LINMR_CHKDIS;
sahilmgandhi	18:6a4db94011d3	971	}
sahilmgandhi	18:6a4db94011d3	972
sahilmgandhi	18:6a4db94011d3	973	/**
sahilmgandhi	18:6a4db94011d3	974	* \brief Enable the checksum during the LIN communication.
sahilmgandhi	18:6a4db94011d3	975	*
sahilmgandhi	18:6a4db94011d3	976	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	977	*/
sahilmgandhi	18:6a4db94011d3	978	void usart_lin_enable_checksum(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	979	{
sahilmgandhi	18:6a4db94011d3	980	p_usart->US_LINMR &= ~US_LINMR_CHKDIS;
sahilmgandhi	18:6a4db94011d3	981	}
sahilmgandhi	18:6a4db94011d3	982
sahilmgandhi	18:6a4db94011d3	983	/**
sahilmgandhi	18:6a4db94011d3	984	* \brief Configure the checksum type during the LIN communication.
sahilmgandhi	18:6a4db94011d3	985	*
sahilmgandhi	18:6a4db94011d3	986	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	987	* \param uc_type 0 for LIN 2.0 Enhanced checksum or 1 for LIN 1.3 Classic
sahilmgandhi	18:6a4db94011d3	988	* checksum.
sahilmgandhi	18:6a4db94011d3	989	*/
sahilmgandhi	18:6a4db94011d3	990	void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type)
sahilmgandhi	18:6a4db94011d3	991	{
sahilmgandhi	18:6a4db94011d3	992	p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_CHKTYP) \|
sahilmgandhi	18:6a4db94011d3	993	(uc_type << 4);
sahilmgandhi	18:6a4db94011d3	994	}
sahilmgandhi	18:6a4db94011d3	995
sahilmgandhi	18:6a4db94011d3	996	/**
sahilmgandhi	18:6a4db94011d3	997	* \brief Configure the data length mode during the LIN communication.
sahilmgandhi	18:6a4db94011d3	998	*
sahilmgandhi	18:6a4db94011d3	999	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1000	* \param uc_mode Indicate the data length type: 0 if the data length is
sahilmgandhi	18:6a4db94011d3	1001	* defined by the DLC of LIN mode register or 1 if the data length is defined
sahilmgandhi	18:6a4db94011d3	1002	* by the bit 5 and 6 of the identifier.
sahilmgandhi	18:6a4db94011d3	1003	*/
sahilmgandhi	18:6a4db94011d3	1004	void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode)
sahilmgandhi	18:6a4db94011d3	1005	{
sahilmgandhi	18:6a4db94011d3	1006	p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLM) \|
sahilmgandhi	18:6a4db94011d3	1007	(uc_mode << 5);
sahilmgandhi	18:6a4db94011d3	1008	}
sahilmgandhi	18:6a4db94011d3	1009
sahilmgandhi	18:6a4db94011d3	1010	/**
sahilmgandhi	18:6a4db94011d3	1011	* \brief Disable the frame slot mode during the LIN communication.
sahilmgandhi	18:6a4db94011d3	1012	*
sahilmgandhi	18:6a4db94011d3	1013	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1014	*/
sahilmgandhi	18:6a4db94011d3	1015	void usart_lin_disable_frame_slot(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1016	{
sahilmgandhi	18:6a4db94011d3	1017	p_usart->US_LINMR \|= US_LINMR_FSDIS;
sahilmgandhi	18:6a4db94011d3	1018	}
sahilmgandhi	18:6a4db94011d3	1019
sahilmgandhi	18:6a4db94011d3	1020	/**
sahilmgandhi	18:6a4db94011d3	1021	* \brief Enable the frame slot mode during the LIN communication.
sahilmgandhi	18:6a4db94011d3	1022	*
sahilmgandhi	18:6a4db94011d3	1023	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1024	*/
sahilmgandhi	18:6a4db94011d3	1025	void usart_lin_enable_frame_slot(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1026	{
sahilmgandhi	18:6a4db94011d3	1027	p_usart->US_LINMR &= ~US_LINMR_FSDIS;
sahilmgandhi	18:6a4db94011d3	1028	}
sahilmgandhi	18:6a4db94011d3	1029
sahilmgandhi	18:6a4db94011d3	1030	/**
sahilmgandhi	18:6a4db94011d3	1031	* \brief Configure the wakeup signal type during the LIN communication.
sahilmgandhi	18:6a4db94011d3	1032	*
sahilmgandhi	18:6a4db94011d3	1033	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1034	* \param uc_type Indicate the checksum type: 0 if the wakeup signal is a
sahilmgandhi	18:6a4db94011d3	1035	* LIN 2.0 wakeup signal; 1 if the wakeup signal is a LIN 1.3 wakeup signal.
sahilmgandhi	18:6a4db94011d3	1036	*/
sahilmgandhi	18:6a4db94011d3	1037	void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type)
sahilmgandhi	18:6a4db94011d3	1038	{
sahilmgandhi	18:6a4db94011d3	1039	p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_WKUPTYP) \|
sahilmgandhi	18:6a4db94011d3	1040	(uc_type << 7);
sahilmgandhi	18:6a4db94011d3	1041	}
sahilmgandhi	18:6a4db94011d3	1042
sahilmgandhi	18:6a4db94011d3	1043	/**
sahilmgandhi	18:6a4db94011d3	1044	* \brief Configure the response data length if the data length is defined by
sahilmgandhi	18:6a4db94011d3	1045	* the DLC field during the LIN communication.
sahilmgandhi	18:6a4db94011d3	1046	*
sahilmgandhi	18:6a4db94011d3	1047	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1048	* \param uc_len Indicate the response data length.
sahilmgandhi	18:6a4db94011d3	1049	*/
sahilmgandhi	18:6a4db94011d3	1050	void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len)
sahilmgandhi	18:6a4db94011d3	1051	{
sahilmgandhi	18:6a4db94011d3	1052	p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLC_Msk) \|
sahilmgandhi	18:6a4db94011d3	1053	((uc_len - 1) << US_LINMR_DLC_Pos);
sahilmgandhi	18:6a4db94011d3	1054	}
sahilmgandhi	18:6a4db94011d3	1055
sahilmgandhi	18:6a4db94011d3	1056	/**
sahilmgandhi	18:6a4db94011d3	1057	* \brief The LIN mode register is not written by the PDC.
sahilmgandhi	18:6a4db94011d3	1058	*
sahilmgandhi	18:6a4db94011d3	1059	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1060	*/
sahilmgandhi	18:6a4db94011d3	1061	void usart_lin_disable_pdc_mode(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1062	{
sahilmgandhi	18:6a4db94011d3	1063	p_usart->US_LINMR &= ~US_LINMR_PDCM;
sahilmgandhi	18:6a4db94011d3	1064	}
sahilmgandhi	18:6a4db94011d3	1065
sahilmgandhi	18:6a4db94011d3	1066	/**
sahilmgandhi	18:6a4db94011d3	1067	* \brief The LIN mode register (except this flag) is written by the PDC.
sahilmgandhi	18:6a4db94011d3	1068	*
sahilmgandhi	18:6a4db94011d3	1069	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1070	*/
sahilmgandhi	18:6a4db94011d3	1071	void usart_lin_enable_pdc_mode(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1072	{
sahilmgandhi	18:6a4db94011d3	1073	p_usart->US_LINMR \|= US_LINMR_PDCM;
sahilmgandhi	18:6a4db94011d3	1074	}
sahilmgandhi	18:6a4db94011d3	1075
sahilmgandhi	18:6a4db94011d3	1076	/**
sahilmgandhi	18:6a4db94011d3	1077	* \brief Configure the LIN identifier when USART works in LIN master mode.
sahilmgandhi	18:6a4db94011d3	1078	*
sahilmgandhi	18:6a4db94011d3	1079	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1080	* \param uc_id The identifier to be transmitted.
sahilmgandhi	18:6a4db94011d3	1081	*/
sahilmgandhi	18:6a4db94011d3	1082	void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id)
sahilmgandhi	18:6a4db94011d3	1083	{
sahilmgandhi	18:6a4db94011d3	1084	p_usart->US_LINIR = (p_usart->US_LINIR & ~US_LINIR_IDCHR_Msk) \|
sahilmgandhi	18:6a4db94011d3	1085	US_LINIR_IDCHR(uc_id);
sahilmgandhi	18:6a4db94011d3	1086	}
sahilmgandhi	18:6a4db94011d3	1087
sahilmgandhi	18:6a4db94011d3	1088	/**
sahilmgandhi	18:6a4db94011d3	1089	* \brief Read the identifier when USART works in LIN mode.
sahilmgandhi	18:6a4db94011d3	1090	*
sahilmgandhi	18:6a4db94011d3	1091	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1092	*
sahilmgandhi	18:6a4db94011d3	1093	* \return The last identifier received in LIN slave mode or the last
sahilmgandhi	18:6a4db94011d3	1094	* identifier transmitted in LIN master mode.
sahilmgandhi	18:6a4db94011d3	1095	*/
sahilmgandhi	18:6a4db94011d3	1096	uint8_t usart_lin_read_identifier(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1097	{
sahilmgandhi	18:6a4db94011d3	1098	return (p_usart->US_LINIR & US_LINIR_IDCHR_Msk);
sahilmgandhi	18:6a4db94011d3	1099	}
sahilmgandhi	18:6a4db94011d3	1100
sahilmgandhi	18:6a4db94011d3	1101	/**
sahilmgandhi	18:6a4db94011d3	1102	* \brief Get data length.
sahilmgandhi	18:6a4db94011d3	1103	*
sahilmgandhi	18:6a4db94011d3	1104	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1105	*
sahilmgandhi	18:6a4db94011d3	1106	* \return Data length.
sahilmgandhi	18:6a4db94011d3	1107	*/
sahilmgandhi	18:6a4db94011d3	1108	uint8_t usart_lin_get_data_length(Usart *usart)
sahilmgandhi	18:6a4db94011d3	1109	{
sahilmgandhi	18:6a4db94011d3	1110	if (usart->US_LINMR & US_LINMR_DLM) {
sahilmgandhi	18:6a4db94011d3	1111	uint8_t data_length = 1 << ((usart->US_LINIR >>
sahilmgandhi	18:6a4db94011d3	1112	(US_LINIR_IDCHR_Pos + 4)) & 0x03);
sahilmgandhi	18:6a4db94011d3	1113	return data_length;
sahilmgandhi	18:6a4db94011d3	1114	} else {
sahilmgandhi	18:6a4db94011d3	1115	return ((usart->US_LINMR & US_LINMR_DLC_Msk) >> US_LINMR_DLC_Pos) + 1;
sahilmgandhi	18:6a4db94011d3	1116	}
sahilmgandhi	18:6a4db94011d3	1117	}
sahilmgandhi	18:6a4db94011d3	1118
sahilmgandhi	18:6a4db94011d3	1119	#endif
sahilmgandhi	18:6a4db94011d3	1120
sahilmgandhi	18:6a4db94011d3	1121	#if (SAMV71 \|\| SAMV70 \|\| SAME70 \|\| SAMS70)
sahilmgandhi	18:6a4db94011d3	1122	/**
sahilmgandhi	18:6a4db94011d3	1123	* \brief Get identifier send status.
sahilmgandhi	18:6a4db94011d3	1124	*
sahilmgandhi	18:6a4db94011d3	1125	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1126	*
sahilmgandhi	18:6a4db94011d3	1127	* \return
sahilmgandhi	18:6a4db94011d3	1128	* 0: No LIN identifier has been sent since the last RSTSTA.
sahilmgandhi	18:6a4db94011d3	1129	* 1: :At least one LIN identifier has been sent since the last RSTSTA.
sahilmgandhi	18:6a4db94011d3	1130	*/
sahilmgandhi	18:6a4db94011d3	1131	uint8_t usart_lin_identifier_send_complete(Usart *usart)
sahilmgandhi	18:6a4db94011d3	1132	{
sahilmgandhi	18:6a4db94011d3	1133	return (usart->US_CSR & US_CSR_LINID) > 0;
sahilmgandhi	18:6a4db94011d3	1134	}
sahilmgandhi	18:6a4db94011d3	1135
sahilmgandhi	18:6a4db94011d3	1136	/**
sahilmgandhi	18:6a4db94011d3	1137	* \brief Get identifier received status.
sahilmgandhi	18:6a4db94011d3	1138	*
sahilmgandhi	18:6a4db94011d3	1139	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1140	*
sahilmgandhi	18:6a4db94011d3	1141	* \return
sahilmgandhi	18:6a4db94011d3	1142	* 0: No LIN identifier has been reveived since the last RSTSTA.
sahilmgandhi	18:6a4db94011d3	1143	* 1: At least one LIN identifier has been received since the last RSTSTA.
sahilmgandhi	18:6a4db94011d3	1144	*/
sahilmgandhi	18:6a4db94011d3	1145	uint8_t usart_lin_identifier_reception_complete(Usart *usart)
sahilmgandhi	18:6a4db94011d3	1146	{
sahilmgandhi	18:6a4db94011d3	1147	return (usart->US_CSR & US_CSR_LINID) > 0;
sahilmgandhi	18:6a4db94011d3	1148	}
sahilmgandhi	18:6a4db94011d3	1149
sahilmgandhi	18:6a4db94011d3	1150	/**
sahilmgandhi	18:6a4db94011d3	1151	* \brief Get transmission status.
sahilmgandhi	18:6a4db94011d3	1152	*
sahilmgandhi	18:6a4db94011d3	1153	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1154	*
sahilmgandhi	18:6a4db94011d3	1155	* \return
sahilmgandhi	18:6a4db94011d3	1156	* 0: The USART is idle or a LIN transfer is ongoing.
sahilmgandhi	18:6a4db94011d3	1157	* 1: A LIN transfer has been completed since the last RSTSTA.
sahilmgandhi	18:6a4db94011d3	1158	*/
sahilmgandhi	18:6a4db94011d3	1159	uint8_t usart_lin_tx_complete(Usart *usart)
sahilmgandhi	18:6a4db94011d3	1160	{
sahilmgandhi	18:6a4db94011d3	1161	return (usart->US_CSR & US_CSR_LINTC) > 0;
sahilmgandhi	18:6a4db94011d3	1162	}
sahilmgandhi	18:6a4db94011d3	1163
sahilmgandhi	18:6a4db94011d3	1164	/**
sahilmgandhi	18:6a4db94011d3	1165	* \brief Configure USART to work in LON mode.
sahilmgandhi	18:6a4db94011d3	1166	*
sahilmgandhi	18:6a4db94011d3	1167	* \note By default, the transmitter and receiver aren't enabled.
sahilmgandhi	18:6a4db94011d3	1168	*
sahilmgandhi	18:6a4db94011d3	1169	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1170	* \param ul_baudrate Baudrate to be used.
sahilmgandhi	18:6a4db94011d3	1171	* \param ul_mck USART module input clock frequency.
sahilmgandhi	18:6a4db94011d3	1172	*
sahilmgandhi	18:6a4db94011d3	1173	* \retval 0 on success.
sahilmgandhi	18:6a4db94011d3	1174	* \retval 1 on failure.
sahilmgandhi	18:6a4db94011d3	1175	*/
sahilmgandhi	18:6a4db94011d3	1176	uint32_t usart_init_lon(Usart *p_usart,uint32_t ul_baudrate,
sahilmgandhi	18:6a4db94011d3	1177	uint32_t ul_mck)
sahilmgandhi	18:6a4db94011d3	1178	{
sahilmgandhi	18:6a4db94011d3	1179	/* Reset the USART and shut down TX and RX. */
sahilmgandhi	18:6a4db94011d3	1180	usart_reset(p_usart);
sahilmgandhi	18:6a4db94011d3	1181
sahilmgandhi	18:6a4db94011d3	1182	/* Set up the baudrate. */
sahilmgandhi	18:6a4db94011d3	1183	if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) {
sahilmgandhi	18:6a4db94011d3	1184	return 1;
sahilmgandhi	18:6a4db94011d3	1185	}
sahilmgandhi	18:6a4db94011d3	1186
sahilmgandhi	18:6a4db94011d3	1187	/* Set LIN master mode. */
sahilmgandhi	18:6a4db94011d3	1188	p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) \|
sahilmgandhi	18:6a4db94011d3	1189	US_MR_USART_MODE_LON;
sahilmgandhi	18:6a4db94011d3	1190
sahilmgandhi	18:6a4db94011d3	1191	usart_enable_rx(p_usart);
sahilmgandhi	18:6a4db94011d3	1192	usart_enable_tx(p_usart);
sahilmgandhi	18:6a4db94011d3	1193
sahilmgandhi	18:6a4db94011d3	1194	return 0;
sahilmgandhi	18:6a4db94011d3	1195	}
sahilmgandhi	18:6a4db94011d3	1196
sahilmgandhi	18:6a4db94011d3	1197	/**
sahilmgandhi	18:6a4db94011d3	1198	* \brief set LON parameter value.
sahilmgandhi	18:6a4db94011d3	1199	*
sahilmgandhi	18:6a4db94011d3	1200	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1201	* \param uc_type 0: LON comm_type = 1 mode,
sahilmgandhi	18:6a4db94011d3	1202	* 1: LON comm_type = 2 mode
sahilmgandhi	18:6a4db94011d3	1203	*/
sahilmgandhi	18:6a4db94011d3	1204	void usart_lon_set_comm_type(Usart *p_usart, uint8_t uc_type)
sahilmgandhi	18:6a4db94011d3	1205	{
sahilmgandhi	18:6a4db94011d3	1206	p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_COMMT) \|
sahilmgandhi	18:6a4db94011d3	1207	(uc_type << 0);
sahilmgandhi	18:6a4db94011d3	1208	}
sahilmgandhi	18:6a4db94011d3	1209
sahilmgandhi	18:6a4db94011d3	1210	/**
sahilmgandhi	18:6a4db94011d3	1211	* \brief Disable LON Collision Detection Feature.
sahilmgandhi	18:6a4db94011d3	1212	*
sahilmgandhi	18:6a4db94011d3	1213	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1214	*/
sahilmgandhi	18:6a4db94011d3	1215	void usart_lon_disable_coll_detection(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1216	{
sahilmgandhi	18:6a4db94011d3	1217	p_usart->US_LONMR \|= US_LONMR_COLDET;
sahilmgandhi	18:6a4db94011d3	1218	}
sahilmgandhi	18:6a4db94011d3	1219
sahilmgandhi	18:6a4db94011d3	1220	/**
sahilmgandhi	18:6a4db94011d3	1221	* \brief Enable LON Collision Detection Feature.
sahilmgandhi	18:6a4db94011d3	1222	*
sahilmgandhi	18:6a4db94011d3	1223	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1224	*/
sahilmgandhi	18:6a4db94011d3	1225	void usart_lon_enable_coll_detection(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1226	{
sahilmgandhi	18:6a4db94011d3	1227	p_usart->US_LONMR &= ~US_LONMR_COLDET;
sahilmgandhi	18:6a4db94011d3	1228	}
sahilmgandhi	18:6a4db94011d3	1229
sahilmgandhi	18:6a4db94011d3	1230	/**
sahilmgandhi	18:6a4db94011d3	1231	* \brief set Terminate Frame upon Collision Notification.
sahilmgandhi	18:6a4db94011d3	1232	*
sahilmgandhi	18:6a4db94011d3	1233	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1234	* \param uc_type 0: Do not terminate the frame in LON comm_type = 1 mode upon collision detection.
sahilmgandhi	18:6a4db94011d3	1235	* 1:Terminate the frame in LON comm_type = 1 mode upon collision detection if possible.
sahilmgandhi	18:6a4db94011d3	1236	*/
sahilmgandhi	18:6a4db94011d3	1237	void usart_lon_set_tcol(Usart *p_usart, uint8_t uc_type)
sahilmgandhi	18:6a4db94011d3	1238	{
sahilmgandhi	18:6a4db94011d3	1239	p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_TCOL) \|
sahilmgandhi	18:6a4db94011d3	1240	(uc_type << 2);
sahilmgandhi	18:6a4db94011d3	1241	}
sahilmgandhi	18:6a4db94011d3	1242
sahilmgandhi	18:6a4db94011d3	1243	/**
sahilmgandhi	18:6a4db94011d3	1244	* \brief set LON Collision Detection on Frame Tail.
sahilmgandhi	18:6a4db94011d3	1245	*
sahilmgandhi	18:6a4db94011d3	1246	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1247	* \param uc_type 0: Detect collisions after CRC has been sent but prior end of transmission in LON comm_type = 1 mode.
sahilmgandhi	18:6a4db94011d3	1248	* 1: Ignore collisions after CRC has been sent but prior end of transmission in LON comm_type = 1 mode.
sahilmgandhi	18:6a4db94011d3	1249	*/
sahilmgandhi	18:6a4db94011d3	1250	void usart_lon_set_cdtail(Usart *p_usart, uint8_t uc_type)
sahilmgandhi	18:6a4db94011d3	1251	{
sahilmgandhi	18:6a4db94011d3	1252	p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_CDTAIL) \|
sahilmgandhi	18:6a4db94011d3	1253	(uc_type << 3);
sahilmgandhi	18:6a4db94011d3	1254	}
sahilmgandhi	18:6a4db94011d3	1255
sahilmgandhi	18:6a4db94011d3	1256	/**
sahilmgandhi	18:6a4db94011d3	1257	* \brief set LON DMA Mode.
sahilmgandhi	18:6a4db94011d3	1258	*
sahilmgandhi	18:6a4db94011d3	1259	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1260	* \param uc_type 0: The LON data length register US_LONDL is not written by the DMA.
sahilmgandhi	18:6a4db94011d3	1261	* 1: The LON data length register US_LONDL is written by the DMA.
sahilmgandhi	18:6a4db94011d3	1262	*/
sahilmgandhi	18:6a4db94011d3	1263	void usart_lon_set_dmam(Usart *p_usart, uint8_t uc_type)
sahilmgandhi	18:6a4db94011d3	1264	{
sahilmgandhi	18:6a4db94011d3	1265	p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_DMAM) \|
sahilmgandhi	18:6a4db94011d3	1266	(uc_type << 4);
sahilmgandhi	18:6a4db94011d3	1267	}
sahilmgandhi	18:6a4db94011d3	1268
sahilmgandhi	18:6a4db94011d3	1269	/**
sahilmgandhi	18:6a4db94011d3	1270	* \brief set LON Beta1 Length after Transmission.
sahilmgandhi	18:6a4db94011d3	1271	*
sahilmgandhi	18:6a4db94011d3	1272	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1273	* \param ul_len 1-16777215: LON beta1 length after transmission in tbit
sahilmgandhi	18:6a4db94011d3	1274	*/
sahilmgandhi	18:6a4db94011d3	1275	void usart_lon_set_beta1_tx_len(Usart *p_usart, uint32_t ul_len)
sahilmgandhi	18:6a4db94011d3	1276	{
sahilmgandhi	18:6a4db94011d3	1277	p_usart->US_LONB1TX = US_LONB1TX_BETA1TX(ul_len);
sahilmgandhi	18:6a4db94011d3	1278	}
sahilmgandhi	18:6a4db94011d3	1279
sahilmgandhi	18:6a4db94011d3	1280	/**
sahilmgandhi	18:6a4db94011d3	1281	* \brief set LON Beta1 Length after Reception.
sahilmgandhi	18:6a4db94011d3	1282	*
sahilmgandhi	18:6a4db94011d3	1283	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1284	* \param ul_len 1-16777215: LON beta1 length after reception in tbit.
sahilmgandhi	18:6a4db94011d3	1285	*/
sahilmgandhi	18:6a4db94011d3	1286	void usart_lon_set_beta1_rx_len(Usart *p_usart, uint32_t ul_len)
sahilmgandhi	18:6a4db94011d3	1287	{
sahilmgandhi	18:6a4db94011d3	1288	p_usart->US_LONB1RX = US_LONB1RX_BETA1RX(ul_len);
sahilmgandhi	18:6a4db94011d3	1289	}
sahilmgandhi	18:6a4db94011d3	1290
sahilmgandhi	18:6a4db94011d3	1291	/**
sahilmgandhi	18:6a4db94011d3	1292	* \brief set LON Priority.
sahilmgandhi	18:6a4db94011d3	1293	*
sahilmgandhi	18:6a4db94011d3	1294	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1295	* \param uc_psnb 0 -127: LON Priority Slot Number.
sahilmgandhi	18:6a4db94011d3	1296	* \param uc_nps 0 -127: LON Node Priority Slot.
sahilmgandhi	18:6a4db94011d3	1297	*/
sahilmgandhi	18:6a4db94011d3	1298	void usart_lon_set_priority(Usart *p_usart, uint8_t uc_psnb, uint8_t uc_nps)
sahilmgandhi	18:6a4db94011d3	1299	{
sahilmgandhi	18:6a4db94011d3	1300	p_usart->US_LONPRIO = US_LONPRIO_PSNB(uc_psnb) \| US_LONPRIO_NPS(uc_nps);
sahilmgandhi	18:6a4db94011d3	1301	}
sahilmgandhi	18:6a4db94011d3	1302
sahilmgandhi	18:6a4db94011d3	1303	/**
sahilmgandhi	18:6a4db94011d3	1304	* \brief set LON Indeterminate Time after Transmission.
sahilmgandhi	18:6a4db94011d3	1305	*
sahilmgandhi	18:6a4db94011d3	1306	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1307	* \param ul_time 1-16777215: LON Indeterminate Time after Transmission (comm_type = 1 mode only).
sahilmgandhi	18:6a4db94011d3	1308	*/
sahilmgandhi	18:6a4db94011d3	1309	void usart_lon_set_tx_idt(Usart *p_usart, uint32_t ul_time)
sahilmgandhi	18:6a4db94011d3	1310	{
sahilmgandhi	18:6a4db94011d3	1311	p_usart->US_IDTTX = US_IDTTX_IDTTX(ul_time);
sahilmgandhi	18:6a4db94011d3	1312	}
sahilmgandhi	18:6a4db94011d3	1313
sahilmgandhi	18:6a4db94011d3	1314	/**
sahilmgandhi	18:6a4db94011d3	1315	* \brief set LON Indeterminate Time after Reception.
sahilmgandhi	18:6a4db94011d3	1316	*
sahilmgandhi	18:6a4db94011d3	1317	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1318	* \param ul_time 1-16777215: LON Indeterminate Time after Reception (comm_type = 1 mode only).
sahilmgandhi	18:6a4db94011d3	1319	*/
sahilmgandhi	18:6a4db94011d3	1320	void usart_lon_set_rx_idt(Usart *p_usart, uint32_t ul_time)
sahilmgandhi	18:6a4db94011d3	1321	{
sahilmgandhi	18:6a4db94011d3	1322	p_usart->US_IDTRX = US_IDTRX_IDTRX(ul_time);
sahilmgandhi	18:6a4db94011d3	1323	}
sahilmgandhi	18:6a4db94011d3	1324
sahilmgandhi	18:6a4db94011d3	1325	/**
sahilmgandhi	18:6a4db94011d3	1326	* \brief set LON Preamble Length.
sahilmgandhi	18:6a4db94011d3	1327	*
sahilmgandhi	18:6a4db94011d3	1328	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1329	* \param ul_len 1-16383: LON preamble length in tbit(without byte-sync).
sahilmgandhi	18:6a4db94011d3	1330	*/
sahilmgandhi	18:6a4db94011d3	1331	void usart_lon_set_pre_len(Usart *p_usart, uint32_t ul_len)
sahilmgandhi	18:6a4db94011d3	1332	{
sahilmgandhi	18:6a4db94011d3	1333	p_usart->US_LONPR = US_LONPR_LONPL(ul_len);
sahilmgandhi	18:6a4db94011d3	1334	}
sahilmgandhi	18:6a4db94011d3	1335
sahilmgandhi	18:6a4db94011d3	1336	/**
sahilmgandhi	18:6a4db94011d3	1337	* \brief set LON Data Length.
sahilmgandhi	18:6a4db94011d3	1338	*
sahilmgandhi	18:6a4db94011d3	1339	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1340	* \param uc_len 0-255: LON data length is LONDL+1 bytes.
sahilmgandhi	18:6a4db94011d3	1341	*/
sahilmgandhi	18:6a4db94011d3	1342	void usart_lon_set_data_len(Usart *p_usart, uint8_t uc_len)
sahilmgandhi	18:6a4db94011d3	1343	{
sahilmgandhi	18:6a4db94011d3	1344	p_usart->US_LONDL = US_LONDL_LONDL(uc_len);
sahilmgandhi	18:6a4db94011d3	1345	}
sahilmgandhi	18:6a4db94011d3	1346
sahilmgandhi	18:6a4db94011d3	1347	/**
sahilmgandhi	18:6a4db94011d3	1348	* \brief set LON Priority.
sahilmgandhi	18:6a4db94011d3	1349	*
sahilmgandhi	18:6a4db94011d3	1350	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1351	* \param uc_bli LON Backlog Increment.
sahilmgandhi	18:6a4db94011d3	1352	* \param uc_altp LON Alternate Path Bit.
sahilmgandhi	18:6a4db94011d3	1353	* \param uc_pb LON Priority Bit.
sahilmgandhi	18:6a4db94011d3	1354	*/
sahilmgandhi	18:6a4db94011d3	1355	void usart_lon_set_l2hdr(Usart *p_usart, uint8_t uc_bli, uint8_t uc_altp, uint8_t uc_pb)
sahilmgandhi	18:6a4db94011d3	1356	{
sahilmgandhi	18:6a4db94011d3	1357	p_usart->US_LONL2HDR = US_LONL2HDR_BLI(uc_bli) \| (uc_altp << 6) \| (uc_pb << 7);
sahilmgandhi	18:6a4db94011d3	1358	}
sahilmgandhi	18:6a4db94011d3	1359
sahilmgandhi	18:6a4db94011d3	1360	/**
sahilmgandhi	18:6a4db94011d3	1361	* \brief Check if LON Transmission End.
sahilmgandhi	18:6a4db94011d3	1362	*
sahilmgandhi	18:6a4db94011d3	1363	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1364	*
sahilmgandhi	18:6a4db94011d3	1365	* \retval 1 At least one transmission has been performed since the last RSTSTA.
sahilmgandhi	18:6a4db94011d3	1366	* \retval 0 Transmission on going or no transmission occurred since the last RSTSTA.
sahilmgandhi	18:6a4db94011d3	1367	*/
sahilmgandhi	18:6a4db94011d3	1368	uint32_t usart_lon_is_tx_end(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1369	{
sahilmgandhi	18:6a4db94011d3	1370	return (p_usart->US_CSR & US_CSR_LTXD) > 0;
sahilmgandhi	18:6a4db94011d3	1371	}
sahilmgandhi	18:6a4db94011d3	1372
sahilmgandhi	18:6a4db94011d3	1373	/**
sahilmgandhi	18:6a4db94011d3	1374	* \brief Check if LON Reception End.
sahilmgandhi	18:6a4db94011d3	1375	*
sahilmgandhi	18:6a4db94011d3	1376	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1377	*
sahilmgandhi	18:6a4db94011d3	1378	* \retval 1 At least one Reception has been performed since the last RSTSTA.
sahilmgandhi	18:6a4db94011d3	1379	* \retval 0 Reception on going or no Reception occurred since the last RSTSTA.
sahilmgandhi	18:6a4db94011d3	1380	*/
sahilmgandhi	18:6a4db94011d3	1381	uint32_t usart_lon_is_rx_end(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1382	{
sahilmgandhi	18:6a4db94011d3	1383	return (p_usart->US_CSR & US_CSR_LRXD) > 0;
sahilmgandhi	18:6a4db94011d3	1384	}
sahilmgandhi	18:6a4db94011d3	1385	#endif
sahilmgandhi	18:6a4db94011d3	1386
sahilmgandhi	18:6a4db94011d3	1387	/**
sahilmgandhi	18:6a4db94011d3	1388	* \brief Enable USART transmitter.
sahilmgandhi	18:6a4db94011d3	1389	*
sahilmgandhi	18:6a4db94011d3	1390	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1391	*/
sahilmgandhi	18:6a4db94011d3	1392	void usart_enable_tx(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1393	{
sahilmgandhi	18:6a4db94011d3	1394	p_usart->US_CR = US_CR_TXEN;
sahilmgandhi	18:6a4db94011d3	1395	}
sahilmgandhi	18:6a4db94011d3	1396
sahilmgandhi	18:6a4db94011d3	1397	/**
sahilmgandhi	18:6a4db94011d3	1398	* \brief Disable USART transmitter.
sahilmgandhi	18:6a4db94011d3	1399	*
sahilmgandhi	18:6a4db94011d3	1400	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1401	*/
sahilmgandhi	18:6a4db94011d3	1402	void usart_disable_tx(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1403	{
sahilmgandhi	18:6a4db94011d3	1404	p_usart->US_CR = US_CR_TXDIS;
sahilmgandhi	18:6a4db94011d3	1405	}
sahilmgandhi	18:6a4db94011d3	1406
sahilmgandhi	18:6a4db94011d3	1407	/**
sahilmgandhi	18:6a4db94011d3	1408	* \brief Immediately stop and disable USART transmitter.
sahilmgandhi	18:6a4db94011d3	1409	*
sahilmgandhi	18:6a4db94011d3	1410	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1411	*/
sahilmgandhi	18:6a4db94011d3	1412	void usart_reset_tx(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1413	{
sahilmgandhi	18:6a4db94011d3	1414	/* Reset transmitter */
sahilmgandhi	18:6a4db94011d3	1415	p_usart->US_CR = US_CR_RSTTX \| US_CR_TXDIS;
sahilmgandhi	18:6a4db94011d3	1416	}
sahilmgandhi	18:6a4db94011d3	1417
sahilmgandhi	18:6a4db94011d3	1418	/**
sahilmgandhi	18:6a4db94011d3	1419	* \brief Configure the transmit timeguard register.
sahilmgandhi	18:6a4db94011d3	1420	*
sahilmgandhi	18:6a4db94011d3	1421	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1422	* \param timeguard The value of transmit timeguard.
sahilmgandhi	18:6a4db94011d3	1423	*/
sahilmgandhi	18:6a4db94011d3	1424	void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard)
sahilmgandhi	18:6a4db94011d3	1425	{
sahilmgandhi	18:6a4db94011d3	1426	p_usart->US_TTGR = timeguard;
sahilmgandhi	18:6a4db94011d3	1427	}
sahilmgandhi	18:6a4db94011d3	1428
sahilmgandhi	18:6a4db94011d3	1429	/**
sahilmgandhi	18:6a4db94011d3	1430	* \brief Enable USART receiver.
sahilmgandhi	18:6a4db94011d3	1431	*
sahilmgandhi	18:6a4db94011d3	1432	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1433	*/
sahilmgandhi	18:6a4db94011d3	1434	void usart_enable_rx(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1435	{
sahilmgandhi	18:6a4db94011d3	1436	p_usart->US_CR = US_CR_RXEN;
sahilmgandhi	18:6a4db94011d3	1437	}
sahilmgandhi	18:6a4db94011d3	1438
sahilmgandhi	18:6a4db94011d3	1439	/**
sahilmgandhi	18:6a4db94011d3	1440	* \brief Disable USART receiver.
sahilmgandhi	18:6a4db94011d3	1441	*
sahilmgandhi	18:6a4db94011d3	1442	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1443	*/
sahilmgandhi	18:6a4db94011d3	1444	void usart_disable_rx(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1445	{
sahilmgandhi	18:6a4db94011d3	1446	p_usart->US_CR = US_CR_RXDIS;
sahilmgandhi	18:6a4db94011d3	1447	}
sahilmgandhi	18:6a4db94011d3	1448
sahilmgandhi	18:6a4db94011d3	1449	/**
sahilmgandhi	18:6a4db94011d3	1450	* \brief Immediately stop and disable USART receiver.
sahilmgandhi	18:6a4db94011d3	1451	*
sahilmgandhi	18:6a4db94011d3	1452	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1453	*/
sahilmgandhi	18:6a4db94011d3	1454	void usart_reset_rx(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1455	{
sahilmgandhi	18:6a4db94011d3	1456	/* Reset Receiver */
sahilmgandhi	18:6a4db94011d3	1457	p_usart->US_CR = US_CR_RSTRX \| US_CR_RXDIS;
sahilmgandhi	18:6a4db94011d3	1458	}
sahilmgandhi	18:6a4db94011d3	1459
sahilmgandhi	18:6a4db94011d3	1460	/**
sahilmgandhi	18:6a4db94011d3	1461	* \brief Configure the receive timeout register.
sahilmgandhi	18:6a4db94011d3	1462	*
sahilmgandhi	18:6a4db94011d3	1463	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1464	* \param timeout The value of receive timeout.
sahilmgandhi	18:6a4db94011d3	1465	*/
sahilmgandhi	18:6a4db94011d3	1466	void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout)
sahilmgandhi	18:6a4db94011d3	1467	{
sahilmgandhi	18:6a4db94011d3	1468	p_usart->US_RTOR = timeout;
sahilmgandhi	18:6a4db94011d3	1469	}
sahilmgandhi	18:6a4db94011d3	1470
sahilmgandhi	18:6a4db94011d3	1471	/**
sahilmgandhi	18:6a4db94011d3	1472	* \brief Enable USART interrupts.
sahilmgandhi	18:6a4db94011d3	1473	*
sahilmgandhi	18:6a4db94011d3	1474	* \param p_usart Pointer to a USART peripheral.
sahilmgandhi	18:6a4db94011d3	1475	* \param ul_sources Interrupt sources bit map.
sahilmgandhi	18:6a4db94011d3	1476	*/
sahilmgandhi	18:6a4db94011d3	1477	void usart_enable_interrupt(Usart *p_usart, uint32_t ul_sources)
sahilmgandhi	18:6a4db94011d3	1478	{
sahilmgandhi	18:6a4db94011d3	1479	p_usart->US_IER = ul_sources;
sahilmgandhi	18:6a4db94011d3	1480	}
sahilmgandhi	18:6a4db94011d3	1481
sahilmgandhi	18:6a4db94011d3	1482	/**
sahilmgandhi	18:6a4db94011d3	1483	* \brief Disable USART interrupts.
sahilmgandhi	18:6a4db94011d3	1484	*
sahilmgandhi	18:6a4db94011d3	1485	* \param p_usart Pointer to a USART peripheral.
sahilmgandhi	18:6a4db94011d3	1486	* \param ul_sources Interrupt sources bit map.
sahilmgandhi	18:6a4db94011d3	1487	*/
sahilmgandhi	18:6a4db94011d3	1488	void usart_disable_interrupt(Usart *p_usart, uint32_t ul_sources)
sahilmgandhi	18:6a4db94011d3	1489	{
sahilmgandhi	18:6a4db94011d3	1490	p_usart->US_IDR = ul_sources;
sahilmgandhi	18:6a4db94011d3	1491	}
sahilmgandhi	18:6a4db94011d3	1492
sahilmgandhi	18:6a4db94011d3	1493	/**
sahilmgandhi	18:6a4db94011d3	1494	* \brief Read USART interrupt mask.
sahilmgandhi	18:6a4db94011d3	1495	*
sahilmgandhi	18:6a4db94011d3	1496	* \param p_usart Pointer to a USART peripheral.
sahilmgandhi	18:6a4db94011d3	1497	*
sahilmgandhi	18:6a4db94011d3	1498	* \return The interrupt mask value.
sahilmgandhi	18:6a4db94011d3	1499	*/
sahilmgandhi	18:6a4db94011d3	1500	uint32_t usart_get_interrupt_mask(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1501	{
sahilmgandhi	18:6a4db94011d3	1502	return p_usart->US_IMR;
sahilmgandhi	18:6a4db94011d3	1503	}
sahilmgandhi	18:6a4db94011d3	1504
sahilmgandhi	18:6a4db94011d3	1505	/**
sahilmgandhi	18:6a4db94011d3	1506	* \brief Get current status.
sahilmgandhi	18:6a4db94011d3	1507	*
sahilmgandhi	18:6a4db94011d3	1508	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1509	*
sahilmgandhi	18:6a4db94011d3	1510	* \return The current USART status.
sahilmgandhi	18:6a4db94011d3	1511	*/
sahilmgandhi	18:6a4db94011d3	1512	uint32_t usart_get_status(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1513	{
sahilmgandhi	18:6a4db94011d3	1514	return p_usart->US_CSR;
sahilmgandhi	18:6a4db94011d3	1515	}
sahilmgandhi	18:6a4db94011d3	1516
sahilmgandhi	18:6a4db94011d3	1517	/**
sahilmgandhi	18:6a4db94011d3	1518	* \brief Reset status bits (PARE, OVER, MANERR, UNRE and PXBRK in US_CSR).
sahilmgandhi	18:6a4db94011d3	1519	*
sahilmgandhi	18:6a4db94011d3	1520	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1521	*/
sahilmgandhi	18:6a4db94011d3	1522	void usart_reset_status(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1523	{
sahilmgandhi	18:6a4db94011d3	1524	p_usart->US_CR = US_CR_RSTSTA;
sahilmgandhi	18:6a4db94011d3	1525	}
sahilmgandhi	18:6a4db94011d3	1526
sahilmgandhi	18:6a4db94011d3	1527	/**
sahilmgandhi	18:6a4db94011d3	1528	* \brief Start transmission of a break.
sahilmgandhi	18:6a4db94011d3	1529	*
sahilmgandhi	18:6a4db94011d3	1530	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1531	*/
sahilmgandhi	18:6a4db94011d3	1532	void usart_start_tx_break(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1533	{
sahilmgandhi	18:6a4db94011d3	1534	p_usart->US_CR = US_CR_STTBRK;
sahilmgandhi	18:6a4db94011d3	1535	}
sahilmgandhi	18:6a4db94011d3	1536
sahilmgandhi	18:6a4db94011d3	1537	/**
sahilmgandhi	18:6a4db94011d3	1538	* \brief Stop transmission of a break.
sahilmgandhi	18:6a4db94011d3	1539	*
sahilmgandhi	18:6a4db94011d3	1540	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1541	*/
sahilmgandhi	18:6a4db94011d3	1542	void usart_stop_tx_break(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1543	{
sahilmgandhi	18:6a4db94011d3	1544	p_usart->US_CR = US_CR_STPBRK;
sahilmgandhi	18:6a4db94011d3	1545	}
sahilmgandhi	18:6a4db94011d3	1546
sahilmgandhi	18:6a4db94011d3	1547	/**
sahilmgandhi	18:6a4db94011d3	1548	* \brief Start waiting for a character before clocking the timeout count.
sahilmgandhi	18:6a4db94011d3	1549	* Reset the status bit TIMEOUT in US_CSR.
sahilmgandhi	18:6a4db94011d3	1550	*
sahilmgandhi	18:6a4db94011d3	1551	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1552	*/
sahilmgandhi	18:6a4db94011d3	1553	void usart_start_rx_timeout(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1554	{
sahilmgandhi	18:6a4db94011d3	1555	p_usart->US_CR = US_CR_STTTO;
sahilmgandhi	18:6a4db94011d3	1556	}
sahilmgandhi	18:6a4db94011d3	1557
sahilmgandhi	18:6a4db94011d3	1558	/**
sahilmgandhi	18:6a4db94011d3	1559	* \brief In Multidrop mode only, the next character written to the US_THR
sahilmgandhi	18:6a4db94011d3	1560	* is sent with the address bit set.
sahilmgandhi	18:6a4db94011d3	1561	*
sahilmgandhi	18:6a4db94011d3	1562	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1563	* \param ul_addr The address to be sent out.
sahilmgandhi	18:6a4db94011d3	1564	*
sahilmgandhi	18:6a4db94011d3	1565	* \retval 0 on success.
sahilmgandhi	18:6a4db94011d3	1566	* \retval 1 on failure.
sahilmgandhi	18:6a4db94011d3	1567	*/
sahilmgandhi	18:6a4db94011d3	1568	uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr)
sahilmgandhi	18:6a4db94011d3	1569	{
sahilmgandhi	18:6a4db94011d3	1570	if ((p_usart->US_MR & US_MR_PAR_MULTIDROP) != US_MR_PAR_MULTIDROP) {
sahilmgandhi	18:6a4db94011d3	1571	return 1;
sahilmgandhi	18:6a4db94011d3	1572	}
sahilmgandhi	18:6a4db94011d3	1573
sahilmgandhi	18:6a4db94011d3	1574	p_usart->US_CR = US_CR_SENDA;
sahilmgandhi	18:6a4db94011d3	1575
sahilmgandhi	18:6a4db94011d3	1576	if (usart_write(p_usart, ul_addr)) {
sahilmgandhi	18:6a4db94011d3	1577	return 1;
sahilmgandhi	18:6a4db94011d3	1578	} else {
sahilmgandhi	18:6a4db94011d3	1579	return 0;
sahilmgandhi	18:6a4db94011d3	1580	}
sahilmgandhi	18:6a4db94011d3	1581	}
sahilmgandhi	18:6a4db94011d3	1582
sahilmgandhi	18:6a4db94011d3	1583	/**
sahilmgandhi	18:6a4db94011d3	1584	* \brief Restart the receive timeout.
sahilmgandhi	18:6a4db94011d3	1585	*
sahilmgandhi	18:6a4db94011d3	1586	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1587	*/
sahilmgandhi	18:6a4db94011d3	1588	void usart_restart_rx_timeout(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1589	{
sahilmgandhi	18:6a4db94011d3	1590	p_usart->US_CR = US_CR_RETTO;
sahilmgandhi	18:6a4db94011d3	1591	}
sahilmgandhi	18:6a4db94011d3	1592
sahilmgandhi	18:6a4db94011d3	1593	#if (SAM3S \|\| SAM4S \|\| SAM3U \|\| SAM4L \|\| SAM4E)
sahilmgandhi	18:6a4db94011d3	1594
sahilmgandhi	18:6a4db94011d3	1595	/**
sahilmgandhi	18:6a4db94011d3	1596	* \brief Drive the pin DTR to 0.
sahilmgandhi	18:6a4db94011d3	1597	*
sahilmgandhi	18:6a4db94011d3	1598	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1599	*/
sahilmgandhi	18:6a4db94011d3	1600	void usart_drive_DTR_pin_low(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1601	{
sahilmgandhi	18:6a4db94011d3	1602	p_usart->US_CR = US_CR_DTREN;
sahilmgandhi	18:6a4db94011d3	1603	}
sahilmgandhi	18:6a4db94011d3	1604
sahilmgandhi	18:6a4db94011d3	1605	/**
sahilmgandhi	18:6a4db94011d3	1606	* \brief Drive the pin DTR to 1.
sahilmgandhi	18:6a4db94011d3	1607	*
sahilmgandhi	18:6a4db94011d3	1608	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1609	*/
sahilmgandhi	18:6a4db94011d3	1610	void usart_drive_DTR_pin_high(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1611	{
sahilmgandhi	18:6a4db94011d3	1612	p_usart->US_CR = US_CR_DTRDIS;
sahilmgandhi	18:6a4db94011d3	1613	}
sahilmgandhi	18:6a4db94011d3	1614
sahilmgandhi	18:6a4db94011d3	1615	#endif
sahilmgandhi	18:6a4db94011d3	1616
sahilmgandhi	18:6a4db94011d3	1617	/**
sahilmgandhi	18:6a4db94011d3	1618	* \brief Drive the pin RTS to 0.
sahilmgandhi	18:6a4db94011d3	1619	*
sahilmgandhi	18:6a4db94011d3	1620	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1621	*/
sahilmgandhi	18:6a4db94011d3	1622	void usart_drive_RTS_pin_low(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1623	{
sahilmgandhi	18:6a4db94011d3	1624	p_usart->US_CR = US_CR_RTSEN;
sahilmgandhi	18:6a4db94011d3	1625	}
sahilmgandhi	18:6a4db94011d3	1626
sahilmgandhi	18:6a4db94011d3	1627	/**
sahilmgandhi	18:6a4db94011d3	1628	* \brief Drive the pin RTS to 1.
sahilmgandhi	18:6a4db94011d3	1629	*
sahilmgandhi	18:6a4db94011d3	1630	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1631	*/
sahilmgandhi	18:6a4db94011d3	1632	void usart_drive_RTS_pin_high(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1633	{
sahilmgandhi	18:6a4db94011d3	1634	p_usart->US_CR = US_CR_RTSDIS;
sahilmgandhi	18:6a4db94011d3	1635	}
sahilmgandhi	18:6a4db94011d3	1636
sahilmgandhi	18:6a4db94011d3	1637	/**
sahilmgandhi	18:6a4db94011d3	1638	* \brief Drive the slave select line NSS (RTS pin) to 0 in SPI master mode.
sahilmgandhi	18:6a4db94011d3	1639	*
sahilmgandhi	18:6a4db94011d3	1640	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1641	*/
sahilmgandhi	18:6a4db94011d3	1642	void usart_spi_force_chip_select(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1643	{
sahilmgandhi	18:6a4db94011d3	1644	p_usart->US_CR = US_CR_FCS;
sahilmgandhi	18:6a4db94011d3	1645	}
sahilmgandhi	18:6a4db94011d3	1646
sahilmgandhi	18:6a4db94011d3	1647	/**
sahilmgandhi	18:6a4db94011d3	1648	* \brief Drive the slave select line NSS (RTS pin) to 1 in SPI master mode.
sahilmgandhi	18:6a4db94011d3	1649	*
sahilmgandhi	18:6a4db94011d3	1650	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1651	*/
sahilmgandhi	18:6a4db94011d3	1652	void usart_spi_release_chip_select(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1653	{
sahilmgandhi	18:6a4db94011d3	1654	p_usart->US_CR = US_CR_RCS;
sahilmgandhi	18:6a4db94011d3	1655	}
sahilmgandhi	18:6a4db94011d3	1656
sahilmgandhi	18:6a4db94011d3	1657	/**
sahilmgandhi	18:6a4db94011d3	1658	* \brief Check if Transmit is Ready.
sahilmgandhi	18:6a4db94011d3	1659	* Check if data have been loaded in USART_THR and are waiting to be loaded
sahilmgandhi	18:6a4db94011d3	1660	* into the Transmit Shift Register (TSR).
sahilmgandhi	18:6a4db94011d3	1661	*
sahilmgandhi	18:6a4db94011d3	1662	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1663	*
sahilmgandhi	18:6a4db94011d3	1664	* \retval 1 No data is in the Transmit Holding Register.
sahilmgandhi	18:6a4db94011d3	1665	* \retval 0 There is data in the Transmit Holding Register.
sahilmgandhi	18:6a4db94011d3	1666	*/
sahilmgandhi	18:6a4db94011d3	1667	uint32_t usart_is_tx_ready(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1668	{
sahilmgandhi	18:6a4db94011d3	1669	return (p_usart->US_CSR & US_CSR_TXRDY) > 0;
sahilmgandhi	18:6a4db94011d3	1670	}
sahilmgandhi	18:6a4db94011d3	1671
sahilmgandhi	18:6a4db94011d3	1672	/**
sahilmgandhi	18:6a4db94011d3	1673	* \brief Check if Transmit Holding Register is empty.
sahilmgandhi	18:6a4db94011d3	1674	* Check if the last data written in USART_THR have been loaded in TSR and the
sahilmgandhi	18:6a4db94011d3	1675	* last data loaded in TSR have been transmitted.
sahilmgandhi	18:6a4db94011d3	1676	*
sahilmgandhi	18:6a4db94011d3	1677	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1678	*
sahilmgandhi	18:6a4db94011d3	1679	* \retval 1 Transmitter is empty.
sahilmgandhi	18:6a4db94011d3	1680	* \retval 0 Transmitter is not empty.
sahilmgandhi	18:6a4db94011d3	1681	*/
sahilmgandhi	18:6a4db94011d3	1682	uint32_t usart_is_tx_empty(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1683	{
sahilmgandhi	18:6a4db94011d3	1684	return (p_usart->US_CSR & US_CSR_TXEMPTY) > 0;
sahilmgandhi	18:6a4db94011d3	1685	}
sahilmgandhi	18:6a4db94011d3	1686
sahilmgandhi	18:6a4db94011d3	1687	/**
sahilmgandhi	18:6a4db94011d3	1688	* \brief Check if the received data are ready.
sahilmgandhi	18:6a4db94011d3	1689	* Check if Data have been received and loaded into USART_RHR.
sahilmgandhi	18:6a4db94011d3	1690	*
sahilmgandhi	18:6a4db94011d3	1691	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1692	*
sahilmgandhi	18:6a4db94011d3	1693	* \retval 1 Some data has been received.
sahilmgandhi	18:6a4db94011d3	1694	* \retval 0 No data has been received.
sahilmgandhi	18:6a4db94011d3	1695	*/
sahilmgandhi	18:6a4db94011d3	1696	uint32_t usart_is_rx_ready(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1697	{
sahilmgandhi	18:6a4db94011d3	1698	return (p_usart->US_CSR & US_CSR_RXRDY) > 0;
sahilmgandhi	18:6a4db94011d3	1699	}
sahilmgandhi	18:6a4db94011d3	1700
sahilmgandhi	18:6a4db94011d3	1701	/**
sahilmgandhi	18:6a4db94011d3	1702	* \brief Write to USART Transmit Holding Register.
sahilmgandhi	18:6a4db94011d3	1703	*
sahilmgandhi	18:6a4db94011d3	1704	* \note Before writing user should check if tx is ready (or empty).
sahilmgandhi	18:6a4db94011d3	1705	*
sahilmgandhi	18:6a4db94011d3	1706	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1707	* \param c Data to be sent.
sahilmgandhi	18:6a4db94011d3	1708	*
sahilmgandhi	18:6a4db94011d3	1709	* \retval 0 on success.
sahilmgandhi	18:6a4db94011d3	1710	* \retval 1 on failure.
sahilmgandhi	18:6a4db94011d3	1711	*/
sahilmgandhi	18:6a4db94011d3	1712	uint32_t usart_write(Usart *p_usart, uint32_t c)
sahilmgandhi	18:6a4db94011d3	1713	{
sahilmgandhi	18:6a4db94011d3	1714	if (!(p_usart->US_CSR & US_CSR_TXRDY)) {
sahilmgandhi	18:6a4db94011d3	1715	return 1;
sahilmgandhi	18:6a4db94011d3	1716	}
sahilmgandhi	18:6a4db94011d3	1717
sahilmgandhi	18:6a4db94011d3	1718	p_usart->US_THR = US_THR_TXCHR(c);
sahilmgandhi	18:6a4db94011d3	1719	return 0;
sahilmgandhi	18:6a4db94011d3	1720	}
sahilmgandhi	18:6a4db94011d3	1721
sahilmgandhi	18:6a4db94011d3	1722	/**
sahilmgandhi	18:6a4db94011d3	1723	* \brief Write to USART Transmit Holding Register.
sahilmgandhi	18:6a4db94011d3	1724	*
sahilmgandhi	18:6a4db94011d3	1725	* \note Before writing user should check if tx is ready (or empty).
sahilmgandhi	18:6a4db94011d3	1726	*
sahilmgandhi	18:6a4db94011d3	1727	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1728	* \param c Data to be sent.
sahilmgandhi	18:6a4db94011d3	1729	*
sahilmgandhi	18:6a4db94011d3	1730	* \retval 0 on success.
sahilmgandhi	18:6a4db94011d3	1731	* \retval 1 on failure.
sahilmgandhi	18:6a4db94011d3	1732	*/
sahilmgandhi	18:6a4db94011d3	1733	uint32_t usart_putchar(Usart *p_usart, uint32_t c)
sahilmgandhi	18:6a4db94011d3	1734	{
sahilmgandhi	18:6a4db94011d3	1735	while (!(p_usart->US_CSR & US_CSR_TXRDY)) {
sahilmgandhi	18:6a4db94011d3	1736	}
sahilmgandhi	18:6a4db94011d3	1737
sahilmgandhi	18:6a4db94011d3	1738	p_usart->US_THR = US_THR_TXCHR(c);
sahilmgandhi	18:6a4db94011d3	1739
sahilmgandhi	18:6a4db94011d3	1740	return 0;
sahilmgandhi	18:6a4db94011d3	1741	}
sahilmgandhi	18:6a4db94011d3	1742
sahilmgandhi	18:6a4db94011d3	1743	/**
sahilmgandhi	18:6a4db94011d3	1744	* \brief Write one-line string through USART.
sahilmgandhi	18:6a4db94011d3	1745	*
sahilmgandhi	18:6a4db94011d3	1746	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1747	* \param string Pointer to one-line string to be sent.
sahilmgandhi	18:6a4db94011d3	1748	*/
sahilmgandhi	18:6a4db94011d3	1749	void usart_write_line(Usart p_usart, const char string)
sahilmgandhi	18:6a4db94011d3	1750	{
sahilmgandhi	18:6a4db94011d3	1751	while (*string != '\0') {
sahilmgandhi	18:6a4db94011d3	1752	usart_putchar(p_usart, *string++);
sahilmgandhi	18:6a4db94011d3	1753	}
sahilmgandhi	18:6a4db94011d3	1754	}
sahilmgandhi	18:6a4db94011d3	1755
sahilmgandhi	18:6a4db94011d3	1756	/**
sahilmgandhi	18:6a4db94011d3	1757	* \brief Read from USART Receive Holding Register.
sahilmgandhi	18:6a4db94011d3	1758	*
sahilmgandhi	18:6a4db94011d3	1759	* \note Before reading user should check if rx is ready.
sahilmgandhi	18:6a4db94011d3	1760	*
sahilmgandhi	18:6a4db94011d3	1761	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1762	* \param c Pointer where the one-byte received data will be stored.
sahilmgandhi	18:6a4db94011d3	1763	*
sahilmgandhi	18:6a4db94011d3	1764	* \retval 0 on success.
sahilmgandhi	18:6a4db94011d3	1765	* \retval 1 if no data is available or errors.
sahilmgandhi	18:6a4db94011d3	1766	*/
sahilmgandhi	18:6a4db94011d3	1767	uint32_t usart_read(Usart p_usart, uint32_t c)
sahilmgandhi	18:6a4db94011d3	1768	{
sahilmgandhi	18:6a4db94011d3	1769	if (!(p_usart->US_CSR & US_CSR_RXRDY)) {
sahilmgandhi	18:6a4db94011d3	1770	return 1;
sahilmgandhi	18:6a4db94011d3	1771	}
sahilmgandhi	18:6a4db94011d3	1772
sahilmgandhi	18:6a4db94011d3	1773	/* Read character */
sahilmgandhi	18:6a4db94011d3	1774	*c = p_usart->US_RHR & US_RHR_RXCHR_Msk;
sahilmgandhi	18:6a4db94011d3	1775
sahilmgandhi	18:6a4db94011d3	1776	return 0;
sahilmgandhi	18:6a4db94011d3	1777	}
sahilmgandhi	18:6a4db94011d3	1778
sahilmgandhi	18:6a4db94011d3	1779	/**
sahilmgandhi	18:6a4db94011d3	1780	* \brief Read from USART Receive Holding Register.
sahilmgandhi	18:6a4db94011d3	1781	* Before reading user should check if rx is ready.
sahilmgandhi	18:6a4db94011d3	1782	*
sahilmgandhi	18:6a4db94011d3	1783	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1784	* \param c Pointer where the one-byte received data will be stored.
sahilmgandhi	18:6a4db94011d3	1785	*
sahilmgandhi	18:6a4db94011d3	1786	* \retval 0 Data has been received.
sahilmgandhi	18:6a4db94011d3	1787	* \retval 1 on failure.
sahilmgandhi	18:6a4db94011d3	1788	*/
sahilmgandhi	18:6a4db94011d3	1789	uint32_t usart_getchar(Usart p_usart, uint32_t c)
sahilmgandhi	18:6a4db94011d3	1790	{
sahilmgandhi	18:6a4db94011d3	1791	/* Wait until it's not empty or timeout has reached. */
sahilmgandhi	18:6a4db94011d3	1792	while (!(p_usart->US_CSR & US_CSR_RXRDY)) {
sahilmgandhi	18:6a4db94011d3	1793	}
sahilmgandhi	18:6a4db94011d3	1794
sahilmgandhi	18:6a4db94011d3	1795	/* Read character */
sahilmgandhi	18:6a4db94011d3	1796	*c = p_usart->US_RHR & US_RHR_RXCHR_Msk;
sahilmgandhi	18:6a4db94011d3	1797
sahilmgandhi	18:6a4db94011d3	1798	return 0;
sahilmgandhi	18:6a4db94011d3	1799	}
sahilmgandhi	18:6a4db94011d3	1800
sahilmgandhi	18:6a4db94011d3	1801	#if (SAM3XA \|\| SAM3U)
sahilmgandhi	18:6a4db94011d3	1802	/**
sahilmgandhi	18:6a4db94011d3	1803	* \brief Get Transmit address for DMA operation.
sahilmgandhi	18:6a4db94011d3	1804	*
sahilmgandhi	18:6a4db94011d3	1805	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1806	*
sahilmgandhi	18:6a4db94011d3	1807	* \return Transmit address for DMA access.
sahilmgandhi	18:6a4db94011d3	1808	*/
sahilmgandhi	18:6a4db94011d3	1809	uint32_t usart_get_tx_access(Usart p_usart)
sahilmgandhi	18:6a4db94011d3	1810	{
sahilmgandhi	18:6a4db94011d3	1811	return (uint32_t *)&(p_usart->US_THR);
sahilmgandhi	18:6a4db94011d3	1812	}
sahilmgandhi	18:6a4db94011d3	1813
sahilmgandhi	18:6a4db94011d3	1814	/**
sahilmgandhi	18:6a4db94011d3	1815	* \brief Get Receive address for DMA operation.
sahilmgandhi	18:6a4db94011d3	1816	*
sahilmgandhi	18:6a4db94011d3	1817	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1818	*
sahilmgandhi	18:6a4db94011d3	1819	* \return Receive address for DMA access.
sahilmgandhi	18:6a4db94011d3	1820	*/
sahilmgandhi	18:6a4db94011d3	1821	uint32_t usart_get_rx_access(Usart p_usart)
sahilmgandhi	18:6a4db94011d3	1822	{
sahilmgandhi	18:6a4db94011d3	1823	return (uint32_t *)&(p_usart->US_RHR);
sahilmgandhi	18:6a4db94011d3	1824	}
sahilmgandhi	18:6a4db94011d3	1825	#endif
sahilmgandhi	18:6a4db94011d3	1826
sahilmgandhi	18:6a4db94011d3	1827	#if (!SAM4L && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70)
sahilmgandhi	18:6a4db94011d3	1828	/**
sahilmgandhi	18:6a4db94011d3	1829	* \brief Get USART PDC base address.
sahilmgandhi	18:6a4db94011d3	1830	*
sahilmgandhi	18:6a4db94011d3	1831	* \param p_usart Pointer to a UART instance.
sahilmgandhi	18:6a4db94011d3	1832	*
sahilmgandhi	18:6a4db94011d3	1833	* \return USART PDC registers base for PDC driver to access.
sahilmgandhi	18:6a4db94011d3	1834	*/
sahilmgandhi	18:6a4db94011d3	1835	Pdc usart_get_pdc_base(Usart p_usart)
sahilmgandhi	18:6a4db94011d3	1836	{
sahilmgandhi	18:6a4db94011d3	1837	Pdc *p_pdc_base;
sahilmgandhi	18:6a4db94011d3	1838
sahilmgandhi	18:6a4db94011d3	1839	p_pdc_base = (Pdc *)NULL;
sahilmgandhi	18:6a4db94011d3	1840
sahilmgandhi	18:6a4db94011d3	1841	#ifdef PDC_USART
sahilmgandhi	18:6a4db94011d3	1842	if (p_usart == USART) {
sahilmgandhi	18:6a4db94011d3	1843	p_pdc_base = PDC_USART;
sahilmgandhi	18:6a4db94011d3	1844	return p_pdc_base;
sahilmgandhi	18:6a4db94011d3	1845	}
sahilmgandhi	18:6a4db94011d3	1846	#endif
sahilmgandhi	18:6a4db94011d3	1847	#ifdef PDC_USART0
sahilmgandhi	18:6a4db94011d3	1848	if (p_usart == USART0) {
sahilmgandhi	18:6a4db94011d3	1849	p_pdc_base = PDC_USART0;
sahilmgandhi	18:6a4db94011d3	1850	return p_pdc_base;
sahilmgandhi	18:6a4db94011d3	1851	}
sahilmgandhi	18:6a4db94011d3	1852	#endif
sahilmgandhi	18:6a4db94011d3	1853	#ifdef PDC_USART1
sahilmgandhi	18:6a4db94011d3	1854	else if (p_usart == USART1) {
sahilmgandhi	18:6a4db94011d3	1855	p_pdc_base = PDC_USART1;
sahilmgandhi	18:6a4db94011d3	1856	return p_pdc_base;
sahilmgandhi	18:6a4db94011d3	1857	}
sahilmgandhi	18:6a4db94011d3	1858	#endif
sahilmgandhi	18:6a4db94011d3	1859	#ifdef PDC_USART2
sahilmgandhi	18:6a4db94011d3	1860	else if (p_usart == USART2) {
sahilmgandhi	18:6a4db94011d3	1861	p_pdc_base = PDC_USART2;
sahilmgandhi	18:6a4db94011d3	1862	return p_pdc_base;
sahilmgandhi	18:6a4db94011d3	1863	}
sahilmgandhi	18:6a4db94011d3	1864	#endif
sahilmgandhi	18:6a4db94011d3	1865	#ifdef PDC_USART3
sahilmgandhi	18:6a4db94011d3	1866	else if (p_usart == USART3) {
sahilmgandhi	18:6a4db94011d3	1867	p_pdc_base = PDC_USART3;
sahilmgandhi	18:6a4db94011d3	1868	return p_pdc_base;
sahilmgandhi	18:6a4db94011d3	1869	}
sahilmgandhi	18:6a4db94011d3	1870	#endif
sahilmgandhi	18:6a4db94011d3	1871	#ifdef PDC_USART4
sahilmgandhi	18:6a4db94011d3	1872	else if (p_usart == USART4) {
sahilmgandhi	18:6a4db94011d3	1873	p_pdc_base = PDC_USART4;
sahilmgandhi	18:6a4db94011d3	1874	return p_pdc_base;
sahilmgandhi	18:6a4db94011d3	1875	}
sahilmgandhi	18:6a4db94011d3	1876	#endif
sahilmgandhi	18:6a4db94011d3	1877	#ifdef PDC_USART5
sahilmgandhi	18:6a4db94011d3	1878	else if (p_usart == USART5) {
sahilmgandhi	18:6a4db94011d3	1879	p_pdc_base = PDC_USART5;
sahilmgandhi	18:6a4db94011d3	1880	return p_pdc_base;
sahilmgandhi	18:6a4db94011d3	1881	}
sahilmgandhi	18:6a4db94011d3	1882	#endif
sahilmgandhi	18:6a4db94011d3	1883	#ifdef PDC_USART6
sahilmgandhi	18:6a4db94011d3	1884	else if (p_usart == USART6) {
sahilmgandhi	18:6a4db94011d3	1885	p_pdc_base = PDC_USART6;
sahilmgandhi	18:6a4db94011d3	1886	return p_pdc_base;
sahilmgandhi	18:6a4db94011d3	1887	}
sahilmgandhi	18:6a4db94011d3	1888	#endif
sahilmgandhi	18:6a4db94011d3	1889	#ifdef PDC_USART7
sahilmgandhi	18:6a4db94011d3	1890	else if (p_usart == USART7) {
sahilmgandhi	18:6a4db94011d3	1891	p_pdc_base = PDC_USART7;
sahilmgandhi	18:6a4db94011d3	1892	return p_pdc_base;
sahilmgandhi	18:6a4db94011d3	1893	}
sahilmgandhi	18:6a4db94011d3	1894	#endif
sahilmgandhi	18:6a4db94011d3	1895
sahilmgandhi	18:6a4db94011d3	1896	return p_pdc_base;
sahilmgandhi	18:6a4db94011d3	1897	}
sahilmgandhi	18:6a4db94011d3	1898	#endif
sahilmgandhi	18:6a4db94011d3	1899
sahilmgandhi	18:6a4db94011d3	1900	/**
sahilmgandhi	18:6a4db94011d3	1901	* \brief Enable write protect of USART registers.
sahilmgandhi	18:6a4db94011d3	1902	*
sahilmgandhi	18:6a4db94011d3	1903	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1904	*/
sahilmgandhi	18:6a4db94011d3	1905	void usart_enable_writeprotect(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1906	{
sahilmgandhi	18:6a4db94011d3	1907	p_usart->US_WPMR = US_WPMR_WPEN \| US_WPMR_WPKEY_PASSWD;
sahilmgandhi	18:6a4db94011d3	1908	}
sahilmgandhi	18:6a4db94011d3	1909
sahilmgandhi	18:6a4db94011d3	1910	/**
sahilmgandhi	18:6a4db94011d3	1911	* \brief Disable write protect of USART registers.
sahilmgandhi	18:6a4db94011d3	1912	*
sahilmgandhi	18:6a4db94011d3	1913	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1914	*/
sahilmgandhi	18:6a4db94011d3	1915	void usart_disable_writeprotect(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1916	{
sahilmgandhi	18:6a4db94011d3	1917	p_usart->US_WPMR = US_WPMR_WPKEY_PASSWD;
sahilmgandhi	18:6a4db94011d3	1918	}
sahilmgandhi	18:6a4db94011d3	1919
sahilmgandhi	18:6a4db94011d3	1920	/**
sahilmgandhi	18:6a4db94011d3	1921	* \brief Get write protect status.
sahilmgandhi	18:6a4db94011d3	1922	*
sahilmgandhi	18:6a4db94011d3	1923	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1924	*
sahilmgandhi	18:6a4db94011d3	1925	* \return 0 if no write protect violation occurred, or 16-bit write protect
sahilmgandhi	18:6a4db94011d3	1926	* violation source.
sahilmgandhi	18:6a4db94011d3	1927	*/
sahilmgandhi	18:6a4db94011d3	1928	uint32_t usart_get_writeprotect_status(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	1929	{
sahilmgandhi	18:6a4db94011d3	1930	uint32_t reg_value;
sahilmgandhi	18:6a4db94011d3	1931
sahilmgandhi	18:6a4db94011d3	1932	reg_value = p_usart->US_WPSR;
sahilmgandhi	18:6a4db94011d3	1933	if (reg_value & US_WPSR_WPVS) {
sahilmgandhi	18:6a4db94011d3	1934	return (reg_value & US_WPSR_WPVSRC_Msk) >> US_WPSR_WPVSRC_Pos;
sahilmgandhi	18:6a4db94011d3	1935	} else {
sahilmgandhi	18:6a4db94011d3	1936	return 0;
sahilmgandhi	18:6a4db94011d3	1937	}
sahilmgandhi	18:6a4db94011d3	1938	}
sahilmgandhi	18:6a4db94011d3	1939
sahilmgandhi	18:6a4db94011d3	1940	#if (SAM3S \|\| SAM4S \|\| SAM3U \|\| SAM3XA \|\| SAM4L \|\| SAM4E \|\| SAM4C \|\| SAM4CP \|\| SAM4CM)
sahilmgandhi	18:6a4db94011d3	1941
sahilmgandhi	18:6a4db94011d3	1942	/**
sahilmgandhi	18:6a4db94011d3	1943	* \brief Configure the transmitter preamble length when the Manchester
sahilmgandhi	18:6a4db94011d3	1944	* encode/decode is enabled.
sahilmgandhi	18:6a4db94011d3	1945	*
sahilmgandhi	18:6a4db94011d3	1946	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1947	* \param uc_len The transmitter preamble length, which should be 0 ~ 15.
sahilmgandhi	18:6a4db94011d3	1948	*/
sahilmgandhi	18:6a4db94011d3	1949	void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len)
sahilmgandhi	18:6a4db94011d3	1950	{
sahilmgandhi	18:6a4db94011d3	1951	p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PL_Msk) \|
sahilmgandhi	18:6a4db94011d3	1952	US_MAN_TX_PL(uc_len);
sahilmgandhi	18:6a4db94011d3	1953	}
sahilmgandhi	18:6a4db94011d3	1954
sahilmgandhi	18:6a4db94011d3	1955	/**
sahilmgandhi	18:6a4db94011d3	1956	* \brief Configure the transmitter preamble pattern when the Manchester
sahilmgandhi	18:6a4db94011d3	1957	* encode/decode is enabled, which should be 0 ~ 3.
sahilmgandhi	18:6a4db94011d3	1958	*
sahilmgandhi	18:6a4db94011d3	1959	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1960	* \param uc_pattern 0 if the preamble is composed of '1's;
sahilmgandhi	18:6a4db94011d3	1961	* 1 if the preamble is composed of '0's;
sahilmgandhi	18:6a4db94011d3	1962	* 2 if the preamble is composed of '01's;
sahilmgandhi	18:6a4db94011d3	1963	* 3 if the preamble is composed of '10's.
sahilmgandhi	18:6a4db94011d3	1964	*/
sahilmgandhi	18:6a4db94011d3	1965	void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern)
sahilmgandhi	18:6a4db94011d3	1966	{
sahilmgandhi	18:6a4db94011d3	1967	p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PP_Msk) \|
sahilmgandhi	18:6a4db94011d3	1968	(uc_pattern << US_MAN_TX_PP_Pos);
sahilmgandhi	18:6a4db94011d3	1969	}
sahilmgandhi	18:6a4db94011d3	1970
sahilmgandhi	18:6a4db94011d3	1971	/**
sahilmgandhi	18:6a4db94011d3	1972	* \brief Configure the transmitter Manchester polarity when the Manchester
sahilmgandhi	18:6a4db94011d3	1973	* encode/decode is enabled.
sahilmgandhi	18:6a4db94011d3	1974	*
sahilmgandhi	18:6a4db94011d3	1975	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1976	* \param uc_polarity Indicate the transmitter Manchester polarity, which
sahilmgandhi	18:6a4db94011d3	1977	* should be 0 or 1.
sahilmgandhi	18:6a4db94011d3	1978	*/
sahilmgandhi	18:6a4db94011d3	1979	void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity)
sahilmgandhi	18:6a4db94011d3	1980	{
sahilmgandhi	18:6a4db94011d3	1981	p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_MPOL) \|
sahilmgandhi	18:6a4db94011d3	1982	(uc_polarity << 12);
sahilmgandhi	18:6a4db94011d3	1983	}
sahilmgandhi	18:6a4db94011d3	1984
sahilmgandhi	18:6a4db94011d3	1985	/**
sahilmgandhi	18:6a4db94011d3	1986	* \brief Configure the detected receiver preamble length when the Manchester
sahilmgandhi	18:6a4db94011d3	1987	* encode/decode is enabled.
sahilmgandhi	18:6a4db94011d3	1988	*
sahilmgandhi	18:6a4db94011d3	1989	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	1990	* \param uc_len The detected receiver preamble length, which should be 0 ~ 15.
sahilmgandhi	18:6a4db94011d3	1991	*/
sahilmgandhi	18:6a4db94011d3	1992	void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len)
sahilmgandhi	18:6a4db94011d3	1993	{
sahilmgandhi	18:6a4db94011d3	1994	p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PL_Msk) \|
sahilmgandhi	18:6a4db94011d3	1995	US_MAN_RX_PL(uc_len);
sahilmgandhi	18:6a4db94011d3	1996	}
sahilmgandhi	18:6a4db94011d3	1997
sahilmgandhi	18:6a4db94011d3	1998	/**
sahilmgandhi	18:6a4db94011d3	1999	* \brief Configure the detected receiver preamble pattern when the Manchester
sahilmgandhi	18:6a4db94011d3	2000	* encode/decode is enabled, which should be 0 ~ 3.
sahilmgandhi	18:6a4db94011d3	2001	*
sahilmgandhi	18:6a4db94011d3	2002	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	2003	* \param uc_pattern 0 if the preamble is composed of '1's;
sahilmgandhi	18:6a4db94011d3	2004	* 1 if the preamble is composed of '0's;
sahilmgandhi	18:6a4db94011d3	2005	* 2 if the preamble is composed of '01's;
sahilmgandhi	18:6a4db94011d3	2006	* 3 if the preamble is composed of '10's.
sahilmgandhi	18:6a4db94011d3	2007	*/
sahilmgandhi	18:6a4db94011d3	2008	void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern)
sahilmgandhi	18:6a4db94011d3	2009	{
sahilmgandhi	18:6a4db94011d3	2010	p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PP_Msk) \|
sahilmgandhi	18:6a4db94011d3	2011	(uc_pattern << US_MAN_RX_PP_Pos);
sahilmgandhi	18:6a4db94011d3	2012	}
sahilmgandhi	18:6a4db94011d3	2013
sahilmgandhi	18:6a4db94011d3	2014	/**
sahilmgandhi	18:6a4db94011d3	2015	* \brief Configure the receiver Manchester polarity when the Manchester
sahilmgandhi	18:6a4db94011d3	2016	* encode/decode is enabled.
sahilmgandhi	18:6a4db94011d3	2017	*
sahilmgandhi	18:6a4db94011d3	2018	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	2019	* \param uc_polarity Indicate the receiver Manchester polarity, which should
sahilmgandhi	18:6a4db94011d3	2020	* be 0 or 1.
sahilmgandhi	18:6a4db94011d3	2021	*/
sahilmgandhi	18:6a4db94011d3	2022	void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity)
sahilmgandhi	18:6a4db94011d3	2023	{
sahilmgandhi	18:6a4db94011d3	2024	p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_MPOL) \|
sahilmgandhi	18:6a4db94011d3	2025	(uc_polarity << 28);
sahilmgandhi	18:6a4db94011d3	2026	}
sahilmgandhi	18:6a4db94011d3	2027
sahilmgandhi	18:6a4db94011d3	2028	/**
sahilmgandhi	18:6a4db94011d3	2029	* \brief Enable drift compensation.
sahilmgandhi	18:6a4db94011d3	2030	*
sahilmgandhi	18:6a4db94011d3	2031	* \note The 16X clock mode must be enabled.
sahilmgandhi	18:6a4db94011d3	2032	*
sahilmgandhi	18:6a4db94011d3	2033	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	2034	*/
sahilmgandhi	18:6a4db94011d3	2035	void usart_man_enable_drift_compensation(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	2036	{
sahilmgandhi	18:6a4db94011d3	2037	p_usart->US_MAN \|= US_MAN_DRIFT;
sahilmgandhi	18:6a4db94011d3	2038	}
sahilmgandhi	18:6a4db94011d3	2039
sahilmgandhi	18:6a4db94011d3	2040	/**
sahilmgandhi	18:6a4db94011d3	2041	* \brief Disable drift compensation.
sahilmgandhi	18:6a4db94011d3	2042	*
sahilmgandhi	18:6a4db94011d3	2043	* \param p_usart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	2044	*/
sahilmgandhi	18:6a4db94011d3	2045	void usart_man_disable_drift_compensation(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	2046	{
sahilmgandhi	18:6a4db94011d3	2047	p_usart->US_MAN &= ~US_MAN_DRIFT;
sahilmgandhi	18:6a4db94011d3	2048	}
sahilmgandhi	18:6a4db94011d3	2049
sahilmgandhi	18:6a4db94011d3	2050	#endif
sahilmgandhi	18:6a4db94011d3	2051
sahilmgandhi	18:6a4db94011d3	2052	#if SAM4L
sahilmgandhi	18:6a4db94011d3	2053
sahilmgandhi	18:6a4db94011d3	2054	uint32_t usart_get_version(Usart *p_usart)
sahilmgandhi	18:6a4db94011d3	2055	{
sahilmgandhi	18:6a4db94011d3	2056	return p_usart->US_VERSION;
sahilmgandhi	18:6a4db94011d3	2057	}
sahilmgandhi	18:6a4db94011d3	2058
sahilmgandhi	18:6a4db94011d3	2059	#endif
sahilmgandhi	18:6a4db94011d3	2060
sahilmgandhi	18:6a4db94011d3	2061	#if SAMG55
sahilmgandhi	18:6a4db94011d3	2062	/**
sahilmgandhi	18:6a4db94011d3	2063	* \brief Set sleepwalking match mode.
sahilmgandhi	18:6a4db94011d3	2064	*
sahilmgandhi	18:6a4db94011d3	2065	* \param p_uart Pointer to a USART instance.
sahilmgandhi	18:6a4db94011d3	2066	* \param ul_low_value First comparison value for received character.
sahilmgandhi	18:6a4db94011d3	2067	* \param ul_high_value Second comparison value for received character.
sahilmgandhi	18:6a4db94011d3	2068	* \param cmpmode ture for start condition, false for flag only.
sahilmgandhi	18:6a4db94011d3	2069	* \param cmppar ture for parity check, false for no.
sahilmgandhi	18:6a4db94011d3	2070	*/
sahilmgandhi	18:6a4db94011d3	2071	void usart_set_sleepwalking(Usart *p_uart, uint8_t ul_low_value,
sahilmgandhi	18:6a4db94011d3	2072	bool cmpmode, bool cmppar, uint8_t ul_high_value)
sahilmgandhi	18:6a4db94011d3	2073	{
sahilmgandhi	18:6a4db94011d3	2074	Assert(ul_low_value <= ul_high_value);
sahilmgandhi	18:6a4db94011d3	2075
sahilmgandhi	18:6a4db94011d3	2076	uint32_t temp = 0;
sahilmgandhi	18:6a4db94011d3	2077
sahilmgandhi	18:6a4db94011d3	2078	if (cmpmode) {
sahilmgandhi	18:6a4db94011d3	2079	temp \|= US_CMPR_CMPMODE_START_CONDITION;
sahilmgandhi	18:6a4db94011d3	2080	}
sahilmgandhi	18:6a4db94011d3	2081
sahilmgandhi	18:6a4db94011d3	2082	if (cmppar) {
sahilmgandhi	18:6a4db94011d3	2083	temp \|= US_CMPR_CMPPAR;
sahilmgandhi	18:6a4db94011d3	2084	}
sahilmgandhi	18:6a4db94011d3	2085
sahilmgandhi	18:6a4db94011d3	2086	temp \|= US_CMPR_VAL1(ul_low_value);
sahilmgandhi	18:6a4db94011d3	2087
sahilmgandhi	18:6a4db94011d3	2088	temp \|= US_CMPR_VAL2(ul_high_value);
sahilmgandhi	18:6a4db94011d3	2089
sahilmgandhi	18:6a4db94011d3	2090	p_uart->US_CMPR= temp;
sahilmgandhi	18:6a4db94011d3	2091	}
sahilmgandhi	18:6a4db94011d3	2092	#endif
sahilmgandhi	18:6a4db94011d3	2093
sahilmgandhi	18:6a4db94011d3	2094	//@}
sahilmgandhi	18:6a4db94011d3	2095
sahilmgandhi	18:6a4db94011d3	2096	/// @cond 0
sahilmgandhi	18:6a4db94011d3	2097	/INDENT-OFF/
sahilmgandhi	18:6a4db94011d3	2098	#ifdef __cplusplus
sahilmgandhi	18:6a4db94011d3	2099	}
sahilmgandhi	18:6a4db94011d3	2100	#endif
sahilmgandhi	18:6a4db94011d3	2101	/INDENT-ON/
sahilmgandhi	18:6a4db94011d3	2102	/// @endcond

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Type:	Program
Created:	25 Apr 2017
Imports:	29
Forks:	0
Commits:	47
Dependents:	0
Dependencies:	2
Followers:	5

The code in this repository is Apache licensed.

mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/usart/usart.c@46:b156ef445742, 2017-06-03 (annotated)

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