Mouse code for the MacroRat
mbed-dev/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/TOOLCHAIN_GCC_ARM/BEETLE.ld@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /* |
sahilmgandhi | 18:6a4db94011d3 | 2 | * BEETLE CMSIS Library |
sahilmgandhi | 18:6a4db94011d3 | 3 | */ |
sahilmgandhi | 18:6a4db94011d3 | 4 | /* |
sahilmgandhi | 18:6a4db94011d3 | 5 | * Copyright (c) 2009-2016 ARM Limited. All rights reserved. |
sahilmgandhi | 18:6a4db94011d3 | 6 | * |
sahilmgandhi | 18:6a4db94011d3 | 7 | * SPDX-License-Identifier: Apache-2.0 |
sahilmgandhi | 18:6a4db94011d3 | 8 | * |
sahilmgandhi | 18:6a4db94011d3 | 9 | * Licensed under the Apache License, Version 2.0 (the License); you may |
sahilmgandhi | 18:6a4db94011d3 | 10 | * not use this file except in compliance with the License. |
sahilmgandhi | 18:6a4db94011d3 | 11 | * You may obtain a copy of the License at |
sahilmgandhi | 18:6a4db94011d3 | 12 | * |
sahilmgandhi | 18:6a4db94011d3 | 13 | * http://www.apache.org/licenses/LICENSE-2.0 |
sahilmgandhi | 18:6a4db94011d3 | 14 | * |
sahilmgandhi | 18:6a4db94011d3 | 15 | * Unless required by applicable law or agreed to in writing, software |
sahilmgandhi | 18:6a4db94011d3 | 16 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
sahilmgandhi | 18:6a4db94011d3 | 17 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
sahilmgandhi | 18:6a4db94011d3 | 18 | * See the License for the specific language governing permissions and |
sahilmgandhi | 18:6a4db94011d3 | 19 | * limitations under the License. |
sahilmgandhi | 18:6a4db94011d3 | 20 | */ |
sahilmgandhi | 18:6a4db94011d3 | 21 | /* |
sahilmgandhi | 18:6a4db94011d3 | 22 | * This file is derivative of CMSIS V5.00 gcc_arm.ld |
sahilmgandhi | 18:6a4db94011d3 | 23 | */ |
sahilmgandhi | 18:6a4db94011d3 | 24 | /* Linker script for mbed BEETLE SoC */ |
sahilmgandhi | 18:6a4db94011d3 | 25 | |
sahilmgandhi | 18:6a4db94011d3 | 26 | /* Linker script to configure memory regions. */ |
sahilmgandhi | 18:6a4db94011d3 | 27 | MEMORY |
sahilmgandhi | 18:6a4db94011d3 | 28 | { |
sahilmgandhi | 18:6a4db94011d3 | 29 | VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400 |
sahilmgandhi | 18:6a4db94011d3 | 30 | FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00040000 - 0x00000400 |
sahilmgandhi | 18:6a4db94011d3 | 31 | RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 |
sahilmgandhi | 18:6a4db94011d3 | 32 | } |
sahilmgandhi | 18:6a4db94011d3 | 33 | |
sahilmgandhi | 18:6a4db94011d3 | 34 | /* Linker script to place sections and symbol values. Should be used together |
sahilmgandhi | 18:6a4db94011d3 | 35 | * with other linker script that defines memory regions FLASH and RAM. |
sahilmgandhi | 18:6a4db94011d3 | 36 | * It references following symbols, which must be defined in code: |
sahilmgandhi | 18:6a4db94011d3 | 37 | * Reset_Handler : Entry of reset handler |
sahilmgandhi | 18:6a4db94011d3 | 38 | * |
sahilmgandhi | 18:6a4db94011d3 | 39 | * It defines following symbols, which code can use without definition: |
sahilmgandhi | 18:6a4db94011d3 | 40 | * __exidx_start |
sahilmgandhi | 18:6a4db94011d3 | 41 | * __exidx_end |
sahilmgandhi | 18:6a4db94011d3 | 42 | * __etext |
sahilmgandhi | 18:6a4db94011d3 | 43 | * __data_start__ |
sahilmgandhi | 18:6a4db94011d3 | 44 | * __preinit_array_start |
sahilmgandhi | 18:6a4db94011d3 | 45 | * __preinit_array_end |
sahilmgandhi | 18:6a4db94011d3 | 46 | * __init_array_start |
sahilmgandhi | 18:6a4db94011d3 | 47 | * __init_array_end |
sahilmgandhi | 18:6a4db94011d3 | 48 | * __fini_array_start |
sahilmgandhi | 18:6a4db94011d3 | 49 | * __fini_array_end |
sahilmgandhi | 18:6a4db94011d3 | 50 | * __data_end__ |
sahilmgandhi | 18:6a4db94011d3 | 51 | * __bss_start__ |
sahilmgandhi | 18:6a4db94011d3 | 52 | * __bss_end__ |
sahilmgandhi | 18:6a4db94011d3 | 53 | * __end__ |
sahilmgandhi | 18:6a4db94011d3 | 54 | * end |
sahilmgandhi | 18:6a4db94011d3 | 55 | * __HeapLimit |
sahilmgandhi | 18:6a4db94011d3 | 56 | * __StackLimit |
sahilmgandhi | 18:6a4db94011d3 | 57 | * __StackTop |
sahilmgandhi | 18:6a4db94011d3 | 58 | * __stack |
sahilmgandhi | 18:6a4db94011d3 | 59 | */ |
sahilmgandhi | 18:6a4db94011d3 | 60 | ENTRY(Reset_Handler) |
sahilmgandhi | 18:6a4db94011d3 | 61 | |
sahilmgandhi | 18:6a4db94011d3 | 62 | /* Heap 1/4 of ram and stack 1/8 */ |
sahilmgandhi | 18:6a4db94011d3 | 63 | __stack_size__ = 0x4000; |
sahilmgandhi | 18:6a4db94011d3 | 64 | __heap_size__ = 0x8000; |
sahilmgandhi | 18:6a4db94011d3 | 65 | |
sahilmgandhi | 18:6a4db94011d3 | 66 | HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; |
sahilmgandhi | 18:6a4db94011d3 | 67 | STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; |
sahilmgandhi | 18:6a4db94011d3 | 68 | |
sahilmgandhi | 18:6a4db94011d3 | 69 | /* Size of the vector table in SRAM */ |
sahilmgandhi | 18:6a4db94011d3 | 70 | M_VECTOR_RAM_SIZE = 0x140; |
sahilmgandhi | 18:6a4db94011d3 | 71 | |
sahilmgandhi | 18:6a4db94011d3 | 72 | SECTIONS |
sahilmgandhi | 18:6a4db94011d3 | 73 | { |
sahilmgandhi | 18:6a4db94011d3 | 74 | .isr_vector : |
sahilmgandhi | 18:6a4db94011d3 | 75 | { |
sahilmgandhi | 18:6a4db94011d3 | 76 | __vector_table = .; |
sahilmgandhi | 18:6a4db94011d3 | 77 | KEEP(*(.vector_table)) |
sahilmgandhi | 18:6a4db94011d3 | 78 | . = ALIGN(4); |
sahilmgandhi | 18:6a4db94011d3 | 79 | } > VECTORS |
sahilmgandhi | 18:6a4db94011d3 | 80 | |
sahilmgandhi | 18:6a4db94011d3 | 81 | /* Note: The uVisor expects this section at a fixed location, as specified |
sahilmgandhi | 18:6a4db94011d3 | 82 | by the porting process configuration parameter: FLASH_OFFSET. */ |
sahilmgandhi | 18:6a4db94011d3 | 83 | __UVISOR_TEXT_OFFSET = 0x0; |
sahilmgandhi | 18:6a4db94011d3 | 84 | __UVISOR_TEXT_START = ORIGIN(FLASH) + __UVISOR_TEXT_OFFSET; |
sahilmgandhi | 18:6a4db94011d3 | 85 | .text __UVISOR_TEXT_START : |
sahilmgandhi | 18:6a4db94011d3 | 86 | { |
sahilmgandhi | 18:6a4db94011d3 | 87 | /* uVisor code and data */ |
sahilmgandhi | 18:6a4db94011d3 | 88 | . = ALIGN(4); |
sahilmgandhi | 18:6a4db94011d3 | 89 | __uvisor_main_start = .; |
sahilmgandhi | 18:6a4db94011d3 | 90 | *(.uvisor.main) |
sahilmgandhi | 18:6a4db94011d3 | 91 | __uvisor_main_end = .; |
sahilmgandhi | 18:6a4db94011d3 | 92 | |
sahilmgandhi | 18:6a4db94011d3 | 93 | *(.text*) |
sahilmgandhi | 18:6a4db94011d3 | 94 | |
sahilmgandhi | 18:6a4db94011d3 | 95 | KEEP(*(.init)) |
sahilmgandhi | 18:6a4db94011d3 | 96 | KEEP(*(.fini)) |
sahilmgandhi | 18:6a4db94011d3 | 97 | |
sahilmgandhi | 18:6a4db94011d3 | 98 | /* .ctors */ |
sahilmgandhi | 18:6a4db94011d3 | 99 | *crtbegin.o(.ctors) |
sahilmgandhi | 18:6a4db94011d3 | 100 | *crtbegin?.o(.ctors) |
sahilmgandhi | 18:6a4db94011d3 | 101 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) |
sahilmgandhi | 18:6a4db94011d3 | 102 | *(SORT(.ctors.*)) |
sahilmgandhi | 18:6a4db94011d3 | 103 | *(.ctors) |
sahilmgandhi | 18:6a4db94011d3 | 104 | |
sahilmgandhi | 18:6a4db94011d3 | 105 | /* .dtors */ |
sahilmgandhi | 18:6a4db94011d3 | 106 | *crtbegin.o(.dtors) |
sahilmgandhi | 18:6a4db94011d3 | 107 | *crtbegin?.o(.dtors) |
sahilmgandhi | 18:6a4db94011d3 | 108 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) |
sahilmgandhi | 18:6a4db94011d3 | 109 | *(SORT(.dtors.*)) |
sahilmgandhi | 18:6a4db94011d3 | 110 | *(.dtors) |
sahilmgandhi | 18:6a4db94011d3 | 111 | |
sahilmgandhi | 18:6a4db94011d3 | 112 | *(.rodata*) |
sahilmgandhi | 18:6a4db94011d3 | 113 | |
sahilmgandhi | 18:6a4db94011d3 | 114 | KEEP(*(.eh_frame*)) |
sahilmgandhi | 18:6a4db94011d3 | 115 | } > FLASH |
sahilmgandhi | 18:6a4db94011d3 | 116 | |
sahilmgandhi | 18:6a4db94011d3 | 117 | .ARM.extab : |
sahilmgandhi | 18:6a4db94011d3 | 118 | { |
sahilmgandhi | 18:6a4db94011d3 | 119 | *(.ARM.extab* .gnu.linkonce.armextab.*) |
sahilmgandhi | 18:6a4db94011d3 | 120 | } > FLASH |
sahilmgandhi | 18:6a4db94011d3 | 121 | |
sahilmgandhi | 18:6a4db94011d3 | 122 | __exidx_start = .; |
sahilmgandhi | 18:6a4db94011d3 | 123 | .ARM.exidx : |
sahilmgandhi | 18:6a4db94011d3 | 124 | { |
sahilmgandhi | 18:6a4db94011d3 | 125 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) |
sahilmgandhi | 18:6a4db94011d3 | 126 | } > FLASH |
sahilmgandhi | 18:6a4db94011d3 | 127 | __exidx_end = .; |
sahilmgandhi | 18:6a4db94011d3 | 128 | |
sahilmgandhi | 18:6a4db94011d3 | 129 | .cordio : |
sahilmgandhi | 18:6a4db94011d3 | 130 | { |
sahilmgandhi | 18:6a4db94011d3 | 131 | *CORDIO_RO_2.1.o |
sahilmgandhi | 18:6a4db94011d3 | 132 | *TRIM_2.1.o |
sahilmgandhi | 18:6a4db94011d3 | 133 | } > FLASH |
sahilmgandhi | 18:6a4db94011d3 | 134 | |
sahilmgandhi | 18:6a4db94011d3 | 135 | .interrupts_ram : |
sahilmgandhi | 18:6a4db94011d3 | 136 | { |
sahilmgandhi | 18:6a4db94011d3 | 137 | . = ALIGN(4); |
sahilmgandhi | 18:6a4db94011d3 | 138 | __VECTOR_RAM__ = .; |
sahilmgandhi | 18:6a4db94011d3 | 139 | __interrupts_ram_start__ = .; /* Create a global symbol at data start */ |
sahilmgandhi | 18:6a4db94011d3 | 140 | . += M_VECTOR_RAM_SIZE; |
sahilmgandhi | 18:6a4db94011d3 | 141 | . = ALIGN(4); |
sahilmgandhi | 18:6a4db94011d3 | 142 | __interrupts_ram_end__ = .; /* Define a global symbol at data end */ |
sahilmgandhi | 18:6a4db94011d3 | 143 | } > RAM |
sahilmgandhi | 18:6a4db94011d3 | 144 | |
sahilmgandhi | 18:6a4db94011d3 | 145 | /* ensure that uvisor bss is at the beginning of memory */ |
sahilmgandhi | 18:6a4db94011d3 | 146 | /* Note: The uVisor expects this section at a fixed location, as specified by |
sahilmgandhi | 18:6a4db94011d3 | 147 | * the porting process configuration parameter: SRAM_OFFSET. */ |
sahilmgandhi | 18:6a4db94011d3 | 148 | __UVISOR_SRAM_OFFSET = 0x140; |
sahilmgandhi | 18:6a4db94011d3 | 149 | __UVISOR_BSS_START = ORIGIN(RAM) + __UVISOR_SRAM_OFFSET; |
sahilmgandhi | 18:6a4db94011d3 | 150 | .uvisor.bss __UVISOR_BSS_START (NOLOAD): |
sahilmgandhi | 18:6a4db94011d3 | 151 | { |
sahilmgandhi | 18:6a4db94011d3 | 152 | . = ALIGN(32); |
sahilmgandhi | 18:6a4db94011d3 | 153 | __uvisor_bss_start = .; |
sahilmgandhi | 18:6a4db94011d3 | 154 | |
sahilmgandhi | 18:6a4db94011d3 | 155 | /* protected uvisor main bss */ |
sahilmgandhi | 18:6a4db94011d3 | 156 | . = ALIGN(32); |
sahilmgandhi | 18:6a4db94011d3 | 157 | __uvisor_bss_main_start = .; |
sahilmgandhi | 18:6a4db94011d3 | 158 | KEEP(*(.keep.uvisor.bss.main)) |
sahilmgandhi | 18:6a4db94011d3 | 159 | . = ALIGN(32); |
sahilmgandhi | 18:6a4db94011d3 | 160 | __uvisor_bss_main_end = .; |
sahilmgandhi | 18:6a4db94011d3 | 161 | |
sahilmgandhi | 18:6a4db94011d3 | 162 | /* protected uvisor secure boxes bss */ |
sahilmgandhi | 18:6a4db94011d3 | 163 | . = ALIGN(32); |
sahilmgandhi | 18:6a4db94011d3 | 164 | __uvisor_bss_boxes_start = .; |
sahilmgandhi | 18:6a4db94011d3 | 165 | KEEP(*(.keep.uvisor.bss.boxes)) |
sahilmgandhi | 18:6a4db94011d3 | 166 | . = ALIGN(32); |
sahilmgandhi | 18:6a4db94011d3 | 167 | __uvisor_bss_boxes_end = .; |
sahilmgandhi | 18:6a4db94011d3 | 168 | |
sahilmgandhi | 18:6a4db94011d3 | 169 | . = ALIGN((1 << LOG2CEIL(LENGTH(RAM))) / 8); |
sahilmgandhi | 18:6a4db94011d3 | 170 | __uvisor_bss_end = .; |
sahilmgandhi | 18:6a4db94011d3 | 171 | } > RAM |
sahilmgandhi | 18:6a4db94011d3 | 172 | |
sahilmgandhi | 18:6a4db94011d3 | 173 | /* Heap space for the page allocator */ |
sahilmgandhi | 18:6a4db94011d3 | 174 | .page_heap (NOLOAD) : |
sahilmgandhi | 18:6a4db94011d3 | 175 | { |
sahilmgandhi | 18:6a4db94011d3 | 176 | . = ALIGN(32); |
sahilmgandhi | 18:6a4db94011d3 | 177 | __uvisor_page_start = .; |
sahilmgandhi | 18:6a4db94011d3 | 178 | KEEP(*(.keep.uvisor.page_heap)) |
sahilmgandhi | 18:6a4db94011d3 | 179 | . = ALIGN(32); |
sahilmgandhi | 18:6a4db94011d3 | 180 | __uvisor_page_end = .; |
sahilmgandhi | 18:6a4db94011d3 | 181 | } > RAM |
sahilmgandhi | 18:6a4db94011d3 | 182 | |
sahilmgandhi | 18:6a4db94011d3 | 183 | .data : |
sahilmgandhi | 18:6a4db94011d3 | 184 | { |
sahilmgandhi | 18:6a4db94011d3 | 185 | PROVIDE(__etext = LOADADDR(.data)); |
sahilmgandhi | 18:6a4db94011d3 | 186 | . = ALIGN(4); |
sahilmgandhi | 18:6a4db94011d3 | 187 | __data_start__ = .; |
sahilmgandhi | 18:6a4db94011d3 | 188 | *(vtable) |
sahilmgandhi | 18:6a4db94011d3 | 189 | *(.data) |
sahilmgandhi | 18:6a4db94011d3 | 190 | *(.data*) |
sahilmgandhi | 18:6a4db94011d3 | 191 | |
sahilmgandhi | 18:6a4db94011d3 | 192 | . = ALIGN(4); |
sahilmgandhi | 18:6a4db94011d3 | 193 | /* preinit data */ |
sahilmgandhi | 18:6a4db94011d3 | 194 | PROVIDE (__preinit_array_start = .); |
sahilmgandhi | 18:6a4db94011d3 | 195 | KEEP(*(.preinit_array)) |
sahilmgandhi | 18:6a4db94011d3 | 196 | PROVIDE (__preinit_array_end = .); |
sahilmgandhi | 18:6a4db94011d3 | 197 | |
sahilmgandhi | 18:6a4db94011d3 | 198 | . = ALIGN(4); |
sahilmgandhi | 18:6a4db94011d3 | 199 | /* init data */ |
sahilmgandhi | 18:6a4db94011d3 | 200 | PROVIDE (__init_array_start = .); |
sahilmgandhi | 18:6a4db94011d3 | 201 | KEEP(*(SORT(.init_array.*))) |
sahilmgandhi | 18:6a4db94011d3 | 202 | KEEP(*(.init_array)) |
sahilmgandhi | 18:6a4db94011d3 | 203 | PROVIDE (__init_array_end = .); |
sahilmgandhi | 18:6a4db94011d3 | 204 | |
sahilmgandhi | 18:6a4db94011d3 | 205 | |
sahilmgandhi | 18:6a4db94011d3 | 206 | . = ALIGN(4); |
sahilmgandhi | 18:6a4db94011d3 | 207 | /* finit data */ |
sahilmgandhi | 18:6a4db94011d3 | 208 | PROVIDE (__fini_array_start = .); |
sahilmgandhi | 18:6a4db94011d3 | 209 | KEEP(*(SORT(.fini_array.*))) |
sahilmgandhi | 18:6a4db94011d3 | 210 | KEEP(*(.fini_array)) |
sahilmgandhi | 18:6a4db94011d3 | 211 | PROVIDE (__fini_array_end = .); |
sahilmgandhi | 18:6a4db94011d3 | 212 | |
sahilmgandhi | 18:6a4db94011d3 | 213 | . = ALIGN(4); |
sahilmgandhi | 18:6a4db94011d3 | 214 | /* All data end */ |
sahilmgandhi | 18:6a4db94011d3 | 215 | __data_end__ = .; |
sahilmgandhi | 18:6a4db94011d3 | 216 | |
sahilmgandhi | 18:6a4db94011d3 | 217 | } > RAM AT > FLASH |
sahilmgandhi | 18:6a4db94011d3 | 218 | |
sahilmgandhi | 18:6a4db94011d3 | 219 | /* uvisor configuration data */ |
sahilmgandhi | 18:6a4db94011d3 | 220 | .uvisor.secure : |
sahilmgandhi | 18:6a4db94011d3 | 221 | { |
sahilmgandhi | 18:6a4db94011d3 | 222 | . = ALIGN(32); |
sahilmgandhi | 18:6a4db94011d3 | 223 | __uvisor_secure_start = .; |
sahilmgandhi | 18:6a4db94011d3 | 224 | |
sahilmgandhi | 18:6a4db94011d3 | 225 | /* uvisor secure boxes configuration tables */ |
sahilmgandhi | 18:6a4db94011d3 | 226 | . = ALIGN(32); |
sahilmgandhi | 18:6a4db94011d3 | 227 | __uvisor_cfgtbl_start = .; |
sahilmgandhi | 18:6a4db94011d3 | 228 | KEEP(*(.keep.uvisor.cfgtbl)) |
sahilmgandhi | 18:6a4db94011d3 | 229 | . = ALIGN(32); |
sahilmgandhi | 18:6a4db94011d3 | 230 | __uvisor_cfgtbl_end = .; |
sahilmgandhi | 18:6a4db94011d3 | 231 | |
sahilmgandhi | 18:6a4db94011d3 | 232 | __uvisor_cfgtbl_ptr_start = .; |
sahilmgandhi | 18:6a4db94011d3 | 233 | KEEP(*(.keep.uvisor.cfgtbl_ptr_first)) |
sahilmgandhi | 18:6a4db94011d3 | 234 | KEEP(*(.keep.uvisor.cfgtbl_ptr)) |
sahilmgandhi | 18:6a4db94011d3 | 235 | __uvisor_cfgtbl_ptr_end = .; |
sahilmgandhi | 18:6a4db94011d3 | 236 | |
sahilmgandhi | 18:6a4db94011d3 | 237 | /* Pointers to all boxes register gateways. These are grouped here to allow |
sahilmgandhi | 18:6a4db94011d3 | 238 | * discoverability and firmware verification. */ |
sahilmgandhi | 18:6a4db94011d3 | 239 | __uvisor_register_gateway_ptr_start = .; |
sahilmgandhi | 18:6a4db94011d3 | 240 | KEEP(*(.keep.uvisor.register_gateway_ptr)) |
sahilmgandhi | 18:6a4db94011d3 | 241 | __uvisor_register_gateway_ptr_end = .; |
sahilmgandhi | 18:6a4db94011d3 | 242 | |
sahilmgandhi | 18:6a4db94011d3 | 243 | . = ALIGN(32); |
sahilmgandhi | 18:6a4db94011d3 | 244 | __uvisor_secure_end = .; |
sahilmgandhi | 18:6a4db94011d3 | 245 | } > FLASH |
sahilmgandhi | 18:6a4db94011d3 | 246 | |
sahilmgandhi | 18:6a4db94011d3 | 247 | /* From now on you can insert any other SRAM region. */ |
sahilmgandhi | 18:6a4db94011d3 | 248 | |
sahilmgandhi | 18:6a4db94011d3 | 249 | .uninitialized (NOLOAD): |
sahilmgandhi | 18:6a4db94011d3 | 250 | { |
sahilmgandhi | 18:6a4db94011d3 | 251 | . = ALIGN(32); |
sahilmgandhi | 18:6a4db94011d3 | 252 | __uninitialized_start = .; |
sahilmgandhi | 18:6a4db94011d3 | 253 | *(.uninitialized) |
sahilmgandhi | 18:6a4db94011d3 | 254 | KEEP(*(.keep.uninitialized)) |
sahilmgandhi | 18:6a4db94011d3 | 255 | . = ALIGN(32); |
sahilmgandhi | 18:6a4db94011d3 | 256 | __uninitialized_end = .; |
sahilmgandhi | 18:6a4db94011d3 | 257 | } > RAM |
sahilmgandhi | 18:6a4db94011d3 | 258 | |
sahilmgandhi | 18:6a4db94011d3 | 259 | .bss : |
sahilmgandhi | 18:6a4db94011d3 | 260 | { |
sahilmgandhi | 18:6a4db94011d3 | 261 | . = ALIGN(4); |
sahilmgandhi | 18:6a4db94011d3 | 262 | __START_BSS = .; |
sahilmgandhi | 18:6a4db94011d3 | 263 | __bss_start__ = .; |
sahilmgandhi | 18:6a4db94011d3 | 264 | *(.bss) |
sahilmgandhi | 18:6a4db94011d3 | 265 | *(.bss*) |
sahilmgandhi | 18:6a4db94011d3 | 266 | *(COMMON) |
sahilmgandhi | 18:6a4db94011d3 | 267 | . = ALIGN(4); |
sahilmgandhi | 18:6a4db94011d3 | 268 | __bss_end__ = .; |
sahilmgandhi | 18:6a4db94011d3 | 269 | __END_BSS = .; |
sahilmgandhi | 18:6a4db94011d3 | 270 | |
sahilmgandhi | 18:6a4db94011d3 | 271 | } > RAM |
sahilmgandhi | 18:6a4db94011d3 | 272 | |
sahilmgandhi | 18:6a4db94011d3 | 273 | bss_size = __bss_end__ - __bss_start__; |
sahilmgandhi | 18:6a4db94011d3 | 274 | |
sahilmgandhi | 18:6a4db94011d3 | 275 | .heap : |
sahilmgandhi | 18:6a4db94011d3 | 276 | { |
sahilmgandhi | 18:6a4db94011d3 | 277 | . = ALIGN(8); |
sahilmgandhi | 18:6a4db94011d3 | 278 | __uvisor_heap_start = .; |
sahilmgandhi | 18:6a4db94011d3 | 279 | __end__ = .; |
sahilmgandhi | 18:6a4db94011d3 | 280 | PROVIDE(end = .); |
sahilmgandhi | 18:6a4db94011d3 | 281 | __HeapBase = .; |
sahilmgandhi | 18:6a4db94011d3 | 282 | . += HEAP_SIZE; |
sahilmgandhi | 18:6a4db94011d3 | 283 | __HeapLimit = .; |
sahilmgandhi | 18:6a4db94011d3 | 284 | __heap_limit = .; /* Add for _sbrk */ |
sahilmgandhi | 18:6a4db94011d3 | 285 | __uvisor_heap_end = .; |
sahilmgandhi | 18:6a4db94011d3 | 286 | } > RAM |
sahilmgandhi | 18:6a4db94011d3 | 287 | |
sahilmgandhi | 18:6a4db94011d3 | 288 | /* Set stack top to end of RAM, and stack limit move down by |
sahilmgandhi | 18:6a4db94011d3 | 289 | * size of stack_dummy section */ |
sahilmgandhi | 18:6a4db94011d3 | 290 | __StackTop = ORIGIN(RAM) + LENGTH(RAM); |
sahilmgandhi | 18:6a4db94011d3 | 291 | __StackLimit = __StackTop - STACK_SIZE; |
sahilmgandhi | 18:6a4db94011d3 | 292 | PROVIDE(__stack = __StackTop); |
sahilmgandhi | 18:6a4db94011d3 | 293 | |
sahilmgandhi | 18:6a4db94011d3 | 294 | /* Check if data + heap + stack exceeds RAM limit */ |
sahilmgandhi | 18:6a4db94011d3 | 295 | ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") |
sahilmgandhi | 18:6a4db94011d3 | 296 | /* Provide physical memory boundaries for uVisor. */ |
sahilmgandhi | 18:6a4db94011d3 | 297 | __uvisor_flash_start = ORIGIN(VECTORS); |
sahilmgandhi | 18:6a4db94011d3 | 298 | __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH); |
sahilmgandhi | 18:6a4db94011d3 | 299 | __uvisor_sram_start = ORIGIN(RAM); |
sahilmgandhi | 18:6a4db94011d3 | 300 | __uvisor_sram_end = ORIGIN(RAM) + LENGTH(RAM); |
sahilmgandhi | 18:6a4db94011d3 | 301 | |
sahilmgandhi | 18:6a4db94011d3 | 302 | } /* End of sections */ |