MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/mmu_Renesas_RZ_A1.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file mmu_Renesas_RZ_A1.c
sahilmgandhi 18:6a4db94011d3 3 * @brief MMU Startup File for
sahilmgandhi 18:6a4db94011d3 4 * mmu_Renesas_RZ_A1 Device Series
sahilmgandhi 18:6a4db94011d3 5 * @version V1.01
sahilmgandhi 18:6a4db94011d3 6 * @date 2 Aug 2013
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @note
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 11 /* Copyright (c) 2011 - 2013 ARM LIMITED
sahilmgandhi 18:6a4db94011d3 12
sahilmgandhi 18:6a4db94011d3 13 All rights reserved.
sahilmgandhi 18:6a4db94011d3 14 Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 15 modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 16 - Redistributions of source code must retain the above copyright
sahilmgandhi 18:6a4db94011d3 17 notice, this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 18 - Redistributions in binary form must reproduce the above copyright
sahilmgandhi 18:6a4db94011d3 19 notice, this list of conditions and the following disclaimer in the
sahilmgandhi 18:6a4db94011d3 20 documentation and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 21 - Neither the name of ARM nor the names of its contributors may be used
sahilmgandhi 18:6a4db94011d3 22 to endorse or promote products derived from this software without
sahilmgandhi 18:6a4db94011d3 23 specific prior written permission.
sahilmgandhi 18:6a4db94011d3 24 *
sahilmgandhi 18:6a4db94011d3 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 27 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
sahilmgandhi 18:6a4db94011d3 28 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
sahilmgandhi 18:6a4db94011d3 29 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
sahilmgandhi 18:6a4db94011d3 30 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
sahilmgandhi 18:6a4db94011d3 31 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
sahilmgandhi 18:6a4db94011d3 32 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
sahilmgandhi 18:6a4db94011d3 33 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
sahilmgandhi 18:6a4db94011d3 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi 18:6a4db94011d3 35 POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 36 ---------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 #define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */
sahilmgandhi 18:6a4db94011d3 40 #define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */
sahilmgandhi 18:6a4db94011d3 41 #define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */
sahilmgandhi 18:6a4db94011d3 42 #define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */
sahilmgandhi 18:6a4db94011d3 43 // L1 Cache info and restrictions about architecture of the caches (CCSIR register):
sahilmgandhi 18:6a4db94011d3 44 // Write-Through support *not* available
sahilmgandhi 18:6a4db94011d3 45 // Write-Back support available.
sahilmgandhi 18:6a4db94011d3 46 // Read allocation support available.
sahilmgandhi 18:6a4db94011d3 47 // Write allocation support available.
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 //Note: You should use the Shareable attribute carefully.
sahilmgandhi 18:6a4db94011d3 50 //For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless the inner cache settings.
sahilmgandhi 18:6a4db94011d3 51 //CA9-RTX uses LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
sahilmgandhi 18:6a4db94011d3 52 //Some A9 implementations does not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 //Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
sahilmgandhi 18:6a4db94011d3 55 //When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
sahilmgandhi 18:6a4db94011d3 56 //When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 //Following MMU configuration is expected
sahilmgandhi 18:6a4db94011d3 60 //SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
sahilmgandhi 18:6a4db94011d3 61 //SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
sahilmgandhi 18:6a4db94011d3 62 //Domain 0 is always the Client domain
sahilmgandhi 18:6a4db94011d3 63 //Descriptors place all memory in domain 0
sahilmgandhi 18:6a4db94011d3 64 //There are no restrictions by privilege level (PL0 can access all memory)
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 #include <stdint.h>
sahilmgandhi 18:6a4db94011d3 67 #include "MBRZA1H.h"
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 //Import symbols from linker
sahilmgandhi 18:6a4db94011d3 70 extern uint32_t Image$$VECTORS$$Base;
sahilmgandhi 18:6a4db94011d3 71 extern uint32_t Image$$RO_DATA$$Base;
sahilmgandhi 18:6a4db94011d3 72 extern uint32_t Image$$RW_DATA$$Base;
sahilmgandhi 18:6a4db94011d3 73 extern uint32_t Image$$ZI_DATA$$Base;
sahilmgandhi 18:6a4db94011d3 74 #if !defined ( __ICCARM__ )
sahilmgandhi 18:6a4db94011d3 75 extern uint32_t Image$$TTB$$ZI$$Base;
sahilmgandhi 18:6a4db94011d3 76 #endif
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78 #if defined( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 79 #elif defined( __ICCARM__ )
sahilmgandhi 18:6a4db94011d3 80 #else
sahilmgandhi 18:6a4db94011d3 81 extern uint32_t Image$$RW_DATA_NC$$Base;
sahilmgandhi 18:6a4db94011d3 82 extern uint32_t Image$$ZI_DATA_NC$$Base;
sahilmgandhi 18:6a4db94011d3 83 #endif
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 extern uint32_t Image$$VECTORS$$Limit;
sahilmgandhi 18:6a4db94011d3 86 extern uint32_t Image$$RO_DATA$$Limit;
sahilmgandhi 18:6a4db94011d3 87 extern uint32_t Image$$RW_DATA$$Limit;
sahilmgandhi 18:6a4db94011d3 88 extern uint32_t Image$$ZI_DATA$$Limit;
sahilmgandhi 18:6a4db94011d3 89 #if defined( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 90 #else
sahilmgandhi 18:6a4db94011d3 91 extern uint32_t Image$$RW_DATA_NC$$Limit;
sahilmgandhi 18:6a4db94011d3 92 extern uint32_t Image$$ZI_DATA_NC$$Limit;
sahilmgandhi 18:6a4db94011d3 93 #endif
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 #if defined( __ICCARM__ )
sahilmgandhi 18:6a4db94011d3 96 #define VECTORS_SIZE (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1)
sahilmgandhi 18:6a4db94011d3 97 #define RO_DATA_SIZE (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1)
sahilmgandhi 18:6a4db94011d3 98 #define RW_DATA_SIZE (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1)
sahilmgandhi 18:6a4db94011d3 99 #define ZI_DATA_SIZE (((uint32_t)Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)Image$$ZI_DATA$$Base >> 20) + 1)
sahilmgandhi 18:6a4db94011d3 100 #else
sahilmgandhi 18:6a4db94011d3 101 #define VECTORS_SIZE (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1)
sahilmgandhi 18:6a4db94011d3 102 #define RO_DATA_SIZE (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1)
sahilmgandhi 18:6a4db94011d3 103 #define RW_DATA_SIZE (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1)
sahilmgandhi 18:6a4db94011d3 104 #define ZI_DATA_SIZE (((uint32_t)&Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA$$Base >> 20) + 1)
sahilmgandhi 18:6a4db94011d3 105 #endif
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 #if defined( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 108 #else
sahilmgandhi 18:6a4db94011d3 109 #define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1)
sahilmgandhi 18:6a4db94011d3 110 #define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1)
sahilmgandhi 18:6a4db94011d3 111 #endif
sahilmgandhi 18:6a4db94011d3 112
sahilmgandhi 18:6a4db94011d3 113 static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
sahilmgandhi 18:6a4db94011d3 114 static uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0
sahilmgandhi 18:6a4db94011d3 115 static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
sahilmgandhi 18:6a4db94011d3 116 static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
sahilmgandhi 18:6a4db94011d3 117 static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
sahilmgandhi 18:6a4db94011d3 118 static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
sahilmgandhi 18:6a4db94011d3 119 static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 /* Define global descriptors */
sahilmgandhi 18:6a4db94011d3 122 static uint32_t Page_L1_4k = 0x0; //generic
sahilmgandhi 18:6a4db94011d3 123 static uint32_t Page_L1_64k = 0x0; //generic
sahilmgandhi 18:6a4db94011d3 124 static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
sahilmgandhi 18:6a4db94011d3 125 static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127 #if defined ( __ICCARM__ )
sahilmgandhi 18:6a4db94011d3 128 __no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram";
sahilmgandhi 18:6a4db94011d3 129 uint32_t Image$$VECTORS$$Base;
sahilmgandhi 18:6a4db94011d3 130 uint32_t Image$$RO_DATA$$Base;
sahilmgandhi 18:6a4db94011d3 131 uint32_t Image$$RW_DATA$$Base;
sahilmgandhi 18:6a4db94011d3 132 uint32_t Image$$ZI_DATA$$Base;
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 uint32_t Image$$VECTORS$$Limit;
sahilmgandhi 18:6a4db94011d3 135 uint32_t Image$$RO_DATA$$Limit;
sahilmgandhi 18:6a4db94011d3 136 uint32_t Image$$RW_DATA$$Limit;
sahilmgandhi 18:6a4db94011d3 137 uint32_t Image$$ZI_DATA$$Limit;
sahilmgandhi 18:6a4db94011d3 138 #endif
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 void create_translation_table(void)
sahilmgandhi 18:6a4db94011d3 141 {
sahilmgandhi 18:6a4db94011d3 142 mmu_region_attributes_Type region;
sahilmgandhi 18:6a4db94011d3 143 #if defined ( __ICCARM__ )
sahilmgandhi 18:6a4db94011d3 144 #pragma section=".intvec"
sahilmgandhi 18:6a4db94011d3 145 #pragma section=".rodata"
sahilmgandhi 18:6a4db94011d3 146 #pragma section=".rwdata"
sahilmgandhi 18:6a4db94011d3 147 #pragma section=".bss"
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149 Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec");
sahilmgandhi 18:6a4db94011d3 150 Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec"));
sahilmgandhi 18:6a4db94011d3 151 Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata");
sahilmgandhi 18:6a4db94011d3 152 Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata"));
sahilmgandhi 18:6a4db94011d3 153 Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata");
sahilmgandhi 18:6a4db94011d3 154 Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata"));
sahilmgandhi 18:6a4db94011d3 155 Image$$ZI_DATA$$Base = (uint32_t) __section_begin(".bss");
sahilmgandhi 18:6a4db94011d3 156 Image$$ZI_DATA$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss"));
sahilmgandhi 18:6a4db94011d3 157 #endif
sahilmgandhi 18:6a4db94011d3 158 /*
sahilmgandhi 18:6a4db94011d3 159 * Generate descriptors. Refer to MBRZA1H.h to get information about attributes
sahilmgandhi 18:6a4db94011d3 160 *
sahilmgandhi 18:6a4db94011d3 161 */
sahilmgandhi 18:6a4db94011d3 162 //Create descriptors for Vectors, RO, RW, ZI sections
sahilmgandhi 18:6a4db94011d3 163 section_normal(Sect_Normal, region);
sahilmgandhi 18:6a4db94011d3 164 section_normal_cod(Sect_Normal_Cod, region);
sahilmgandhi 18:6a4db94011d3 165 section_normal_ro(Sect_Normal_RO, region);
sahilmgandhi 18:6a4db94011d3 166 section_normal_rw(Sect_Normal_RW, region);
sahilmgandhi 18:6a4db94011d3 167 //Create descriptors for peripherals
sahilmgandhi 18:6a4db94011d3 168 section_device_ro(Sect_Device_RO, region);
sahilmgandhi 18:6a4db94011d3 169 section_device_rw(Sect_Device_RW, region);
sahilmgandhi 18:6a4db94011d3 170 section_normal_nc(Sect_Normal_NC, region);
sahilmgandhi 18:6a4db94011d3 171 //Create descriptors for 64k pages
sahilmgandhi 18:6a4db94011d3 172 page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
sahilmgandhi 18:6a4db94011d3 173 //Create descriptors for 4k pages
sahilmgandhi 18:6a4db94011d3 174 page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 /*
sahilmgandhi 18:6a4db94011d3 177 * Define MMU flat-map regions and attributes
sahilmgandhi 18:6a4db94011d3 178 *
sahilmgandhi 18:6a4db94011d3 179 */
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 //Create 4GB of faulting entries
sahilmgandhi 18:6a4db94011d3 182 __TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
sahilmgandhi 18:6a4db94011d3 183
sahilmgandhi 18:6a4db94011d3 184 // R7S72100 memory map.
sahilmgandhi 18:6a4db94011d3 185 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO);
sahilmgandhi 18:6a4db94011d3 186 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO);
sahilmgandhi 18:6a4db94011d3 187 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW);
sahilmgandhi 18:6a4db94011d3 188 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW);
sahilmgandhi 18:6a4db94011d3 189 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA0 , 64, Sect_Normal_RW);
sahilmgandhi 18:6a4db94011d3 190 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA1 , 64, Sect_Normal_RW);
sahilmgandhi 18:6a4db94011d3 191 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO0 , 64, Sect_Normal_RO);
sahilmgandhi 18:6a4db94011d3 192 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO1 , 64, Sect_Normal_RO);
sahilmgandhi 18:6a4db94011d3 193 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_BASE , 10, Sect_Normal_RW);
sahilmgandhi 18:6a4db94011d3 194 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW);
sahilmgandhi 18:6a4db94011d3 195 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_BSC_BASE , 1, Sect_Device_RW);
sahilmgandhi 18:6a4db94011d3 196 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW);
sahilmgandhi 18:6a4db94011d3 197 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW);
sahilmgandhi 18:6a4db94011d3 198
sahilmgandhi 18:6a4db94011d3 199 #if defined( __ICCARM__ )
sahilmgandhi 18:6a4db94011d3 200 //Define Image
sahilmgandhi 18:6a4db94011d3 201 __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_Cod);
sahilmgandhi 18:6a4db94011d3 202 __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod);
sahilmgandhi 18:6a4db94011d3 203 __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW);
sahilmgandhi 18:6a4db94011d3 204 __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW);
sahilmgandhi 18:6a4db94011d3 205 #else
sahilmgandhi 18:6a4db94011d3 206 //Define Image
sahilmgandhi 18:6a4db94011d3 207 __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_Cod);
sahilmgandhi 18:6a4db94011d3 208 __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod);
sahilmgandhi 18:6a4db94011d3 209 __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW);
sahilmgandhi 18:6a4db94011d3 210 __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW);
sahilmgandhi 18:6a4db94011d3 211 #endif
sahilmgandhi 18:6a4db94011d3 212
sahilmgandhi 18:6a4db94011d3 213 #if defined( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 214 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE, 10, Sect_Normal_NC);
sahilmgandhi 18:6a4db94011d3 215 #elif defined ( __ICCARM__ )
sahilmgandhi 18:6a4db94011d3 216 __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE, 10, Sect_Normal_NC);
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218 #else
sahilmgandhi 18:6a4db94011d3 219 __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC);
sahilmgandhi 18:6a4db94011d3 220 __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC);
sahilmgandhi 18:6a4db94011d3 221 #endif
sahilmgandhi 18:6a4db94011d3 222
sahilmgandhi 18:6a4db94011d3 223 /* Set location of level 1 page table
sahilmgandhi 18:6a4db94011d3 224 ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
sahilmgandhi 18:6a4db94011d3 225 ; 13:7 - 0x0
sahilmgandhi 18:6a4db94011d3 226 ; 6 - IRGN[0] 0x0 (Inner WB WA)
sahilmgandhi 18:6a4db94011d3 227 ; 5 - NOS 0x0 (Non-shared)
sahilmgandhi 18:6a4db94011d3 228 ; 4:3 - RGN 0x1 (Outer WB WA)
sahilmgandhi 18:6a4db94011d3 229 ; 2 - IMP 0x0 (Implementation Defined)
sahilmgandhi 18:6a4db94011d3 230 ; 1 - S 0x0 (Non-shared)
sahilmgandhi 18:6a4db94011d3 231 ; 0 - IRGN[1] 0x1 (Inner WB WA) */
sahilmgandhi 18:6a4db94011d3 232 __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
sahilmgandhi 18:6a4db94011d3 233
sahilmgandhi 18:6a4db94011d3 234 /* Set up domain access control register
sahilmgandhi 18:6a4db94011d3 235 ; We set domain 0 to Client and all other domains to No Access.
sahilmgandhi 18:6a4db94011d3 236 ; All translation table entries specify domain 0 */
sahilmgandhi 18:6a4db94011d3 237 __set_DACR(1);
sahilmgandhi 18:6a4db94011d3 238 }
sahilmgandhi 18:6a4db94011d3 239
sahilmgandhi 18:6a4db94011d3 240
sahilmgandhi 18:6a4db94011d3 241 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 242 * end of file
sahilmgandhi 18:6a4db94011d3 243 *---------------------------------------------------------------------------*/