MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/device/NCS36510.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************/
sahilmgandhi 18:6a4db94011d3 2 /**
sahilmgandhi 18:6a4db94011d3 3 * @file NCS36510.h
sahilmgandhi 18:6a4db94011d3 4 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
sahilmgandhi 18:6a4db94011d3 5 * for CM3 Device Series
sahilmgandhi 18:6a4db94011d3 6 * @version V1.05
sahilmgandhi 18:6a4db94011d3 7 * @date 26. July 2011
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * @note
sahilmgandhi 18:6a4db94011d3 10 * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
sahilmgandhi 18:6a4db94011d3 11 *
sahilmgandhi 18:6a4db94011d3 12 * @par
sahilmgandhi 18:6a4db94011d3 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
sahilmgandhi 18:6a4db94011d3 14 * processor based microcontrollers. This file can be freely distributed
sahilmgandhi 18:6a4db94011d3 15 * within development tools that are supporting such ARM based processors.
sahilmgandhi 18:6a4db94011d3 16 *
sahilmgandhi 18:6a4db94011d3 17 * @par
sahilmgandhi 18:6a4db94011d3 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
sahilmgandhi 18:6a4db94011d3 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 #ifndef ARMCM3_H
sahilmgandhi 18:6a4db94011d3 27 #define ARMCM3_H
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 /**
sahilmgandhi 18:6a4db94011d3 30 * ==========================================================================
sahilmgandhi 18:6a4db94011d3 31 * ---------- Interrupt Number Definition -----------------------------------
sahilmgandhi 18:6a4db94011d3 32 * ==========================================================================
sahilmgandhi 18:6a4db94011d3 33 */
sahilmgandhi 18:6a4db94011d3 34 typedef enum IRQn {
sahilmgandhi 18:6a4db94011d3 35 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
sahilmgandhi 18:6a4db94011d3 36 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */
sahilmgandhi 18:6a4db94011d3 37 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 38 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
sahilmgandhi 18:6a4db94011d3 39 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 40 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 41 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
sahilmgandhi 18:6a4db94011d3 42 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
sahilmgandhi 18:6a4db94011d3 43 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
sahilmgandhi 18:6a4db94011d3 44 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /****** ARMCM3 specific Interrupt Numbers ********************************************************/
sahilmgandhi 18:6a4db94011d3 47 Tim0_IRQn = 0,
sahilmgandhi 18:6a4db94011d3 48 Tim1_IRQn = 1,
sahilmgandhi 18:6a4db94011d3 49 Tim2_IRQn = 2,
sahilmgandhi 18:6a4db94011d3 50 Uart1_IRQn = 3,
sahilmgandhi 18:6a4db94011d3 51 Spi_IRQn = 4,
sahilmgandhi 18:6a4db94011d3 52 I2C_IRQn = 5,
sahilmgandhi 18:6a4db94011d3 53 Gpio_IRQn = 6,
sahilmgandhi 18:6a4db94011d3 54 Rtc_IRQn = 7,
sahilmgandhi 18:6a4db94011d3 55 Flash_IRQn = 8,
sahilmgandhi 18:6a4db94011d3 56 MacHw_IRQn = 9,
sahilmgandhi 18:6a4db94011d3 57 Aes_IRQn = 10,
sahilmgandhi 18:6a4db94011d3 58 Adc_IRQn = 11,
sahilmgandhi 18:6a4db94011d3 59 ClockCal_IRQn = 12,
sahilmgandhi 18:6a4db94011d3 60 Uart2_IRQn = 13,
sahilmgandhi 18:6a4db94011d3 61 Uvi_IRQn = 14,
sahilmgandhi 18:6a4db94011d3 62 Dma_IRQn = 15,
sahilmgandhi 18:6a4db94011d3 63 DbgPwrUp_IRQn = 16,
sahilmgandhi 18:6a4db94011d3 64 Spi2_IRQn = 17,
sahilmgandhi 18:6a4db94011d3 65 I2C2_IRQn = 18,
sahilmgandhi 18:6a4db94011d3 66 FVDDHComp_IRQn = 19
sahilmgandhi 18:6a4db94011d3 67 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 /**
sahilmgandhi 18:6a4db94011d3 70 * ==========================================================================
sahilmgandhi 18:6a4db94011d3 71 * ----------- Processor and Core Peripheral Section ------------------------
sahilmgandhi 18:6a4db94011d3 72 * ==========================================================================
sahilmgandhi 18:6a4db94011d3 73 */
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 /** Configuration of the Cortex-M3 Processor and Core Peripherals */
sahilmgandhi 18:6a4db94011d3 76 #define __CM3_REV 0x0201 /*!< Core Revision r2p1 */
sahilmgandhi 18:6a4db94011d3 77 #define __MPU_PRESENT 1 /*!< MPU present or not */
sahilmgandhi 18:6a4db94011d3 78 #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
sahilmgandhi 18:6a4db94011d3 79 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 //#define YOTTA_CFG_CMSIS_NVIC_USER_IRQ_OFFSET 16
sahilmgandhi 18:6a4db94011d3 82 //#define YOTTA_CFG_CMSIS_NVIC_USER_IRQ_NUMBER 20
sahilmgandhi 18:6a4db94011d3 83 //#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 //#define YOTTA_CFG_CMSIS_NVIC_RAM_VECTOR_ADDRESS
sahilmgandhi 18:6a4db94011d3 86 //#define YOTTA_CFG_CMSIS_NVIC_FLASH_VECTOR_ADDRESS 0x3000
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 #include <core_cm3.h> /* Cortex-M3 processor and core peripherals */
sahilmgandhi 18:6a4db94011d3 89 #include "system_NCS36510.h" /* System Header */
sahilmgandhi 18:6a4db94011d3 90
sahilmgandhi 18:6a4db94011d3 91 #endif /* ARMCM3_H */