MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralNames.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2015 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #ifndef MBED_PERIPHERALNAMES_H
sahilmgandhi 18:6a4db94011d3 17 #define MBED_PERIPHERALNAMES_H
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #include <compiler.h>
sahilmgandhi 18:6a4db94011d3 20 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 21 #include "PinNames.h"
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 24 extern "C" {
sahilmgandhi 18:6a4db94011d3 25 #endif
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 #define _SERCOM_SPI_NAME(n, unused) \
sahilmgandhi 18:6a4db94011d3 28 SPI##n,
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 #define _SERCOM_PAD_NAME(n, pad) \
sahilmgandhi 18:6a4db94011d3 31 SERCOM##n##_PAD##pad = ((n & 0xF) | ((pad & 0xF) << 4)),
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 #define _SERCOM_I2C_NAME(n, unused) \
sahilmgandhi 18:6a4db94011d3 34 I2C##n,
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 typedef enum {
sahilmgandhi 18:6a4db94011d3 39 UART_0 = (int)0x42000800UL, // Base address of SERCOM0
sahilmgandhi 18:6a4db94011d3 40 UART_1 = (int)0x42000C00UL, // Base address of SERCOM1
sahilmgandhi 18:6a4db94011d3 41 UART_2 = (int)0x42001000UL, // Base address of SERCOM2
sahilmgandhi 18:6a4db94011d3 42 UART_3 = (int)0x42001400UL, // Base address of SERCOM3
sahilmgandhi 18:6a4db94011d3 43 UART_4 = (int)0x42001800UL, // Base address of SERCOM4
sahilmgandhi 18:6a4db94011d3 44 UART_5 = (int)0x42001C00UL // Base address of SERCOM5
sahilmgandhi 18:6a4db94011d3 45 } UARTName;
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 typedef enum { // for each input control mux 4,5,6,7,16,17,10,11 used in R21
sahilmgandhi 18:6a4db94011d3 48 ADC_2 = 0x2ul,
sahilmgandhi 18:6a4db94011d3 49 ADC_3 = 0x3ul,
sahilmgandhi 18:6a4db94011d3 50 ADC_4 = 0x4ul,
sahilmgandhi 18:6a4db94011d3 51 ADC_5 = 0x5ul,
sahilmgandhi 18:6a4db94011d3 52 ADC_6 = 0x6ul,
sahilmgandhi 18:6a4db94011d3 53 ADC_7 = 0x7ul,
sahilmgandhi 18:6a4db94011d3 54 ADC_8 = 0x8ul,
sahilmgandhi 18:6a4db94011d3 55 ADC_10 = 0xAul,
sahilmgandhi 18:6a4db94011d3 56 ADC_11 = 0xBul,
sahilmgandhi 18:6a4db94011d3 57 ADC_16 = 0x10ul,
sahilmgandhi 18:6a4db94011d3 58 ADC_17 = 0x11ul,
sahilmgandhi 18:6a4db94011d3 59 ADC_18 = 0x12ul,
sahilmgandhi 18:6a4db94011d3 60 ADC_19 = 0x13ul
sahilmgandhi 18:6a4db94011d3 61 } ADCName;
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 typedef enum { // for each channel
sahilmgandhi 18:6a4db94011d3 64 EXTINT_0 = 0,
sahilmgandhi 18:6a4db94011d3 65 EXTINT_1,
sahilmgandhi 18:6a4db94011d3 66 EXTINT_2,
sahilmgandhi 18:6a4db94011d3 67 EXTINT_3,
sahilmgandhi 18:6a4db94011d3 68 EXTINT_4,
sahilmgandhi 18:6a4db94011d3 69 EXTINT_5,
sahilmgandhi 18:6a4db94011d3 70 EXTINT_6,
sahilmgandhi 18:6a4db94011d3 71 EXTINT_7,
sahilmgandhi 18:6a4db94011d3 72 EXTINT_8,
sahilmgandhi 18:6a4db94011d3 73 EXTINT_9,
sahilmgandhi 18:6a4db94011d3 74 EXTINT_10,
sahilmgandhi 18:6a4db94011d3 75 EXTINT_11,
sahilmgandhi 18:6a4db94011d3 76 EXTINT_12,
sahilmgandhi 18:6a4db94011d3 77 EXTINT_13,
sahilmgandhi 18:6a4db94011d3 78 EXTINT_14,
sahilmgandhi 18:6a4db94011d3 79 EXTINT_15
sahilmgandhi 18:6a4db94011d3 80 } EXTINTName;
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 typedef enum {
sahilmgandhi 18:6a4db94011d3 83 MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_NAME, ~)
sahilmgandhi 18:6a4db94011d3 84 } SPIName;
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 typedef enum {
sahilmgandhi 18:6a4db94011d3 87 MREPEAT(SERCOM_INST_NUM, _SERCOM_I2C_NAME, ~)
sahilmgandhi 18:6a4db94011d3 88 } I2CName;
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 typedef enum {
sahilmgandhi 18:6a4db94011d3 91 /* Pad 0 definitions */
sahilmgandhi 18:6a4db94011d3 92 MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 0)
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 /* Pad 1 definitions */
sahilmgandhi 18:6a4db94011d3 95 MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 1)
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 /* Pad 2 definitions */
sahilmgandhi 18:6a4db94011d3 98 MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 2)
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 /* Pad 3 definitions */
sahilmgandhi 18:6a4db94011d3 101 MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 3)
sahilmgandhi 18:6a4db94011d3 102 } SercomPadName;
sahilmgandhi 18:6a4db94011d3 103
sahilmgandhi 18:6a4db94011d3 104 typedef enum {
sahilmgandhi 18:6a4db94011d3 105 PWM_0 = (0x42002000UL), /**< \brief (TCC0) APB Base Address */
sahilmgandhi 18:6a4db94011d3 106 PWM_1 = (0x42002400UL), /**< \brief (TCC1) APB Base Address */
sahilmgandhi 18:6a4db94011d3 107 PWM_2 = (0x42002800UL), /**< \brief (TCC2) APB Base Address */
sahilmgandhi 18:6a4db94011d3 108 } PWMName;
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 struct pwm_pin_channel {
sahilmgandhi 18:6a4db94011d3 111 PinName pin;
sahilmgandhi 18:6a4db94011d3 112 PWMName pwm;
sahilmgandhi 18:6a4db94011d3 113 uint8_t channel_index;
sahilmgandhi 18:6a4db94011d3 114 };
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 #define STDIO_UART_TX USBTX
sahilmgandhi 18:6a4db94011d3 117 #define STDIO_UART_RX USBRX
sahilmgandhi 18:6a4db94011d3 118 #define STDIO_UART UART_0
sahilmgandhi 18:6a4db94011d3 119
sahilmgandhi 18:6a4db94011d3 120 // Default peripherals
sahilmgandhi 18:6a4db94011d3 121 #define MBED_SPI0 PB22, PB02, PB23, PA14
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 #define MBED_UART0 PA04, PA05
sahilmgandhi 18:6a4db94011d3 124 #define MBED_UARTUSB USBTX, USBRX
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 #define MBED_I2C0 PA16, PA17
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 #define MBED_ANALOGIN0 PA04
sahilmgandhi 18:6a4db94011d3 129 #define MBED_ANALOGIN1 PA05
sahilmgandhi 18:6a4db94011d3 130 #define MBED_ANALOGIN2 PA06
sahilmgandhi 18:6a4db94011d3 131 #define MBED_ANALOGIN3 PA07
sahilmgandhi 18:6a4db94011d3 132 #define MBED_ANALOGIN4 PB02
sahilmgandhi 18:6a4db94011d3 133 #define MBED_ANALOGIN5 PB03
sahilmgandhi 18:6a4db94011d3 134 #define MBED_ANALOGIN7 PA08
sahilmgandhi 18:6a4db94011d3 135 #define MBED_ANALOGIN8 PA09
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 #define MBED_PWMOUT0 PA18
sahilmgandhi 18:6a4db94011d3 138 #define MBED_PWMOUT1 PA19
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 141 }
sahilmgandhi 18:6a4db94011d3 142 #endif
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 #endif