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Nucleo_Encoder_16_bits.cpp@2:3fcf36c1b1af, 2018-12-17 (annotated)

Committer:
calmantara186
Date:
Mon Dec 17 17:02:43 2018 +0000
Revision:
2:3fcf36c1b1af
Parent:
1:e82009479b5c
Child:
3:d43c60d01569
TIM_encoder

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kkoichy 0:ebd170807e11 1 #include "Nucleo_Encoder_16_bits.h"
kkoichy 0:ebd170807e11 2
calmantara186 2:3fcf36c1b1af 3 int32_t Soft_32_Counter_TIM1,Soft_32_Counter_TIM2, Soft_32_Counter_TIM3, Soft_32_Counter_TIM4, Soft_32_Counter_TIM5;
calmantara186 2:3fcf36c1b1af 4
calmantara186 2:3fcf36c1b1af 5 void Overflow_Routine_TIM1()
calmantara186 2:3fcf36c1b1af 6 {
calmantara186 2:3fcf36c1b1af 7 if(TIM1->SR & 0x0001)
calmantara186 2:3fcf36c1b1af 8 {
calmantara186 2:3fcf36c1b1af 9 //////printf("Overflow Routine");
calmantara186 2:3fcf36c1b1af 10 TIM1->SR &= 0xfffe;
calmantara186 2:3fcf36c1b1af 11 if(!(TIM1->CR1&TIM_CR1_DIR))
calmantara186 2:3fcf36c1b1af 12 Soft_32_Counter_TIM1 += 0xffff;
calmantara186 2:3fcf36c1b1af 13 else
calmantara186 2:3fcf36c1b1af 14 Soft_32_Counter_TIM1 -= 0xffff;
calmantara186 2:3fcf36c1b1af 15 }
calmantara186 2:3fcf36c1b1af 16 }
kkoichy 0:ebd170807e11 17
kkoichy 0:ebd170807e11 18 void Overflow_Routine_TIM2()
kkoichy 0:ebd170807e11 19 {
kkoichy 0:ebd170807e11 20 if(TIM2->SR & 0x0001)
kkoichy 0:ebd170807e11 21 {
calmantara186 2:3fcf36c1b1af 22 //////printf("Overflow Routine");
kkoichy 0:ebd170807e11 23 TIM2->SR &= 0xfffe;
kkoichy 0:ebd170807e11 24 if(!(TIM2->CR1&TIM_CR1_DIR))
kkoichy 0:ebd170807e11 25 Soft_32_Counter_TIM2 += 0xffff;
kkoichy 0:ebd170807e11 26 else
kkoichy 0:ebd170807e11 27 Soft_32_Counter_TIM2 -= 0xffff;
kkoichy 0:ebd170807e11 28 }
kkoichy 0:ebd170807e11 29 }
kkoichy 0:ebd170807e11 30
kkoichy 0:ebd170807e11 31 void Overflow_Routine_TIM3()
kkoichy 0:ebd170807e11 32 {
kkoichy 0:ebd170807e11 33 if(TIM3->SR & 0x0001)
kkoichy 0:ebd170807e11 34 {
calmantara186 2:3fcf36c1b1af 35 //////printf("Overflow Routine");
kkoichy 0:ebd170807e11 36 TIM3->SR &= 0xfffe;
kkoichy 0:ebd170807e11 37 if(!(TIM3->CR1&TIM_CR1_DIR))
kkoichy 0:ebd170807e11 38 Soft_32_Counter_TIM3 += 0xffff;
kkoichy 0:ebd170807e11 39 else
kkoichy 0:ebd170807e11 40 Soft_32_Counter_TIM3 -= 0xffff;
kkoichy 0:ebd170807e11 41 }
kkoichy 0:ebd170807e11 42 }
kkoichy 0:ebd170807e11 43 void Overflow_Routine_TIM4()
kkoichy 0:ebd170807e11 44 {
kkoichy 0:ebd170807e11 45 if(TIM4->SR & 0x0001)
kkoichy 0:ebd170807e11 46 {
calmantara186 2:3fcf36c1b1af 47 //////////printf("Overflow Routine");
kkoichy 0:ebd170807e11 48 TIM4->SR &= 0xfffe;
kkoichy 0:ebd170807e11 49 if(!(TIM4->CR1&TIM_CR1_DIR))
kkoichy 0:ebd170807e11 50 Soft_32_Counter_TIM4 += 0xffff;
kkoichy 0:ebd170807e11 51 else
kkoichy 0:ebd170807e11 52 Soft_32_Counter_TIM4 -= 0xffff;
kkoichy 0:ebd170807e11 53 }
kkoichy 0:ebd170807e11 54 }
kkoichy 0:ebd170807e11 55 void Overflow_Routine_TIM5()
kkoichy 0:ebd170807e11 56 {
kkoichy 0:ebd170807e11 57 if(TIM5->SR & 0x0001)
kkoichy 0:ebd170807e11 58 {
calmantara186 2:3fcf36c1b1af 59 ////printf("Overflow Routine");
kkoichy 0:ebd170807e11 60 TIM5->SR &= 0xfffe;
kkoichy 0:ebd170807e11 61 if(!(TIM5->CR1&TIM_CR1_DIR))
kkoichy 0:ebd170807e11 62 Soft_32_Counter_TIM5 += 0xffff;
kkoichy 0:ebd170807e11 63 else
kkoichy 0:ebd170807e11 64 Soft_32_Counter_TIM5 -= 0xffff;
kkoichy 0:ebd170807e11 65 }
kkoichy 0:ebd170807e11 66 }
kkoichy 0:ebd170807e11 67
kkoichy 0:ebd170807e11 68 namespace mbed
kkoichy 0:ebd170807e11 69 {
kkoichy 1:e82009479b5c 70
kkoichy 1:e82009479b5c 71 Nucleo_Encoder_16_bits::Nucleo_Encoder_16_bits(TIM_TypeDef * _TIM)
kkoichy 1:e82009479b5c 72 {
kkoichy 1:e82009479b5c 73 TIM = _TIM;
kkoichy 1:e82009479b5c 74 // Initialisation of the TIM module as an encoder counter
kkoichy 1:e82009479b5c 75 EncoderInit(&encoder, &timer, _TIM, 0xffff, TIM_ENCODERMODE_TI12);
kkoichy 1:e82009479b5c 76
kkoichy 1:e82009479b5c 77 // Update (aka over- and underflow) interrupt enabled
kkoichy 1:e82009479b5c 78 TIM->DIER |= 0x0001;
kkoichy 1:e82009479b5c 79 // The initialisation process generates an update interrupt, so we'll have to clear the update flag before anything else
kkoichy 1:e82009479b5c 80 TIM->SR &= 0xfffe;
kkoichy 1:e82009479b5c 81
kkoichy 1:e82009479b5c 82 // Setting the ISR for the corresponding interrupt vector
kkoichy 1:e82009479b5c 83 switch((uint32_t)TIM)
kkoichy 1:e82009479b5c 84 {
kkoichy 1:e82009479b5c 85 case TIM2_BASE :
kkoichy 1:e82009479b5c 86 NVIC_SetVector(TIM2_IRQn, (uint32_t)&Overflow_Routine_TIM2);
kkoichy 1:e82009479b5c 87 NVIC_EnableIRQ(TIM2_IRQn);
kkoichy 1:e82009479b5c 88 Soft_32_Counter_TIM2 = 0;
kkoichy 1:e82009479b5c 89 break;
kkoichy 1:e82009479b5c 90
kkoichy 1:e82009479b5c 91 case TIM3_BASE :
kkoichy 1:e82009479b5c 92 NVIC_SetVector(TIM3_IRQn, (uint32_t)&Overflow_Routine_TIM3);
kkoichy 1:e82009479b5c 93 NVIC_EnableIRQ(TIM3_IRQn);
kkoichy 1:e82009479b5c 94 Soft_32_Counter_TIM3 = 0;
kkoichy 1:e82009479b5c 95 break;
kkoichy 1:e82009479b5c 96
kkoichy 1:e82009479b5c 97 case TIM4_BASE :
kkoichy 1:e82009479b5c 98 NVIC_SetVector(TIM4_IRQn, (uint32_t)&Overflow_Routine_TIM4);
kkoichy 1:e82009479b5c 99 NVIC_EnableIRQ(TIM4_IRQn);
kkoichy 1:e82009479b5c 100 Soft_32_Counter_TIM4 = 0;
kkoichy 1:e82009479b5c 101 break;
kkoichy 1:e82009479b5c 102
kkoichy 1:e82009479b5c 103 case TIM5_BASE :
kkoichy 1:e82009479b5c 104 NVIC_SetVector(TIM5_IRQn, (uint32_t)&Overflow_Routine_TIM5);
kkoichy 1:e82009479b5c 105 NVIC_EnableIRQ(TIM5_IRQn);
kkoichy 1:e82009479b5c 106 Soft_32_Counter_TIM5 = 0;
kkoichy 1:e82009479b5c 107 break;
kkoichy 1:e82009479b5c 108
kkoichy 1:e82009479b5c 109 default :
kkoichy 1:e82009479b5c 110
kkoichy 1:e82009479b5c 111 break;
kkoichy 1:e82009479b5c 112 }
kkoichy 1:e82009479b5c 113
kkoichy 1:e82009479b5c 114 }
kkoichy 0:ebd170807e11 115 Nucleo_Encoder_16_bits::Nucleo_Encoder_16_bits(TIM_TypeDef * _TIM, uint32_t _maxcount, uint32_t _encmode)
kkoichy 0:ebd170807e11 116 {
kkoichy 0:ebd170807e11 117 TIM = _TIM;
kkoichy 0:ebd170807e11 118 // Initialisation of the TIM module as an encoder counter
kkoichy 0:ebd170807e11 119 EncoderInit(&encoder, &timer, _TIM, _maxcount, _encmode);
kkoichy 0:ebd170807e11 120
kkoichy 0:ebd170807e11 121 // Update (aka over- and underflow) interrupt enabled
kkoichy 0:ebd170807e11 122 TIM->DIER |= 0x0001;
kkoichy 0:ebd170807e11 123 // The initialisation process generates an update interrupt, so we'll have to clear the update flag before anything else
kkoichy 0:ebd170807e11 124 TIM->SR &= 0xfffe;
kkoichy 0:ebd170807e11 125
kkoichy 0:ebd170807e11 126 // Setting the ISR for the corresponding interrupt vector
kkoichy 0:ebd170807e11 127 switch((uint32_t)TIM)
kkoichy 0:ebd170807e11 128 {
calmantara186 2:3fcf36c1b1af 129
kkoichy 0:ebd170807e11 130 case TIM2_BASE :
kkoichy 0:ebd170807e11 131 NVIC_SetVector(TIM2_IRQn, (uint32_t)&Overflow_Routine_TIM2);
kkoichy 0:ebd170807e11 132 NVIC_EnableIRQ(TIM2_IRQn);
kkoichy 0:ebd170807e11 133 Soft_32_Counter_TIM2 = 0;
kkoichy 0:ebd170807e11 134 break;
kkoichy 0:ebd170807e11 135
kkoichy 0:ebd170807e11 136 case TIM3_BASE :
kkoichy 0:ebd170807e11 137 NVIC_SetVector(TIM3_IRQn, (uint32_t)&Overflow_Routine_TIM3);
kkoichy 0:ebd170807e11 138 NVIC_EnableIRQ(TIM3_IRQn);
kkoichy 0:ebd170807e11 139 Soft_32_Counter_TIM3 = 0;
kkoichy 0:ebd170807e11 140 break;
kkoichy 0:ebd170807e11 141
kkoichy 0:ebd170807e11 142 case TIM4_BASE :
kkoichy 0:ebd170807e11 143 NVIC_SetVector(TIM4_IRQn, (uint32_t)&Overflow_Routine_TIM4);
kkoichy 0:ebd170807e11 144 NVIC_EnableIRQ(TIM4_IRQn);
kkoichy 0:ebd170807e11 145 Soft_32_Counter_TIM4 = 0;
kkoichy 0:ebd170807e11 146 break;
kkoichy 0:ebd170807e11 147
kkoichy 0:ebd170807e11 148 case TIM5_BASE :
kkoichy 0:ebd170807e11 149 NVIC_SetVector(TIM5_IRQn, (uint32_t)&Overflow_Routine_TIM5);
kkoichy 0:ebd170807e11 150 NVIC_EnableIRQ(TIM5_IRQn);
kkoichy 0:ebd170807e11 151 Soft_32_Counter_TIM5 = 0;
kkoichy 0:ebd170807e11 152 break;
kkoichy 0:ebd170807e11 153
kkoichy 0:ebd170807e11 154 default :
kkoichy 0:ebd170807e11 155
kkoichy 0:ebd170807e11 156 break;
kkoichy 0:ebd170807e11 157 }
kkoichy 0:ebd170807e11 158
kkoichy 0:ebd170807e11 159 }
kkoichy 0:ebd170807e11 160
kkoichy 0:ebd170807e11 161 Nucleo_Encoder_16_bits::Nucleo_Encoder_16_bits(TIM_Encoder_InitTypeDef * _encoder, TIM_HandleTypeDef * _timer, TIM_TypeDef * _TIM, uint32_t _maxcount, uint32_t _encmode)
kkoichy 0:ebd170807e11 162 {
kkoichy 0:ebd170807e11 163 timer = *_timer;
kkoichy 0:ebd170807e11 164 encoder = *_encoder;
kkoichy 0:ebd170807e11 165 TIM = _TIM;
kkoichy 0:ebd170807e11 166 // Initialisation of the TIM module as an encoder counter
kkoichy 0:ebd170807e11 167 EncoderInit(&encoder, &timer, _TIM, _maxcount, _encmode);
kkoichy 0:ebd170807e11 168
kkoichy 0:ebd170807e11 169 // Update (aka over- and underflow) interrupt enabled
kkoichy 0:ebd170807e11 170 TIM->DIER |= 0x0001;
kkoichy 0:ebd170807e11 171 // The initialisation process generates an update interrupt, so we'll have to clear the update flag before anything else
kkoichy 0:ebd170807e11 172 TIM->SR &= 0xfffe;
kkoichy 0:ebd170807e11 173
kkoichy 0:ebd170807e11 174 // Setting the ISR for the corresponding interrupt vector
kkoichy 0:ebd170807e11 175 switch((uint32_t)TIM)
kkoichy 0:ebd170807e11 176 {
calmantara186 2:3fcf36c1b1af 177
kkoichy 0:ebd170807e11 178 case TIM2_BASE :
kkoichy 0:ebd170807e11 179 NVIC_SetVector(TIM2_IRQn, (uint32_t)&Overflow_Routine_TIM2);
kkoichy 0:ebd170807e11 180 NVIC_EnableIRQ(TIM2_IRQn);
kkoichy 0:ebd170807e11 181 Soft_32_Counter_TIM2 = 0;
kkoichy 0:ebd170807e11 182 break;
kkoichy 0:ebd170807e11 183
kkoichy 0:ebd170807e11 184 case TIM3_BASE :
kkoichy 0:ebd170807e11 185 NVIC_SetVector(TIM3_IRQn, (uint32_t)&Overflow_Routine_TIM3);
kkoichy 0:ebd170807e11 186 NVIC_EnableIRQ(TIM3_IRQn);
kkoichy 0:ebd170807e11 187 Soft_32_Counter_TIM3 = 0;
kkoichy 0:ebd170807e11 188 break;
kkoichy 0:ebd170807e11 189
kkoichy 0:ebd170807e11 190 case TIM4_BASE :
kkoichy 0:ebd170807e11 191 NVIC_SetVector(TIM4_IRQn, (uint32_t)&Overflow_Routine_TIM4);
kkoichy 0:ebd170807e11 192 NVIC_EnableIRQ(TIM4_IRQn);
kkoichy 0:ebd170807e11 193 Soft_32_Counter_TIM4 = 0;
kkoichy 0:ebd170807e11 194 break;
kkoichy 0:ebd170807e11 195
kkoichy 0:ebd170807e11 196 case TIM5_BASE :
kkoichy 0:ebd170807e11 197 NVIC_SetVector(TIM5_IRQn, (uint32_t)&Overflow_Routine_TIM5);
kkoichy 0:ebd170807e11 198 NVIC_EnableIRQ(TIM5_IRQn);
kkoichy 0:ebd170807e11 199 Soft_32_Counter_TIM5 = 0;
kkoichy 0:ebd170807e11 200 break;
kkoichy 0:ebd170807e11 201
kkoichy 0:ebd170807e11 202 default :
kkoichy 0:ebd170807e11 203
kkoichy 0:ebd170807e11 204 break;
kkoichy 0:ebd170807e11 205 }
kkoichy 0:ebd170807e11 206
kkoichy 0:ebd170807e11 207 }
kkoichy 0:ebd170807e11 208
kkoichy 0:ebd170807e11 209
calmantara186 2:3fcf36c1b1af 210 int32_t Nucleo_Encoder_16_bits::GetCounter(bool reset)
kkoichy 0:ebd170807e11 211 {
kkoichy 0:ebd170807e11 212 uint16_t count = TIM->CNT;
calmantara186 2:3fcf36c1b1af 213 if(reset){
calmantara186 2:3fcf36c1b1af 214 switch((uint32_t)TIM){
calmantara186 2:3fcf36c1b1af 215 case TIM1_BASE :
calmantara186 2:3fcf36c1b1af 216 TIM1->CNT = 0;
calmantara186 2:3fcf36c1b1af 217 Soft_32_Counter_TIM1 = 0;
calmantara186 2:3fcf36c1b1af 218 break;
calmantara186 2:3fcf36c1b1af 219
calmantara186 2:3fcf36c1b1af 220 case TIM2_BASE :
calmantara186 2:3fcf36c1b1af 221 TIM2->CNT = 0;
calmantara186 2:3fcf36c1b1af 222 Soft_32_Counter_TIM2 = 0;
calmantara186 2:3fcf36c1b1af 223 break;
calmantara186 2:3fcf36c1b1af 224
calmantara186 2:3fcf36c1b1af 225 case TIM3_BASE :
calmantara186 2:3fcf36c1b1af 226 TIM3->CNT = 0;
calmantara186 2:3fcf36c1b1af 227 Soft_32_Counter_TIM3 = 0;
calmantara186 2:3fcf36c1b1af 228 break;
calmantara186 2:3fcf36c1b1af 229
calmantara186 2:3fcf36c1b1af 230 case TIM4_BASE :
calmantara186 2:3fcf36c1b1af 231 TIM4->CNT = 0;
calmantara186 2:3fcf36c1b1af 232 Soft_32_Counter_TIM4 = 0;
calmantara186 2:3fcf36c1b1af 233 break;
calmantara186 2:3fcf36c1b1af 234
calmantara186 2:3fcf36c1b1af 235 case TIM5_BASE :
calmantara186 2:3fcf36c1b1af 236 TIM5->CNT = 0;
calmantara186 2:3fcf36c1b1af 237 Soft_32_Counter_TIM5 = 0;
calmantara186 2:3fcf36c1b1af 238 break;
calmantara186 2:3fcf36c1b1af 239 }
calmantara186 2:3fcf36c1b1af 240 }
calmantara186 2:3fcf36c1b1af 241 else{
calmantara186 2:3fcf36c1b1af 242 switch((uint32_t)TIM)
calmantara186 2:3fcf36c1b1af 243 {
calmantara186 2:3fcf36c1b1af 244 case TIM1_BASE :
calmantara186 2:3fcf36c1b1af 245 return (int32_t)count + Soft_32_Counter_TIM1;
calmantara186 2:3fcf36c1b1af 246 break;
calmantara186 2:3fcf36c1b1af 247
calmantara186 2:3fcf36c1b1af 248 case TIM2_BASE :
calmantara186 2:3fcf36c1b1af 249 return (int32_t)count + Soft_32_Counter_TIM2;
calmantara186 2:3fcf36c1b1af 250 break;
calmantara186 2:3fcf36c1b1af 251
calmantara186 2:3fcf36c1b1af 252 case TIM3_BASE :
calmantara186 2:3fcf36c1b1af 253 return (int32_t)count + Soft_32_Counter_TIM3;
calmantara186 2:3fcf36c1b1af 254 break;
calmantara186 2:3fcf36c1b1af 255
calmantara186 2:3fcf36c1b1af 256 case TIM4_BASE :
calmantara186 2:3fcf36c1b1af 257 return (int32_t)count + Soft_32_Counter_TIM4;
calmantara186 2:3fcf36c1b1af 258 break;
calmantara186 2:3fcf36c1b1af 259
calmantara186 2:3fcf36c1b1af 260 case TIM5_BASE :
calmantara186 2:3fcf36c1b1af 261 return (int32_t)count + Soft_32_Counter_TIM5;
calmantara186 2:3fcf36c1b1af 262 break;
calmantara186 2:3fcf36c1b1af 263 }
kkoichy 0:ebd170807e11 264 }
kkoichy 0:ebd170807e11 265
kkoichy 0:ebd170807e11 266 return (int32_t)count;
calmantara186 2:3fcf36c1b1af 267 }
kkoichy 0:ebd170807e11 268
kkoichy 0:ebd170807e11 269 TIM_HandleTypeDef* Nucleo_Encoder_16_bits::GetTimer()
kkoichy 0:ebd170807e11 270 {
kkoichy 0:ebd170807e11 271 return &timer;
kkoichy 0:ebd170807e11 272 }
kkoichy 0:ebd170807e11 273
kkoichy 0:ebd170807e11 274
kkoichy 0:ebd170807e11 275
kkoichy 0:ebd170807e11 276
kkoichy 0:ebd170807e11 277
kkoichy 0:ebd170807e11 278
kkoichy 0:ebd170807e11 279 }