Diff: Nucleo_Encoder_16_bits.cpp

Revision:

2:3fcf36c1b1af

Parent:

1:e82009479b5c

Child:

3:d43c60d01569

--- a/Nucleo_Encoder_16_bits.cpp	Thu May 26 16:21:43 2016 +0000
+++ b/Nucleo_Encoder_16_bits.cpp	Mon Dec 17 17:02:43 2018 +0000
@@ -1,12 +1,25 @@
 #include "Nucleo_Encoder_16_bits.h"
 
-int32_t Soft_32_Counter_TIM2, Soft_32_Counter_TIM3, Soft_32_Counter_TIM4, Soft_32_Counter_TIM5;
+int32_t Soft_32_Counter_TIM1,Soft_32_Counter_TIM2, Soft_32_Counter_TIM3, Soft_32_Counter_TIM4, Soft_32_Counter_TIM5;
+
+void Overflow_Routine_TIM1()
+{
+    if(TIM1->SR & 0x0001)
+    {
+        //////printf("Overflow Routine");
+        TIM1->SR &= 0xfffe;
+        if(!(TIM1->CR1&TIM_CR1_DIR))
+            Soft_32_Counter_TIM1 += 0xffff;
+        else
+            Soft_32_Counter_TIM1 -= 0xffff;
+    }
+}
 
 void Overflow_Routine_TIM2()
 {
     if(TIM2->SR & 0x0001)
     {
-        printf("Overflow Routine");
+        //////printf("Overflow Routine");
         TIM2->SR &= 0xfffe;
         if(!(TIM2->CR1&TIM_CR1_DIR))
             Soft_32_Counter_TIM2 += 0xffff;
@@ -19,7 +32,7 @@
 {
     if(TIM3->SR & 0x0001)
     {
-        printf("Overflow Routine");
+        //////printf("Overflow Routine");
         TIM3->SR &= 0xfffe;
         if(!(TIM3->CR1&TIM_CR1_DIR))
             Soft_32_Counter_TIM3 += 0xffff;
@@ -31,7 +44,7 @@
 {
     if(TIM4->SR & 0x0001)
     {
-        printf("Overflow Routine");
+        //////////printf("Overflow Routine");
         TIM4->SR &= 0xfffe;
         if(!(TIM4->CR1&TIM_CR1_DIR))
             Soft_32_Counter_TIM4 += 0xffff;
@@ -43,7 +56,7 @@
 {
     if(TIM5->SR & 0x0001)
     {
-        printf("Overflow Routine");
+        ////printf("Overflow Routine");
         TIM5->SR &= 0xfffe;
         if(!(TIM5->CR1&TIM_CR1_DIR))
             Soft_32_Counter_TIM5 += 0xffff;
@@ -113,6 +126,7 @@
         // Setting the ISR for the corresponding interrupt vector
         switch((uint32_t)TIM)
         {
+            
             case TIM2_BASE :
             NVIC_SetVector(TIM2_IRQn, (uint32_t)&Overflow_Routine_TIM2);
             NVIC_EnableIRQ(TIM2_IRQn);
@@ -160,6 +174,7 @@
         // Setting the ISR for the corresponding interrupt vector
         switch((uint32_t)TIM)
         {
+            
             case TIM2_BASE :
             NVIC_SetVector(TIM2_IRQn, (uint32_t)&Overflow_Routine_TIM2);
             NVIC_EnableIRQ(TIM2_IRQn);
@@ -192,30 +207,64 @@
     }
 
     
-    int32_t Nucleo_Encoder_16_bits::GetCounter()
+    int32_t Nucleo_Encoder_16_bits::GetCounter(bool reset)
     {
         uint16_t count = TIM->CNT;
-        switch((uint32_t)TIM)
-        {
-            case TIM2_BASE :
-            return (int32_t)count + Soft_32_Counter_TIM2;
-            break;
-            
-            case TIM3_BASE :
-            return (int32_t)count + Soft_32_Counter_TIM3;
-            break;
-            
-            case TIM4_BASE :
-            return (int32_t)count + Soft_32_Counter_TIM4;
-            break;
-            
-            case TIM5_BASE :
-            return (int32_t)count + Soft_32_Counter_TIM5;
-            break;
+        if(reset){
+            switch((uint32_t)TIM){
+                case TIM1_BASE :
+                    TIM1->CNT = 0;
+                    Soft_32_Counter_TIM1 = 0;
+                break;
+                
+                case TIM2_BASE :
+                    TIM2->CNT = 0;
+                    Soft_32_Counter_TIM2 = 0;
+                break;
+                
+                case TIM3_BASE :
+                    TIM3->CNT = 0;
+                    Soft_32_Counter_TIM3 = 0;
+                break;
+                
+                case TIM4_BASE :
+                    TIM4->CNT = 0;
+                    Soft_32_Counter_TIM4 = 0;
+                break;
+                
+                case TIM5_BASE :
+                    TIM5->CNT = 0;
+                    Soft_32_Counter_TIM5 = 0;
+                break;
+            }
+        }
+        else{
+            switch((uint32_t)TIM)
+            {
+                case TIM1_BASE :
+                    return (int32_t)count + Soft_32_Counter_TIM1;
+                break;
+                
+                case TIM2_BASE :
+                    return (int32_t)count + Soft_32_Counter_TIM2;
+                break;
+                
+                case TIM3_BASE :
+                    return (int32_t)count + Soft_32_Counter_TIM3;
+                break;
+                
+                case TIM4_BASE :
+                    return (int32_t)count + Soft_32_Counter_TIM4;
+                break;
+                
+                case TIM5_BASE :
+                    return (int32_t)count + Soft_32_Counter_TIM5;
+                break;
+            }
         }
         
         return (int32_t)count;
-    } 
+    }
     
     TIM_HandleTypeDef* Nucleo_Encoder_16_bits::GetTimer()
     {