DCS_TEAM / DPG_FINAL

uses pushing box to publish to google spreadsheets with a state machine instead of a while loop

Dependents:   DCS_FINAL_CODE

Fork of GSM_PUSHING_BOX_STATE_MACHINE by DCS_TEAM

GSMLibrary.cpp@17:360afa1e6809, 2015-03-07 (annotated)

Committer:
danilob
Date:
Sat Mar 07 23:35:12 2015 +0000
Revision:
17:360afa1e6809
Parent:
16:6807d437cd48
Child:
18:7642909bfcfc
addign h file

Who changed what in which revision?

UserRevisionLine numberNew contents of line
danilob 0:41904adca656 1 #include "GSMLibrary.h"
danilob 0:41904adca656 2 #include "gsmqueue.h"
danilob 2:8352ad91f2ee 3 #include <string.h>
danilob 0:41904adca656 4
danilob 15:19ae032e2e54 5 #define TIME_CONST .3
danilob 15:19ae032e2e54 6 #define SECONDS_TIMEOUT 40
danilob 15:19ae032e2e54 7 #define TIMEOUTLIMIT SECONDS_TIMEOUT/TIME_CONST //$change check with main code this will set up condition fior timeout.
danilob 0:41904adca656 8
danilob 0:41904adca656 9 //definition for AT comands
danilob 0:41904adca656 10 #define AT_OK "AT"
danilob 0:41904adca656 11 #define AT_CSQ "AT+CSQ"
danilob 0:41904adca656 12 #define AT_CREG "AT+CREG?"
danilob 0:41904adca656 13 #define AT_CMGF "AT+CMGF=1"
danilob 0:41904adca656 14 #define RECEIVER_PHONE_NUMBER "\"+18014722842\""
danilob 0:41904adca656 15 #define AT_CMGS "AT+CMGS=" RECEIVER_PHONE_NUMBER
danilob 15:19ae032e2e54 16 #define MESSAGE_BODY "stress test\32\32"
danilob 0:41904adca656 17
es_marble 16:6807d437cd48 18 //Definition for AT repsonses
danilob 0:41904adca656 19 //Please notice that after ":" the gsm will usually send aditional information
danilob 0:41904adca656 20 #define AT_OK_RESPONSE "OK" //Response after sending "AT" message
es_marble 6:3ccc86304c2c 21 #define AT_CSQ_RESPONSE "+CSQ:" //+CSQ: <arg1>,<arg2> where <arg1> is signal strength arg1 = 0-30 where a number below 10 means low signal strength and 99 is not knwn or detectable signal and arg2 is bit error rate form 0-7, 99 will represent error
danilob 13:9ac5ff131214 22 #define AT_CREG_RESPONSE "+CREG:"//+CREG: <arg1>,<arg2> where <arg1> = 0-2(see AT command descriptions), <arg2> = 0-5, 0 not registered to nework and not looking for one. 1 is conected to network, 2 is not conected but searching
danilob 0:41904adca656 23 #define AT_CMGF_RESPONSE "OK"
danilob 14:56a2c371ce18 24 #define AT_CMGS_RESPONSE ">" //Message is written aftersymbol
danilob 15:19ae032e2e54 25 #define AT_SENDSMS_RESPONSE ">" // +CMGS: <id> this will include the message id. CMGS ERROR for error and
danilob 17:360afa1e6809 26 #define AT_SUCCESS_RESPONSE "+CMGS:"
danilob 0:41904adca656 27
es_marble 16:6807d437cd48 28 //External variables
danilob 0:41904adca656 29 extern Serial pc;
danilob 0:41904adca656 30 extern Serial gsm;
danilob 0:41904adca656 31 extern uint8_t buffer[BUFFER_LENGTH];//buffer storing char
es_marble 16:6807d437cd48 32
es_marble 16:6807d437cd48 33 //Internal variables
danilob 0:41904adca656 34 gsm_states gsm_current_state = GSM_INITIALIZE;
danilob 0:41904adca656 35 char send = 0;
danilob 12:f3ccc43c4d3c 36 int timeout_count = 0;
danilob 0:41904adca656 37
es_marble 16:6807d437cd48 38 void gsm_tick()
es_marble 16:6807d437cd48 39 {
es_marble 16:6807d437cd48 40 if (getGSMIdleBit() || gsm_timeOut() || (send && gsm_current_state == GSM_INITIALIZE)) //question with send...
es_marble 16:6807d437cd48 41 {
es_marble 16:6807d437cd48 42 resetGSMIdleBit(); //reset GSM idle bit
es_marble 16:6807d437cd48 43 gsm_nextStateLogic(); //Next state
es_marble 16:6807d437cd48 44 gsm_mealyOutputs(); //Mealy outputs
es_marble 16:6807d437cd48 45 flushQueue(); //Flush the queue
es_marble 16:6807d437cd48 46 }
es_marble 16:6807d437cd48 47 }
es_marble 16:6807d437cd48 48
es_marble 16:6807d437cd48 49
es_marble 16:6807d437cd48 50
es_marble 16:6807d437cd48 51 //Advance timeout counter; if timeout, return true
es_marble 16:6807d437cd48 52 bool gsm_timeOut()
es_marble 16:6807d437cd48 53 {
es_marble 16:6807d437cd48 54 if(++timeout_count >= TIMEOUTLIMIT){
danilob 15:19ae032e2e54 55 timeout_count=0;
danilob 15:19ae032e2e54 56 gsm_current_state = GSM_INITIALIZE;
es_marble 16:6807d437cd48 57 return true;
danilob 15:19ae032e2e54 58 }
es_marble 16:6807d437cd48 59 else
es_marble 16:6807d437cd48 60 return false;
es_marble 16:6807d437cd48 61 }
es_marble 16:6807d437cd48 62
es_marble 16:6807d437cd48 63 //Next state logic -----------------------------------------------------
es_marble 16:6807d437cd48 64 void gsm_nextStateLogic()
es_marble 16:6807d437cd48 65 {
es_marble 16:6807d437cd48 66 printQueue(); //$debug
es_marble 16:6807d437cd48 67
es_marble 16:6807d437cd48 68 switch(gsm_current_state)
es_marble 16:6807d437cd48 69 {
danilob 0:41904adca656 70 case GSM_INITIALIZE:
es_marble 16:6807d437cd48 71 pc.printf("gsm_initialize state\r\n");//&debug
danilob 2:8352ad91f2ee 72 timeout_count = 0;
es_marble 16:6807d437cd48 73 if (send)
es_marble 16:6807d437cd48 74 gsm_current_state = GSM_AT_OK; //unconditional (check it)
danilob 0:41904adca656 75 break;
danilob 0:41904adca656 76 case GSM_AT_OK:
danilob 12:f3ccc43c4d3c 77 pc.printf("inside AT_OK state\r\n");//&debug
es_marble 16:6807d437cd48 78 if (findInQueue(AT_OK_RESPONSE))
es_marble 16:6807d437cd48 79 gsm_current_state = GSM_AT_CSQ;
danilob 12:f3ccc43c4d3c 80 break;
danilob 12:f3ccc43c4d3c 81 case GSM_AT_CSQ:
danilob 12:f3ccc43c4d3c 82 pc.printf("inside AT_CSQ state \r\n");//&debug
es_marble 16:6807d437cd48 83 if(findInQueue(AT_CSQ_RESPONSE))
es_marble 16:6807d437cd48 84 gsm_current_state = GSM_AT_CREG;
danilob 2:8352ad91f2ee 85 break;
danilob 0:41904adca656 86 case GSM_AT_CREG:
danilob 7:6c0b6ab3cafe 87 pc.printf("gsm_creg state\r\n");//&debug
es_marble 16:6807d437cd48 88 if(findInQueue(AT_CREG_RESPONSE))
es_marble 16:6807d437cd48 89 {
es_marble 16:6807d437cd48 90 pc.printf("creg parse Int1: %d\r\n",parseInt());//&debug
es_marble 16:6807d437cd48 91 int q = parseInt();
es_marble 16:6807d437cd48 92 pc.printf("creg parse Int2: %d\r\n",q);//&debug
es_marble 16:6807d437cd48 93 if(q == 1)
es_marble 16:6807d437cd48 94 gsm_current_state = GSM_AT_CMGF;
danilob 12:f3ccc43c4d3c 95 }
danilob 0:41904adca656 96 break;
danilob 0:41904adca656 97 case GSM_AT_CMGF:
danilob 12:f3ccc43c4d3c 98 pc.printf("gsm_cmgf state\r\n");//&debug
es_marble 16:6807d437cd48 99 if(findInQueue(AT_CMGF_RESPONSE))
es_marble 16:6807d437cd48 100 gsm_current_state = GSM_AT_CMGS;
danilob 0:41904adca656 101 break;
danilob 0:41904adca656 102 case GSM_AT_CMGS:
es_marble 16:6807d437cd48 103 pc.printf("gsm_cmgs state\r\n");//&debug
es_marble 16:6807d437cd48 104 if(findInQueue(AT_CMGS_RESPONSE))
es_marble 16:6807d437cd48 105 gsm_current_state = GSM_AT_SENDSMS;
danilob 0:41904adca656 106 break;
danilob 0:41904adca656 107 case GSM_AT_SENDSMS:
danilob 12:f3ccc43c4d3c 108 pc.printf("gsm_send_sms state\r\n");//&debug
es_marble 16:6807d437cd48 109 if(findInQueue(AT_SENDSMS_RESPONSE))
es_marble 16:6807d437cd48 110 gsm_current_state = GSM_SUCCESS;
es_marble 16:6807d437cd48 111 else
es_marble 16:6807d437cd48 112 gsm_current_state = GSM_AT_CMGS; //The only spot we can go backwards
danilob 0:41904adca656 113 break;
danilob 0:41904adca656 114 case GSM_SUCCESS:
danilob 7:6c0b6ab3cafe 115 pc.printf("gsm_success state\r\n");//&debug
danilob 17:360afa1e6809 116 if(findInQueue(AT_SUCCESS_RESPONSE)) //This appears to be a bug. It was in Danilo's original code as well.
es_marble 16:6807d437cd48 117 pc.printf("Message SENT! msgID: %iY\r\n",parseInt());//&debug
es_marble 16:6807d437cd48 118 gsm_current_state = GSM_AT_CMGS; //Confusing part. Do we always go backwards here?
danilob 0:41904adca656 119 break;
danilob 0:41904adca656 120 default:
danilob 0:41904adca656 121 pc.printf("This is a state error");
danilob 0:41904adca656 122 }
danilob 0:41904adca656 123 }
es_marble 16:6807d437cd48 124
es_marble 16:6807d437cd48 125 //Mealy output logic ------------------------------------------------------
es_marble 16:6807d437cd48 126 void gsm_mealyOutputs()
es_marble 16:6807d437cd48 127 {
es_marble 16:6807d437cd48 128 switch(gsm_current_state)
es_marble 16:6807d437cd48 129 {
es_marble 16:6807d437cd48 130 case GSM_INITIALIZE:
es_marble 16:6807d437cd48 131 pc.printf("No Mealy initialize state output\r\n");//&debug
es_marble 16:6807d437cd48 132 break;
es_marble 16:6807d437cd48 133 case GSM_AT_OK:
es_marble 16:6807d437cd48 134 pc.printf("sending AT_OK\r\n");//&debug
es_marble 16:6807d437cd48 135 gsm.puts(AT_OK);
es_marble 16:6807d437cd48 136 gsm.puts("\r\n");
es_marble 16:6807d437cd48 137 break;
es_marble 16:6807d437cd48 138 case GSM_AT_CSQ:
es_marble 16:6807d437cd48 139 pc.printf("sending AT_CSQ\r\n");//&debug
es_marble 16:6807d437cd48 140 gsm.puts(AT_CSQ);
es_marble 16:6807d437cd48 141 gsm.puts("\r\n");
es_marble 16:6807d437cd48 142 break;
es_marble 16:6807d437cd48 143 case GSM_AT_CREG:
es_marble 16:6807d437cd48 144 pc.printf("sending AT_CREG\r\n");//&debug
es_marble 16:6807d437cd48 145 gsm.puts(AT_CREG);
es_marble 16:6807d437cd48 146 gsm.puts("\r\n");
es_marble 16:6807d437cd48 147 break;
es_marble 16:6807d437cd48 148 case GSM_AT_CMGF:
es_marble 16:6807d437cd48 149 pc.printf("sending AT_CMGF\r\n");//&debug
es_marble 16:6807d437cd48 150 gsm.puts(AT_CMGF);
es_marble 16:6807d437cd48 151 gsm.puts("\r\n");
es_marble 16:6807d437cd48 152 break;
es_marble 16:6807d437cd48 153 case GSM_AT_CMGS:
es_marble 16:6807d437cd48 154 pc.printf("sending AT_CMGS\r\n");//&debug
es_marble 16:6807d437cd48 155 gsm.puts(AT_CMGS);
es_marble 16:6807d437cd48 156 gsm.puts("\r\n");
es_marble 16:6807d437cd48 157 break;
es_marble 16:6807d437cd48 158 case GSM_AT_SENDSMS:
es_marble 16:6807d437cd48 159 pc.printf("sending MESSAGE_BODY\r\n");//&debug
es_marble 16:6807d437cd48 160 gsm.puts(MESSAGE_BODY); //substitute char included
es_marble 16:6807d437cd48 161 gsm.puts("\r\n");
es_marble 16:6807d437cd48 162 break;
es_marble 16:6807d437cd48 163 case GSM_SUCCESS:
es_marble 16:6807d437cd48 164 pc.printf("No Mealy success state output\r\n");//&debug
es_marble 16:6807d437cd48 165 default:
es_marble 16:6807d437cd48 166 pc.printf("This is a state error");
es_marble 16:6807d437cd48 167 }
es_marble 16:6807d437cd48 168 }
es_marble 16:6807d437cd48 169
danilob 7:6c0b6ab3cafe 170 //set send falg on
danilob 7:6c0b6ab3cafe 171 void gsm_send_sms(){
danilob 7:6c0b6ab3cafe 172 send = 1;
danilob 7:6c0b6ab3cafe 173 }
es_marble 16:6807d437cd48 174
danilob 0:41904adca656 175 //
danilob 0:41904adca656 176 void gsm_reset();
danilob 0:41904adca656 177
danilob 0:41904adca656 178
danilob 0:41904adca656 179 //
es_marble 16:6807d437cd48 180 void gsm_initialize(){
danilob 7:6c0b6ab3cafe 181 SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK; //enabling dmamux clock
danilob 12:f3ccc43c4d3c 182 SIM_SCGC7 |= SIM_SCGC7_DMA_MASK; // enebaling dma clock
es_marble 16:6807d437cd48 183 pc.printf("initializing registers...!\r\n");
danilob 0:41904adca656 184 // control register mux, enabling uart3 receive
danilob 0:41904adca656 185 DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK|DMAMUX_CHCFG_SOURCE(8);
danilob 0:41904adca656 186
danilob 0:41904adca656 187 // Enable request signal for channel 0
danilob 0:41904adca656 188 DMA_ERQ = DMA_ERQ_ERQ0_MASK;
danilob 0:41904adca656 189
danilob 0:41904adca656 190 // select round-robin arbitration priority
danilob 0:41904adca656 191 DMA_CR |= DMA_CR_ERCA_MASK;
danilob 0:41904adca656 192
danilob 0:41904adca656 193 //enabled error interrupt for DMA0
danilob 0:41904adca656 194 //DMA_EEI = DMA_EEI_EEI0_MASK ;
danilob 0:41904adca656 195 //Addres for buffer
danilob 0:41904adca656 196 DMA_TCD0_SADDR = (uint32_t) &UART_D_REG(UART3_BASE_PTR);
danilob 0:41904adca656 197 DMA_TCD0_DADDR = (uint32_t) buffer;
danilob 0:41904adca656 198 // Set an offset for source and destination address
danilob 0:41904adca656 199 DMA_TCD0_SOFF = 0x00;
danilob 0:41904adca656 200 DMA_TCD0_DOFF = 0x01; // Destination address offset of 1 byte per transaction
danilob 0:41904adca656 201
danilob 0:41904adca656 202 // Set source and destination data transfer size
danilob 0:41904adca656 203 DMA_TCD0_ATTR = DMA_ATTR_SSIZE(0) | DMA_ATTR_DSIZE(0);
danilob 0:41904adca656 204
danilob 0:41904adca656 205 // Number of bytes to be transfered in each service request of the channel
danilob 0:41904adca656 206 DMA_TCD0_NBYTES_MLNO = 0x01;
danilob 0:41904adca656 207 // Current major iteration count
danilob 0:41904adca656 208 DMA_TCD0_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(BUFFER_LENGTH);
danilob 0:41904adca656 209 DMA_TCD0_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(BUFFER_LENGTH);
danilob 0:41904adca656 210 // Adjustment value used to restore the source and destiny address to the initial value
danilob 0:41904adca656 211 // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
es_marble 16:6807d437cd48 212 DMA_TCD0_SLAST = 0; // Source address adjustment
es_marble 16:6807d437cd48 213 DMA_TCD0_DLASTSGA = -BUFFER_LENGTH; // Destination address adjustment
danilob 0:41904adca656 214 // Setup control and status register
danilob 0:41904adca656 215 DMA_TCD0_CSR = 0;
danilob 0:41904adca656 216
danilob 0:41904adca656 217 // enable interrupt call at end of major loop
danilob 0:41904adca656 218 DMA_TCD0_CSR |= DMA_CSR_INTMAJOR_MASK;
danilob 0:41904adca656 219
danilob 0:41904adca656 220 //Activate dma trasnfer rx interrupt
danilob 0:41904adca656 221 UART_C2_REG(UART3) |= UART_C2_RIE_MASK;
danilob 0:41904adca656 222 UART_C5_REG(UART3) |= UART_C5_RDMAS_MASK | UART_C5_ILDMAS_MASK | UART_C5_LBKDDMAS_MASK;
danilob 0:41904adca656 223 //activate p fifo
danilob 0:41904adca656 224 UART_PFIFO_REG(UART3) |= UART_PFIFO_RXFE_MASK; //RXFE and buffer size of 1 word
danilob 7:6c0b6ab3cafe 225 queueInit();
danilob 0:41904adca656 226 pc.printf("Initialization done...\n\r");
danilob 0:41904adca656 227 }
danilob 0:41904adca656 228
danilob 0:41904adca656 229
danilob 0:41904adca656 230
danilob 0:41904adca656 231 //initialization debuging purposes
danilob 0:41904adca656 232 void print_registers() {
danilob 0:41904adca656 233
danilob 0:41904adca656 234
danilob 0:41904adca656 235 pc.printf("\n\rDMA REGISTERS\n\r");
danilob 0:41904adca656 236 pc.printf("DMA_MUX: 0x%08x\r\n",DMAMUX_CHCFG0);
danilob 0:41904adca656 237 pc.printf("SADDR0: 0x%08x\r\n",DMA_TCD0_SADDR);
danilob 0:41904adca656 238 pc.printf("DADDR0: 0x%08x\r\n",DMA_TCD0_DADDR);
danilob 0:41904adca656 239 pc.printf("CITER0: 0x%08x\r\n",DMA_TCD0_CITER_ELINKNO);
danilob 0:41904adca656 240 pc.printf("BITER0: 0x%08x\r\n",DMA_TCD0_BITER_ELINKNO);
danilob 0:41904adca656 241 pc.printf("DMA_CR: %08x\r\n", DMA_CR);
danilob 0:41904adca656 242 pc.printf("DMA_ES: %08x\r\n", DMA_ES);
danilob 0:41904adca656 243 pc.printf("DMA_ERQ: %08x\r\n", DMA_ERQ);
danilob 0:41904adca656 244 pc.printf("DMA_EEI: %08x\r\n", DMA_EEI);
danilob 0:41904adca656 245 pc.printf("DMA_CEEI: %02x\r\n", DMA_CEEI);
danilob 0:41904adca656 246 pc.printf("DMA_SEEI: %02x\r\n", DMA_SEEI);
danilob 0:41904adca656 247 pc.printf("DMA_CERQ: %02x\r\n", DMA_CERQ);
danilob 0:41904adca656 248 pc.printf("DMA_SERQ: %02x\r\n", DMA_SERQ);
danilob 0:41904adca656 249 pc.printf("DMA_CDNE: %02x\r\n", DMA_CDNE);
danilob 0:41904adca656 250 pc.printf("DMA_SSRT: %02x\r\n", DMA_SSRT);
danilob 0:41904adca656 251 pc.printf("DMA_CERR: %02x\r\n", DMA_CERR);
danilob 0:41904adca656 252 pc.printf("DMA_CINT: %02x\r\n", DMA_CINT);
danilob 0:41904adca656 253 pc.printf("DMA_INT: %08x\r\n", DMA_INT);
danilob 0:41904adca656 254 pc.printf("DMA_ERR: %08x\r\n", DMA_ERR);
danilob 0:41904adca656 255 pc.printf("DMA_HRS: %08x\r\n", DMA_HRS);
danilob 0:41904adca656 256 pc.printf("DMA_TCD0_DOFF: %08x\r\n",DMA_TCD0_DOFF);
danilob 0:41904adca656 257 pc.printf("\n\rUART REGISTERS\n\r");
danilob 0:41904adca656 258 pc.printf("UART_BDH_REG: %08x\r\n",UART_BDH_REG(UART3));
danilob 0:41904adca656 259 pc.printf("UART_C1_REG: %08x\r\n",UART_C1_REG(UART3));
danilob 0:41904adca656 260 pc.printf("UART_C2_REG: %08x\r\n",UART_C2_REG(UART3));
danilob 0:41904adca656 261 pc.printf("UART_S1_REG: %08x\r\n",UART_S1_REG(UART3));
es_marble 16:6807d437cd48 262 pc.printf("UART_s2_REG: %08x\r\n",UART_S2_REG(UART3));
danilob 0:41904adca656 263 pc.printf("UART_C3_REG: %08x\r\n",UART_C3_REG(UART3));
danilob 0:41904adca656 264 pc.printf("UART_D_REG: %08x\r\n",UART_D_REG(UART3));
danilob 0:41904adca656 265 pc.printf("UART_MA1_REG: %08x\r\n",UART_MA1_REG(UART3));
danilob 0:41904adca656 266 pc.printf("UART_MA2_REG: %08x\r\n",UART_MA2_REG(UART3));
danilob 0:41904adca656 267 pc.printf("UART_C4_REG: %08x\r\n",UART_C4_REG(UART3));
danilob 0:41904adca656 268 pc.printf("UART_C5_REG: %08x\r\n",UART_C5_REG(UART3));
es_marble 16:6807d437cd48 269 pc.printf("UART_ED_REG: %08x\r\n",UART_ED_REG(UART3));
danilob 0:41904adca656 270 pc.printf("UART_MODEM_REG: %08x\r\n",UART_MODEM_REG(UART3));
danilob 0:41904adca656 271 pc.printf("UART_IR_REG: %08x\r\n",UART_IR_REG(UART3));
danilob 0:41904adca656 272 pc.printf("UART_PFIFO_REG: %08x\r\n",UART_PFIFO_REG(UART3));
danilob 0:41904adca656 273 pc.printf("UART_CFIFO_REG: %08x\r\n",UART_CFIFO_REG(UART3));
danilob 0:41904adca656 274 pc.printf("UART_SFIFO_REG: %08x\r\n",UART_SFIFO_REG(UART3));
danilob 0:41904adca656 275 pc.printf("UART_TWFIFO_REG: %08x\r\n",UART_TWFIFO_REG(UART3));
danilob 0:41904adca656 276 pc.printf("UART_TCFIFO_REG: %08x\r\n",UART_TCFIFO_REG(UART3));
danilob 0:41904adca656 277 pc.printf("UART_RWFIFO_REG: %08x\r\n",UART_RWFIFO_REG(UART3));
danilob 0:41904adca656 278 pc.printf("UART_RCFIFO_REG: %08x\r\n",UART_RCFIFO_REG(UART3));
danilob 0:41904adca656 279
danilob 0:41904adca656 280 }