DCS_TEAM / DPG_FINAL

uses pushing box to publish to google spreadsheets with a state machine instead of a while loop

Dependents:   DCS_FINAL_CODE

Fork of GSM_PUSHING_BOX_STATE_MACHINE by DCS_TEAM

GSMLibrary.cpp@13:9ac5ff131214, 2015-03-06 (annotated)

Committer:
danilob
Date:
Fri Mar 06 01:11:58 2015 +0000
Revision:
13:9ac5ff131214
Parent:
12:f3ccc43c4d3c
Child:
14:56a2c371ce18
yes!

Who changed what in which revision?

UserRevisionLine numberNew contents of line
danilob 0:41904adca656 1 #include "GSMLibrary.h"
danilob 0:41904adca656 2 #include "gsmqueue.h"
danilob 2:8352ad91f2ee 3 #include <string.h>
danilob 0:41904adca656 4
danilob 2:8352ad91f2ee 5 #define TIME_CONST 1
danilob 12:f3ccc43c4d3c 6 #define SECONDS_TIMEOUT 100
danilob 2:8352ad91f2ee 7 #define TIMEOUTLIMIT TIME_CONST //$change check with main code this will set up condition fior timeout.
danilob 0:41904adca656 8
danilob 0:41904adca656 9 //definition for AT comands
danilob 0:41904adca656 10 #define AT_OK "AT"
danilob 0:41904adca656 11 #define AT_CSQ "AT+CSQ"
danilob 0:41904adca656 12 #define AT_CREG "AT+CREG?"
danilob 0:41904adca656 13 #define AT_CMGF "AT+CMGF=1"
danilob 0:41904adca656 14 #define RECEIVER_PHONE_NUMBER "\"+18014722842\""
danilob 0:41904adca656 15 #define AT_CMGS "AT+CMGS=" RECEIVER_PHONE_NUMBER
danilob 12:f3ccc43c4d3c 16 #define MESSAGE_BODY "hi joseph"
danilob 0:41904adca656 17
danilob 0:41904adca656 18 //Definition for at repsonses
danilob 0:41904adca656 19 //Please notice that after ":" the gsm will usually send aditional information
danilob 0:41904adca656 20 #define AT_OK_RESPONSE "OK" //Response after sending "AT" message
es_marble 6:3ccc86304c2c 21 #define AT_CSQ_RESPONSE "+CSQ:" //+CSQ: <arg1>,<arg2> where <arg1> is signal strength arg1 = 0-30 where a number below 10 means low signal strength and 99 is not knwn or detectable signal and arg2 is bit error rate form 0-7, 99 will represent error
danilob 13:9ac5ff131214 22 #define AT_CREG_RESPONSE "+CREG:"//+CREG: <arg1>,<arg2> where <arg1> = 0-2(see AT command descriptions), <arg2> = 0-5, 0 not registered to nework and not looking for one. 1 is conected to network, 2 is not conected but searching
danilob 0:41904adca656 23 #define AT_CMGF_RESPONSE "OK"
danilob 13:9ac5ff131214 24 #define AT_CMGS_RESPONSE "> " //Message is written aftersymbol
danilob 0:41904adca656 25 #define AT_SENDSMS_RESPONSE "+CMGS:" // +CMGS: <id> this will include the message id. CMGS ERROR for error and
danilob 0:41904adca656 26 #define AT_SUCCESS_REPSONSE "OK"
danilob 0:41904adca656 27
danilob 0:41904adca656 28
danilob 0:41904adca656 29 extern Serial pc;
danilob 0:41904adca656 30 extern Serial gsm;
danilob 0:41904adca656 31 extern uint8_t buffer[BUFFER_LENGTH];//buffer storing char
danilob 0:41904adca656 32 gsm_states gsm_current_state = GSM_INITIALIZE;
danilob 0:41904adca656 33
danilob 0:41904adca656 34 char correct = 0;
danilob 0:41904adca656 35 char send = 0;
danilob 12:f3ccc43c4d3c 36 int timeout_count = 0;
danilob 0:41904adca656 37 char received = 0;
danilob 2:8352ad91f2ee 38 char timeout_limit = TIMEOUTLIMIT;
danilob 0:41904adca656 39
danilob 0:41904adca656 40 void gsm_tick(){
danilob 0:41904adca656 41
danilob 0:41904adca656 42 //post action
danilob 12:f3ccc43c4d3c 43 //if(++timeout_count >= timeout_limit){
danilob 12:f3ccc43c4d3c 44 // timeout_count=0;
danilob 12:f3ccc43c4d3c 45 // gsm_current_state = GSM_INITIALIZE;
danilob 12:f3ccc43c4d3c 46 //}
danilob 0:41904adca656 47 switch(gsm_current_state){
danilob 2:8352ad91f2ee 48 //when send flag is on , send AT_OK message to gsm.
danilob 0:41904adca656 49 case GSM_INITIALIZE:
danilob 2:8352ad91f2ee 50 pc.printf("gsm_initilize state\r\n");//&debug
danilob 2:8352ad91f2ee 51 timeout_count = 0;
danilob 2:8352ad91f2ee 52 if(send){ //send first at_ok message
danilob 2:8352ad91f2ee 53 resetGSMIdleBit();
danilob 2:8352ad91f2ee 54 pc.printf("sending AT_OK\r\n");//&debug
danilob 0:41904adca656 55 gsm.puts(AT_OK);
danilob 12:f3ccc43c4d3c 56 gsm.puts("\r\n");
danilob 2:8352ad91f2ee 57 gsm_current_state = GSM_AT_OK;
danilob 0:41904adca656 58 }
danilob 0:41904adca656 59 else
danilob 0:41904adca656 60 gsm_current_state = GSM_INITIALIZE;
danilob 0:41904adca656 61 break;
danilob 12:f3ccc43c4d3c 62
danilob 2:8352ad91f2ee 63 // check for repsonse to AT and if correct send AT+CSQ message
danilob 0:41904adca656 64 case GSM_AT_OK:
danilob 12:f3ccc43c4d3c 65 pc.printf("inside AT_OK state\r\n");//&debug
danilob 2:8352ad91f2ee 66 if(getGSMIdleBit()){
danilob 2:8352ad91f2ee 67 printQueue(); //$debug
danilob 12:f3ccc43c4d3c 68 if(findInQueue(AT_OK_RESPONSE)){
danilob 2:8352ad91f2ee 69 resetGSMIdleBit();
danilob 2:8352ad91f2ee 70 pc.printf("sending AT_CSQ\r\n");//&debug
danilob 2:8352ad91f2ee 71 gsm.puts(AT_CSQ);
danilob 2:8352ad91f2ee 72 gsm.puts("\r\n");
danilob 2:8352ad91f2ee 73 gsm_current_state = GSM_AT_CSQ;
danilob 2:8352ad91f2ee 74 }
danilob 12:f3ccc43c4d3c 75 else{
danilob 12:f3ccc43c4d3c 76 gsm.puts(AT_OK);
danilob 12:f3ccc43c4d3c 77 gsm.puts("\r\n");
danilob 12:f3ccc43c4d3c 78 }
danilob 2:8352ad91f2ee 79 }
danilob 12:f3ccc43c4d3c 80 break;
danilob 12:f3ccc43c4d3c 81
danilob 12:f3ccc43c4d3c 82 //CHECK FOR RESPOSE TO at+csq AND SEND at+creg
danilob 12:f3ccc43c4d3c 83 case GSM_AT_CSQ:
danilob 12:f3ccc43c4d3c 84 pc.printf("inside AT_CSQ state \r\n");//&debug
danilob 12:f3ccc43c4d3c 85 if(getGSMIdleBit()){
danilob 12:f3ccc43c4d3c 86 printQueue(); //$debug
danilob 12:f3ccc43c4d3c 87 if(findInQueue(AT_CSQ_RESPONSE)){
danilob 12:f3ccc43c4d3c 88 if(parseInt() > 9){
danilob 12:f3ccc43c4d3c 89 resetGSMIdleBit();
danilob 12:f3ccc43c4d3c 90 pc.printf("sending AT_CREG\r\n");//&debug
danilob 12:f3ccc43c4d3c 91 gsm.puts(AT_CREG);
danilob 12:f3ccc43c4d3c 92 gsm.puts("\r\n");
danilob 12:f3ccc43c4d3c 93 gsm_current_state = GSM_AT_CREG;
danilob 12:f3ccc43c4d3c 94 }
danilob 12:f3ccc43c4d3c 95 }
danilob 12:f3ccc43c4d3c 96 else{
danilob 12:f3ccc43c4d3c 97 gsm.puts(AT_CSQ);
danilob 12:f3ccc43c4d3c 98 gsm.puts("\r\n");
danilob 12:f3ccc43c4d3c 99 }
danilob 12:f3ccc43c4d3c 100 }
danilob 2:8352ad91f2ee 101 break;
danilob 0:41904adca656 102
danilob 12:f3ccc43c4d3c 103 //check for AT creg and if correct send AT+CMGF
danilob 0:41904adca656 104 case GSM_AT_CREG:
danilob 7:6c0b6ab3cafe 105 pc.printf("gsm_creg state\r\n");//&debug
danilob 12:f3ccc43c4d3c 106 if(getGSMIdleBit()){
danilob 12:f3ccc43c4d3c 107 printQueue(); //$debug
danilob 12:f3ccc43c4d3c 108 if(findInQueue(AT_CREG_RESPONSE)){
danilob 13:9ac5ff131214 109 pc.printf("creg parse Int1: %d\r\n",parseInt());//&debug
danilob 13:9ac5ff131214 110 int q = parseInt();
danilob 13:9ac5ff131214 111 pc.printf("creg parse Int2: %d\r\n",q);//&debug
danilob 13:9ac5ff131214 112 if(q == 1){
danilob 12:f3ccc43c4d3c 113 resetGSMIdleBit();
danilob 12:f3ccc43c4d3c 114 pc.printf("sending AT_CMGF\r\n");//&debug
danilob 12:f3ccc43c4d3c 115 gsm.puts(AT_CMGF);
danilob 12:f3ccc43c4d3c 116 gsm.puts("\r\n");
danilob 12:f3ccc43c4d3c 117 gsm_current_state = GSM_AT_CMGF;
danilob 12:f3ccc43c4d3c 118 }
danilob 12:f3ccc43c4d3c 119 }
danilob 12:f3ccc43c4d3c 120 if(gsm_current_state == GSM_AT_CREG){
danilob 12:f3ccc43c4d3c 121 gsm.puts(AT_CREG);
danilob 12:f3ccc43c4d3c 122 gsm.puts("\r\n");
danilob 12:f3ccc43c4d3c 123 }
danilob 12:f3ccc43c4d3c 124 }
danilob 0:41904adca656 125 break;
danilob 12:f3ccc43c4d3c 126
danilob 12:f3ccc43c4d3c 127 //check for cmgf esponse and if correct go to at_cmgs
danilob 0:41904adca656 128 case GSM_AT_CMGF:
danilob 12:f3ccc43c4d3c 129 pc.printf("gsm_cmgf state\r\n");//&debug
danilob 12:f3ccc43c4d3c 130 if(getGSMIdleBit()){
danilob 12:f3ccc43c4d3c 131 printQueue(); //$debug
danilob 12:f3ccc43c4d3c 132 if(findInQueue(AT_CMGF_RESPONSE)){
danilob 12:f3ccc43c4d3c 133 resetGSMIdleBit();
danilob 12:f3ccc43c4d3c 134 pc.printf("sending AT_CMGS\r\n");//&debug
danilob 12:f3ccc43c4d3c 135 gsm.puts(AT_CMGS);
danilob 12:f3ccc43c4d3c 136 gsm.puts("\r\n");
danilob 12:f3ccc43c4d3c 137 gsm_current_state = GSM_AT_CMGS;
danilob 12:f3ccc43c4d3c 138 }
danilob 12:f3ccc43c4d3c 139 else{
danilob 12:f3ccc43c4d3c 140 gsm.puts(AT_CMGF);
danilob 12:f3ccc43c4d3c 141 gsm.puts("\r\n");
danilob 12:f3ccc43c4d3c 142 }
danilob 12:f3ccc43c4d3c 143 }
danilob 0:41904adca656 144 break;
danilob 12:f3ccc43c4d3c 145
danilob 12:f3ccc43c4d3c 146 //check cmgs response if correct send SMS
danilob 0:41904adca656 147 case GSM_AT_CMGS:
danilob 7:6c0b6ab3cafe 148 pc.printf("gsm_cmgs state\r\n");//&debug
danilob 12:f3ccc43c4d3c 149 if(getGSMIdleBit()){
danilob 12:f3ccc43c4d3c 150 printQueue(); //$debug
danilob 12:f3ccc43c4d3c 151 if(findInQueue(AT_CMGS_RESPONSE)){
danilob 12:f3ccc43c4d3c 152 resetGSMIdleBit();
danilob 12:f3ccc43c4d3c 153 pc.printf("sending MESSAGE_BODY\r\n");//&debug
danilob 12:f3ccc43c4d3c 154 gsm.puts(MESSAGE_BODY); //substitute
danilob 12:f3ccc43c4d3c 155 gsm.putc((char)26);
danilob 12:f3ccc43c4d3c 156 gsm.puts("\r\n");
danilob 12:f3ccc43c4d3c 157 gsm_current_state = GSM_AT_SENDSMS;
danilob 12:f3ccc43c4d3c 158 }
danilob 12:f3ccc43c4d3c 159 else
danilob 12:f3ccc43c4d3c 160 {
danilob 12:f3ccc43c4d3c 161 gsm.puts(AT_CMGS);
danilob 12:f3ccc43c4d3c 162 gsm.puts("\r\n");
danilob 12:f3ccc43c4d3c 163 }
danilob 12:f3ccc43c4d3c 164 }
danilob 0:41904adca656 165 break;
danilob 12:f3ccc43c4d3c 166
danilob 12:f3ccc43c4d3c 167 //check if message was sent correctly and if so
danilob 0:41904adca656 168 case GSM_AT_SENDSMS:
danilob 12:f3ccc43c4d3c 169 pc.printf("gsm_send_sms state\r\n");//&debug
danilob 12:f3ccc43c4d3c 170 if(getGSMIdleBit()){
danilob 12:f3ccc43c4d3c 171 printQueue(); //$debug
danilob 12:f3ccc43c4d3c 172 if(findInQueue(AT_SENDSMS_RESPONSE)){
danilob 12:f3ccc43c4d3c 173 resetGSMIdleBit();
danilob 12:f3ccc43c4d3c 174 pc.printf("sending message ID: %iY\r\n",parseInt());//&debug
danilob 12:f3ccc43c4d3c 175 gsm_current_state = GSM_SUCCESS;
danilob 12:f3ccc43c4d3c 176 }
danilob 12:f3ccc43c4d3c 177 else
danilob 12:f3ccc43c4d3c 178 {
danilob 12:f3ccc43c4d3c 179 gsm.puts(AT_CMGF);
danilob 12:f3ccc43c4d3c 180 gsm.puts("\r\n");
danilob 12:f3ccc43c4d3c 181 gsm_current_state = GSM_AT_CMGF;
danilob 12:f3ccc43c4d3c 182 }
danilob 12:f3ccc43c4d3c 183 }
danilob 0:41904adca656 184 break;
danilob 12:f3ccc43c4d3c 185
danilob 12:f3ccc43c4d3c 186
danilob 0:41904adca656 187 case GSM_SUCCESS:
danilob 7:6c0b6ab3cafe 188 pc.printf("gsm_success state\r\n");//&debug
danilob 12:f3ccc43c4d3c 189 if(findInQueue(AT_SENDSMS_RESPONSE))
danilob 12:f3ccc43c4d3c 190 pc.printf("Message SENT!\r\n");//&debug
danilob 0:41904adca656 191 gsm_current_state = GSM_INITIALIZE;
danilob 0:41904adca656 192 break;
danilob 0:41904adca656 193 default:
danilob 0:41904adca656 194 pc.printf("This is a state error");
danilob 0:41904adca656 195 }
danilob 0:41904adca656 196
danilob 0:41904adca656 197 }
danilob 7:6c0b6ab3cafe 198 //set send falg on
danilob 7:6c0b6ab3cafe 199 void gsm_send_sms(){
danilob 7:6c0b6ab3cafe 200 send = 1;
danilob 7:6c0b6ab3cafe 201 }
danilob 0:41904adca656 202 //
danilob 0:41904adca656 203 void gsm_reset();
danilob 0:41904adca656 204
danilob 0:41904adca656 205
danilob 0:41904adca656 206 //
danilob 0:41904adca656 207 void gsm_initialize(){
danilob 7:6c0b6ab3cafe 208 SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK; //enabling dmamux clock
danilob 12:f3ccc43c4d3c 209 SIM_SCGC7 |= SIM_SCGC7_DMA_MASK; // enebaling dma clock
danilob 0:41904adca656 210 pc.printf("initializing tregisters...!\r\n");
danilob 0:41904adca656 211 // control register mux, enabling uart3 receive
danilob 0:41904adca656 212 DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK|DMAMUX_CHCFG_SOURCE(8);
danilob 0:41904adca656 213
danilob 0:41904adca656 214 // Enable request signal for channel 0
danilob 0:41904adca656 215 DMA_ERQ = DMA_ERQ_ERQ0_MASK;
danilob 0:41904adca656 216
danilob 0:41904adca656 217 // select round-robin arbitration priority
danilob 0:41904adca656 218 DMA_CR |= DMA_CR_ERCA_MASK;
danilob 0:41904adca656 219
danilob 0:41904adca656 220 //enabled error interrupt for DMA0
danilob 0:41904adca656 221 //DMA_EEI = DMA_EEI_EEI0_MASK ;
danilob 0:41904adca656 222 //Addres for buffer
danilob 0:41904adca656 223 DMA_TCD0_SADDR = (uint32_t) &UART_D_REG(UART3_BASE_PTR);
danilob 0:41904adca656 224 DMA_TCD0_DADDR = (uint32_t) buffer;
danilob 0:41904adca656 225 // Set an offset for source and destination address
danilob 0:41904adca656 226 DMA_TCD0_SOFF = 0x00;
danilob 0:41904adca656 227 DMA_TCD0_DOFF = 0x01; // Destination address offset of 1 byte per transaction
danilob 0:41904adca656 228
danilob 0:41904adca656 229 // Set source and destination data transfer size
danilob 0:41904adca656 230 DMA_TCD0_ATTR = DMA_ATTR_SSIZE(0) | DMA_ATTR_DSIZE(0);
danilob 0:41904adca656 231
danilob 0:41904adca656 232 // Number of bytes to be transfered in each service request of the channel
danilob 0:41904adca656 233 DMA_TCD0_NBYTES_MLNO = 0x01;
danilob 0:41904adca656 234 // Current major iteration count
danilob 0:41904adca656 235 DMA_TCD0_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(BUFFER_LENGTH);
danilob 0:41904adca656 236 DMA_TCD0_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(BUFFER_LENGTH);
danilob 0:41904adca656 237 // Adjustment value used to restore the source and destiny address to the initial value
danilob 0:41904adca656 238 // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
danilob 0:41904adca656 239 DMA_TCD0_SLAST = 0; // Source address adjustment
danilob 0:41904adca656 240 DMA_TCD0_DLASTSGA = -BUFFER_LENGTH; // Destination address adjustment
danilob 0:41904adca656 241 // Setup control and status register
danilob 0:41904adca656 242 DMA_TCD0_CSR = 0;
danilob 0:41904adca656 243
danilob 0:41904adca656 244 // enable interrupt call at end of major loop
danilob 0:41904adca656 245 DMA_TCD0_CSR |= DMA_CSR_INTMAJOR_MASK;
danilob 0:41904adca656 246
danilob 0:41904adca656 247 //Activate dma trasnfer rx interrupt
danilob 0:41904adca656 248 UART_C2_REG(UART3) |= UART_C2_RIE_MASK;
danilob 0:41904adca656 249 UART_C5_REG(UART3) |= UART_C5_RDMAS_MASK | UART_C5_ILDMAS_MASK | UART_C5_LBKDDMAS_MASK;
danilob 0:41904adca656 250 //activate p fifo
danilob 0:41904adca656 251 UART_PFIFO_REG(UART3) |= UART_PFIFO_RXFE_MASK; //RXFE and buffer size of 1 word
danilob 7:6c0b6ab3cafe 252 queueInit();
danilob 0:41904adca656 253 pc.printf("Initialization done...\n\r");
danilob 0:41904adca656 254 }
danilob 0:41904adca656 255
danilob 0:41904adca656 256
danilob 0:41904adca656 257
danilob 0:41904adca656 258 //initialization debuging purposes
danilob 0:41904adca656 259 void print_registers() {
danilob 0:41904adca656 260
danilob 0:41904adca656 261
danilob 0:41904adca656 262 pc.printf("\n\rDMA REGISTERS\n\r");
danilob 0:41904adca656 263 pc.printf("DMA_MUX: 0x%08x\r\n",DMAMUX_CHCFG0);
danilob 0:41904adca656 264 pc.printf("SADDR0: 0x%08x\r\n",DMA_TCD0_SADDR);
danilob 0:41904adca656 265 pc.printf("DADDR0: 0x%08x\r\n",DMA_TCD0_DADDR);
danilob 0:41904adca656 266 pc.printf("CITER0: 0x%08x\r\n",DMA_TCD0_CITER_ELINKNO);
danilob 0:41904adca656 267 pc.printf("BITER0: 0x%08x\r\n",DMA_TCD0_BITER_ELINKNO);
danilob 0:41904adca656 268 pc.printf("DMA_CR: %08x\r\n", DMA_CR);
danilob 0:41904adca656 269 pc.printf("DMA_ES: %08x\r\n", DMA_ES);
danilob 0:41904adca656 270 pc.printf("DMA_ERQ: %08x\r\n", DMA_ERQ);
danilob 0:41904adca656 271 pc.printf("DMA_EEI: %08x\r\n", DMA_EEI);
danilob 0:41904adca656 272 pc.printf("DMA_CEEI: %02x\r\n", DMA_CEEI);
danilob 0:41904adca656 273 pc.printf("DMA_SEEI: %02x\r\n", DMA_SEEI);
danilob 0:41904adca656 274 pc.printf("DMA_CERQ: %02x\r\n", DMA_CERQ);
danilob 0:41904adca656 275 pc.printf("DMA_SERQ: %02x\r\n", DMA_SERQ);
danilob 0:41904adca656 276 pc.printf("DMA_CDNE: %02x\r\n", DMA_CDNE);
danilob 0:41904adca656 277 pc.printf("DMA_SSRT: %02x\r\n", DMA_SSRT);
danilob 0:41904adca656 278 pc.printf("DMA_CERR: %02x\r\n", DMA_CERR);
danilob 0:41904adca656 279 pc.printf("DMA_CINT: %02x\r\n", DMA_CINT);
danilob 0:41904adca656 280 pc.printf("DMA_INT: %08x\r\n", DMA_INT);
danilob 0:41904adca656 281 pc.printf("DMA_ERR: %08x\r\n", DMA_ERR);
danilob 0:41904adca656 282 pc.printf("DMA_HRS: %08x\r\n", DMA_HRS);
danilob 0:41904adca656 283 pc.printf("DMA_TCD0_DOFF: %08x\r\n",DMA_TCD0_DOFF);
danilob 0:41904adca656 284 pc.printf("\n\rUART REGISTERS\n\r");
danilob 0:41904adca656 285 pc.printf("UART_BDH_REG: %08x\r\n",UART_BDH_REG(UART3));
danilob 0:41904adca656 286 pc.printf("UART_C1_REG: %08x\r\n",UART_C1_REG(UART3));
danilob 0:41904adca656 287 pc.printf("UART_C2_REG: %08x\r\n",UART_C2_REG(UART3));
danilob 0:41904adca656 288 pc.printf("UART_S1_REG: %08x\r\n",UART_S1_REG(UART3));
danilob 0:41904adca656 289 pc.printf("UART_s2_REG: %08x\r\n",UART_S2_REG(UART3));
danilob 0:41904adca656 290 pc.printf("UART_C3_REG: %08x\r\n",UART_C3_REG(UART3));
danilob 0:41904adca656 291 pc.printf("UART_D_REG: %08x\r\n",UART_D_REG(UART3));
danilob 0:41904adca656 292 pc.printf("UART_MA1_REG: %08x\r\n",UART_MA1_REG(UART3));
danilob 0:41904adca656 293 pc.printf("UART_MA2_REG: %08x\r\n",UART_MA2_REG(UART3));
danilob 0:41904adca656 294 pc.printf("UART_C4_REG: %08x\r\n",UART_C4_REG(UART3));
danilob 0:41904adca656 295 pc.printf("UART_C5_REG: %08x\r\n",UART_C5_REG(UART3));
danilob 0:41904adca656 296 pc.printf("UART_ED_REG: %08x\r\n",UART_ED_REG(UART3));
danilob 0:41904adca656 297 pc.printf("UART_MODEM_REG: %08x\r\n",UART_MODEM_REG(UART3));
danilob 0:41904adca656 298 pc.printf("UART_IR_REG: %08x\r\n",UART_IR_REG(UART3));
danilob 0:41904adca656 299 pc.printf("UART_PFIFO_REG: %08x\r\n",UART_PFIFO_REG(UART3));
danilob 0:41904adca656 300 pc.printf("UART_CFIFO_REG: %08x\r\n",UART_CFIFO_REG(UART3));
danilob 0:41904adca656 301 pc.printf("UART_SFIFO_REG: %08x\r\n",UART_SFIFO_REG(UART3));
danilob 0:41904adca656 302 pc.printf("UART_TWFIFO_REG: %08x\r\n",UART_TWFIFO_REG(UART3));
danilob 0:41904adca656 303 pc.printf("UART_TCFIFO_REG: %08x\r\n",UART_TCFIFO_REG(UART3));
danilob 0:41904adca656 304 pc.printf("UART_RWFIFO_REG: %08x\r\n",UART_RWFIFO_REG(UART3));
danilob 0:41904adca656 305 pc.printf("UART_RCFIFO_REG: %08x\r\n",UART_RCFIFO_REG(UART3));
danilob 0:41904adca656 306
danilob 0:41904adca656 307 }