File content as of revision 1:f0a5690db73f:

// TODO: 
#include "mbed.h"
#include <string>

#include <stdio.h>
#include "PeripheralNames.h"
#include "PeripheralPins.h"
#include "fsl_adc_hal.h"
#include "fsl_clock_manager.h"
#include "fsl_dspi_hal.h"



Serial pc(USBTX, USBRX);

/*
#if DEBUG
#define DEBUG_PRINT(x) pc.printf(x)
#else
#define DEBUG_PRINT(x) do {} while(0)
#endif
*/
DigitalOut led_red(LED_RED);
DigitalOut led_green(LED_GREEN);
DigitalOut led_blue(LED_BLUE);


#define MAX_FADC 6000000

#define TimerInterruptInMicroSeconds 25 // This is for 40 kHz


#define CarrierFrequency 200

#define ISR_counter_loop_reset 8 // 10 kHz sampling of the signal

int ISR_counter = 1;

#define MaxNumSamples 0  //set to 0 if want continuous sampling (i.e. run forever)
#define NumSamplesAverageInADC 32 //hardware averaging default is 2. values 0..32. Higher values reduce noise and maximum sample rate
#define NumADCbits 16

int CyclesInState = 0;
// While 32 is the minimum, it seems to take a few cycles to get things to work right. 32 + 18 + 18 + 18
#define PreCalculateCycles 256
#define NumCalculatedAverages 500
#define PRINTTIMER 1

int printCounter = 0;

AnalogOut WaveOut(DAC0_OUT);
AnalogIn WaveIn1(A0);
AnalogIn WaveIn2(A2);


double previousTime = 0;


volatile unsigned long counter = 0; //keep track of how many times the timer interrupt executes


volatile int phase_counter = 0;
float twopi = 3.14159265359 * 2;

#define pre_compute_length 4000
float i_mod_pre[pre_compute_length];
float q_mod_pre[pre_compute_length];
int out_val_pre[pre_compute_length]; 

float current_i_mod;
float current_q_mod;


#define lp_fir_length 2048


float x_0_i[lp_fir_length];
float x_0_q[lp_fir_length];
float x_1_i[lp_fir_length];
float x_1_q[lp_fir_length];

float real_ip = 0;
float real_ip_total = 0;
float imag_ip = 0;
float imag_ip_total = 0;
float y_0_squared = 0;
float y_1_squared = 0;

int y_0, y_1;


int max_0 = -1;
int min_0 = 65536;
int max_1 = -1;
int min_1 = 65536;


// Coefficients for FIR low-pass filter
// Order: 511
// Fs = 5000
// Fpass = 5
// Fstop = 25
// Density Factor 20
float lp_filter_coeff[lp_fir_length] = {
2.25877153377331e-06,
2.66244224670397e-07,
2.81092420097884e-07,
2.97200797125842e-07,
3.13057205526705e-07,
3.30279379977406e-07,
3.47320034430519e-07,
3.65790534295599e-07,
3.84037888145959e-07,
4.03659300931941e-07,
4.22883429696171e-07,
4.43414078442301e-07,
4.63474354546465e-07,
4.85127823306893e-07,
5.06629365749489e-07,
5.30402400375842e-07,
5.53883059492054e-07,
5.79062251172147e-07,
6.00698053897355e-07,
6.27541356389415e-07,
6.53603188407001e-07,
6.79457125689371e-07,
7.06900952158772e-07,
7.34607521511639e-07,
7.63210937527310e-07,
7.92457626845786e-07,
8.22319204892483e-07,
8.52904112434704e-07,
8.83993876825403e-07,
9.15965803598408e-07,
9.48565090704124e-07,
9.82217633251451e-07,
1.01643933513151e-06,
1.05143714735623e-06,
1.08676147556840e-06,
1.12300409054529e-06,
1.16035624735089e-06,
1.19822784284488e-06,
1.23612003796729e-06,
1.27597253424280e-06,
1.31548405641171e-06,
1.35656260640872e-06,
1.39768396625082e-06,
1.44009364782760e-06,
1.48263736669695e-06,
1.52645417739943e-06,
1.57052770327227e-06,
1.61590430260585e-06,
1.66152581672090e-06,
1.70832466623602e-06,
1.75531183154730e-06,
1.80354697649463e-06,
1.85213180801677e-06,
1.90190541457320e-06,
1.95172125266670e-06,
2.00274982053528e-06,
2.05440229847222e-06,
2.10671996122087e-06,
2.15960953108923e-06,
2.21344673621392e-06,
2.26753452245018e-06,
2.32270367024371e-06,
2.37811232502338e-06,
2.43461484557276e-06,
2.49131860508909e-06,
2.54904626588095e-06,
2.60694079790385e-06,
2.66588370269542e-06,
2.72502556403521e-06,
2.78515359568984e-06,
2.84534746585168e-06,
2.90651253940365e-06,
2.96789707905998e-06,
3.03026815024548e-06,
3.09250439907414e-06,
3.15586112065294e-06,
3.21917116992942e-06,
3.28329739015491e-06,
3.34755725225876e-06,
3.41254082601689e-06,
3.47759844620301e-06,
3.54333509849531e-06,
3.60908996231663e-06,
3.67551457730312e-06,
3.74192777791326e-06,
3.80892935787303e-06,
3.87581985935145e-06,
3.94325856674703e-06,
4.01062965420015e-06,
4.07851955438422e-06,
4.14618562570372e-06,
4.21424927012473e-06,
4.28219961892930e-06,
4.35043829085821e-06,
4.41836938506806e-06,
4.48672487737745e-06,
4.55459997845769e-06,
4.62281849455623e-06,
4.69055023332375e-06,
4.75852881449136e-06,
4.82598777828551e-06,
4.89357790491499e-06,
4.96055708038026e-06,
5.02759963577756e-06,
5.09401623836012e-06,
5.16043301207036e-06,
5.22609616909151e-06,
5.29163941340404e-06,
5.35641256312241e-06,
5.42102571618858e-06,
5.48469577560834e-06,
5.54811134917779e-06,
5.61062044360571e-06,
5.67265321372291e-06,
5.73373682457175e-06,
5.79431080305923e-06,
5.85377619609459e-06,
5.91266194714808e-06,
5.97030085360536e-06,
6.02728122072791e-06,
6.08294572989760e-06,
6.13786180337324e-06,
6.19132752972891e-06,
6.24392081949063e-06,
6.29499279506742e-06,
6.34512332808420e-06,
6.39358822958236e-06,
6.44096494373972e-06,
6.48662130412141e-06,
6.53110576502919e-06,
6.57367526411895e-06,
6.61504319391059e-06,
6.65439635608727e-06,
6.69234997696170e-06,
6.72823177451458e-06,
6.76256992228003e-06,
6.79475276861382e-06,
6.82527935353772e-06,
6.85350874920331e-06,
6.87995435672755e-06,
6.90400455258515e-06,
6.92617579276020e-06,
6.94581178960161e-06,
6.96341207782413e-06,
6.97837546570650e-06,
6.99121320837930e-06,
7.00126691500350e-06,
7.00904991575129e-06,
7.01399146065940e-06,
7.01649463335420e-06,
7.01598906903671e-06,
7.01299335632421e-06,
7.00682651919766e-06,
6.99805670472170e-06,
6.98598387232265e-06,
6.97115918378061e-06,
6.95293670913433e-06,
6.93184262641915e-06,
6.90721796243191e-06,
6.87956544369715e-06,
6.84826575659092e-06,
6.81383582649206e-06,
6.77563271791333e-06,
6.73414912642070e-06,
6.68879222648781e-06,
6.64004566255543e-06,
6.58726001945506e-06,
6.53097084557196e-06,
6.47057633363911e-06,
6.40649492549257e-06,
6.33820922296577e-06,
6.26611753900958e-06,
6.18969752493548e-06,
6.10938733149237e-06,
6.02460876343180e-06,
5.93581228618980e-06,
5.84243268710826e-06,
5.74494125723676e-06,
5.64275663266799e-06,
5.53633239754493e-06,
5.42511044796520e-06,
5.30955851436901e-06,
5.18909082922882e-06,
5.06417106483642e-06,
4.93426738681860e-06,
4.79981139928378e-06,
4.66022392940390e-06,
4.51602630845954e-06,
4.36660747560401e-06,
4.21247294402037e-06,
4.05305110546832e-06,
3.88878763289571e-06,
3.71916450048738e-06,
3.54462712478025e-06,
3.36465155419938e-06,
3.17967167761456e-06,
2.98917613191769e-06,
2.79361738719780e-06,
2.59247412473194e-06,
2.38618565979242e-06,
2.17426059604335e-06,
1.95714227397860e-06,
1.73430496738356e-06,
1.50620956228030e-06,
1.27238963764761e-06,
1.03324761527409e-06,
7.88323211174950e-07,
5.38057114445362e-07,
2.81944291020029e-07,
2.04836906979221e-08,
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9.99472748819797e-05,
0.000102363447520479,
0.000104783014763168,
0.000107205025896024,
0.000109629029400713,
0.000112054039942443,
0.000114479594239356,
0.000116904687981786,
0.000119328839927821,
0.000121751025536885,
0.000124170741112682,
0.000126586955396263,
0.000128999137073690,
0.000131406237902807,
0.000133807710854935,
0.000136202494636464,
0.000138590020743407,
0.000140969217664355,
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0.000145699758496409,
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0.000150387365819865,
0.000152712978884051,
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0.000157323233199747,
0.000159606113351142,
0.000161873135563338,
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0.000166355539329688,
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0.000204155202780923,
0.000205835317231766,
0.000207477624265485,
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};




int lp_fifo_num = 1;
int bp_fifo_num = 1;


int value[] = {0,0};

float mag = 0;
float calc_mag = 0;
double mag_total = 0;
float phase = 0;
float calc_phase = 0;
float phase_total = 0;
int NumInBlock = 0;

float mag_result = 0;
float phase_result = 0;
/*
int diff_0[3] = {0, 0, 0};
int diff_1[3] = {0, 0, 0};
*/
double final_mag = 0;
float final_phase = 0;

// Finite State Machine
int current_state = 0;

// Flag
bool ADC_reading = false;
bool isTransmitting = false;


//IntervalTimer timer0;
Ticker timer0;
Timer t1;

int adc_cal(void)
{
    ADC0_CFG1 |= (ADC_CFG1_MODE(3)  | // 16 bits mode
                  ADC_CFG1_ADICLK(1)| // Input Bus Clock divided by 2 (20-25 MHz out of reset (FEI mode) / 2)
                  ADC_CFG1_ADIV(2)) ; // Clock divide by 4 (2.5-3 MHz)
    
    ADC0_SC3 |= ADC_SC3_AVGE_MASK |   // Enable HW average
                ADC_SC3_AVGS(3)   |   // Set HW average of 32 samples
                ADC_SC3_CAL_MASK;     // Start calibration process
    
    while(ADC0_SC3 & ADC_SC3_CAL_MASK); // Wait for calibration to end
    
    if(ADC0_SC3 & ADC_SC3_CALF_MASK) return 1;  // Check for successful calibration
    
    uint16_t calib = 0; // calibration variable 
    calib += ADC0->CLPS + ADC0_CLP4 + ADC0_CLP3 + ADC0_CLP2 + ADC0_CLP1 + ADC0_CLP0;
    calib /= 2;
    calib |= 0x8000;    // Set MSB 
    ADC0_PG = calib;
    calib = 0;
    calib += ADC0_CLMS + ADC0_CLM4 + ADC0_CLM3 + ADC0_CLM2 + ADC0_CLM1 + ADC0_CLM0;
    calib /= 2;
    calib |= 0x8000;    // Set MSB
    ADC0_MG = calib;
    
    return 0;
}

void adc_init()
{
    // red, indicating not ready

    
    // Turn on the ADC0 and ADC1 clocks
    SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK;
    SIM_SCGC3 |= SIM_SCGC3_ADC1_MASK;
    
    
     __disable_irq();
     adc_cal();
    //if(adc_cal()) {red = 0; green = 0;} // if calibration fails, display yellow
    __enable_irq();


    
    // Setup Configuration Register 1 
    ADC0_CFG1 = 0; // clear register
    ADC0_CFG1 |= ADC_CFG1_ADICLK(0);    // select bus clock
    ADC0_CFG1 |= ADC_CFG1_MODE(3);      // select 16-bit 2's complement output  
    ADC0_CFG1 |= ADC_CFG1_ADIV(0);      // clock divisor = 0.
    ADC0_CFG1 &= ~ADC_CFG1_ADLSMP_MASK; // select short sample time   //QUESTION
    ADC0_CFG1 &= ~ADC_CFG1_ADLPC_MASK;  // select normal power configuration
    ADC1_CFG1 = 0; // clear register
    ADC1_CFG1 |= ADC_CFG1_ADICLK(0);    // select bus clock
    ADC1_CFG1 |= ADC_CFG1_MODE(3);      // select 16-bit 2's complement output
    ADC1_CFG1 |= ADC_CFG1_ADIV(0);      // clock divisor = 0.
    ADC1_CFG1 &= ~ADC_CFG1_ADLSMP_MASK; // select short sample time
    ADC1_CFG1 &= ~ADC_CFG1_ADLPC_MASK;  // select normal power configuration
    
    // Setup Configuration Register 2 
    ADC0_CFG2 = 0; // clear register
    //ADC0_CFG2 |= ADC_CFG2_ADHSC_MASK ;  // select high-speed conversion
    ADC0_CFG2 |= ADC_CFG2_MUXSEL_MASK; // select a channels    //possibly change to channel b.
    ADC1_CFG2 = 0; // clear register
    //ADC1_CFG2 |= ADC_CFG2_ADHSC_MASK ;  // select high-speed conversion
    ADC1_CFG2 &= ~ADC_CFG2_MUXSEL_MASK; // select a channels    
    
    // Setup Status and Control Register 2 
    ADC0_SC2 = 0;                    // clear register
    ADC0_SC2 |= ADC_SC2_REFSEL(0);   // select external voltage reference   //QUESTION
    //ADC0_SC2 |= ADC_SC2_DMAEN_MASK;  // enable DMA
    //ADC0_SC2 &= ~ADC_SC2_ADTRG_MASK; // select hardware trigger  //QESTION
    ADC1_SC2 = 0;                    // clear register
    ADC1_SC2 |= ADC_SC2_REFSEL(0);   // select external voltage reference
    //ADC1_SC2 |= ADC_SC2_DMAEN_MASK;  // enable DMA
    //ADC1_SC2 &= ~ADC_SC2_ADTRG_MASK; // select hardware trigger
   
   
    ADC0_SC3 = ADC_SC3_AVGS(0) | ADC_SC3_AVGE_MASK; // Hardware Average set to 16 samples averaged
                                                    // select single conversion mode
    ADC1_SC3 = ADC_SC3_AVGS(0) | ADC_SC3_AVGE_MASK; // Hardware Average set to 16 samples averaged 
    // Setup Status and Control Register 3 now that calibration is complete
    ADC0_SC3 = 0; // Hardware Average set to 4 samples averaged
                  // Hardware Average Disabled
                  // select single conversion mode
    ADC1_SC3 = 0; // Hardware Average set to 4 samples averaged
                  // Hardware Average Disabled
                  // select single conversion mode
    //ADC1_SC3 = ADC_SC3_AVGS(0) |  ADC_SC3_AVGE_MASK;//JARED COME BACK AND LOOK AT THIS
    
    // Setup Status and Control Register 1A 
    ADC0_SC1A = 0; // clear register
    ADC0_SC1A &= ~ADC_SC1_DIFF_MASK; // select single-ended mode
    ADC0_SC1A |= ADC_SC1_AIEN_MASK;  // enable interrupt (for debugging)
    ADC0_SC1A |= ADC_SC1_ADCH(12);   // select channel 13
    ADC1_SC1A = 0; // clear register
    ADC1_SC1A &= ~ADC_SC1_DIFF_MASK; // select single-ended mode
    ADC1_SC1A |= ADC_SC1_AIEN_MASK;  // enable interrupt (for debugging)
    ADC1_SC1A |= ADC_SC1_ADCH(14);   // select channel 14
    
    
    // Check if ADC is finished initializing  TODO:  This part doesn't seem right, but I did it according to 871
    while( (ADC0_SC1B&ADC_SC1_COCO_MASK)) {}
    int gain = ADC0_RA; // read the register to clear SC1A[COCO]  //possibly a
    while( (ADC1_SC1A&ADC_SC1_COCO_MASK)) {}
    gain = ADC1_RA; // read the register to clear SC1A[COCO]
    
    
//QUESTION
    ADC0_SC3 &= ~ADC_SC3_ADCO_MASK;  // single conversion mode
    ADC1_SC3 &= ~ADC_SC3_ADCO_MASK;  // single conversion mode
    ADC0_SC2 &= ~ADC_SC2_ADTRG_MASK; // set ADC to software trigger
    ADC1_SC2 &= ~ADC_SC2_ADTRG_MASK; // set ADC to software trigger
    ADC0_SC1A |= ADC_SC1_ADCH(12);   // write to SC1B causing a trigger
    ADC1_SC1A |= ADC_SC1_ADCH(14);   // write to SC1A causing a trigger
}



void pre_compute_tables() {
  // This function will precompute the cos and sin tables used in the rest of the program
  for(int precompute_counter = 0; precompute_counter < pre_compute_length; precompute_counter++){
    out_val_pre[precompute_counter] = (int) (cos(twopi * CarrierFrequency * TimerInterruptInMicroSeconds * 1e-6 * precompute_counter) * 4965.0 + 49650.0);
    i_mod_pre[precompute_counter] = (cos(twopi * CarrierFrequency * TimerInterruptInMicroSeconds * 1e-6 * precompute_counter));
    q_mod_pre[precompute_counter] = (-sin(twopi * CarrierFrequency * TimerInterruptInMicroSeconds * 1e-6 * precompute_counter));

  }
} //pre_compute_tables




void ISR_repeat() {//40 KHz
  // Calculation of loop for generating signal to output on DAC
  
  WaveOut.write_u16(out_val_pre[phase_counter]);  //creates a wave that bounces between 0 & 3.3 V

  // ISR counter reset and increment
  if (ISR_counter >= ISR_counter_loop_reset)//10KHz
  {
    ISR_counter = 1;
  //JARED ADD THESE 2 LINES BACK IN
    ADC0_SC1A |= ADC_SC1_ADCH(12);   // start ADC process Possibly change to B.
    ADC1_SC1A |= ADC_SC1_ADCH(14);   // start ADC process
    
    ADC_reading = true;
    current_i_mod = i_mod_pre[phase_counter];
    current_q_mod = q_mod_pre[phase_counter];
  }
  else {
    ISR_counter++;
  }
  
  phase_counter++;
  if (phase_counter >= pre_compute_length) phase_counter = 0;
  
} //ISR_repeat


void execute_DSP() {
/*
bp_fifo_num++;  
  if (bp_fifo_num >= bp_fir_length) bp_fifo_num = 0;

   x_0[bp_fifo_num] = (float) (value[1] - value[0]);
   x_1[bp_fifo_num] = (float) (value[0] - 32768);

   // Band pass filter of incoming data
  float y_0 = x_0[bp_fifo_num] * bp_filter_coeff[0];
  float y_1 = x_1[bp_fifo_num] * bp_filter_coeff[0];
  
  for(int fir_counter = 1; fir_counter < bp_fir_length; fir_counter++){
    int fir_index = bp_fifo_num + fir_counter;
    if (fir_index >= bp_fir_length) {
      fir_index -= bp_fir_length;
    }
    y_0 += x_0[fir_index] * bp_filter_coeff[fir_counter];
    y_1 += x_1[fir_index] * bp_filter_coeff[fir_counter];
  }
*/
y_0 = (value[0]);
y_1 = (value[1]);
  //y_0 = (value[0] - 32768);
  //y_1 = (value[1] - 32768);
  current_i_mod = i_mod_pre[phase_counter];
  current_q_mod = q_mod_pre[phase_counter];

  // Demodulation of the signal
  x_0_i[lp_fifo_num] = (y_0 * current_i_mod);
  x_0_q[lp_fifo_num] = (y_0 * current_q_mod);
  x_1_i[lp_fifo_num] = (y_1 * current_i_mod);
  x_1_q[lp_fifo_num] = (y_1 * current_q_mod); 

  lp_fifo_num++;  
  if (lp_fifo_num >= lp_fir_length) lp_fifo_num = 0;

  // Low pass filter of demodulated signal
  float y_0_i = x_0_i[lp_fifo_num] * lp_filter_coeff[0];
  float y_0_q = x_0_q[lp_fifo_num] * lp_filter_coeff[0];
  float y_1_i = x_1_i[lp_fifo_num] * lp_filter_coeff[0];
  float y_1_q = x_1_q[lp_fifo_num] * lp_filter_coeff[0];

  for(int fir_counter = 1; fir_counter < lp_fir_length; fir_counter++){
    int fir_index = lp_fifo_num + fir_counter;
    if (fir_index >= lp_fir_length) {
      fir_index -= lp_fir_length;
    }
    y_0_i += x_0_i[fir_index] * lp_filter_coeff[fir_counter];
    y_0_q += x_0_q[fir_index] * lp_filter_coeff[fir_counter];
    y_1_i += x_1_i[fir_index] * lp_filter_coeff[fir_counter];
    y_1_q += x_1_q[fir_index] * lp_filter_coeff[fir_counter];
  }  
   
  real_ip = y_0_i * y_1_i + y_0_q * y_1_q;
  imag_ip = y_0_q * y_1_i - y_0_i * y_1_q;
  y_0_squared = y_0_i * y_0_i + y_0_q * y_0_q; 
  y_1_squared = y_1_i * y_1_i + y_1_q * y_1_q;

//  float mag = sqrt((real_ip * real_ip + imag_ip * imag_ip) / y_0_squared;
  mag = sqrt(((float) real_ip * (float) real_ip + (float) imag_ip * (float) imag_ip)) / ((float) y_0_squared);
  mag_total += mag;
  calc_mag = mag_total / NumInBlock;

  real_ip_total += real_ip;
  imag_ip_total += imag_ip;
  phase = -atan2(imag_ip_total, real_ip_total);
  calc_phase = phase_total / NumInBlock;
}



void setup() { 
printf("Starting UP");
  adc_init();
  pre_compute_tables();
  wait(1); 
} //setup

using namespace std;
 
int main() {
    led_blue = 1;
    led_green = 1;
    led_red = 0;
    
    setup();
    int count = 0;
    t1.start();
    
    pc.baud(115200);
    
    for(int i = 0; i < 86; i++) 
    {
        if(NVIC_GetPriority((IRQn_Type) i) == 0) NVIC_SetPriority((IRQn_Type) i, 2);
    }
    
    // Give hardware associated with 
    // sampling the highest priority
    NVIC_SetPriority(ADC1_IRQn,0);
    NVIC_SetPriority(ADC0_IRQn,0);
    NVIC_SetPriority(PDB0_IRQn,0);
    NVIC_SetPriority(DMA0_IRQn,0);
    NVIC_SetPriority(DMA1_IRQn,0);
    NVIC_SetPriority(DMA2_IRQn,0);
    
    NVIC_SetPriority(ENET_1588_Timer_IRQn,1);
    NVIC_SetPriority(ENET_Transmit_IRQn,1);
    NVIC_SetPriority(ENET_Receive_IRQn,1);
    NVIC_SetPriority(ENET_Error_IRQn,1);

    led_green = 1;
    led_red = 1;
    led_blue = 1;

    timer0.attach_us(&ISR_repeat, TimerInterruptInMicroSeconds);
    while(true) {
                
                count++;
                //printf("Loop");
                
                while (!ADC_reading)  
                {
                    
                led_blue = 0;
                }

            
              counter++;
              
              CyclesInState++;
              
              
              execute_DSP();
              

                NumInBlock++; 
                if (NumInBlock >= NumCalculatedAverages) {
                  printCounter++;
                  mag_result = calc_mag;
                  phase_result = calc_phase;
                  final_mag = mag_result;
                  final_phase = phase_result;
                  NumInBlock = 0;
                  mag_total = 0;
                  real_ip_total = 0;
                  imag_ip_total = 0;
                  if (printCounter>PRINTTIMER)
                  {
                      printf("Coeficient%f Phase%f\n\r", final_mag, final_phase);
                      printCounter = 0;
                  }
                  
                }

              
                      
          value[0] = ADC0_RA;//Read adc
          value[1] = ADC1_RA;//Read adc
          //printf("%f %f\n\r", value[0], value[1]);
          ADC_reading = false;//lower flag

    }// end while(true) 
}// end main