CaryCoders / SX1276Lib

local copy of sx1276 library

Dependents:   SX1276_GPS demo_SX1276_standalone

Fork of SX1276Lib by Gregory Cristian

sx1276/sx1276.cpp@17:20ce6dab2237, 2015-09-03 (annotated)

Committer:
ftagius
Date:
Thu Sep 03 14:33:00 2015 +0000
Revision:
17:20ce6dab2237
Parent:
16:29f09ac61412 
add debug messages;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
GregCr 8:0fe3e0e8007b 7 ( C )2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: Actual implementation of a SX1276 radio, inherits Radio
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #include "sx1276.h"
GregCr 0:e6ceb13d2d05 16
GregCr 0:e6ceb13d2d05 17 const FskBandwidth_t SX1276::FskBandwidths[] =
GregCr 0:e6ceb13d2d05 18 {
GregCr 0:e6ceb13d2d05 19 { 2600 , 0x17 },
GregCr 0:e6ceb13d2d05 20 { 3100 , 0x0F },
GregCr 0:e6ceb13d2d05 21 { 3900 , 0x07 },
GregCr 0:e6ceb13d2d05 22 { 5200 , 0x16 },
GregCr 0:e6ceb13d2d05 23 { 6300 , 0x0E },
GregCr 0:e6ceb13d2d05 24 { 7800 , 0x06 },
GregCr 0:e6ceb13d2d05 25 { 10400 , 0x15 },
GregCr 0:e6ceb13d2d05 26 { 12500 , 0x0D },
GregCr 0:e6ceb13d2d05 27 { 15600 , 0x05 },
GregCr 0:e6ceb13d2d05 28 { 20800 , 0x14 },
GregCr 0:e6ceb13d2d05 29 { 25000 , 0x0C },
GregCr 0:e6ceb13d2d05 30 { 31300 , 0x04 },
GregCr 0:e6ceb13d2d05 31 { 41700 , 0x13 },
GregCr 0:e6ceb13d2d05 32 { 50000 , 0x0B },
GregCr 0:e6ceb13d2d05 33 { 62500 , 0x03 },
GregCr 0:e6ceb13d2d05 34 { 83333 , 0x12 },
GregCr 0:e6ceb13d2d05 35 { 100000, 0x0A },
GregCr 0:e6ceb13d2d05 36 { 125000, 0x02 },
GregCr 0:e6ceb13d2d05 37 { 166700, 0x11 },
GregCr 0:e6ceb13d2d05 38 { 200000, 0x09 },
GregCr 0:e6ceb13d2d05 39 { 250000, 0x01 }
GregCr 0:e6ceb13d2d05 40 };
GregCr 0:e6ceb13d2d05 41
GregCr 0:e6ceb13d2d05 42
GregCr 7:2b555111463f 43 SX1276::SX1276( void ( *txDone )( ), void ( *txTimeout ) ( ), void ( *rxDone ) ( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr ),
mluis 13:618826a997e2 44 void ( *rxTimeout ) ( ), void ( *rxError ) ( ), void ( *fhssChangeChannel ) ( uint8_t channelIndex ), void ( *cadDone ) ( bool channelActivityDetected ),
mluis 13:618826a997e2 45 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
GregCr 0:e6ceb13d2d05 46 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
mluis 13:618826a997e2 47 : Radio( txDone, txTimeout, rxDone, rxTimeout, rxError, fhssChangeChannel, cadDone ),
mluis 13:618826a997e2 48 spi( mosi, miso, sclk ),
mluis 13:618826a997e2 49 nss( nss ),
mluis 13:618826a997e2 50 reset( reset ),
mluis 13:618826a997e2 51 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
mluis 13:618826a997e2 52 isRadioActive( false )
GregCr 0:e6ceb13d2d05 53 {
mluis 13:618826a997e2 54 wait_ms( 10 );
mluis 13:618826a997e2 55 this->rxTx = 0;
mluis 13:618826a997e2 56 this->rxBuffer = new uint8_t[RX_BUFFER_SIZE];
mluis 13:618826a997e2 57 previousOpMode = RF_OPMODE_STANDBY;
mluis 13:618826a997e2 58
mluis 13:618826a997e2 59 this->dioIrq = new DioIrqHandler[6];
GregCr 0:e6ceb13d2d05 60
mluis 13:618826a997e2 61 this->dioIrq[0] = &SX1276::OnDio0Irq;
mluis 13:618826a997e2 62 this->dioIrq[1] = &SX1276::OnDio1Irq;
mluis 13:618826a997e2 63 this->dioIrq[2] = &SX1276::OnDio2Irq;
mluis 13:618826a997e2 64 this->dioIrq[3] = &SX1276::OnDio3Irq;
mluis 13:618826a997e2 65 this->dioIrq[4] = &SX1276::OnDio4Irq;
mluis 13:618826a997e2 66 this->dioIrq[5] = NULL;
mluis 13:618826a997e2 67
mluis 13:618826a997e2 68 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 69 }
GregCr 0:e6ceb13d2d05 70
GregCr 0:e6ceb13d2d05 71 SX1276::~SX1276( )
GregCr 0:e6ceb13d2d05 72 {
mluis 13:618826a997e2 73 delete this->rxBuffer;
mluis 13:618826a997e2 74 delete this->dioIrq;
GregCr 0:e6ceb13d2d05 75 }
GregCr 0:e6ceb13d2d05 76
GregCr 0:e6ceb13d2d05 77 void SX1276::RxChainCalibration( void )
GregCr 0:e6ceb13d2d05 78 {
GregCr 0:e6ceb13d2d05 79 uint8_t regPaConfigInitVal;
GregCr 0:e6ceb13d2d05 80 uint32_t initialFreq;
GregCr 0:e6ceb13d2d05 81
GregCr 0:e6ceb13d2d05 82 // Save context
GregCr 0:e6ceb13d2d05 83 regPaConfigInitVal = this->Read( REG_PACONFIG );
GregCr 0:e6ceb13d2d05 84 initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
GregCr 0:e6ceb13d2d05 85 ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
GregCr 0:e6ceb13d2d05 86 ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
GregCr 0:e6ceb13d2d05 87
GregCr 0:e6ceb13d2d05 88 // Cut the PA just in case, RFO output, power = -1 dBm
GregCr 0:e6ceb13d2d05 89 this->Write( REG_PACONFIG, 0x00 );
GregCr 0:e6ceb13d2d05 90
GregCr 0:e6ceb13d2d05 91 // Launch Rx chain calibration for LF band
GregCr 0:e6ceb13d2d05 92 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
GregCr 0:e6ceb13d2d05 93 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
GregCr 0:e6ceb13d2d05 94 {
GregCr 0:e6ceb13d2d05 95 }
GregCr 0:e6ceb13d2d05 96
GregCr 0:e6ceb13d2d05 97 // Sets a Frequency in HF band
GregCr 0:e6ceb13d2d05 98 settings.Channel= 868000000 ;
GregCr 0:e6ceb13d2d05 99
GregCr 0:e6ceb13d2d05 100 // Launch Rx chain calibration for HF band
GregCr 0:e6ceb13d2d05 101 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
GregCr 0:e6ceb13d2d05 102 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
GregCr 0:e6ceb13d2d05 103 {
GregCr 0:e6ceb13d2d05 104 }
GregCr 0:e6ceb13d2d05 105
GregCr 0:e6ceb13d2d05 106 // Restore context
GregCr 0:e6ceb13d2d05 107 this->Write( REG_PACONFIG, regPaConfigInitVal );
GregCr 0:e6ceb13d2d05 108 SetChannel( initialFreq );
GregCr 0:e6ceb13d2d05 109 }
GregCr 0:e6ceb13d2d05 110
GregCr 0:e6ceb13d2d05 111 RadioState SX1276::GetState( void )
GregCr 0:e6ceb13d2d05 112 {
GregCr 0:e6ceb13d2d05 113 return this->settings.State;
GregCr 0:e6ceb13d2d05 114 }
GregCr 0:e6ceb13d2d05 115
GregCr 0:e6ceb13d2d05 116 void SX1276::SetChannel( uint32_t freq )
GregCr 0:e6ceb13d2d05 117 {
GregCr 0:e6ceb13d2d05 118 this->settings.Channel = freq;
GregCr 0:e6ceb13d2d05 119 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 120 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 121 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 122 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
GregCr 0:e6ceb13d2d05 123 }
GregCr 0:e6ceb13d2d05 124
ftagius 16:29f09ac61412 125 float SX1276::GetChannel(void)
ftagius 16:29f09ac61412 126 {
ftagius 16:29f09ac61412 127 uint32_t frf;
ftagius 16:29f09ac61412 128 uint8_t lsb, mid, msb;
ftagius 16:29f09ac61412 129 float MHz;
ftagius 16:29f09ac61412 130
ftagius 16:29f09ac61412 131 msb = Read(REG_FRFMSB);
ftagius 16:29f09ac61412 132 mid = Read(REG_FRFMID);
ftagius 16:29f09ac61412 133 lsb = Read(REG_FRFLSB);
ftagius 16:29f09ac61412 134 frf = msb;
ftagius 16:29f09ac61412 135 frf <<= 8;
ftagius 16:29f09ac61412 136 frf += mid;
ftagius 16:29f09ac61412 137 frf <<= 8;
ftagius 16:29f09ac61412 138 frf += lsb;
ftagius 16:29f09ac61412 139 MHz = frf * FREQ_STEP_MHZ;
ftagius 16:29f09ac61412 140 //printf("frf=%d mhz=%f\r\n", frf, MHz);
ftagius 16:29f09ac61412 141 return MHz;
ftagius 16:29f09ac61412 142 }
ftagius 16:29f09ac61412 143
ftagius 16:29f09ac61412 144
GregCr 0:e6ceb13d2d05 145 bool SX1276::IsChannelFree( ModemType modem, uint32_t freq, int8_t rssiThresh )
GregCr 0:e6ceb13d2d05 146 {
GregCr 7:2b555111463f 147 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 148
GregCr 0:e6ceb13d2d05 149 SetModem( modem );
GregCr 0:e6ceb13d2d05 150
GregCr 0:e6ceb13d2d05 151 SetChannel( freq );
GregCr 0:e6ceb13d2d05 152
GregCr 0:e6ceb13d2d05 153 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 154
GregCr 4:f0ce52e94d3f 155 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 156
GregCr 0:e6ceb13d2d05 157 rssi = GetRssi( modem );
GregCr 0:e6ceb13d2d05 158
GregCr 0:e6ceb13d2d05 159 Sleep( );
GregCr 0:e6ceb13d2d05 160
GregCr 7:2b555111463f 161 if( rssi > ( int16_t )rssiThresh )
GregCr 0:e6ceb13d2d05 162 {
GregCr 0:e6ceb13d2d05 163 return false;
GregCr 0:e6ceb13d2d05 164 }
GregCr 0:e6ceb13d2d05 165 return true;
GregCr 0:e6ceb13d2d05 166 }
GregCr 0:e6ceb13d2d05 167
GregCr 0:e6ceb13d2d05 168 uint32_t SX1276::Random( void )
GregCr 0:e6ceb13d2d05 169 {
GregCr 0:e6ceb13d2d05 170 uint8_t i;
GregCr 0:e6ceb13d2d05 171 uint32_t rnd = 0;
GregCr 0:e6ceb13d2d05 172
GregCr 0:e6ceb13d2d05 173 /*
GregCr 0:e6ceb13d2d05 174 * Radio setup for random number generation
GregCr 0:e6ceb13d2d05 175 */
GregCr 0:e6ceb13d2d05 176 // Set LoRa modem ON
GregCr 0:e6ceb13d2d05 177 SetModem( MODEM_LORA );
GregCr 0:e6ceb13d2d05 178
GregCr 0:e6ceb13d2d05 179 // Disable LoRa modem interrupts
GregCr 0:e6ceb13d2d05 180 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 181 RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 182 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 0:e6ceb13d2d05 183 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 184 RFLR_IRQFLAGS_TXDONE |
ftagius 17:20ce6dab2237 185 //RFLR_IRQFLAGS_CADDONE |
ftagius 17:20ce6dab2237 186 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL// |
ftagius 17:20ce6dab2237 187 //RFLR_IRQFLAGS_CADDETECTED
ftagius 17:20ce6dab2237 188 );
GregCr 0:e6ceb13d2d05 189
GregCr 0:e6ceb13d2d05 190 // Set radio in continuous reception
GregCr 0:e6ceb13d2d05 191 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 192
GregCr 0:e6ceb13d2d05 193 for( i = 0; i < 32; i++ )
GregCr 0:e6ceb13d2d05 194 {
GregCr 4:f0ce52e94d3f 195 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 196 // Unfiltered RSSI value reading. Only takes the LSB value
GregCr 0:e6ceb13d2d05 197 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
GregCr 0:e6ceb13d2d05 198 }
GregCr 0:e6ceb13d2d05 199
GregCr 0:e6ceb13d2d05 200 Sleep( );
GregCr 0:e6ceb13d2d05 201
GregCr 0:e6ceb13d2d05 202 return rnd;
GregCr 0:e6ceb13d2d05 203 }
GregCr 0:e6ceb13d2d05 204
GregCr 0:e6ceb13d2d05 205 /*!
GregCr 0:e6ceb13d2d05 206 * Returns the known FSK bandwidth registers value
GregCr 0:e6ceb13d2d05 207 *
GregCr 0:e6ceb13d2d05 208 * \param [IN] bandwidth Bandwidth value in Hz
GregCr 0:e6ceb13d2d05 209 * \retval regValue Bandwidth register value.
GregCr 0:e6ceb13d2d05 210 */
GregCr 0:e6ceb13d2d05 211 uint8_t SX1276::GetFskBandwidthRegValue( uint32_t bandwidth )
GregCr 0:e6ceb13d2d05 212 {
GregCr 0:e6ceb13d2d05 213 uint8_t i;
GregCr 0:e6ceb13d2d05 214
GregCr 0:e6ceb13d2d05 215 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
GregCr 0:e6ceb13d2d05 216 {
GregCr 0:e6ceb13d2d05 217 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
GregCr 0:e6ceb13d2d05 218 {
GregCr 0:e6ceb13d2d05 219 return FskBandwidths[i].RegValue;
GregCr 0:e6ceb13d2d05 220 }
GregCr 0:e6ceb13d2d05 221 }
GregCr 0:e6ceb13d2d05 222 // ERROR: Value not found
GregCr 0:e6ceb13d2d05 223 while( 1 );
GregCr 0:e6ceb13d2d05 224 }
GregCr 0:e6ceb13d2d05 225
GregCr 0:e6ceb13d2d05 226 void SX1276::SetRxConfig( ModemType modem, uint32_t bandwidth,
GregCr 0:e6ceb13d2d05 227 uint32_t datarate, uint8_t coderate,
GregCr 0:e6ceb13d2d05 228 uint32_t bandwidthAfc, uint16_t preambleLen,
GregCr 0:e6ceb13d2d05 229 uint16_t symbTimeout, bool fixLen,
mluis 13:618826a997e2 230 uint8_t payloadLen,
mluis 13:618826a997e2 231 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
GregCr 6:e7f02929cd3d 232 bool iqInverted, bool rxContinuous )
GregCr 0:e6ceb13d2d05 233 {
GregCr 0:e6ceb13d2d05 234 SetModem( modem );
GregCr 0:e6ceb13d2d05 235
GregCr 0:e6ceb13d2d05 236 switch( modem )
GregCr 0:e6ceb13d2d05 237 {
GregCr 0:e6ceb13d2d05 238 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 239 {
GregCr 0:e6ceb13d2d05 240 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 241 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 242 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
GregCr 0:e6ceb13d2d05 243 this->settings.Fsk.FixLen = fixLen;
mluis 13:618826a997e2 244 this->settings.Fsk.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 245 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 246 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 247 this->settings.Fsk.RxContinuous = rxContinuous;
GregCr 0:e6ceb13d2d05 248 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 249
GregCr 0:e6ceb13d2d05 250 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 251 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 252 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 253
GregCr 0:e6ceb13d2d05 254 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
GregCr 0:e6ceb13d2d05 255 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
GregCr 0:e6ceb13d2d05 256
GregCr 0:e6ceb13d2d05 257 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 258 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 259
GregCr 0:e6ceb13d2d05 260 Write( REG_PACKETCONFIG1,
GregCr 0:e6ceb13d2d05 261 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 262 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 263 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 264 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 265 ( crcOn << 4 ) );
mluis 13:618826a997e2 266 if( fixLen == 1 )
mluis 13:618826a997e2 267 {
mluis 13:618826a997e2 268 Write( REG_PAYLOADLENGTH, payloadLen );
mluis 13:618826a997e2 269 }
GregCr 0:e6ceb13d2d05 270 }
GregCr 0:e6ceb13d2d05 271 break;
GregCr 0:e6ceb13d2d05 272 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 273 {
GregCr 0:e6ceb13d2d05 274 if( bandwidth > 2 )
GregCr 0:e6ceb13d2d05 275 {
GregCr 0:e6ceb13d2d05 276 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 277 while( 1 );
GregCr 0:e6ceb13d2d05 278 }
GregCr 0:e6ceb13d2d05 279 bandwidth += 7;
GregCr 0:e6ceb13d2d05 280 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 281 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 282 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 283 this->settings.LoRa.FixLen = fixLen;
mluis 13:618826a997e2 284 this->settings.LoRa.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 285 this->settings.LoRa.CrcOn = crcOn;
mluis 13:618826a997e2 286 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 287 this->settings.LoRa.HopPeriod = hopPeriod;
GregCr 0:e6ceb13d2d05 288 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 289 this->settings.LoRa.RxContinuous = rxContinuous;
mluis 13:618826a997e2 290
GregCr 0:e6ceb13d2d05 291 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 292 {
GregCr 0:e6ceb13d2d05 293 datarate = 12;
GregCr 0:e6ceb13d2d05 294 }
GregCr 0:e6ceb13d2d05 295 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 296 {
GregCr 0:e6ceb13d2d05 297 datarate = 6;
GregCr 0:e6ceb13d2d05 298 }
GregCr 0:e6ceb13d2d05 299
GregCr 0:e6ceb13d2d05 300 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
GregCr 0:e6ceb13d2d05 301 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
GregCr 0:e6ceb13d2d05 302 {
GregCr 0:e6ceb13d2d05 303 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 304 }
GregCr 0:e6ceb13d2d05 305 else
GregCr 0:e6ceb13d2d05 306 {
GregCr 0:e6ceb13d2d05 307 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 308 }
GregCr 0:e6ceb13d2d05 309
GregCr 0:e6ceb13d2d05 310 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 311 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 312 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 313 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 314 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
GregCr 0:e6ceb13d2d05 315 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 316 fixLen );
GregCr 0:e6ceb13d2d05 317
GregCr 0:e6ceb13d2d05 318 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 319 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 320 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 321 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
GregCr 0:e6ceb13d2d05 322 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
GregCr 0:e6ceb13d2d05 323 ( datarate << 4 ) | ( crcOn << 2 ) |
GregCr 0:e6ceb13d2d05 324 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
GregCr 0:e6ceb13d2d05 325
GregCr 0:e6ceb13d2d05 326 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 327 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 328 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 329 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 330
GregCr 0:e6ceb13d2d05 331 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
GregCr 0:e6ceb13d2d05 332
GregCr 0:e6ceb13d2d05 333 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 334 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 335
mluis 13:618826a997e2 336 if( fixLen == 1 )
mluis 13:618826a997e2 337 {
mluis 13:618826a997e2 338 Write( REG_LR_PAYLOADLENGTH, payloadLen );
mluis 13:618826a997e2 339 }
mluis 13:618826a997e2 340
GregCr 6:e7f02929cd3d 341 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 342 {
GregCr 6:e7f02929cd3d 343 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 344 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 345 }
GregCr 6:e7f02929cd3d 346
GregCr 0:e6ceb13d2d05 347 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 348 {
GregCr 0:e6ceb13d2d05 349 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 350 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 351 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 352 RFLR_DETECTIONOPTIMIZE_SF6 );
GregCr 0:e6ceb13d2d05 353 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 354 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 355 }
GregCr 0:e6ceb13d2d05 356 else
GregCr 0:e6ceb13d2d05 357 {
GregCr 0:e6ceb13d2d05 358 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 359 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 360 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 361 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 362 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 363 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 364 }
GregCr 0:e6ceb13d2d05 365 }
GregCr 0:e6ceb13d2d05 366 break;
GregCr 0:e6ceb13d2d05 367 }
GregCr 0:e6ceb13d2d05 368 }
ftagius 16:29f09ac61412 369
GregCr 0:e6ceb13d2d05 370 void SX1276::SetTxConfig( ModemType modem, int8_t power, uint32_t fdev,
GregCr 0:e6ceb13d2d05 371 uint32_t bandwidth, uint32_t datarate,
GregCr 0:e6ceb13d2d05 372 uint8_t coderate, uint16_t preambleLen,
mluis 13:618826a997e2 373 bool fixLen, bool crcOn, bool freqHopOn,
mluis 13:618826a997e2 374 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
GregCr 0:e6ceb13d2d05 375 {
GregCr 0:e6ceb13d2d05 376 uint8_t paConfig = 0;
GregCr 0:e6ceb13d2d05 377 uint8_t paDac = 0;
GregCr 0:e6ceb13d2d05 378
GregCr 0:e6ceb13d2d05 379 SetModem( modem );
GregCr 0:e6ceb13d2d05 380
GregCr 0:e6ceb13d2d05 381 paConfig = Read( REG_PACONFIG );
GregCr 0:e6ceb13d2d05 382 paDac = Read( REG_PADAC );
GregCr 0:e6ceb13d2d05 383
GregCr 0:e6ceb13d2d05 384 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
GregCr 0:e6ceb13d2d05 385 paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
GregCr 0:e6ceb13d2d05 386
ftagius 16:29f09ac61412 387 printf("getpa = %x paConfig =%x power = %d\r\n",GetPaSelect( this->settings.Channel),paConfig, power );
GregCr 0:e6ceb13d2d05 388 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
GregCr 0:e6ceb13d2d05 389 {
GregCr 0:e6ceb13d2d05 390 if( power > 17 )
GregCr 0:e6ceb13d2d05 391 {
GregCr 0:e6ceb13d2d05 392 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
GregCr 0:e6ceb13d2d05 393 }
GregCr 0:e6ceb13d2d05 394 else
GregCr 0:e6ceb13d2d05 395 {
GregCr 0:e6ceb13d2d05 396 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
GregCr 0:e6ceb13d2d05 397 }
GregCr 0:e6ceb13d2d05 398 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
GregCr 0:e6ceb13d2d05 399 {
ftagius 16:29f09ac61412 400 //printf("padacc20dbm on\r\n");
GregCr 0:e6ceb13d2d05 401 if( power < 5 )
GregCr 0:e6ceb13d2d05 402 {
GregCr 0:e6ceb13d2d05 403 power = 5;
GregCr 0:e6ceb13d2d05 404 }
GregCr 0:e6ceb13d2d05 405 if( power > 20 )
GregCr 0:e6ceb13d2d05 406 {
GregCr 0:e6ceb13d2d05 407 power = 20;
GregCr 0:e6ceb13d2d05 408 }
ftagius 16:29f09ac61412 409 //printf("radfta set power - 5, power = %d\r\n",power);
GregCr 0:e6ceb13d2d05 410 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
GregCr 0:e6ceb13d2d05 411 }
GregCr 0:e6ceb13d2d05 412 else
GregCr 0:e6ceb13d2d05 413 {
ftagius 16:29f09ac61412 414 // printf("padacc20dbm not on\r\n");
GregCr 0:e6ceb13d2d05 415 if( power < 2 )
GregCr 0:e6ceb13d2d05 416 {
GregCr 0:e6ceb13d2d05 417 power = 2;
GregCr 0:e6ceb13d2d05 418 }
GregCr 0:e6ceb13d2d05 419 if( power > 17 )
GregCr 0:e6ceb13d2d05 420 {
GregCr 0:e6ceb13d2d05 421 power = 17;
GregCr 0:e6ceb13d2d05 422 }
ftagius 16:29f09ac61412 423 //printf("radfta set power - 2, power=%d\r\n",power);
GregCr 0:e6ceb13d2d05 424 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
GregCr 0:e6ceb13d2d05 425 }
GregCr 0:e6ceb13d2d05 426 }
GregCr 0:e6ceb13d2d05 427 else
GregCr 0:e6ceb13d2d05 428 {
GregCr 0:e6ceb13d2d05 429 if( power < -1 )
GregCr 0:e6ceb13d2d05 430 {
GregCr 0:e6ceb13d2d05 431 power = -1;
GregCr 0:e6ceb13d2d05 432 }
GregCr 0:e6ceb13d2d05 433 if( power > 14 )
GregCr 0:e6ceb13d2d05 434 {
ftagius 16:29f09ac61412 435 printf("Max power for this radio is 14dBm\r\n");
GregCr 0:e6ceb13d2d05 436 power = 14;
GregCr 0:e6ceb13d2d05 437 }
GregCr 0:e6ceb13d2d05 438 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
GregCr 0:e6ceb13d2d05 439 }
GregCr 0:e6ceb13d2d05 440 Write( REG_PACONFIG, paConfig );
GregCr 0:e6ceb13d2d05 441 Write( REG_PADAC, paDac );
GregCr 0:e6ceb13d2d05 442
GregCr 0:e6ceb13d2d05 443 switch( modem )
GregCr 0:e6ceb13d2d05 444 {
GregCr 0:e6ceb13d2d05 445 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 446 {
GregCr 0:e6ceb13d2d05 447 this->settings.Fsk.Power = power;
GregCr 0:e6ceb13d2d05 448 this->settings.Fsk.Fdev = fdev;
GregCr 0:e6ceb13d2d05 449 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 450 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 451 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 452 this->settings.Fsk.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 453 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 454 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 455 this->settings.Fsk.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 456
GregCr 0:e6ceb13d2d05 457 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 458 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
GregCr 0:e6ceb13d2d05 459 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
GregCr 0:e6ceb13d2d05 460
GregCr 0:e6ceb13d2d05 461 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 462 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 463 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 464
GregCr 0:e6ceb13d2d05 465 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 466 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 467
GregCr 0:e6ceb13d2d05 468 Write( REG_PACKETCONFIG1,
GregCr 0:e6ceb13d2d05 469 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 470 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 471 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 472 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 473 ( crcOn << 4 ) );
GregCr 0:e6ceb13d2d05 474 }
GregCr 0:e6ceb13d2d05 475 break;
GregCr 0:e6ceb13d2d05 476 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 477 {
GregCr 0:e6ceb13d2d05 478 this->settings.LoRa.Power = power;
GregCr 0:e6ceb13d2d05 479 if( bandwidth > 2 )
GregCr 0:e6ceb13d2d05 480 {
GregCr 0:e6ceb13d2d05 481 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 482 while( 1 );
GregCr 0:e6ceb13d2d05 483 }
GregCr 0:e6ceb13d2d05 484 bandwidth += 7;
GregCr 0:e6ceb13d2d05 485 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 486 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 487 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 488 this->settings.LoRa.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 489 this->settings.LoRa.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 490 this->settings.LoRa.CrcOn = crcOn;
mluis 13:618826a997e2 491 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 492 this->settings.LoRa.HopPeriod = hopPeriod;
GregCr 0:e6ceb13d2d05 493 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 494 this->settings.LoRa.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 495
GregCr 0:e6ceb13d2d05 496 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 497 {
GregCr 0:e6ceb13d2d05 498 datarate = 12;
GregCr 0:e6ceb13d2d05 499 }
GregCr 0:e6ceb13d2d05 500 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 501 {
GregCr 0:e6ceb13d2d05 502 datarate = 6;
GregCr 0:e6ceb13d2d05 503 }
GregCr 0:e6ceb13d2d05 504 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
GregCr 0:e6ceb13d2d05 505 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
GregCr 0:e6ceb13d2d05 506 {
GregCr 0:e6ceb13d2d05 507 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 508 }
GregCr 0:e6ceb13d2d05 509 else
GregCr 0:e6ceb13d2d05 510 {
GregCr 0:e6ceb13d2d05 511 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 512 }
GregCr 6:e7f02929cd3d 513
GregCr 6:e7f02929cd3d 514 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 515 {
GregCr 6:e7f02929cd3d 516 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 517 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 518 }
GregCr 6:e7f02929cd3d 519
GregCr 0:e6ceb13d2d05 520 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 521 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 522 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 523 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 524 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
GregCr 0:e6ceb13d2d05 525 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 526 fixLen );
GregCr 0:e6ceb13d2d05 527
GregCr 0:e6ceb13d2d05 528 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 529 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 530 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 531 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
GregCr 0:e6ceb13d2d05 532 ( datarate << 4 ) | ( crcOn << 2 ) );
GregCr 0:e6ceb13d2d05 533
GregCr 0:e6ceb13d2d05 534 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 535 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 536 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 537 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 538
GregCr 0:e6ceb13d2d05 539 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 540 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 541
GregCr 0:e6ceb13d2d05 542 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 543 {
GregCr 0:e6ceb13d2d05 544 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 545 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 546 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 547 RFLR_DETECTIONOPTIMIZE_SF6 );
GregCr 0:e6ceb13d2d05 548 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 549 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 550 }
GregCr 0:e6ceb13d2d05 551 else
GregCr 0:e6ceb13d2d05 552 {
GregCr 0:e6ceb13d2d05 553 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 554 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 555 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 556 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 557 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 558 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 559 }
GregCr 0:e6ceb13d2d05 560 }
GregCr 0:e6ceb13d2d05 561 break;
GregCr 0:e6ceb13d2d05 562 }
GregCr 0:e6ceb13d2d05 563 }
GregCr 0:e6ceb13d2d05 564
GregCr 0:e6ceb13d2d05 565 double SX1276::TimeOnAir( ModemType modem, uint8_t pktLen )
GregCr 0:e6ceb13d2d05 566 {
GregCr 0:e6ceb13d2d05 567 double airTime = 0.0;
GregCr 0:e6ceb13d2d05 568
GregCr 0:e6ceb13d2d05 569 switch( modem )
GregCr 0:e6ceb13d2d05 570 {
GregCr 0:e6ceb13d2d05 571 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 572 {
GregCr 4:f0ce52e94d3f 573 airTime = ceil( ( 8 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 574 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
GregCr 0:e6ceb13d2d05 575 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
GregCr 0:e6ceb13d2d05 576 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
GregCr 0:e6ceb13d2d05 577 pktLen +
GregCr 0:e6ceb13d2d05 578 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
GregCr 0:e6ceb13d2d05 579 this->settings.Fsk.Datarate ) * 1e6 );
GregCr 0:e6ceb13d2d05 580 }
GregCr 0:e6ceb13d2d05 581 break;
GregCr 0:e6ceb13d2d05 582 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 583 {
GregCr 0:e6ceb13d2d05 584 double bw = 0.0;
GregCr 0:e6ceb13d2d05 585 // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 586 switch( this->settings.LoRa.Bandwidth )
GregCr 0:e6ceb13d2d05 587 {
GregCr 0:e6ceb13d2d05 588 //case 0: // 7.8 kHz
GregCr 0:e6ceb13d2d05 589 // bw = 78e2;
GregCr 0:e6ceb13d2d05 590 // break;
GregCr 0:e6ceb13d2d05 591 //case 1: // 10.4 kHz
GregCr 0:e6ceb13d2d05 592 // bw = 104e2;
GregCr 0:e6ceb13d2d05 593 // break;
GregCr 0:e6ceb13d2d05 594 //case 2: // 15.6 kHz
GregCr 0:e6ceb13d2d05 595 // bw = 156e2;
GregCr 0:e6ceb13d2d05 596 // break;
GregCr 0:e6ceb13d2d05 597 //case 3: // 20.8 kHz
GregCr 0:e6ceb13d2d05 598 // bw = 208e2;
GregCr 0:e6ceb13d2d05 599 // break;
GregCr 0:e6ceb13d2d05 600 //case 4: // 31.2 kHz
GregCr 0:e6ceb13d2d05 601 // bw = 312e2;
GregCr 0:e6ceb13d2d05 602 // break;
GregCr 0:e6ceb13d2d05 603 //case 5: // 41.4 kHz
GregCr 0:e6ceb13d2d05 604 // bw = 414e2;
GregCr 0:e6ceb13d2d05 605 // break;
GregCr 0:e6ceb13d2d05 606 //case 6: // 62.5 kHz
GregCr 0:e6ceb13d2d05 607 // bw = 625e2;
GregCr 0:e6ceb13d2d05 608 // break;
GregCr 0:e6ceb13d2d05 609 case 7: // 125 kHz
GregCr 0:e6ceb13d2d05 610 bw = 125e3;
GregCr 0:e6ceb13d2d05 611 break;
GregCr 0:e6ceb13d2d05 612 case 8: // 250 kHz
GregCr 0:e6ceb13d2d05 613 bw = 250e3;
GregCr 0:e6ceb13d2d05 614 break;
GregCr 0:e6ceb13d2d05 615 case 9: // 500 kHz
GregCr 0:e6ceb13d2d05 616 bw = 500e3;
GregCr 0:e6ceb13d2d05 617 break;
GregCr 0:e6ceb13d2d05 618 }
GregCr 0:e6ceb13d2d05 619
GregCr 0:e6ceb13d2d05 620 // Symbol rate : time for one symbol (secs)
GregCr 0:e6ceb13d2d05 621 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
GregCr 0:e6ceb13d2d05 622 double ts = 1 / rs;
GregCr 0:e6ceb13d2d05 623 // time of preamble
GregCr 0:e6ceb13d2d05 624 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
GregCr 0:e6ceb13d2d05 625 // Symbol length of payload and time
GregCr 0:e6ceb13d2d05 626 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
GregCr 0:e6ceb13d2d05 627 28 + 16 * this->settings.LoRa.CrcOn -
GregCr 0:e6ceb13d2d05 628 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
GregCr 0:e6ceb13d2d05 629 ( double )( 4 * this->settings.LoRa.Datarate -
GregCr 0:e6ceb13d2d05 630 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 8 : 0 ) ) ) *
GregCr 0:e6ceb13d2d05 631 ( this->settings.LoRa.Coderate + 4 );
GregCr 0:e6ceb13d2d05 632 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
GregCr 0:e6ceb13d2d05 633 double tPayload = nPayload * ts;
GregCr 0:e6ceb13d2d05 634 // Time on air
GregCr 0:e6ceb13d2d05 635 double tOnAir = tPreamble + tPayload;
GregCr 0:e6ceb13d2d05 636 // return us secs
GregCr 0:e6ceb13d2d05 637 airTime = floor( tOnAir * 1e6 + 0.999 );
GregCr 0:e6ceb13d2d05 638 }
GregCr 0:e6ceb13d2d05 639 break;
GregCr 0:e6ceb13d2d05 640 }
GregCr 0:e6ceb13d2d05 641 return airTime;
GregCr 0:e6ceb13d2d05 642 }
GregCr 0:e6ceb13d2d05 643
GregCr 0:e6ceb13d2d05 644 void SX1276::Send( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 645 {
GregCr 0:e6ceb13d2d05 646 uint32_t txTimeout = 0;
GregCr 0:e6ceb13d2d05 647
GregCr 5:11ec8a6ba4f0 648 this->settings.State = IDLE;
GregCr 5:11ec8a6ba4f0 649
GregCr 0:e6ceb13d2d05 650 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 651 {
GregCr 0:e6ceb13d2d05 652 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 653 {
GregCr 0:e6ceb13d2d05 654 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 655 this->settings.FskPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 656
GregCr 0:e6ceb13d2d05 657 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 658 {
GregCr 0:e6ceb13d2d05 659 WriteFifo( ( uint8_t* )&size, 1 );
GregCr 0:e6ceb13d2d05 660 }
GregCr 0:e6ceb13d2d05 661 else
GregCr 0:e6ceb13d2d05 662 {
GregCr 0:e6ceb13d2d05 663 Write( REG_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 664 }
GregCr 0:e6ceb13d2d05 665
GregCr 0:e6ceb13d2d05 666 if( ( size > 0 ) && ( size <= 64 ) )
GregCr 0:e6ceb13d2d05 667 {
GregCr 0:e6ceb13d2d05 668 this->settings.FskPacketHandler.ChunkSize = size;
GregCr 0:e6ceb13d2d05 669 }
GregCr 0:e6ceb13d2d05 670 else
GregCr 0:e6ceb13d2d05 671 {
GregCr 0:e6ceb13d2d05 672 this->settings.FskPacketHandler.ChunkSize = 32;
GregCr 0:e6ceb13d2d05 673 }
GregCr 0:e6ceb13d2d05 674
GregCr 0:e6ceb13d2d05 675 // Write payload buffer
GregCr 0:e6ceb13d2d05 676 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 677 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 678 txTimeout = this->settings.Fsk.TxTimeout;
GregCr 0:e6ceb13d2d05 679 }
GregCr 0:e6ceb13d2d05 680 break;
GregCr 0:e6ceb13d2d05 681 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 682 {
GregCr 0:e6ceb13d2d05 683 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 684 {
GregCr 0:e6ceb13d2d05 685 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
GregCr 0:e6ceb13d2d05 686 }
GregCr 0:e6ceb13d2d05 687 else
GregCr 0:e6ceb13d2d05 688 {
GregCr 0:e6ceb13d2d05 689 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 690 }
GregCr 0:e6ceb13d2d05 691
GregCr 0:e6ceb13d2d05 692 this->settings.LoRaPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 693
GregCr 0:e6ceb13d2d05 694 // Initializes the payload size
GregCr 0:e6ceb13d2d05 695 Write( REG_LR_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 696
GregCr 0:e6ceb13d2d05 697 // Full buffer used for Tx
GregCr 0:e6ceb13d2d05 698 Write( REG_LR_FIFOTXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 699 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 700
GregCr 0:e6ceb13d2d05 701 // FIFO operations can not take place in Sleep mode
GregCr 0:e6ceb13d2d05 702 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 703 {
GregCr 0:e6ceb13d2d05 704 Standby( );
GregCr 4:f0ce52e94d3f 705 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 706 }
GregCr 0:e6ceb13d2d05 707 // Write payload buffer
GregCr 0:e6ceb13d2d05 708 WriteFifo( buffer, size );
GregCr 0:e6ceb13d2d05 709 txTimeout = this->settings.LoRa.TxTimeout;
GregCr 0:e6ceb13d2d05 710 }
GregCr 0:e6ceb13d2d05 711 break;
GregCr 0:e6ceb13d2d05 712 }
GregCr 0:e6ceb13d2d05 713
GregCr 0:e6ceb13d2d05 714 Tx( txTimeout );
GregCr 0:e6ceb13d2d05 715 }
GregCr 0:e6ceb13d2d05 716
GregCr 0:e6ceb13d2d05 717 void SX1276::Sleep( void )
GregCr 0:e6ceb13d2d05 718 {
mluis 13:618826a997e2 719 // Initialize driver timeout timers
mluis 13:618826a997e2 720 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 721 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 722 SetOpMode( RF_OPMODE_SLEEP );
GregCr 0:e6ceb13d2d05 723 }
GregCr 0:e6ceb13d2d05 724
GregCr 0:e6ceb13d2d05 725 void SX1276::Standby( void )
GregCr 0:e6ceb13d2d05 726 {
GregCr 0:e6ceb13d2d05 727 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 728 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 729 SetOpMode( RF_OPMODE_STANDBY );
GregCr 0:e6ceb13d2d05 730 }
GregCr 0:e6ceb13d2d05 731
GregCr 0:e6ceb13d2d05 732 void SX1276::Rx( uint32_t timeout )
GregCr 0:e6ceb13d2d05 733 {
GregCr 0:e6ceb13d2d05 734 bool rxContinuous = false;
GregCr 6:e7f02929cd3d 735
GregCr 0:e6ceb13d2d05 736 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 737 {
GregCr 0:e6ceb13d2d05 738 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 739 {
GregCr 0:e6ceb13d2d05 740 rxContinuous = this->settings.Fsk.RxContinuous;
GregCr 0:e6ceb13d2d05 741
GregCr 0:e6ceb13d2d05 742 // DIO0=PayloadReady
GregCr 0:e6ceb13d2d05 743 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 744 // DIO2=SyncAddr
GregCr 0:e6ceb13d2d05 745 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 746 // DIO4=Preamble
GregCr 0:e6ceb13d2d05 747 // DIO5=ModeReady
GregCr 5:11ec8a6ba4f0 748 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & RF_DIOMAPPING1_DIO1_MASK &
GregCr 0:e6ceb13d2d05 749 RF_DIOMAPPING1_DIO2_MASK ) |
GregCr 0:e6ceb13d2d05 750 RF_DIOMAPPING1_DIO0_00 |
GregCr 0:e6ceb13d2d05 751 RF_DIOMAPPING1_DIO2_11 );
GregCr 0:e6ceb13d2d05 752
GregCr 0:e6ceb13d2d05 753 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 754 RF_DIOMAPPING2_MAP_MASK ) |
GregCr 0:e6ceb13d2d05 755 RF_DIOMAPPING2_DIO4_11 |
GregCr 0:e6ceb13d2d05 756 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
GregCr 0:e6ceb13d2d05 757
GregCr 0:e6ceb13d2d05 758 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 759
GregCr 0:e6ceb13d2d05 760 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 761 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 762 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 763 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 764 }
GregCr 0:e6ceb13d2d05 765 break;
GregCr 0:e6ceb13d2d05 766 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 767 {
GregCr 0:e6ceb13d2d05 768 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 769 {
GregCr 0:e6ceb13d2d05 770 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 771 }
GregCr 0:e6ceb13d2d05 772 else
GregCr 0:e6ceb13d2d05 773 {
GregCr 0:e6ceb13d2d05 774 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 775 }
ftagius 16:29f09ac61412 776 // printf("radfta lora rx\n\r");
GregCr 0:e6ceb13d2d05 777 rxContinuous = this->settings.LoRa.RxContinuous;
GregCr 0:e6ceb13d2d05 778
GregCr 6:e7f02929cd3d 779 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 780 {
GregCr 6:e7f02929cd3d 781 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 782 //RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 783 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 4:f0ce52e94d3f 784 RFLR_IRQFLAGS_VALIDHEADER |
ftagius 17:20ce6dab2237 785 RFLR_IRQFLAGS_TXDONE // |
ftagius 17:20ce6dab2237 786 //x RFLR_IRQFLAGS_CADDONE |
GregCr 6:e7f02929cd3d 787 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
ftagius 17:20ce6dab2237 788 //x RFLR_IRQFLAGS_CADDETECTED
ftagius 17:20ce6dab2237 789 );
GregCr 6:e7f02929cd3d 790
mluis 13:618826a997e2 791 // DIO0=RxDone, DIO2=FhssChangeChannel
mluis 13:618826a997e2 792 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 793 }
GregCr 6:e7f02929cd3d 794 else
GregCr 6:e7f02929cd3d 795 {
GregCr 6:e7f02929cd3d 796 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 6:e7f02929cd3d 797 //RFLR_IRQFLAGS_RXDONE |
GregCr 6:e7f02929cd3d 798 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 6:e7f02929cd3d 799 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 6:e7f02929cd3d 800 RFLR_IRQFLAGS_TXDONE |
ftagius 17:20ce6dab2237 801 // RFLR_IRQFLAGS_CADDONE |
ftagius 17:20ce6dab2237 802 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL //|
ftagius 17:20ce6dab2237 803 // RFLR_IRQFLAGS_CADDETECTED
ftagius 17:20ce6dab2237 804 );
GregCr 6:e7f02929cd3d 805
GregCr 6:e7f02929cd3d 806 // DIO0=RxDone
GregCr 6:e7f02929cd3d 807 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 6:e7f02929cd3d 808 }
ftagius 17:20ce6dab2237 809
GregCr 0:e6ceb13d2d05 810 Write( REG_LR_FIFORXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 811 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 812 }
GregCr 0:e6ceb13d2d05 813 break;
GregCr 0:e6ceb13d2d05 814 }
GregCr 0:e6ceb13d2d05 815
GregCr 0:e6ceb13d2d05 816 memset( rxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
GregCr 0:e6ceb13d2d05 817
GregCr 0:e6ceb13d2d05 818 this->settings.State = RX;
GregCr 0:e6ceb13d2d05 819 if( timeout != 0 )
GregCr 0:e6ceb13d2d05 820 {
GregCr 0:e6ceb13d2d05 821 rxTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 822 }
GregCr 0:e6ceb13d2d05 823
GregCr 0:e6ceb13d2d05 824 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 825 {
GregCr 0:e6ceb13d2d05 826 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 827
GregCr 0:e6ceb13d2d05 828 if( rxContinuous == false )
GregCr 0:e6ceb13d2d05 829 {
GregCr 0:e6ceb13d2d05 830 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 831 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 832 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 833 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 834 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 835 }
GregCr 0:e6ceb13d2d05 836 }
GregCr 0:e6ceb13d2d05 837 else
GregCr 0:e6ceb13d2d05 838 {
GregCr 0:e6ceb13d2d05 839 if( rxContinuous == true )
GregCr 0:e6ceb13d2d05 840 {
ftagius 16:29f09ac61412 841 //printf("radfta rx continuous \r\n");
GregCr 0:e6ceb13d2d05 842 SetOpMode( RFLR_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 843 }
GregCr 0:e6ceb13d2d05 844 else
GregCr 0:e6ceb13d2d05 845 {
ftagius 16:29f09ac61412 846
ftagius 16:29f09ac61412 847 //printf("radfta rx single \r\n");
GregCr 0:e6ceb13d2d05 848 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
GregCr 0:e6ceb13d2d05 849 }
GregCr 0:e6ceb13d2d05 850 }
GregCr 0:e6ceb13d2d05 851 }
GregCr 0:e6ceb13d2d05 852
GregCr 0:e6ceb13d2d05 853 void SX1276::Tx( uint32_t timeout )
GregCr 0:e6ceb13d2d05 854 {
GregCr 0:e6ceb13d2d05 855 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 856 {
GregCr 0:e6ceb13d2d05 857 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 858 {
GregCr 0:e6ceb13d2d05 859 // DIO0=PacketSent
GregCr 0:e6ceb13d2d05 860 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 861 // DIO2=FifoFull
GregCr 0:e6ceb13d2d05 862 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 863 // DIO4=LowBat
GregCr 0:e6ceb13d2d05 864 // DIO5=ModeReady
GregCr 5:11ec8a6ba4f0 865 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & RF_DIOMAPPING1_DIO1_MASK &
GregCr 0:e6ceb13d2d05 866 RF_DIOMAPPING1_DIO2_MASK ) );
GregCr 0:e6ceb13d2d05 867
GregCr 0:e6ceb13d2d05 868 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 869 RF_DIOMAPPING2_MAP_MASK ) );
GregCr 0:e6ceb13d2d05 870 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 871 }
GregCr 0:e6ceb13d2d05 872 break;
GregCr 0:e6ceb13d2d05 873 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 874 {
GregCr 6:e7f02929cd3d 875
GregCr 6:e7f02929cd3d 876 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 877 {
GregCr 6:e7f02929cd3d 878 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 6:e7f02929cd3d 879 RFLR_IRQFLAGS_RXDONE |
GregCr 6:e7f02929cd3d 880 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 6:e7f02929cd3d 881 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 6:e7f02929cd3d 882 //RFLR_IRQFLAGS_TXDONE |
GregCr 6:e7f02929cd3d 883 RFLR_IRQFLAGS_CADDONE |
GregCr 6:e7f02929cd3d 884 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 6:e7f02929cd3d 885 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 886
GregCr 6:e7f02929cd3d 887 // DIO0=TxDone
GregCr 8:0fe3e0e8007b 888 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
GregCr 6:e7f02929cd3d 889 // DIO2=FhssChangeChannel
GregCr 6:e7f02929cd3d 890 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 891 }
GregCr 6:e7f02929cd3d 892 else
GregCr 6:e7f02929cd3d 893 {
GregCr 6:e7f02929cd3d 894 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 895 RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 896 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 0:e6ceb13d2d05 897 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 898 //RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 899 RFLR_IRQFLAGS_CADDONE |
GregCr 0:e6ceb13d2d05 900 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 901 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 902
GregCr 6:e7f02929cd3d 903 // DIO0=TxDone
GregCr 6:e7f02929cd3d 904 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
GregCr 6:e7f02929cd3d 905 }
GregCr 0:e6ceb13d2d05 906 }
GregCr 0:e6ceb13d2d05 907 break;
GregCr 0:e6ceb13d2d05 908 }
GregCr 0:e6ceb13d2d05 909
GregCr 0:e6ceb13d2d05 910 this->settings.State = TX;
mluis 13:618826a997e2 911 txTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 912 SetOpMode( RF_OPMODE_TRANSMITTER );
GregCr 0:e6ceb13d2d05 913 }
GregCr 0:e6ceb13d2d05 914
GregCr 7:2b555111463f 915 void SX1276::StartCad( void )
GregCr 0:e6ceb13d2d05 916 {
GregCr 7:2b555111463f 917 switch( this->settings.Modem )
GregCr 7:2b555111463f 918 {
GregCr 7:2b555111463f 919 case MODEM_FSK:
GregCr 7:2b555111463f 920 {
GregCr 7:2b555111463f 921
GregCr 7:2b555111463f 922 }
GregCr 7:2b555111463f 923 break;
GregCr 7:2b555111463f 924 case MODEM_LORA:
GregCr 7:2b555111463f 925 {
GregCr 7:2b555111463f 926 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 7:2b555111463f 927 RFLR_IRQFLAGS_RXDONE |
GregCr 7:2b555111463f 928 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 7:2b555111463f 929 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 7:2b555111463f 930 RFLR_IRQFLAGS_TXDONE |
GregCr 7:2b555111463f 931 //RFLR_IRQFLAGS_CADDONE |
ftagius 17:20ce6dab2237 932 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL //|
GregCr 12:aa5b3bf7fdf4 933 //RFLR_IRQFLAGS_CADDETECTED
GregCr 12:aa5b3bf7fdf4 934 );
GregCr 7:2b555111463f 935
GregCr 7:2b555111463f 936 // DIO3=CADDone
GregCr 7:2b555111463f 937 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 7:2b555111463f 938
GregCr 7:2b555111463f 939 this->settings.State = CAD;
GregCr 7:2b555111463f 940 SetOpMode( RFLR_OPMODE_CAD );
GregCr 7:2b555111463f 941 }
GregCr 7:2b555111463f 942 break;
GregCr 7:2b555111463f 943 default:
GregCr 7:2b555111463f 944 break;
GregCr 7:2b555111463f 945 }
GregCr 7:2b555111463f 946 }
GregCr 7:2b555111463f 947
GregCr 7:2b555111463f 948 int16_t SX1276::GetRssi( ModemType modem )
GregCr 7:2b555111463f 949 {
GregCr 7:2b555111463f 950 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 951
GregCr 0:e6ceb13d2d05 952 switch( modem )
GregCr 0:e6ceb13d2d05 953 {
GregCr 0:e6ceb13d2d05 954 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 955 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 956 break;
GregCr 0:e6ceb13d2d05 957 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 958 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 959 {
GregCr 0:e6ceb13d2d05 960 rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 961 }
GregCr 0:e6ceb13d2d05 962 else
GregCr 0:e6ceb13d2d05 963 {
GregCr 0:e6ceb13d2d05 964 rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 965 }
GregCr 0:e6ceb13d2d05 966 break;
GregCr 0:e6ceb13d2d05 967 default:
GregCr 0:e6ceb13d2d05 968 rssi = -1;
GregCr 0:e6ceb13d2d05 969 break;
GregCr 0:e6ceb13d2d05 970 }
ftagius 16:29f09ac61412 971 if (rssi > 100)
ftagius 16:29f09ac61412 972 {
ftagius 16:29f09ac61412 973 rssi *= -1;
ftagius 16:29f09ac61412 974 printf("rssi sign change %d\r\n",rssi);
ftagius 16:29f09ac61412 975 }
ftagius 16:29f09ac61412 976 else
ftagius 16:29f09ac61412 977 printf("no rssi sign change %d\r\n", rssi
ftagius 16:29f09ac61412 978 );
GregCr 0:e6ceb13d2d05 979 return rssi;
GregCr 0:e6ceb13d2d05 980 }
GregCr 0:e6ceb13d2d05 981
GregCr 0:e6ceb13d2d05 982 void SX1276::SetOpMode( uint8_t opMode )
GregCr 0:e6ceb13d2d05 983 {
GregCr 0:e6ceb13d2d05 984 if( opMode != previousOpMode )
GregCr 0:e6ceb13d2d05 985 {
GregCr 0:e6ceb13d2d05 986 previousOpMode = opMode;
GregCr 0:e6ceb13d2d05 987 if( opMode == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 988 {
GregCr 0:e6ceb13d2d05 989 SetAntSwLowPower( true );
GregCr 0:e6ceb13d2d05 990 }
GregCr 0:e6ceb13d2d05 991 else
GregCr 0:e6ceb13d2d05 992 {
GregCr 0:e6ceb13d2d05 993 SetAntSwLowPower( false );
GregCr 0:e6ceb13d2d05 994 if( opMode == RF_OPMODE_TRANSMITTER )
GregCr 0:e6ceb13d2d05 995 {
GregCr 0:e6ceb13d2d05 996 SetAntSw( 1 );
GregCr 0:e6ceb13d2d05 997 }
GregCr 0:e6ceb13d2d05 998 else
GregCr 0:e6ceb13d2d05 999 {
GregCr 0:e6ceb13d2d05 1000 SetAntSw( 0 );
GregCr 0:e6ceb13d2d05 1001 }
GregCr 0:e6ceb13d2d05 1002 }
GregCr 0:e6ceb13d2d05 1003 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
GregCr 0:e6ceb13d2d05 1004 }
GregCr 0:e6ceb13d2d05 1005 }
GregCr 0:e6ceb13d2d05 1006
GregCr 0:e6ceb13d2d05 1007 void SX1276::SetModem( ModemType modem )
GregCr 0:e6ceb13d2d05 1008 {
GregCr 4:f0ce52e94d3f 1009 if( this->settings.Modem != modem )
GregCr 0:e6ceb13d2d05 1010 {
mluis 13:618826a997e2 1011 this->settings.Modem = modem;
mluis 13:618826a997e2 1012 switch( this->settings.Modem )
mluis 13:618826a997e2 1013 {
mluis 13:618826a997e2 1014 default:
mluis 13:618826a997e2 1015 case MODEM_FSK:
mluis 13:618826a997e2 1016 SetOpMode( RF_OPMODE_SLEEP );
mluis 13:618826a997e2 1017 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
mluis 13:618826a997e2 1018
mluis 13:618826a997e2 1019 Write( REG_DIOMAPPING1, 0x00 );
mluis 13:618826a997e2 1020 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
mluis 13:618826a997e2 1021 break;
mluis 13:618826a997e2 1022 case MODEM_LORA:
mluis 13:618826a997e2 1023 SetOpMode( RF_OPMODE_SLEEP );
mluis 13:618826a997e2 1024 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
mluis 13:618826a997e2 1025 Write( 0x30, 0x00 ); // IF = 0
mluis 13:618826a997e2 1026 Write( REG_LR_DETECTOPTIMIZE, ( Read( REG_LR_DETECTOPTIMIZE ) & 0x7F ) ); // Manual IF
mluis 13:618826a997e2 1027 Write( REG_DIOMAPPING1, 0x00 );
mluis 13:618826a997e2 1028 Write( REG_DIOMAPPING2, 0x00 );
mluis 13:618826a997e2 1029 break;
mluis 13:618826a997e2 1030 }
GregCr 0:e6ceb13d2d05 1031 }
GregCr 0:e6ceb13d2d05 1032 }
GregCr 0:e6ceb13d2d05 1033
GregCr 0:e6ceb13d2d05 1034 void SX1276::OnTimeoutIrq( void )
GregCr 0:e6ceb13d2d05 1035 {
GregCr 0:e6ceb13d2d05 1036 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1037 {
GregCr 0:e6ceb13d2d05 1038 case RX:
GregCr 0:e6ceb13d2d05 1039 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 1040 {
GregCr 0:e6ceb13d2d05 1041 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1042 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1043 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1044 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1045
GregCr 0:e6ceb13d2d05 1046 // Clear Irqs
GregCr 0:e6ceb13d2d05 1047 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 1048 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 1049 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 1050 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 1051
GregCr 0:e6ceb13d2d05 1052 if( this->settings.Fsk.RxContinuous == true )
GregCr 0:e6ceb13d2d05 1053 {
GregCr 0:e6ceb13d2d05 1054 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1055 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1056 }
GregCr 0:e6ceb13d2d05 1057 else
GregCr 0:e6ceb13d2d05 1058 {
GregCr 5:11ec8a6ba4f0 1059 this->settings.State = IDLE;
GregCr 5:11ec8a6ba4f0 1060 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1061 }
GregCr 0:e6ceb13d2d05 1062 }
GregCr 0:e6ceb13d2d05 1063 if( ( rxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1064 {
GregCr 0:e6ceb13d2d05 1065 rxTimeout( );
GregCr 0:e6ceb13d2d05 1066 }
GregCr 0:e6ceb13d2d05 1067 break;
GregCr 0:e6ceb13d2d05 1068 case TX:
mluis 13:618826a997e2 1069 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1070 if( ( txTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1071 {
GregCr 0:e6ceb13d2d05 1072 txTimeout( );
GregCr 0:e6ceb13d2d05 1073 }
GregCr 0:e6ceb13d2d05 1074 break;
GregCr 0:e6ceb13d2d05 1075 default:
GregCr 0:e6ceb13d2d05 1076 break;
GregCr 0:e6ceb13d2d05 1077 }
GregCr 0:e6ceb13d2d05 1078 }
GregCr 0:e6ceb13d2d05 1079
GregCr 0:e6ceb13d2d05 1080 void SX1276::OnDio0Irq( void )
GregCr 0:e6ceb13d2d05 1081 {
GregCr 0:e6ceb13d2d05 1082 __IO uint8_t irqFlags = 0;
GregCr 0:e6ceb13d2d05 1083
ftagius 17:20ce6dab2237 1084 //printf("radfta dio0irq\r\n");
GregCr 0:e6ceb13d2d05 1085 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1086 {
GregCr 0:e6ceb13d2d05 1087 case RX:
GregCr 0:e6ceb13d2d05 1088 //TimerStop( &RxTimeoutTimer );
GregCr 0:e6ceb13d2d05 1089 // RxDone interrupt
GregCr 0:e6ceb13d2d05 1090 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1091 {
GregCr 0:e6ceb13d2d05 1092 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1093 irqFlags = Read( REG_IRQFLAGS2 );
GregCr 0:e6ceb13d2d05 1094 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
GregCr 0:e6ceb13d2d05 1095 {
GregCr 0:e6ceb13d2d05 1096 // Clear Irqs
GregCr 0:e6ceb13d2d05 1097 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 1098 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 1099 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 1100 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 1101
GregCr 0:e6ceb13d2d05 1102 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1103 {
GregCr 0:e6ceb13d2d05 1104 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1105 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 1106 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 1107 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 1108 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 1109 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 1110 }
GregCr 0:e6ceb13d2d05 1111 else
GregCr 0:e6ceb13d2d05 1112 {
GregCr 0:e6ceb13d2d05 1113 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1114 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1115 }
GregCr 0:e6ceb13d2d05 1116 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1117
GregCr 0:e6ceb13d2d05 1118 if( ( rxError != NULL ) )
GregCr 0:e6ceb13d2d05 1119 {
GregCr 0:e6ceb13d2d05 1120 rxError( );
GregCr 0:e6ceb13d2d05 1121 }
GregCr 0:e6ceb13d2d05 1122 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1123 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1124 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1125 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1126 break;
GregCr 0:e6ceb13d2d05 1127 }
GregCr 0:e6ceb13d2d05 1128
GregCr 0:e6ceb13d2d05 1129 // Read received packet size
GregCr 0:e6ceb13d2d05 1130 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1131 {
GregCr 0:e6ceb13d2d05 1132 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1133 {
GregCr 0:e6ceb13d2d05 1134 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1135 }
GregCr 0:e6ceb13d2d05 1136 else
GregCr 0:e6ceb13d2d05 1137 {
GregCr 0:e6ceb13d2d05 1138 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1139 }
GregCr 0:e6ceb13d2d05 1140 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1141 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1142 }
GregCr 0:e6ceb13d2d05 1143 else
GregCr 0:e6ceb13d2d05 1144 {
GregCr 0:e6ceb13d2d05 1145 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1146 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1147 }
GregCr 0:e6ceb13d2d05 1148
GregCr 0:e6ceb13d2d05 1149 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1150 {
GregCr 0:e6ceb13d2d05 1151 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1152 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 1153 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 1154 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 1155 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 1156 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 1157 }
GregCr 0:e6ceb13d2d05 1158 else
GregCr 0:e6ceb13d2d05 1159 {
GregCr 0:e6ceb13d2d05 1160 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1161 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1162 }
GregCr 0:e6ceb13d2d05 1163 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1164
GregCr 0:e6ceb13d2d05 1165 if( (rxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1166 {
GregCr 0:e6ceb13d2d05 1167 rxDone( rxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
GregCr 0:e6ceb13d2d05 1168 }
GregCr 0:e6ceb13d2d05 1169 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1170 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1171 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1172 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1173 break;
GregCr 0:e6ceb13d2d05 1174 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1175 {
GregCr 0:e6ceb13d2d05 1176 uint8_t snr = 0;
GregCr 0:e6ceb13d2d05 1177
GregCr 0:e6ceb13d2d05 1178 // Clear Irq
GregCr 0:e6ceb13d2d05 1179 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
GregCr 0:e6ceb13d2d05 1180
GregCr 0:e6ceb13d2d05 1181 irqFlags = Read( REG_LR_IRQFLAGS );
GregCr 0:e6ceb13d2d05 1182 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
GregCr 0:e6ceb13d2d05 1183 {
GregCr 0:e6ceb13d2d05 1184 // Clear Irq
GregCr 0:e6ceb13d2d05 1185 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
GregCr 0:e6ceb13d2d05 1186
GregCr 0:e6ceb13d2d05 1187 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1188 {
GregCr 0:e6ceb13d2d05 1189 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1190 }
GregCr 0:e6ceb13d2d05 1191 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1192
GregCr 4:f0ce52e94d3f 1193 if( ( rxError != NULL ) )
GregCr 0:e6ceb13d2d05 1194 {
GregCr 0:e6ceb13d2d05 1195 rxError( );
GregCr 0:e6ceb13d2d05 1196 }
GregCr 0:e6ceb13d2d05 1197 break;
GregCr 0:e6ceb13d2d05 1198 }
GregCr 0:e6ceb13d2d05 1199
GregCr 0:e6ceb13d2d05 1200 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
GregCr 0:e6ceb13d2d05 1201 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
GregCr 0:e6ceb13d2d05 1202 {
GregCr 0:e6ceb13d2d05 1203 // Invert and divide by 4
GregCr 0:e6ceb13d2d05 1204 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1205 snr = -snr;
GregCr 0:e6ceb13d2d05 1206 }
GregCr 0:e6ceb13d2d05 1207 else
GregCr 0:e6ceb13d2d05 1208 {
GregCr 0:e6ceb13d2d05 1209 // Divide by 4
GregCr 0:e6ceb13d2d05 1210 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1211 }
GregCr 0:e6ceb13d2d05 1212
GregCr 7:2b555111463f 1213 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
ftagius 16:29f09ac61412 1214
GregCr 0:e6ceb13d2d05 1215 if( this->settings.LoRaPacketHandler.SnrValue < 0 )
GregCr 0:e6ceb13d2d05 1216 {
GregCr 0:e6ceb13d2d05 1217 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1218 {
GregCr 0:e6ceb13d2d05 1219 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1220 snr;
ftagius 16:29f09ac61412 1221 //printf("1 rssi=%x snr=%d rssi_4=%x\r\n", rssi, snr, rssi>> 4);
GregCr 0:e6ceb13d2d05 1222 }
GregCr 0:e6ceb13d2d05 1223 else
GregCr 0:e6ceb13d2d05 1224 {
GregCr 0:e6ceb13d2d05 1225 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1226 snr;
ftagius 16:29f09ac61412 1227 //printf("2\r\n");
GregCr 0:e6ceb13d2d05 1228 }
GregCr 0:e6ceb13d2d05 1229 }
GregCr 0:e6ceb13d2d05 1230 else
GregCr 0:e6ceb13d2d05 1231 {
GregCr 0:e6ceb13d2d05 1232 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1233 {
GregCr 0:e6ceb13d2d05 1234 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
ftagius 16:29f09ac61412 1235 //printf("3\r\n");
ftagius 16:29f09ac61412 1236 //printf("3 rssi=%x snr=%d rssi_4=%x\r\n", rssi, snr, rssi>> 4);
GregCr 0:e6ceb13d2d05 1237 }
GregCr 0:e6ceb13d2d05 1238 else
GregCr 0:e6ceb13d2d05 1239 {
GregCr 0:e6ceb13d2d05 1240 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
ftagius 16:29f09ac61412 1241 //printf("4\r\n");
GregCr 0:e6ceb13d2d05 1242 }
GregCr 0:e6ceb13d2d05 1243 }
ftagius 16:29f09ac61412 1244
ftagius 16:29f09ac61412 1245 if (this->settings.LoRaPacketHandler.RssiValue > 50)
ftagius 16:29f09ac61412 1246 {
ftagius 16:29f09ac61412 1247 this->settings.LoRaPacketHandler.RssiValue16 = this->settings.LoRaPacketHandler.RssiValue - 256;
ftagius 16:29f09ac61412 1248 //printf("rssi in irq done, WAS FIXED is %d\r\n", this->settings.LoRaPacketHandler.RssiValue16);
ftagius 16:29f09ac61412 1249 }
ftagius 16:29f09ac61412 1250 else
ftagius 16:29f09ac61412 1251 this->settings.LoRaPacketHandler.RssiValue16 = this->settings.LoRaPacketHandler.RssiValue;
GregCr 0:e6ceb13d2d05 1252
ftagius 16:29f09ac61412 1253
GregCr 0:e6ceb13d2d05 1254 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
GregCr 0:e6ceb13d2d05 1255 ReadFifo( rxBuffer, this->settings.LoRaPacketHandler.Size );
GregCr 0:e6ceb13d2d05 1256
GregCr 0:e6ceb13d2d05 1257 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1258 {
GregCr 0:e6ceb13d2d05 1259 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1260 }
GregCr 0:e6ceb13d2d05 1261 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1262
GregCr 0:e6ceb13d2d05 1263 if( ( rxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1264 {
ftagius 16:29f09ac61412 1265 rxDone( rxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue16, this->settings.LoRaPacketHandler.SnrValue );
GregCr 0:e6ceb13d2d05 1266 }
GregCr 0:e6ceb13d2d05 1267 }
GregCr 0:e6ceb13d2d05 1268 break;
GregCr 0:e6ceb13d2d05 1269 default:
GregCr 0:e6ceb13d2d05 1270 break;
GregCr 0:e6ceb13d2d05 1271 }
GregCr 0:e6ceb13d2d05 1272 break;
GregCr 0:e6ceb13d2d05 1273 case TX:
GregCr 0:e6ceb13d2d05 1274 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1275 // TxDone interrupt
GregCr 0:e6ceb13d2d05 1276 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1277 {
GregCr 0:e6ceb13d2d05 1278 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1279 // Clear Irq
GregCr 0:e6ceb13d2d05 1280 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
GregCr 0:e6ceb13d2d05 1281 // Intentional fall through
GregCr 0:e6ceb13d2d05 1282 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1283 default:
GregCr 0:e6ceb13d2d05 1284 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1285 if( ( txDone != NULL ) )
GregCr 0:e6ceb13d2d05 1286 {
GregCr 0:e6ceb13d2d05 1287 txDone( );
GregCr 0:e6ceb13d2d05 1288 }
GregCr 0:e6ceb13d2d05 1289 break;
GregCr 0:e6ceb13d2d05 1290 }
GregCr 0:e6ceb13d2d05 1291 break;
GregCr 0:e6ceb13d2d05 1292 default:
GregCr 0:e6ceb13d2d05 1293 break;
GregCr 0:e6ceb13d2d05 1294 }
GregCr 0:e6ceb13d2d05 1295 }
GregCr 0:e6ceb13d2d05 1296
GregCr 0:e6ceb13d2d05 1297 void SX1276::OnDio1Irq( void )
GregCr 0:e6ceb13d2d05 1298 {
ftagius 17:20ce6dab2237 1299 printf("ondio1 irq\r\n");
GregCr 0:e6ceb13d2d05 1300 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1301 {
GregCr 0:e6ceb13d2d05 1302 case RX:
GregCr 0:e6ceb13d2d05 1303 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1304 {
GregCr 0:e6ceb13d2d05 1305 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1306 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1307 // Read received packet size
GregCr 0:e6ceb13d2d05 1308 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1309 {
GregCr 0:e6ceb13d2d05 1310 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1311 {
GregCr 0:e6ceb13d2d05 1312 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1313 }
GregCr 0:e6ceb13d2d05 1314 else
GregCr 0:e6ceb13d2d05 1315 {
GregCr 0:e6ceb13d2d05 1316 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1317 }
GregCr 0:e6ceb13d2d05 1318 }
GregCr 0:e6ceb13d2d05 1319
GregCr 0:e6ceb13d2d05 1320 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
GregCr 0:e6ceb13d2d05 1321 {
GregCr 0:e6ceb13d2d05 1322 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
GregCr 0:e6ceb13d2d05 1323 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
GregCr 0:e6ceb13d2d05 1324 }
GregCr 0:e6ceb13d2d05 1325 else
GregCr 0:e6ceb13d2d05 1326 {
GregCr 0:e6ceb13d2d05 1327 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1328 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1329 }
GregCr 0:e6ceb13d2d05 1330 break;
GregCr 0:e6ceb13d2d05 1331 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1332 // Sync time out
GregCr 0:e6ceb13d2d05 1333 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1334 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1335 if( ( rxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1336 {
GregCr 0:e6ceb13d2d05 1337 rxTimeout( );
GregCr 0:e6ceb13d2d05 1338 }
GregCr 0:e6ceb13d2d05 1339 break;
GregCr 0:e6ceb13d2d05 1340 default:
GregCr 0:e6ceb13d2d05 1341 break;
GregCr 0:e6ceb13d2d05 1342 }
GregCr 0:e6ceb13d2d05 1343 break;
GregCr 0:e6ceb13d2d05 1344 case TX:
GregCr 0:e6ceb13d2d05 1345 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1346 {
GregCr 0:e6ceb13d2d05 1347 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1348 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1349 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
GregCr 0:e6ceb13d2d05 1350 {
GregCr 0:e6ceb13d2d05 1351 WriteFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 1352 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 1353 }
GregCr 0:e6ceb13d2d05 1354 else
GregCr 0:e6ceb13d2d05 1355 {
GregCr 0:e6ceb13d2d05 1356 // Write the last chunk of data
GregCr 0:e6ceb13d2d05 1357 WriteFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1358 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
GregCr 0:e6ceb13d2d05 1359 }
GregCr 0:e6ceb13d2d05 1360 break;
GregCr 0:e6ceb13d2d05 1361 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1362 break;
GregCr 0:e6ceb13d2d05 1363 default:
GregCr 0:e6ceb13d2d05 1364 break;
GregCr 0:e6ceb13d2d05 1365 }
GregCr 0:e6ceb13d2d05 1366 break;
GregCr 0:e6ceb13d2d05 1367 default:
GregCr 0:e6ceb13d2d05 1368 break;
GregCr 0:e6ceb13d2d05 1369 }
GregCr 0:e6ceb13d2d05 1370 }
GregCr 0:e6ceb13d2d05 1371
GregCr 0:e6ceb13d2d05 1372 void SX1276::OnDio2Irq( void )
GregCr 0:e6ceb13d2d05 1373 {
ftagius 17:20ce6dab2237 1374 // printf("ondio2 irq\r\n");
GregCr 0:e6ceb13d2d05 1375 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1376 {
GregCr 0:e6ceb13d2d05 1377 case RX:
GregCr 0:e6ceb13d2d05 1378 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1379 {
GregCr 0:e6ceb13d2d05 1380 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1381 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
GregCr 0:e6ceb13d2d05 1382 {
GregCr 0:e6ceb13d2d05 1383 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1384
GregCr 0:e6ceb13d2d05 1385 this->settings.FskPacketHandler.SyncWordDetected = true;
GregCr 0:e6ceb13d2d05 1386
GregCr 0:e6ceb13d2d05 1387 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 1388
GregCr 0:e6ceb13d2d05 1389 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
GregCr 0:e6ceb13d2d05 1390 ( uint16_t )Read( REG_AFCLSB ) ) *
GregCr 0:e6ceb13d2d05 1391 ( double )FREQ_STEP;
GregCr 0:e6ceb13d2d05 1392 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
GregCr 0:e6ceb13d2d05 1393 }
GregCr 0:e6ceb13d2d05 1394 break;
GregCr 0:e6ceb13d2d05 1395 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1396 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1397 {
GregCr 6:e7f02929cd3d 1398 // Clear Irq
GregCr 6:e7f02929cd3d 1399 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
GregCr 6:e7f02929cd3d 1400
mluis 13:618826a997e2 1401 if( ( fhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1402 {
mluis 13:618826a997e2 1403 fhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1404 }
GregCr 6:e7f02929cd3d 1405 }
GregCr 0:e6ceb13d2d05 1406 break;
GregCr 0:e6ceb13d2d05 1407 default:
GregCr 0:e6ceb13d2d05 1408 break;
GregCr 0:e6ceb13d2d05 1409 }
GregCr 0:e6ceb13d2d05 1410 break;
GregCr 0:e6ceb13d2d05 1411 case TX:
GregCr 0:e6ceb13d2d05 1412 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1413 {
GregCr 0:e6ceb13d2d05 1414 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1415 break;
GregCr 0:e6ceb13d2d05 1416 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1417 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1418 {
GregCr 6:e7f02929cd3d 1419 // Clear Irq
GregCr 6:e7f02929cd3d 1420 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
GregCr 6:e7f02929cd3d 1421
mluis 13:618826a997e2 1422 if( ( fhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1423 {
mluis 13:618826a997e2 1424 fhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1425 }
GregCr 6:e7f02929cd3d 1426 }
GregCr 0:e6ceb13d2d05 1427 break;
GregCr 0:e6ceb13d2d05 1428 default:
GregCr 0:e6ceb13d2d05 1429 break;
GregCr 0:e6ceb13d2d05 1430 }
GregCr 0:e6ceb13d2d05 1431 break;
GregCr 0:e6ceb13d2d05 1432 default:
GregCr 0:e6ceb13d2d05 1433 break;
GregCr 0:e6ceb13d2d05 1434 }
GregCr 0:e6ceb13d2d05 1435 }
GregCr 0:e6ceb13d2d05 1436
GregCr 0:e6ceb13d2d05 1437 void SX1276::OnDio3Irq( void )
GregCr 0:e6ceb13d2d05 1438 {
ftagius 17:20ce6dab2237 1439 // printf("dio3 irq\r\n");
GregCr 0:e6ceb13d2d05 1440 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1441 {
GregCr 0:e6ceb13d2d05 1442 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1443 break;
GregCr 0:e6ceb13d2d05 1444 case MODEM_LORA:
mluis 13:618826a997e2 1445 if( ( Read( REG_LR_IRQFLAGS ) & 0x01 ) == 0x01 )
mluis 13:618826a997e2 1446 {
mluis 13:618826a997e2 1447 // Clear Irq
ftagius 17:20ce6dab2237 1448 // printf("clear cad irq 1\r\n");
mluis 13:618826a997e2 1449 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED_MASK | RFLR_IRQFLAGS_CADDONE);
mluis 13:618826a997e2 1450 if( ( cadDone != NULL ) )
mluis 13:618826a997e2 1451 {
ftagius 17:20ce6dab2237 1452 printf("call caddone with true");
mluis 13:618826a997e2 1453 cadDone( true );
mluis 13:618826a997e2 1454 }
GregCr 12:aa5b3bf7fdf4 1455 }
GregCr 12:aa5b3bf7fdf4 1456 else
mluis 13:618826a997e2 1457 {
mluis 13:618826a997e2 1458 // Clear Irq
ftagius 17:20ce6dab2237 1459 // printf("clear cad irq 2 \r\n");
mluis 13:618826a997e2 1460 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
mluis 13:618826a997e2 1461 if( ( cadDone != NULL ) )
mluis 13:618826a997e2 1462 {
mluis 13:618826a997e2 1463 cadDone( false );
mluis 13:618826a997e2 1464 }
GregCr 7:2b555111463f 1465 }
GregCr 0:e6ceb13d2d05 1466 break;
GregCr 0:e6ceb13d2d05 1467 default:
GregCr 0:e6ceb13d2d05 1468 break;
GregCr 0:e6ceb13d2d05 1469 }
GregCr 0:e6ceb13d2d05 1470 }
GregCr 0:e6ceb13d2d05 1471
GregCr 0:e6ceb13d2d05 1472 void SX1276::OnDio4Irq( void )
GregCr 0:e6ceb13d2d05 1473 {
GregCr 0:e6ceb13d2d05 1474 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1475 {
GregCr 0:e6ceb13d2d05 1476 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1477 {
GregCr 0:e6ceb13d2d05 1478 if( this->settings.FskPacketHandler.PreambleDetected == false )
GregCr 0:e6ceb13d2d05 1479 {
GregCr 0:e6ceb13d2d05 1480 this->settings.FskPacketHandler.PreambleDetected = true;
GregCr 0:e6ceb13d2d05 1481 }
GregCr 0:e6ceb13d2d05 1482 }
GregCr 0:e6ceb13d2d05 1483 break;
GregCr 0:e6ceb13d2d05 1484 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1485 break;
GregCr 0:e6ceb13d2d05 1486 default:
GregCr 0:e6ceb13d2d05 1487 break;
GregCr 0:e6ceb13d2d05 1488 }
GregCr 0:e6ceb13d2d05 1489 }
GregCr 0:e6ceb13d2d05 1490
GregCr 0:e6ceb13d2d05 1491 void SX1276::OnDio5Irq( void )
GregCr 0:e6ceb13d2d05 1492 {
ftagius 17:20ce6dab2237 1493 // printf("radfta dio5 irq\r\n");
GregCr 0:e6ceb13d2d05 1494 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1495 {
GregCr 0:e6ceb13d2d05 1496 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1497 break;
GregCr 0:e6ceb13d2d05 1498 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1499 break;
GregCr 0:e6ceb13d2d05 1500 default:
GregCr 0:e6ceb13d2d05 1501 break;
GregCr 0:e6ceb13d2d05 1502 }
mluis 13:618826a997e2 1503 }